Method for manufacturing a semiconductor device and semiconductor device

Abstract

The application provides a semiconductor device manufacturing method and a semiconductor device. The semiconductor device manufacturing method comprises the following steps: providing a substrate, a first recess, a barrier layer, a first oxide layer and a second oxide layer. The substrate comprises a high-voltage device area and a low-voltage device area. The low-voltage device area is located on one side of the high-voltage device area. The barrier layer is located on the high-voltage device area. The first recess is located in the low-voltage device area. The first oxide layer is located on the surface of the barrier layer away from the high-voltage device area. The second oxide layer covers the sidewall of the first recess. The thickness of the first oxide layer is smaller than the thickness of the second oxide layer. The first oxide layer and part of the second oxide layer are removed so that the barrier layer is exposed. After the barrier layer is removed, the remaining second oxide layer is removed. The semiconductor device manufacturing method does not affect the active area critical dimension, and ensures that the device performance is good.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more specifically, to a method for manufacturing a semiconductor device and the semiconductor device itself. Background Technology

[0002] During the fabrication of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) structure, removing the protective layer of the HV (High Voltage) device region can damage the exposed sidewalls of the LV (Low Voltage) device region, thereby affecting the critical dimensions of the active region and consequently impacting the overall performance of the device.

[0003] Therefore, there is an urgent need for a method to solve the problem of damage to the sidewalls of the LV region when removing the protective layer of the HV region, which affects the device performance.

[0004] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0005] The main objective of this application is to provide a method for fabricating a semiconductor device and a semiconductor device in order to solve the problem of damage to the sidewalls of the LV region when removing the protective layer of the HV region, which affects the device performance.

[0006] To achieve the above objectives, according to one aspect of this application, a method for fabricating a semiconductor device is provided, comprising: providing a substrate, a first trench, a barrier layer, a first oxide layer, and a second oxide layer, wherein the substrate includes a high-voltage device region and a low-voltage device region, the low-voltage device region is located on one side of the high-voltage device region, the barrier layer is located on the high-voltage device region, the first trench is located in the low-voltage device region, the first oxide layer is located on the surface of the barrier layer away from the high-voltage device region, the second oxide layer covers the sidewall of the first trench, and the thickness of the first oxide layer is less than the thickness of the second oxide layer; removing the first oxide layer and a portion of the second oxide layer to expose the barrier layer; and after removing the barrier layer, removing the remaining second oxide layer.

[0007] Optionally, a substrate, a first trench, a barrier layer, a first oxide layer, and a second oxide layer are provided, comprising: providing a pre-substrate, the pre-substrate including the high-voltage device region and the low-voltage device region; removing a portion of the pre-substrate to form a second trench in the low-voltage device region; forming a pre-barrier layer on the high-voltage device region; oxidizing the exposed sidewalls of the second trench and the pre-barrier layer to form the second oxide layer and the first oxide layer, respectively, the remaining pre-barrier layer forming the barrier layer, and the remaining second trench forming the first trench.

[0008] Optionally, the exposed sidewalls of the second groove and the pre-prepared barrier layer are oxidized, including: oxidizing the exposed sidewalls of the second groove and the pre-prepared barrier layer using a furnace tube wet oxidation process.

[0009] Optionally, removing a portion of the pre-substrate to form a second groove in the low-voltage device region includes: removing a portion of the pre-substrate, forming a third groove in the high-voltage device region, and forming a fourth groove in the low-voltage device region; filling the third groove and the fourth groove with an oxide material, and the filled fourth groove forming the second groove.

[0010] Optionally, removing a portion of the pre-substrate to form a third groove in the high-voltage device region and a fourth groove in the low-voltage device region includes: sequentially stacking a gate oxide layer and a dielectric layer on the pre-substrate; removing a portion of the gate oxide layer, a portion of the dielectric layer, and a portion of the pre-substrate to form a third groove penetrating the gate oxide layer and the dielectric layer to the high-voltage device region, and forming a fourth groove penetrating the gate oxide layer and the dielectric layer to the low-voltage device region; the remaining gate oxide layer on the high-voltage device region forms a first gate oxide portion, and the remaining gate oxide layer on the low-voltage device region forms a second gate oxide portion.

[0011] Optionally, after removing the remaining second oxide layer, the method further includes removing the remaining dielectric layer and the second gate oxide portion.

[0012] Optionally, there are multiple low-voltage device regions, and at least some of the low-voltage device regions correspond to different device voltages. There are multiple first grooves, and each first groove is located in a corresponding low-voltage device region.

[0013] Optionally, the oxidation rate of the substrate material is greater than the oxidation rate of the barrier layer material.

[0014] Optionally, the substrate is made of silicon, and the barrier layer is made of polycrystalline silicon.

[0015] According to another aspect of this application, a semiconductor device is provided, said semiconductor device being manufactured using any of the methods described.

[0016] According to the technical solution of this application, the method for fabricating the semiconductor device first provides a substrate including a high-voltage device region and a low-voltage device region, a first groove located in the first low-voltage device region, a barrier layer, a first oxide layer, and a second oxide layer. The barrier layer is located on the high-voltage device region. The first oxide layer covers the surface of the barrier layer away from the high-voltage device region, and the second oxide layer covers the sidewall of the first groove. The thickness of the first oxide layer is less than the thickness of the second oxide layer. Then, the first oxide layer and a portion of the second oxide layer are removed. Finally, the remaining second oxide layer and the barrier layer are removed. The method of this application, by growing the first oxide layer and the second oxide layer such that the thickness of the first oxide layer is less than the thickness of the second oxide layer, ensures that the second oxide layer is not completely removed when the first oxide layer is removed. Thus, when the barrier layer is removed, the remaining second oxide layer protects the sidewall of the first groove from damage, ensuring that the critical dimensions of the active region in the low-voltage device region are not affected, thereby ensuring good device performance. Attached Figure Description

[0017] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0018] Figure 1 A schematic diagram of the structure in which the SiN protective layer is damaged during the etching of the oxide layer is shown in a specific embodiment;

[0019] Figure 2 It shows that Figure 1 A schematic diagram of the structure obtained by replacing the SiN protective layer with a Poly protective layer;

[0020] Figure 3 It shows the removal Figure 2 A schematic diagram of the structure obtained after the Poly protective layer is applied;

[0021] Figure 4 A schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of this application is shown;

[0022] Figure 5 A schematic diagram of the structure obtained after forming a second groove and a pre-prepared barrier layer on a pre-prepared substrate, according to an embodiment of this application, is shown.

[0023] Figure 6 An embodiment of the present application is shown. Figure 5 A schematic diagram of the structure obtained after oxidation of the shown structure;

[0024] Figure 7 Removal according to an embodiment of this application is shown. Figure 6 A schematic diagram of the semiconductor structure obtained after the first oxide layer and part of the second oxide layer are shown.

[0025] Figure 8 A schematic diagram of a semiconductor structure according to an embodiment of this application is shown.

[0026] The above figures include the following reference numerals:

[0027] 100. First groove; 101. Barrier layer; 102. First oxide layer; 103. Second oxide layer; 104. High voltage device area; 105. Low voltage device area; 106. Remaining second oxide layer; 107. Second groove; 108. Preparatory barrier layer; 109. First gate oxide portion; 110. Second gate oxide portion; 111. Dielectric layer; 112. Oxide material. Detailed Implementation

[0028] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0029] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0030] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0031] In practical applications, such as Figure 1As shown, during the etching of the oxide layers in the LV and LLV (Low Low Voltage) regions to expose the sidewalls of the LV and LLV regions to form grooves, the HV region needs to be protected. Generally, a SiN protective layer is formed on the surface of the HV region. However, the etching process of the oxide layer can also damage the SiN protective layer, thereby affecting the integrity of the gate oxide layer in the HV region.

[0032] To solve the above problems, such as Figure 2 As shown, it can be Figure 1 The SiN protective layer was replaced with a polysilicon (polycrystalline silicon) protective layer. However, the subsequent removal of the poly protective layer inevitably damages the exposed sidewall Si in the LV and LLV regions, such as... Figure 3 As shown, this affects the critical dimensions of the active region and thus the device performance.

[0033] To address the above problems, this application proposes a method for fabricating a semiconductor device and a semiconductor device thereof.

[0034] According to an embodiment of this application, a method for fabricating a semiconductor device is provided.

[0035] Figure 4 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application. Figure 4 As shown, the method includes the following steps:

[0036] Step S101, as follows Figure 6 As shown, a substrate, a first groove 100, a barrier layer 101, a first oxide layer 102, and a second oxide layer 103 are provided. The substrate includes a high-voltage device region 104 and a low-voltage device region 105. The low-voltage device region 105 is located on one side of the high-voltage device region 104. The barrier layer 101 is located on the high-voltage device region. The first groove 100 is located in the low-voltage device region 105. The first oxide layer 102 is located on the surface of the barrier layer 101 away from the high-voltage device region 104. The second oxide layer 103 covers the sidewall of the first groove 100, and the thickness of the first oxide layer 102 is less than the thickness of the second oxide layer 103.

[0037] Step S102, as follows Figure 7 As shown, the first oxide layer 102 and part of the second oxide layer 103 are removed to expose the barrier layer 101.

[0038] Step S103: After removing the barrier layer 101, remove the remaining second oxide layer 106 to obtain the following... Figure 8 The structure shown.

[0039] In the above-described semiconductor device fabrication method, a substrate including a high-voltage device region and a low-voltage device region is first provided, along with a first trench located in the first low-voltage device region, a barrier layer, a first oxide layer, and a second oxide layer. The barrier layer is located on the high-voltage device region, the first oxide layer covers the surface of the barrier layer away from the high-voltage device region, and the second oxide layer covers the sidewall of the first trench. The thickness of the first oxide layer is less than the thickness of the second oxide layer. Then, the first oxide layer and a portion of the second oxide layer are removed. Finally, the remaining second oxide layer and the barrier layer are removed. The method described in this application, by growing the first oxide layer and the second oxide layer such that the thickness of the first oxide layer is less than the thickness of the second oxide layer, ensures that the second oxide layer is not completely removed during the removal of the first oxide layer. This allows the remaining second oxide layer to protect the sidewall of the first trench from damage during the removal of the barrier layer, ensuring that the critical dimensions of the active region in the low-voltage device region are not affected, thereby guaranteeing better device performance.

[0040] To facilitate the formation of the aforementioned thinner first oxide layer and the aforementioned thicker second oxide layer, according to a specific embodiment of this application, a substrate, a first trench, a barrier layer, a first oxide layer, and a second oxide layer are provided, including: as... Figure 5 and Figure 6 As shown, a pre-substrate is provided, comprising the high-voltage device region 104 and the low-voltage device region 105. A portion of the pre-substrate is removed to form a second groove 107 in the low-voltage device region 105. A pre-blocking layer 108 is formed on the high-voltage device region 104. The exposed sidewalls of the second groove 107 and the pre-blocking layer 108 are oxidized to form a second oxide layer 103 and a first oxide layer 102, respectively. The remaining pre-blocking layer 108 forms the blocking layer 101, and the remaining second groove 107 forms the first groove 100. In this embodiment, by simultaneously oxidizing the pre-blocking layer and the sidewalls of the second groove, first oxide layers and second oxide layers of different thicknesses are obtained, and the thickness of the first oxide layer is less than the thickness of the second oxide layer. This further ensures that the first oxide layer and the second oxide layer are generated more simply, and further ensures that the remaining second oxide layer can protect the sidewalls of the first groove from damage.

[0041] Of course, those skilled in the art can also use other feasible methods to obtain the first oxide layer and the second oxide layer of different thicknesses. In a specific embodiment of this application, the oxidation of the exposed sidewall of the second groove and the preparatory barrier layer includes: oxidizing the exposed sidewall of the second groove and the preparatory barrier layer using a furnace tube wet oxidation process.

[0042] In one specific embodiment, the oxidation rate of the substrate material is greater than the oxidation rate of the barrier layer material. Because the oxidation rates of the substrate material (i.e., the sidewall material of the second groove) and the pre-barrier layer material are different, and the oxidation rate of the substrate material is greater than that of the barrier layer material, it can be further ensured that after simultaneous oxidation of the sidewall of the second groove and the pre-barrier layer, the resulting first oxide layer is thinner and the second oxide layer is thicker, further achieving a first oxide layer thickness smaller than the second oxide layer thickness.

[0043] Specifically, the substrate is made of silicon, and the barrier layer is made of polycrystalline silicon. In a more specific embodiment, the substrate is made of silicon, and the barrier layer is made of polycrystalline silicon. Because the oxidation rate of silicon is greater than that of polycrystalline silicon, under the same conditions, the thickness of silicon oxide obtained after silicon oxidation will be greater than the thickness of silicon oxide obtained after polycrystalline silicon oxidation.

[0044] Those skilled in the art can use any feasible method to form the aforementioned second groove. According to another specific embodiment of this application, removing a portion of the pre-substrate to form the second groove in the low-voltage device region includes: removing a portion of the pre-substrate, forming a third groove in the high-voltage device region, and forming a fourth groove in the low-voltage device region; such as... Figure 5 As shown, oxide material 112 is filled into the third and fourth grooves respectively, and the filled fourth groove forms the second groove 107. This simplifies the manufacturing process of the second groove.

[0045] According to another specific embodiment of this application, by removing a portion of the pre-substrate, a third groove is formed in the high-voltage device region, and a fourth groove is formed in the low-voltage device region, including: Figure 5As shown, a gate oxide layer and a dielectric layer 111 are sequentially stacked on the aforementioned pre-substrate; a portion of the aforementioned gate oxide layer, a portion of the aforementioned dielectric layer, and a portion of the aforementioned pre-substrate are removed to form a third groove penetrating the aforementioned gate oxide layer and the aforementioned dielectric layer to the aforementioned high-voltage device region, and a fourth groove penetrating the aforementioned gate oxide layer and the aforementioned dielectric layer to the aforementioned low-voltage device region. The remaining aforementioned gate oxide layer located in the aforementioned high-voltage device region forms a first gate oxide portion 109, and the remaining aforementioned gate oxide layer located in the aforementioned low-voltage device region forms a second gate oxide portion 110.

[0046] In practical applications, the thickness of the gate oxide layer formed on the high-voltage device region is greater than the thickness of the gate oxide layer formed on the low-voltage device region. Consequently, the thickness of the first gate oxide portion is greater than the thickness of the second gate oxide portion. This ensures that the high-voltage device formed in the high-voltage device region can withstand higher voltages.

[0047] In practical applications, after removing the remaining second oxide layer, the method further includes removing the remaining dielectric layer and the second gate oxide layer.

[0048] To further achieve miniaturization of the aforementioned semiconductor devices and increase their integration density, in another specific embodiment of this application, there are multiple low-voltage device regions, at least some of which correspond to devices with different voltages. There are also multiple first grooves, each located one-to-one within a low-voltage device region. By forming multiple low-voltage device regions with different device voltages on the substrate, the resulting semiconductor device integrates devices with different operating voltages, ensuring a high integration density.

[0049] According to another specific embodiment of this application, the oxide material comprises silicon oxide, and the materials of the first gate oxide layer and the second gate oxide layer each comprise silicon oxide. Of course, the materials of the oxide material, the first gate oxide layer, and the second gate oxide layer are not limited to those described above, and may also include any other feasible materials in the prior art.

[0050] Specifically, the aforementioned oxide material, the material of the aforementioned first gate oxide layer, and the material of the aforementioned second gate oxide layer are all silicon oxide.

[0051] According to another typical embodiment of this application, a semiconductor device is also provided, which is manufactured using any of the above-described semiconductor device manufacturing methods.

[0052] The aforementioned semiconductor device is fabricated by any of the aforementioned semiconductor device fabrication methods. The method grows the first oxide layer and the second oxide layer such that the thickness of the first oxide layer is less than the thickness of the second oxide layer. When the first oxide layer is removed, the second oxide layer is not completely removed. Thus, when the barrier layer is removed, the remaining second oxide layer can protect the sidewall of the first groove from damage, ensuring that the critical dimensions of the active region in the low-voltage device region are not affected, thereby ensuring good device performance.

[0053] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0054] 1. In the method for fabricating the semiconductor device described in this application, a substrate including a high-voltage device region and a low-voltage device region is first provided, along with a first trench located in the first low-voltage device region, a barrier layer, a first oxide layer, and a second oxide layer. The barrier layer is located on the high-voltage device region, the first oxide layer covers the surface of the barrier layer away from the high-voltage device region, and the second oxide layer covers the sidewall of the first trench. The thickness of the first oxide layer is less than the thickness of the second oxide layer. Then, the first oxide layer and a portion of the second oxide layer are removed. Finally, the remaining second oxide layer and the barrier layer are removed. By growing the first oxide layer and the second oxide layer such that the thickness of the first oxide layer is less than the thickness of the second oxide layer, the second oxide layer is not completely removed during the removal of the first oxide layer. Thus, during the removal of the barrier layer, the remaining second oxide layer protects the sidewall of the first trench from damage, ensuring that the critical dimensions of the active region in the low-voltage device region are not affected, thereby ensuring better device performance.

[0055] 2. The semiconductor device described above in this application is manufactured by any of the above-described semiconductor device manufacturing methods. The above method grows the first oxide layer and the second oxide layer, and makes the thickness of the first oxide layer less than the thickness of the second oxide layer. When the first oxide layer is removed, the second oxide layer is not completely removed. In this way, when the barrier layer is removed, the remaining second oxide layer can protect the sidewall of the first groove from damage, ensuring that the critical dimensions of the active region in the low-voltage device region are not affected, thereby ensuring good device performance.

[0056] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate, a first groove, a barrier layer, a first oxide layer, and a second oxide layer are provided. The substrate includes a high-voltage device region and a low-voltage device region. The low-voltage device region is located on one side of the high-voltage device region. The barrier layer is located on the high-voltage device region. The first groove is located in the low-voltage device region. The first oxide layer is located on the surface of the barrier layer away from the high-voltage device region. The second oxide layer covers the sidewall of the first groove, and the thickness of the first oxide layer is less than the thickness of the second oxide layer. Remove the first oxide layer and a portion of the second oxide layer to expose the barrier layer; After removing the barrier layer, remove the remaining second oxide layer.

2. The method according to claim 1, characterized in that, The system provides a substrate, a first trench, a barrier layer, a first oxide layer, and a second oxide layer, comprising: A pre-substrate is provided, the pre-substrate including the high-voltage device region and the low-voltage device region; A portion of the prepared substrate is removed to form a second groove in the low-voltage device region; A preliminary barrier layer is formed on the high-voltage device region; The exposed sidewalls of the second groove and the pre-reserved barrier layer are oxidized to form the second oxide layer and the first oxide layer, respectively. The remaining pre-reserved barrier layer forms the barrier layer, and the remaining second groove forms the first groove.

3. The method according to claim 2, characterized in that, Oxidation of the exposed sidewalls of the second groove and the pre-prepared barrier layer includes: The exposed sidewalls of the second groove and the preparatory barrier layer are oxidized using a furnace tube wet oxidation process.

4. The method according to claim 2, characterized in that, Removing a portion of the pre-substrate to form a second recess in the low-voltage device region includes: A portion of the pre-substrate is removed, a third groove is formed in the high-voltage device region, and a fourth groove is formed in the low-voltage device region; The third and fourth grooves are respectively filled with oxide material, and the filled fourth groove forms the second groove.

5. The method according to claim 4, characterized in that, Removing a portion of the pre-substrate, forming a third groove in the high-voltage device region, and forming a fourth groove in the low-voltage device region, including: A gate oxide layer and a dielectric layer are sequentially stacked on the prepared substrate; A portion of the gate oxide layer, a portion of the dielectric layer, and a portion of the pre-substrate are removed to form a third groove penetrating the gate oxide layer, the dielectric layer, and into the high-voltage device region, and a fourth groove penetrating the gate oxide layer, the dielectric layer, and into the low-voltage device region. The remaining gate oxide layer on the high-voltage device region forms a first gate oxide portion, and the remaining gate oxide layer on the low-voltage device region forms a second gate oxide portion.

6. The method according to claim 5, characterized in that, After removing the remaining second oxide layer, the method further includes: Remove the remaining dielectric layer and the second gate oxide portion.

7. The method according to any one of claims 1 to 6, characterized in that, There are multiple low-voltage device areas, and at least some of the low-voltage device areas correspond to devices with different voltages. There are multiple first grooves, and each first groove is located in a corresponding low-voltage device area.

8. The method according to any one of claims 1 to 6, characterized in that, The oxidation rate of the substrate material is greater than the oxidation rate of the barrier layer material.

9. The method according to claim 8, characterized in that, The substrate is made of silicon, and the barrier layer is made of polycrystalline silicon.

10. A semiconductor device, characterized in that, The semiconductor device is manufactured using the method described in any one of claims 1 to 9.

Images