A fan-out packaging device and a method for preparing the same

Abstract

The present application discloses a fan-out packaging device and a preparation method thereof, the fan-out packaging device comprising: a first chip, comprising a first functional surface and a first non-functional surface arranged opposite to each other, and a first pad is arranged on the first functional surface; a first rewiring layer is located on one side of the first functional surface and is electrically connected to the first pad; a second chip and a third chip arranged in the same layer are located on the side of the first rewiring layer away from the first chip; a through conductive hole is arranged inside the third chip, one end of the conductive hole is electrically connected to the first rewiring layer; a second rewiring layer is electrically connected to the second pad and the other end of the conductive hole. Through the above-mentioned fan-out packaging device, the present application can interconnect multiple non-singular chips and integrate them into a highly integrated package.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to a fan-out packaging device and a preparation method thereof. Background Art

[0002] With the rise of MCM (Multi Chip Module), packaging has gradually taken on the concept of integration. The essence of advanced packaging has shifted from the basic needs of chip protection, scale enlargement and electrical connection to the integration of chips in the package to achieve the purpose of modules, components or systematization.

[0003] In order to optimize the electrical performance between chips, the requirements for the integration of chips in the package are getting higher and higher. Unlike the traditional method that all chips need to be electrically connected through the substrate to achieve electrical connection between chips, more and more solutions are based on through-hole technology, using dielectric layers with through-holes or silicon through-holes in the chips themselves for stacking. Multiple chips are connected to the substrate only through the stacking surface. This method can better meet the modularization requirements of similar chip packaging, but it is difficult to integrate non-single interconnections between multiple chips into a highly integrated package. Summary of the invention

[0004] The main technical problem solved by the present application is to provide a fan-out packaging device and a preparation method thereof, which can realize high-integration packaging of multiple chips.

[0005] To solve the above technical problems, a technical solution adopted in the present application is: to provide a fan-out packaging device, comprising: a first chip, comprising a first functional surface and a first non-functional surface arranged opposite to each other, and a first solder pad is arranged on the first functional surface; a first rewiring layer, located on one side of the first functional surface, and electrically connected to the first solder pad; a second chip and a third chip arranged in the same layer, located on the side of the first rewiring layer away from the first chip; wherein the second chip comprises a second functional surface and a second non-functional surface arranged opposite to each other, a second solder pad is arranged on the second functional surface, and the second non-functional surface faces the first rewiring layer; in the direction from the first chip to the first rewiring layer, a through conductive hole is arranged inside the third chip, and one end of the conductive hole is electrically connected to the first rewiring layer; a second rewiring layer, located on the side of the second chip and the third chip away from the first chip, and the second rewiring layer is electrically connected to the second solder pad and the other end of the conductive hole.

[0006] Among them, the fan-out packaging device also includes: a first plastic encapsulation layer, covering at least the side of the first chip; a second plastic encapsulation layer, covering the side of the second chip and the third chip, and the second redistribution layer is located on the side of the second plastic encapsulation layer away from the first chip.

[0007] Among them, the surface of the first plastic packaging layer facing away from the first re-wiring layer is flush with the first non-functional surface; the fan-out packaging device also includes: an insulating layer, covering the first non-functional surface and the surface of the first plastic packaging layer facing away from the first re-wiring layer.

[0008] There is a gap between the third chip and the first redistribution layer, and the packaging device further includes: solder, which is located in the gap, and the conductive hole is electrically connected to the first redistribution layer through the solder; bottom filling glue, which covers the periphery of the solder and fills the gap.

[0009] To solve the above technical problems, another technical solution adopted in the present application is: providing a method for preparing a fan-out packaging device, comprising: forming a first rewiring layer on a first functional surface of a first chip, and the first rewiring layer is electrically connected to the first pad on the first functional surface; arranging a second chip and a third chip on the side of the first rewiring layer away from the first chip; wherein the second non-functional surface of the second chip faces the first rewiring layer; in the direction from the first chip to the first rewiring layer, a through conductive hole is arranged inside the third chip, and one end of the conductive hole is electrically connected to the first rewiring layer; forming a second rewiring layer on the side of the second chip and the third chip away from the first chip, and the second rewiring layer is electrically connected to the second pad on the second functional surface of the second chip, and to the other end of the conductive hole.

[0010] Among them, before the step of forming the first rewiring layer on the first functional surface of the first chip, it includes: setting the first chip on a carrier, with the first functional surface of the first chip facing the carrier; forming a first plastic packaging layer on the side and first non-functional surface of the first chip; removing the carrier.

[0011] Among them, the step of arranging the second chip and the third chip on the side of the first redistribution layer away from the first chip includes: fixing the second non-functional surface of the second chip to the first redistribution layer by using an adhesive layer; using solder to electrically connect one end of the conductive hole of the third chip to the first redistribution layer, and forming an underfill glue around the solder.

[0012] Among them, before the step of forming a second re-wiring layer on the side of the second chip and the third chip facing away from the first chip, the step includes: forming a second plastic encapsulation layer on the side of the first re-wiring layer where the second chip and the third chip are arranged, the second plastic encapsulation layer covering the second functional surface of the second chip and the other end of the conductive hole of the third chip; grinding the second plastic encapsulation layer on the side facing away from the first chip so that the second pad and the other end of the conductive hole of the third chip are exposed from the second plastic encapsulation layer.

[0013] After the step of forming a second rewiring layer on the side of the second chip and the third chip away from the first chip, the method further includes: forming solder balls on the side of the second rewiring layer away from the first chip.

[0014] Among them, after the step of forming solder balls on the side of the second re-wiring layer away from the first chip, it includes: grinding the first plastic packaging layer from the side of the first plastic packaging layer away from the first re-wiring layer so that the first plastic packaging layer is flush with the first non-functional surface; and setting an insulating layer on the flush first non-functional surface and one side of the first plastic packaging layer.

[0015] The beneficial effects of the present application are as follows: Different from the prior art, the fan-out packaging device and its preparation method proposed in the present application are provided by setting a first rewiring layer on one side of the functional surface of the first chip, and setting a second chip and a third chip in the same layer on the side of the first rewiring layer away from the first chip, wherein a conductive hole is provided inside the third chip. A second rewiring layer is provided on the side of the second chip and the third chip away from the first chip. The first rewiring layer is electrically connected to the pad on the functional surface of the first chip and one end of the conductive hole of the third chip, and the second wiring layer is electrically connected to the pad on the functional surface of the second chip and the other end of the conductive hole of the third chip. In the fan-out packaging device proposed in the present application, information transmission can be achieved between the first chip and the third chip through the first rewiring layer, information transmission can be achieved between the second chip and the third chip through the second rewiring layer, and information transmission can be achieved between the first chip and the second chip through the third chip, that is, the present application can interconnect multiple non-singular chips and integrate them into a highly integrated package. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0017] Figure 1 It is a structural schematic diagram of an implementation scheme of a fan-out packaging device of the present application;

[0018] Figure 2 It is a schematic flow chart of an implementation method of a method for preparing a fan-out packaging device of the present application;

[0019] Figure 3 is a flowchart corresponding to an implementation method before step S101;

[0020] Figure 4ais a cross-sectional structural schematic diagram of an implementation method corresponding to step S201;

[0021] Figure 4b is a cross-sectional structural schematic diagram of an implementation method corresponding to step S202;

[0022] Figure 4c is a cross-sectional structural schematic diagram of an implementation method corresponding to step S203;

[0023] Figure 5a is a cross-sectional structural schematic diagram of an implementation method corresponding to step S101;

[0024] Figure 6a is a cross-sectional structural schematic diagram of an implementation method corresponding to step S102;

[0025] Figure 7 It is a flowchart of an implementation method corresponding to step S103;

[0026] Figure 8a is a cross-sectional structural schematic diagram of an implementation method corresponding to step S401;

[0027] Figure 8b is a cross-sectional structural schematic diagram of an implementation method corresponding to step S402;

[0028] Figure 8c is a cross-sectional structural schematic diagram of an implementation method corresponding to step S103;

[0029] Figure 8d It is a schematic cross-sectional structural diagram of another implementation method corresponding to step S103. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0031] See also Figure 1 , Figure 1 : is a schematic diagram of the structure of an embodiment of a fan-out packaging device proposed in the present application. The fan-out packaging device provided in the present application includes:

[0032] The first chip 100 includes a first functional surface 1001 and a first non-functional surface 1002 which are arranged back to back, and a first pad 10 is arranged on the first functional surface 1001; optionally, the first pad 10 may protrude from the first functional surface 1001; or, the surface of the first pad 10 may also be flush with the first functional surface 1001.

[0033] The first rewiring layer 101 is located on one side of the first functional surface 1001 and is electrically connected to the first pad 10. Optionally, the first rewiring layer 101 includes a first dielectric layer and a patterned first metal layer; wherein the first dielectric layer is provided with a first via hole at a position corresponding to the first pad 10; and the first metal layer is located on the side of the first dielectric layer away from the first chip 100 and fills the first via hole. In addition, the number of layers of the first rewiring layer 101 may be one or more layers, which is not limited in the present application.

[0034] The second chip 200 and the third chip 300 are arranged in the same layer and are located on the side of the first rewiring layer 101 away from the first chip 100; wherein the second chip 200 includes a second functional surface 2001 and a second non-functional surface 2002 arranged opposite to each other, the second functional surface 2001 is provided with a second solder pad 20, and the second non-functional surface 2002 faces the first rewiring layer 101; in the direction from the first chip 100 to the first rewiring layer 101, a through conductive hole 30 is provided inside the third chip 300, and one end of the conductive hole 30 is electrically connected to the first rewiring layer 101.

[0035] The second rewiring layer 201 is located on the side of the second chip 200 and the third chip 300 away from the first chip 100, and the second rewiring layer 201 is electrically connected to the second pad 20 and the other end of the conductive hole 30. Optionally, the second rewiring layer 201 includes a second dielectric layer and a patterned second metal layer; wherein the second dielectric layer is provided with a second via at the position corresponding to the second pad 20 and the conductive hole 30 on the third chip 300; the second metal layer is located on the side of the second dielectric layer away from the first chip 100, and fills the second via. In addition, the number of layers of the second rewiring layer 201 can be one or more layers, which is not limited in this application.

[0036] In the above-mentioned design method, in the fan-out packaging device, information can be transmitted between the first chip 100 and the third chip 300 through the first redistribution layer 101, information can be transmitted between the second chip 200 and the third chip 300 through the second redistribution layer 201, and information can be transmitted between the first chip 100 and the second chip 200 through the third chip 300, that is, the present application can interconnect multiple non-single chips and integrate them into a highly integrated package.

[0037] In one embodiment, please refer to Figure 1, the fan-out packaging device provided by the present application also includes: a first plastic encapsulation layer 110, which at least covers the side of the first chip 100. The material of the first plastic encapsulation layer 110 can be epoxy resin, etc., which can play a certain protective role on the first chip 100. Optionally, in this embodiment, the first plastic encapsulation layer 110 can only cover the side of the first chip 100, and the surface of the first plastic encapsulation layer 110 facing away from the second chip can be flush with the first chip to improve the heat dissipation effect. On this basis, the fan-out packaging device provided by the present application can also include: an insulating layer 600, covering the first non-functional surface 1002 and the surface of the first plastic encapsulation layer 110 facing away from the first rewiring layer 101. The insulating layer 600 can improve the protection of the first chip 100 while ensuring the heat dissipation effect. Optionally, the material of the insulating layer 600 can be silicon dioxide or polyimide, etc.

[0038] In another embodiment, please continue to refer to Figure 1 The fan-out package device provided in the present application further includes: a second plastic encapsulation layer 120, covering the side of the second chip 200 and the third chip 300, and the second redistribution layer 201 is located on the side of the second plastic encapsulation layer 120 away from the first chip 100. The material of the second plastic encapsulation layer 120 can be epoxy resin, etc. The second plastic encapsulation layer 120 can play a certain role in protecting and limiting the second chip 200 and the third chip 300.

[0039] In another embodiment, there is a gap between the third chip 300 and the first redistribution layer 101, and the fan-out packaging device provided in the present application further includes: solder, which is located in the gap, and the conductive via 30 is electrically connected to the first redistribution layer 101 through the solder; and an underfill 500, which covers the periphery of the solder and fills the gap. The underfill 500 can play a certain role in limiting the position of the third chip 300.

[0040] See also Figure 2 , Figure 2 1 is a flow chart of an embodiment of a method for preparing a fan-out packaging device proposed in the present application, the method comprising:

[0041] S101: forming a first redistribution layer on a first functional surface of a first chip, wherein the first redistribution layer is electrically connected to a first pad on the first functional surface.

[0042] See also Figure 3 , Figure 3 for Figure 2 The process flow diagram before step S101 corresponds to an implementation method, and the process flow diagram before step S101 also includes:

[0043] S201: Dispose a first chip on a carrier, with a first functional surface of the first chip facing the carrier.

[0044] Specifically, see Figure 4a , Figure 4a yes Figure 3 A cross-sectional structural diagram of an embodiment corresponding to step S201 in FIG. Figure 4a It is just for illustration and for ease of understanding. Figure 4a Only one first chip 100 is drawn above, and the first chip 100 includes six pads. In actual applications, multiple first chips 100 can be arranged on the carrier 50 to be packaged into multiple highly integrated chips, and a single highly integrated chip can be obtained by cutting the middle part of two adjacent highly integrated chips; each first chip 100 can also include multiple first pads 10 to receive and / or transmit signals.

[0045] In one application, step S201 specifically includes: setting a first chip 100 on a carrier 50, the first chip 100 including a first functional surface 1001 and a first non-functional surface 1002 arranged opposite to each other, a plurality of first solder pads 10 are arranged on the first functional surface 1001, and the first functional surface 1001 of the first chip 100 faces the carrier 50.

[0046] Optionally, the first functional surface 1001 of the first chip 100 can be fixed to the carrier 50 by bonding glue, the first pad 10 is buried in the bonding glue, and the first pad 10 is separated from the carrier 50, so that the carrier 50 does not directly contact the first pad 10. The material of the carrier 50 can be one of silicon, glass, metal and organic composite materials, etc. The carrier 50 can play a certain protective role on one side of the first functional surface 1001 of the first chip 100, so that the first functional surface 1001 of the first chip 100 is not exposed. It is also possible to attach double-sided tape on the carrier 50 and stick at least one first chip 100 to the double-sided tape, in which case the first functional surface 1001 of the first chip 100 faces the carrier 50.

[0047] S202: forming a first plastic encapsulation layer on the side surface and the first non-functional surface of the first chip.

[0048] Specifically, see Figure 4b , Figure 4b yes Figure 3 Schematic diagram of a cross-sectional structure of an embodiment corresponding to step S202 in FIG. In one application mode, step S202 specifically includes: forming a first plastic encapsulation layer 110 on the side surface of the first chip 100 and the first non-functional surface 1002 to protect the side surface of the first chip 100 and the first non-functional surface 1002. The material of the first plastic encapsulation layer 110 can be epoxy resin, etc., which can be formed by a lamination process.

[0049] S203: removing the carrier board.

[0050] Specifically, see Figure 4c , Figure 4c yes Figure 3 In one application mode, step S203 specifically includes: separating the first functional surface 1001 of the first chip 100 from the carrier 50 to expose the first functional surface 1001 of the first chip 100 and the first pad 10 on the first functional surface 1001, so as to facilitate the implementation of step S101.

[0051] For further information, see Figure 5a , Figure 5a for Figure 2 A schematic cross-sectional structure diagram of an embodiment corresponding to step S101 in the above-mentioned step S101. The above-mentioned step S101 specifically includes: forming a first rewiring layer 101 on the first functional surface 1001 of the first chip 100, and the first rewiring layer 101 is electrically connected to the first pad 10 on the first functional surface 1001. Among them, a first mask layer 102 can also be formed on the surface of the first rewiring layer 101 to play a certain role in protecting the first rewiring layer 101, and the material of the first mask layer 102 can be at least one of photoresist, silicon oxide, silicon nitride, and amorphous carbon. Optionally, the above-mentioned first rewiring layer 101 includes a first dielectric layer and a patterned first metal layer; wherein the first dielectric layer is provided with a first via hole at a position corresponding to the first pad 10; the first metal layer is located on the side of the first dielectric layer away from the first chip 100, and fills the first via hole. In addition, the number of layers of the above-mentioned first rewiring layer 101 can be one or more layers, which is not limited in this application.

[0052] S102: Arrange a second chip and a third chip on a side of the first redistribution layer away from the first chip.

[0053] See also Figure 6a , Figure 6a for Figure 2 Step S102 corresponds to a schematic cross-sectional structure diagram of an embodiment. In an application mode, step S102 specifically includes: using an adhesive layer 130 to arrange the second chip 200 and the third chip 300 in the same layer on the side of the first rewiring layer 101 away from the first chip 100. Specifically, the second chip 200 includes a second functional surface 2001 and a second non-functional surface 2002 arranged opposite to each other, and the adhesive layer 130 can be formed on the second non-functional surface 2002 of the second chip 200, and the second non-functional surface 2002 of the second chip 200 is fixed to the first rewiring layer 101 by the adhesive layer 130, so as to limit the second chip 200.

[0054] The third chip 300 is provided with a plurality of through conductive holes 30, and the conductive holes are filled with solder, and the solder forms protrusions at both ends of the conductive holes 30. The solder is used to electrically connect one end of the conductive hole 30 of the third chip 300 with the first rewiring layer 101, and the third chip 300 can realize information exchange with the first chip 100 through the first rewiring layer 101. There is a gap between the third chip 300 and the first rewiring layer 101, and an underfill 500 is formed around the solder to cover the periphery of the solder and fill the gap. The underfill 500 can play a certain role in limiting the position of the third chip 300. Among them, before using the solder to electrically connect one end of the conductive hole 30 of the third chip 300 with the first rewiring layer 101, it includes using a dry etching process to remove the first mask layer 102 on the surface of the first rewiring layer 101, so that the conductive hole 30 is connected to the first rewiring layer 101 through the solder. Optionally, the third chip 300 is not limited to TSV (Through Silicon Via), TGV (Through Glass Via), TMV (Through Epoxy Via).

[0055] S103: forming a second redistribution layer on the side of the second chip and the third chip facing away from the first chip, and the second redistribution layer is electrically connected to the second pad on the second functional surface of the second chip and to the other end of the conductive via.

[0056] Specifically, see Figure 7 , Figure 7 for Figure 2 The flowchart of an implementation method corresponding to step S103 in the embodiment, before step S103, further includes:

[0057] S401: forming a second plastic packaging layer on a side of the first redistribution layer where the second chip and the third chip are arranged.

[0058] See also Figure 8a , Figure 8a for Figure 7 A schematic cross-sectional structure diagram of an embodiment corresponding to step S401 in FIG. In one application mode, step S401 specifically includes: forming a second plastic encapsulation layer 120 on the side where the second chip 200 and the third chip 300 are arranged on the first redistribution layer 101, and the second plastic encapsulation layer 120 covers the second functional surface 2001 of the second chip 200 and the other end of the conductive hole of the third chip 300, which can play a certain role in protecting and limiting the second chip 200 and the third chip 300. Among them, the material of the second plastic encapsulation layer 120 can be epoxy resin, etc., which can be formed by a lamination process.

[0059] S402: Grinding the second plastic packaging layer on a side facing away from the first chip so that the second pad and the other end of the conductive via of the third chip are exposed from the second plastic packaging layer.

[0060] See also Figure 8b , Figure 8b for Figure 7 In one application, step S402 specifically includes: grinding the second plastic encapsulation layer 120 away from the first chip 100 to expose the second pad 20 on the second functional surface 2001 of the second chip 200 and the other end of the conductive hole 30 of the third chip 300.

[0061] For further information, see Figure 8c , Figure 8c for Figure 2 Step S103 corresponds to a schematic cross-sectional structure diagram of an embodiment. In one application mode, step S103 specifically includes: forming a second rewiring layer 201 on the side of the second chip 200 and the third chip 300 away from the first chip 100, and the second rewiring layer 201 is electrically connected to the second pad 20 on the second functional surface 2001 of the second chip 200 exposed in the above step S402, and is electrically connected to the other end of the conductive hole 30 of the third chip 300, and the second chip 200 and the third chip 300 can realize information exchange through the second rewiring layer. Among them, a second mask layer 202 can also be formed on the surface of the second rewiring layer 201 to protect the second rewiring layer 201, and the material of the second mask layer 202 can be at least one of photoresist, silicon oxide, silicon nitride, and amorphous carbon. Optionally, the second rewiring layer 201 includes a second dielectric layer and a patterned second metal layer; wherein the second dielectric layer is provided with a second via hole at a position corresponding to the second pad 20 and the conductive hole 30 on the third chip 300; the second metal layer is located on a side of the second dielectric layer away from the first chip 100, and fills the second via hole. In addition, the number of layers of the second rewiring layer 201 may be one or more layers, which is not limited in the present application.

[0062] For further information, see Figure 8d , Figure 8d for Figure 2 In one application, solder balls 70 may be formed on the side of the second redistribution layer 201 away from the first chip 100, and the solder balls 70 may be electrically connected to any substrate (not shown) to enable the chip signal to interact with the substrate.

[0063] For further information, see Figure 1After forming the solder ball 70 on the side of the second rewiring layer 201 away from the first chip 100, the first plastic encapsulation layer 110 is ground from the side of the first plastic encapsulation layer 110 away from the first rewiring layer 101, so that the first plastic encapsulation layer 110 is flush with the first non-functional surface 1002 of the first chip 100, and an insulating layer 600 is arranged on the side of the flush first non-functional surface 1002 and the first plastic encapsulation layer 110, and the insulating layer 600 covers the first non-functional surface 1002 and the surface of the first plastic encapsulation layer 110 away from the first rewiring layer 101. Grinding the first plastic encapsulation layer 110 can reduce the overall thickness of the chip after packaging and improve the heat dissipation effect. Among them, the material of the insulating layer 600 can be silicon dioxide or polyimide, etc. The insulating layer 600 can isolate the semiconductor material on the first non-functional surface 1002 of the first chip 100 from other electrical components while ensuring the heat dissipation effect, so as to improve the stability and safety of the first chip 100.

[0064] Optionally, the first plastic encapsulation layer 110 can be appropriately ground from the side of the first plastic encapsulation layer 110 away from the first redistribution layer 101 without exposing the first non-functional surface 1002 of the first chip 100. This method reduces the overall thickness of the chip after packaging and does not require an additional insulating layer. The first plastic encapsulation layer isolates the semiconductor material on the first non-functional surface 1002 of the first chip 100 from other electrical components to improve the stability and safety of the first chip 100.

[0065] The fan-out packaging device preparation method proposed in the present application is to arrange a first rewiring layer 101 on one side of the first functional surface 1001 of the first chip 100, and arrange a second chip 200 and a third chip 300 in the same layer on the side of the first rewiring layer 101 away from the first chip 100, wherein a plurality of conductive holes 30 are arranged inside the third chip 300. The second rewiring layer 201 is arranged on the side of the second chip 200 and the third chip 300 away from the first chip 100. The first rewiring layer 101 is electrically connected to the first pad 10 on the first functional surface 1001 of the first chip 100 and one end of the conductive hole 30 of the third chip 300, and the second rewiring layer 201 is electrically connected to the second pad 20 on the second functional surface 2001 of the second chip 200 and the other end of the conductive hole 30 of the third chip 300. That is, information can be transmitted between the first chip 100 and the third chip 300 through the first redistribution layer 101, information can be transmitted between the second chip 200 and the third chip 300 through the second redistribution layer 201, and information can be transmitted between the first chip 100 and the second chip 200 through the third chip 300. That is, the fan-out device preparation method proposed in the present application can interconnect multiple non-single chips and integrate them into a highly integrated package.

[0066] Optionally, the preparation method of the fan-out packaging device proposed in the present application is not limited to the packaging of only the first chip, the second chip and the third chip. According to actual conditions, the first chip structure mentioned in the present application may also be composed of multiple first chips arranged in the same layer, and the first redistribution layer is electrically connected to the pads on all the functional surfaces of the first chips to realize information interaction between all the first chips; the second chip structure may also be composed of multiple second chips arranged in the same layer, and the second redistribution layer is electrically connected to the pads on all the functional surfaces of the second chips to realize information interaction between all the second chips.

[0067] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A fan-out packaging device, characterized in that: include: A first chip comprises a first functional surface and a first non-functional surface which are arranged opposite to each other, and a first pad is arranged on the first functional surface; A first redistribution layer, located on one side of the first functional surface and electrically connected to the first pad; The second chip and the third chip are arranged in the same layer and are located on the side of the first rewiring layer away from the first chip; wherein the second chip comprises a second functional surface and a second non-functional surface arranged opposite to each other, a second pad is arranged on the second functional surface, and the second non-functional surface faces the first rewiring layer; in the direction from the first chip to the first rewiring layer, a through conductive hole is arranged inside the third chip, and one end of the conductive hole is electrically connected to the first rewiring layer; The second rewiring layer is located on the side of the second chip and the third chip away from the first chip, and the second rewiring layer is electrically connected to the second pad and the other end of the conductive hole; wherein, information is transmitted between the first chip and the third chip through the first rewiring layer, information is transmitted between the second chip and the third chip through the second rewiring layer, and information is transmitted between the first chip and the second chip through the third chip.

2. The fan-out package device according to claim 1, characterized in that: Also includes: a first plastic packaging layer, covering at least a side surface of the first chip; The second plastic encapsulation layer covers the side surfaces of the second chip and the third chip, and the second redistribution layer is located on a side of the second plastic encapsulation layer away from the first chip.

3. The fan-out package device according to claim 2, characterized in that: The surface of the first plastic encapsulation layer facing away from the first redistribution layer is flush with the first non-functional surface; the fan-out packaging device further includes: An insulating layer covers the first non-functional surface and a surface of the first plastic packaging layer on a side away from the first redistribution layer.

4. The fan-out package device according to claim 1, characterized in that: There is a gap between the third chip and the first redistribution layer, and the fan-out packaging device further includes: Solder is located in the gap, and the conductive hole is electrically connected to the first redistribution layer through the solder; The bottom filler covers the periphery of the solder and fills the gap.

5. A method for preparing a fan-out packaging device, characterized in that: include: forming a first redistribution layer on the first functional surface of the first chip, wherein the first redistribution layer is electrically connected to the first pad on the first functional surface; A second chip and a third chip are arranged on the side of the first rewiring layer away from the first chip; wherein the second non-functional surface of the second chip faces the first rewiring layer; a through conductive hole is arranged inside the third chip in the direction from the first chip to the first rewiring layer, and one end of the conductive hole is electrically connected to the first rewiring layer; A second rewiring layer is formed on the side of the second chip and the third chip facing away from the first chip, and the second rewiring layer is electrically connected to the second pad on the second functional surface of the second chip and to the other end of the conductive hole, so that information is transferred between the first chip and the third chip through the first rewiring layer, information is transferred between the second chip and the third chip through the second rewiring layer, and information is transferred between the first chip and the second chip through the third chip.

6. The method for preparing a fan-out package device according to claim 5, characterized in that: include: Before the step of forming a first redistribution layer on the first functional surface of the first chip, the step includes: Disposing the first chip on a carrier board, with the first functional surface of the first chip facing the carrier board; forming a first plastic encapsulation layer on the side surface and the first non-functional surface of the first chip; The carrier plate is removed.

7. The method for preparing a fan-out package device according to claim 5, characterized in that: include: The step of arranging the second chip and the third chip on the side of the first rewiring layer away from the first chip comprises: fixing the second non-functional surface of the second chip to the first redistribution layer by using an adhesive layer; Solder is used to electrically connect one end of the conductive hole of the third chip to the first redistribution layer, and an underfill is formed around the solder.

8. The method for preparing a fan-out package device according to claim 5, characterized in that: include: Before the step of forming a second rewiring layer on the second chip and the third chip facing away from the first chip, the method includes: A second plastic encapsulation layer is formed on one side of the first redistribution layer where the second chip and the third chip are arranged, wherein the second plastic encapsulation layer covers the second functional surface of the second chip and the other end of the conductive hole of the third chip; The second plastic packaging layer is ground on a side facing away from the first chip, so that the second pad and the other end of the conductive hole of the third chip are exposed from the second plastic packaging layer.

9. The method for preparing a fan-out package device according to claim 5, characterized in that: include: After the step of forming a second rewiring layer on the second chip and the third chip facing away from the first chip, the method further comprises: Solder balls are formed on a side of the second redistribution layer facing away from the first chip.

10. The method for preparing a fan-out package device according to claim 9, characterized in that: include: After the step of forming solder balls on the side of the second redistribution layer facing away from the first chip, the method includes: Grinding the first plastic encapsulation layer from a side of the first plastic encapsulation layer away from the first redistribution layer so that the first plastic encapsulation layer is flush with the first non-functional surface; An insulating layer is disposed on the flush first non-functional surface and one side of the first plastic packaging layer.

Images