A memory and a method for preparing the same

Abstract

An embodiment of the present invention provides a memory and a method for preparing the memory, wherein the memory includes: a first semiconductor structure, the first semiconductor structure includes at least a three-dimensional NAND array and an array access circuit, the array access circuit includes at least a word line driver and a page buffer; a second semiconductor structure, the second semiconductor structure includes at least a peripheral circuit; a circuit board, the circuit board includes at least a first connection contact and a second connection contact that are electrically connected; wherein the first semiconductor structure is fixed to the first connection contact of the circuit board, and the second semiconductor structure is fixed to the second connection contact of the circuit board.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a memory and a preparation method thereof. Background Art

[0002] Memory, such as three-dimensional NAND memory, is a non-volatile memory whose unique cell and array structure provides small cell size, high density, low write current, and high data throughput.

[0003] However, in traditional technology, three-dimensional NAND memory still faces many challenges. Summary of the invention

[0004] In view of this, an embodiment of the present invention provides a memory and a method for manufacturing the same in order to solve at least one problem existing in the background technology.

[0005] To achieve the above object, the technical solution of the present invention is achieved as follows:

[0006] An embodiment of the present invention provides a memory, comprising: a first semiconductor structure, the first semiconductor structure at least comprising a three-dimensional NAND array and an array access circuit, the array access circuit at least comprising a word line driver and a page buffer; a second semiconductor structure, the second semiconductor structure at least comprising a peripheral circuit; a circuit board, the circuit board at least comprising a first connection contact and a second connection contact electrically connected; wherein the first semiconductor structure is fixed to the first connection contact of the circuit board, and the second semiconductor structure is fixed to the second connection contact of the circuit board.

[0007] In the above solution, the first semiconductor structure includes a first chip and a second chip that are stacked and bonded; wherein the page buffer is located in the first chip, and the three-dimensional NAND array and the word line driver are located in the second chip.

[0008] In the above solution, the first semiconductor structure also includes a first conductive contact, which is located on a side of the first chip away from the second chip; wherein the first conductive contact of the first semiconductor structure is correspondingly connected to the first connection contact of the circuit board.

[0009] In the above solution, the first chip includes: a first substrate; the page buffer located on the first substrate; and a first bonding layer located on the page buffer;

[0010] The second chip includes: a second substrate, the word line driver located on the second substrate; the three-dimensional NAND array located on the word line driver; and a second bonding layer located on the three-dimensional NAND array;

[0011] The first chip and the second chip are bonded and connected via the first bonding layer and the second bonding layer.

[0012] In the above scheme, the second substrate includes a first side and a second side arranged opposite to each other in a first direction; the word line driver includes a first sub-driver arranged on the first side and a second sub-driver arranged on the second side; the three-dimensional NAND array includes a plurality of first word lines and a plurality of second word lines; wherein the first sub-driver is located below the plurality of first word lines and connected to the plurality of first word lines, and the second sub-driver is located below the plurality of second word lines and connected to the plurality of second word lines.

[0013] In the above scheme, the word line driver also includes a third sub-driver arranged on the first side and a fourth sub-driver arranged on the second side; the third sub-driver is located below the multiple second word lines and connected to the multiple second word lines, and the fourth sub-driver is located below the multiple first word lines and connected to the multiple first word lines.

[0014] In the above scheme, the first substrate includes a third side and a fourth side arranged opposite to each other in the second direction; the page buffer includes a first sub-buffer arranged on the third side and a second sub-buffer arranged on the fourth side; the three-dimensional NAND array includes a plurality of first bit lines and a plurality of second bit lines extending along the second direction; wherein the first sub-buffer is located above the plurality of first bit lines and connected to the plurality of first bit lines, and the second sub-buffer is located above the plurality of second bit lines and connected to the plurality of second bit lines.

[0015] In the above scheme, the first substrate includes a third side and a fourth side arranged opposite to each other in the second direction; the page buffer includes a first sub-buffer and a second sub-buffer arranged at a middle position between the third side and the fourth side; the three-dimensional NAND array includes a plurality of first bit lines and a plurality of second bit lines extending along the second direction; wherein the first sub-buffer is located above the plurality of first bit lines and connected to the plurality of first bit lines, and the second sub-buffer is located above the plurality of second bit lines and connected to the plurality of second bit lines.

[0016] In the above scheme, the second semiconductor structure includes a third substrate, the peripheral circuit located on the third substrate, and a second conductive contact located on the peripheral circuit; wherein the second conductive contact of the second semiconductor structure is correspondingly connected to the second connection contact of the circuit board.

[0017] An embodiment of the present invention further provides a method for manufacturing a memory, the method comprising: forming a first semiconductor structure, the first semiconductor structure comprising at least a three-dimensional NAND array and an array access circuit, the array access circuit comprising at least a word line driver and a page buffer;

[0018] forming a second semiconductor structure, the second semiconductor structure comprising at least a peripheral circuit;

[0019] The first semiconductor structure and the second semiconductor structure are fixed to a circuit board respectively; wherein the circuit board comprises at least a first connecting contact and a second connecting contact which are electrically connected, the first semiconductor structure is fixed to the first connecting contact of the circuit board, and the second semiconductor structure is fixed to the second connecting contact of the circuit board.

[0020] In the above solution, the first semiconductor structure includes a first chip, a second chip and a first conductive contact; forming the first semiconductor structure includes:

[0021] forming the first chip, wherein the first chip includes the page buffer;

[0022] forming the second chip, wherein the second chip includes a three-dimensional NAND array and the word line driver;

[0023] Stacking and bonding the second chip to the first chip;

[0024] The first conductive contact is formed on a surface of the first chip away from the second chip, and the first conductive contact is used to be connected to the first connection contact on the circuit board accordingly.

[0025] In the above solution, forming the first chip includes: providing a first substrate; forming a page buffer on the first substrate; forming a first bonding layer on the page buffer;

[0026] Forming the second chip includes: providing a second substrate; forming a word line driver on the second substrate; forming a three-dimensional NAND array on the word line driver; forming a second bonding layer on the three-dimensional NAND array;

[0027] The stacking and bonding of the second chip and the first chip includes: bonding a second bonding layer of the second chip and a first bonding layer of the first chip.

[0028] In the above solution, forming the second semiconductor structure includes:

[0029] providing a third substrate;

[0030] forming a peripheral circuit on the third substrate;

[0031] A second conductive contact is formed on the peripheral circuit, and the second conductive contact is used to be connected to the second connection contact on the circuit board accordingly.

[0032] The memory and the manufacturing method thereof provided by the embodiment of the present invention, wherein the memory comprises: a first semiconductor structure, the first semiconductor structure at least comprises a three-dimensional NAND array and an array access circuit, the array access circuit at least comprises a word line driver and a page buffer; a second semiconductor structure, the second semiconductor structure at least comprises a peripheral circuit; a circuit board, the circuit board at least comprises a first connection contact and a second connection contact electrically connected; wherein the first semiconductor structure is fixed on the first connection contact of the circuit board, and the second semiconductor structure is fixed on the second connection contact of the circuit board. The memory provided by the embodiment of the present invention integrates the three-dimensional NAND array and the array access circuit in the first semiconductor structure, integrates the peripheral circuit in the second semiconductor structure, and connects the first semiconductor structure and the second semiconductor structure through the circuit board. Compared with the prior art in which a three-dimensional NAND array, an array access circuit, and a peripheral circuit are integrated into one semiconductor structure, the embodiments of the present invention have at least the following advantages: First, the first semiconductor structure and the second semiconductor structure are formed on different wafers, and after formation, yield tests are performed separately, and only the first semiconductor structure and the second semiconductor structure that have passed the test are connected to the circuit board, so that the yield of the entire memory can be improved; Second, the first semiconductor structure and the second semiconductor structure have smaller sizes than the semiconductor structures in the prior art. During preparation, the same number of wafers can be used to prepare more memories, that is, the device yield of a single wafer can be improved, and the production cost of the memory can be reduced.

[0033] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A schematic diagram of the structure of a memory provided by an embodiment of the present invention;

[0035] Figure 2 A schematic diagram of a partial layout of a first semiconductor structure provided by an embodiment of the present invention;

[0036] Figure 3 A schematic diagram of a partial layout of a second semiconductor structure provided by an embodiment of the present invention;

[0037] Figure 4 A schematic cross-sectional structure diagram of a memory provided by an embodiment of the present invention;

[0038] Figures 5 to 7 Schematic diagram of the composition of the first semiconductor structure provided by different embodiments of the present invention.

[0039] Figure 8 A flowchart of a method for preparing a memory provided by an embodiment of the present invention;

[0040] Figures 9 to 16 A process flow chart of a method for preparing a memory provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0041] The exemplary embodiments disclosed in the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0042] In the following description, a large number of specific details are given to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0043] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0044] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present invention necessarily has the first element, component, region, layer or part.

[0045] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0046] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0047] In the related art, a three-dimensional NAND array, array access circuit and peripheral circuit in a three-dimensional NAND memory are usually integrated into a semiconductor structure. The semiconductor structure includes a substrate, and the NAND array, array storage circuit and peripheral circuit are arranged in different areas of the substrate.

[0048] However, the array efficiency of the three-dimensional NAND memory in the above-mentioned related art is low and the bit cost is high.

[0049] Based on this, an embodiment of the present invention provides a memory, including:

[0050] A first semiconductor structure, the first semiconductor structure at least comprising a three-dimensional NAND array and an array access circuit, the array access circuit at least comprising a word line driver and a page buffer;

[0051] a second semiconductor structure, the second semiconductor structure comprising at least a peripheral circuit;

[0052] A circuit board, the circuit board at least comprising a first connection contact and a second connection contact which are electrically connected; wherein the first semiconductor structure is fixed on the first connection contact of the circuit board, and the second semiconductor structure is fixed on the second connection contact of the circuit board.

[0053] The memory provided by the embodiment of the present invention integrates a three-dimensional NAND array and an array access circuit into a first semiconductor structure, integrates a peripheral circuit into a second semiconductor structure, and connects the first semiconductor structure and the second semiconductor structure through a circuit board. Compared with the prior art in which a three-dimensional NAND array, an array access circuit, and a peripheral circuit are integrated into one semiconductor structure, the embodiment of the present invention has at least the following advantages: First, the first semiconductor structure and the second semiconductor structure are formed on different wafers, and after formation, yield detection is performed separately, and only the first semiconductor structure and the second semiconductor structure that pass the detection are connected to the circuit board, so that the yield of the entire memory can be improved; Second, the first semiconductor structure and the second semiconductor structure have smaller sizes than the semiconductor structures in the prior art. During preparation, the same number of wafers can be used to prepare more memories, that is, the device yield of a single wafer can be improved, and the production cost of the memory can be reduced.

[0054] In order to make the above-mentioned purposes, features and advantages of the present invention more clearly understood, the specific implementation methods of the present invention are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present invention in detail, for the convenience of explanation, the schematic diagrams will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention.

[0055] Figure 1 A schematic diagram of the structure of a memory provided by an embodiment of the present invention, Figure 2 A schematic diagram of a partial layout of a first semiconductor structure provided in an embodiment of the present invention, Figure 3 A schematic diagram of a partial layout of a second semiconductor structure provided in an embodiment of the present invention, Figure 4 A schematic cross-sectional structure diagram of a memory provided in an embodiment of the present invention.

[0056] like Figure 1 As shown, the memory comprises: a first semiconductor structure 10, the first semiconductor structure 10 comprises at least a three-dimensional NAND array 121 and an array access circuit AC1, the array access AC1 comprises at least a word line driver 122 and a page buffer 112;

[0057] A second semiconductor structure 20, wherein the second semiconductor structure 20 at least includes a peripheral circuit 21;

[0058] The circuit board 30 includes at least a first connection contact 31 and a second connection contact 32 which are electrically connected; wherein the first semiconductor structure 10 is fixed on the first connection contact 31 of the circuit board 30, and the second semiconductor structure 20 is fixed on the second connection contact 32 of the circuit board 30.

[0059] Next, combine Figures 2 to 4 The first and second semiconductor structures of the memory are further described in detail. It should be noted that: Figures 2 to 4 The first semiconductor structure and the second semiconductor structure shown are only used as examples and are not used to limit the first and second semiconductor structures of the memory in the embodiment of the present invention.

[0060] like Figure 2 As shown, in one embodiment, the first semiconductor structure 10 includes a first chip 11 and a second chip 12 that are stacked and bonded; wherein the page buffer 112 is located in the first chip 11, and the three-dimensional NAND array 121 and the word line driver 122 are located in the second chip 12.

[0061] Specifically, the first chip 11 includes: a first substrate 110; the page buffer 112 located on the first substrate 110; and a first bonding layer 114 located on the page buffer 112;

[0062] The second chip 12 includes: a second substrate 120, the word line driver 122 located on the second substrate 120; the three-dimensional NAND array 121 located on the word line driver 122; and a second bonding layer 124 located on the three-dimensional NAND array 121;

[0063] The first chip 11 and the second chip 12 are bonded and connected via the first bonding layer 114 and the second bonding layer 124 .

[0064] The first bonding layer 114 includes a plurality of first bonding contacts 115 , and the second bonding layer 124 includes a plurality of second bonding contacts 125 . The plurality of first bonding contacts 115 and the second bonding contacts 125 are connected to each other correspondingly.

[0065] Here, the three-dimensional NAND array 121 includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells for storing data. The word line driver 122 is connected to the plurality of word lines WL, and the page buffer 112 is connected to the plurality of bit lines BL.

[0066] In one embodiment, the array storage circuit AC1 further includes a first control circuit 113 and a second control circuit 123, wherein the first control circuit 113 is located in the first chip 11, and the second control circuit 123 is located in the second chip 12. The first control circuit 113 may include but is not limited to analog circuits and logic circuits, and the second control circuit 123 may include but is not limited to drive circuits, read-write circuits, state machines, logic circuits, etc.

[0067] Continue to see Figure 2 The first semiconductor structure 10 also includes a first conductive contact 111, which is located on a side of the first chip 11 away from the second chip 12; wherein the first conductive contact 111 of the first semiconductor structure 10 is correspondingly connected to the first connection contact 31 of the circuit board 30.

[0068] In some embodiments, the first conductive contact 111 is disposed on a side of the first substrate 110 away from the page buffer 112, and a hydrogen barrier layer 116 and a first dielectric layer 117 are sequentially disposed between the first substrate 110 and the first conductive contact 111, wherein the hydrogen barrier layer 116 is used to prevent hydrogen from being discharged from the area where the page buffer 112 is located toward the direction where the first conductive contact 111 is located. The material of the hydrogen barrier layer 116 includes but is not limited to silicon nitride, aluminum oxide, etc.; the material of the first dielectric layer 117 includes but is not limited to oxide, nitride, oxynitride, etc.

[0069] In practical applications, a conductive connection column 118 is provided in the first substrate 110, the hydrogen barrier layer 116 and the first dielectric layer 117, and the conductive connection column 118 is used to form an electrical connection between the first semiconductor structure 10 and the first conductive contact 111. It can be understood that the hydrogen barrier layer 116 is also provided between the conductive connection column 118 and the first substrate 110 and the first dielectric layer 117, and the function of the hydrogen barrier layer 116 is the same as that described in the previous paragraph, which will not be described in detail here.

[0070] In the embodiment of the present invention, a page buffer and a first control circuit are formed in the first chip, a word line driver, a second control circuit and a three-dimensional NAND array are formed in the second chip, and then the first chip and the second chip are bonded to form a first semiconductor structure arranged vertically, which is beneficial to reducing the substrate occupied area of ​​the first semiconductor structure and improving the array efficiency of the memory. In addition, the vertical interconnection method effectively shortens the communication distance between the first chip and the second chip, and improves the communication efficiency of the memory.

[0071] like Figure 3As shown, the second semiconductor structure 20 includes a third substrate 210, the peripheral circuit 21 located on the third substrate, and a second conductive contact 211 located on the peripheral circuit 21; wherein the second conductive contact 211 of the second semiconductor structure 20 is correspondingly connected to the second connection contact 32 of the circuit board 30.

[0072] The peripheral circuit 21 may include, but is not limited to, a voltage generator, a current generator, a fuse protection circuit, an analog circuit, a control logic circuit, and an input / output (I / O) circuit. Preferably, the peripheral circuit 21 includes an analog circuit, a voltage generator, a control logic circuit, and an I / O circuit. The voltage generator may generate various types of word line voltages for each of the address lines to be supplied based on the control of the control logic circuit, and the voltage may be applied to the selected word line through a word line driver.

[0073] like Figure 4 As shown, the first conductive contact 111 of the first semiconductor structure 10 is electrically connected to the first connection contact 31 of the circuit board 30 , and the second conductive contact 211 of the second semiconductor structure 20 is electrically connected to the second connection contact 32 of the circuit board 30 .

[0074] In the actual process, the circuit board 30 may further include a third connection contact 33, and the third connection contact 33 is located on the opposite side to the first connection contact 31 and the second connection contact 32. It can be understood that the third connection contact 33 can be contact-connected with a printed circuit board (PCB board).

[0075] It is understandable that the circuit board 30 may be a circuit board with a wiring circuit, or may be a substrate formed of silicon (e.g., single crystal silicon), ceramic, glass, or any other suitable material. The material of the first connection contact 111, the second connection contact 211, and the third connection contact 33 includes a conductive material, and the conductive material includes but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof.

[0076] In the memory provided by the embodiment of the present invention, the first semiconductor structure and the second semiconductor structure are attached to the circuit board after being formed separately. Before being attached, the first semiconductor structure and the second semiconductor structure are selected for electrical characteristics, which can improve the yield of the entire memory. In addition, the first semiconductor structure and the second semiconductor structure are manufactured separately, and compared with the prior art, the same number of wafers can produce more memories, that is, the device yield of a single wafer can be improved, and the production cost of the memory can be reduced.

[0077] Figures 5 to 7Schematic diagram of the composition of the first semiconductor structure provided by different embodiments of the present invention.

[0078] like Figure 5 As shown, the first semiconductor structure 10 is formed by stacking and bonding a first chip 11 and a second chip 12. The second chip 12 includes a second substrate 120, and the second substrate 120 includes a first side S1 and a second side S2 arranged opposite to each other in a first direction; the word line driver 122 includes a first sub-driver 1221 arranged on the first side S1 and a second sub-driver 1222 arranged on the second side S2; the three-dimensional NAND array 121 includes a plurality of first word lines WL1 and a plurality of second word lines WL2; wherein the first sub-driver 1221 is located below the plurality of first word lines WL1 and connected to the plurality of first word lines WL1, and the second sub-driver 1221 is located below the plurality of second word lines WL2 and connected to the plurality of second word lines WL2.

[0079] The first chip 11 includes a first substrate 110, and the first substrate 110 includes a third side S3 and a fourth side S4 arranged opposite to each other in the second direction; the page buffer 112 includes a first sub-buffer 1121 arranged on the third side and a second sub-buffer 1122 arranged on the fourth side; the three-dimensional NAND array 121 includes a plurality of first bit lines BL1 and a plurality of second bit lines BL2 extending along the second direction; wherein the first sub-buffer 1121 is located above the plurality of first bit lines BL1 and connected to the plurality of first bit lines BL1, and the second sub-buffer 1122 is located above the plurality of second bit lines BL2 and connected to the plurality of second bit lines BL2.

[0080] In this embodiment, the word line driver 122 includes a first sub-driver 1221 and a second sub-driver 1221, and the first sub-driver 1221 and the second sub-driver 1221 are respectively connected to multiple first word lines WL1 and multiple second word lines WL2; the page buffer 112 includes a first sub-buffer 1121 and a second sub-buffer 1122, and the first sub-buffer 1121 and the second sub-buffer 1122 are respectively connected to multiple first bit lines BL1 and multiple second bit lines BL2.

[0081] It should be noted that the first bit line BL1 and the second bit line BL2 are formed on the second chip 12. Figures 5 to 7 It is drawn on the first chip 11 in order to accurately show the positional relationship between the first bit line BL1 , the second bit line BL2 and the page buffer 112 .

[0082] In another embodiment, Figure 6As shown, the word line driver 122 further includes a third sub-driver 1223 disposed on the first side S1 and a fourth sub-driver 1224 disposed on the second side S2; the third sub-driver 1223 is located below the plurality of second word lines WL2 and connected to the plurality of second word lines WL2, and the fourth sub-driver 1224 is located below the plurality of first word lines WL1 and connected to the plurality of first word lines WL1. In this embodiment, the positional relationship between the first sub-driver 1221, the second sub-driver 1222 and the first word lines WL1 and the second word lines WL2, and the positional relationship between the first sub-buffer 1121, the second sub-buffer 1122 and the first bit lines BL1 and the second bit lines BL2 are the same as those in the previous embodiment ( Figure 5 ) are the same and will not be repeated here.

[0083] In this embodiment, each word line is connected to two sub-drivers at the same time, and when performing an access operation, the access time of the word line can be effectively reduced by half.

[0084] In yet another embodiment, Figure 7 As shown, the first chip 11 includes a first substrate 110, and the first substrate 110 includes a third side S3 and a fourth side S4 arranged opposite to each other in the second direction; the page buffer 112 includes a first sub-buffer 1121 and a second sub-buffer 1122 arranged at a middle position between the third side S3 and the fourth side S4; the three-dimensional NAND array 121 includes a plurality of first bit lines BL1 and a plurality of second bit lines BL2 extending along the second direction; wherein the first sub-buffer 1121 is located above the plurality of first bit lines BL1 and connected to the plurality of first bit lines BL1, and the second sub-buffer 1122 is located above the plurality of second bit lines BL2 and connected to the plurality of second bit lines BL2. In this embodiment, the positional relationship between the word line driver 122 and the first word line WL1 and the second word line WL2 in the second chip 12 can be the same as that in the previous embodiment ( Figure 6 ), but not limited thereto, the positional relationship between the word line driver 122 in the second chip 12 and the first word line WL1 and the second word line WL2 may also be the same as Figure 5 The corresponding embodiments are the same and will not be described again here.

[0085] In this embodiment, since the page buffer 112 is located at the middle position of the first chip, the page buffer 112 can be connected to the middle position of the bit line BL, which can effectively improve the delay phenomenon of the bit line BL.

[0086] In the actual process, a first wafer having a plurality of first chips can be formed on one wafer and a second wafer having a plurality of second chips can be formed on another wafer, and then the first wafer and the second wafer can be bonded and then divided to form a first semiconductor structure. Subsequently, an electrical characteristic sorting test is performed on the first semiconductor structure to select a first semiconductor structure with good performance to wait for fixed connection with a circuit board. It can be understood that a similar method can be used to form a second semiconductor structure, that is, a third wafer having a plurality of peripheral circuit structures is formed on other wafers, and then the third wafer is divided into a plurality of peripheral circuit chips to form a second semiconductor structure. Subsequently, an electrical characteristic sorting test is performed on the second semiconductor structure to select a second semiconductor structure with good performance to wait for fixed connection with a circuit board. The above-mentioned method of forming the first semiconductor structure and the second semiconductor structure can improve the yield of the memory finally formed and reduce the production cost.

[0087] It should be noted that in Figure 5 , Figure 6 and Figure 7 In the embodiment, only the three first bit lines BL1 are schematically connected to the first sub-buffer 1121 located above them, and the three second bit lines BL2 are schematically connected to the second sub-buffer 1122 located above them. However, in actual applications, the specific positions of the first bit lines BL1 and the second bit lines BL2 formed on the chip and the number and shape of the first bit lines BL1 and the second bit lines BL2 are not affected. Figure 5 , Figure 6 and Figure 7 It can be understood that the first bit line BL1 and the second bit line BL2 are formed on the second chip; the number of the first bit line BL1 can be one or more and the shape of the first bit line BL1 can also be other shapes. Similarly, the number of the second bit line BL2 can also be one or more and the shape of the second bit line BL2 can also be other shapes. Specifically, the position, number and shape of the first bit line BL1 and the second bit line BL2 can be set accordingly according to actual conditions.

[0088] Similarly, in Figure 5 , Figure 6 and Figure 7 In the embodiment, only a first word line WL1 is schematically drawn to be connected to the word line driver 112 located below it, and a second word line WL2 is schematically drawn to be connected to the word line driver 112 located below it. However, in actual applications, the specific positions where the first word line WL1 and the second word line WL2 are formed on the chip, and the number and shape of the first word line WL1 and the second word line WL2 are not affected. Figure 5 , Figure 6 and Figure 7It is understandable that the number of the first word lines WL1 can be one or more, and the shape of the first word lines WL1 can also be other shapes. Similarly, the number of the second word lines WL2 can also be one or more, and the shape of the second word lines WL2 can also be other shapes. Specifically, the positions, numbers and shapes of the first word lines WL1 and the second word lines WL2 can be set accordingly according to actual conditions.

[0089] In the embodiment of the present invention, the first chip and the second chip are bonded to form a first semiconductor structure arranged vertically, which effectively improves the array efficiency and communication efficiency of the memory. In addition, the first semiconductor structure and the second semiconductor structure are formed on different substrates, respectively. After the two are fixed on the circuit board, the first semiconductor structure and the second semiconductor structure can be electrically connected and communicated. Compared with the conventional technology, the embodiment of the present invention effectively reduces the area of ​​a single substrate, which is conducive to improving the array efficiency, communication efficiency, and reducing the bit cost.

[0090] The present invention also provides a method for preparing a memory, such as Figure 8 As shown, the method includes the following steps:

[0091] Step 310: forming a first semiconductor structure, wherein the first semiconductor structure at least includes a three-dimensional NAND array and an array access circuit, wherein the array access circuit at least includes a word line driver and a page buffer;

[0092] Step 320: forming a second semiconductor structure, wherein the second semiconductor structure at least includes a peripheral circuit;

[0093] Step 330: Fix the first semiconductor structure and the second semiconductor structure to a circuit board respectively; wherein the circuit board comprises at least a first connecting contact and a second connecting contact which are electrically connected, the first semiconductor structure is fixed to the first connecting contact of the circuit board, and the second semiconductor structure is fixed to the second connecting contact of the circuit board.

[0094] The memory provided by the embodiment of the present invention integrates a three-dimensional NAND array and an array access circuit into a first semiconductor structure, integrates a peripheral circuit into a second semiconductor structure, and connects the first semiconductor structure and the second semiconductor structure through a circuit board. Compared with the prior art in which a three-dimensional NAND array, an array access circuit, and a peripheral circuit are integrated into one semiconductor structure, the embodiment of the present invention has at least the following advantages: First, the first semiconductor structure and the second semiconductor structure are formed on different wafers, and after formation, yield detection is performed separately, and only the first semiconductor structure and the second semiconductor structure that pass the detection are connected to the circuit board, so that the yield of the entire memory can be improved; Second, the first semiconductor structure and the second semiconductor structure have smaller sizes than the semiconductor structures in the prior art. During preparation, the same number of wafers can be used to prepare more memories, that is, the device yield of a single wafer can be improved, and the production cost of the memory can be reduced.

[0095] Next, combine Figures 9 to 16 The method for preparing the memory provided by the embodiment of the present invention is further described in detail.

[0096] First, if Figures 9 to 14 As shown, step 310 is performed to form a first semiconductor structure 10 . The first semiconductor structure 10 at least includes a three-dimensional NAND array 121 and an array access circuit AC1 . The array access circuit AC1 at least includes a word line driver 122 and a page buffer 112 .

[0097] In some embodiments, the first semiconductor structure 10 includes a first chip 11, a second chip 12, and a first conductive contact 111; forming the first semiconductor structure 10 includes:

[0098] The first chip 11 is formed, and the first chip 11 includes the page buffer 112. Figures 9 and 10 As shown;

[0099] The second chip 12 is formed, and the second chip 12 includes a three-dimensional NAND array 121 and the word line driver 122. Figure 11 to Figure 12 As shown;

[0100] The second chip 12 is stacked and bonded with the first chip 11. For details, please refer to Fig.13 ;

[0101] The first conductive contact 111 is formed on a surface of the first chip 11 away from the second chip 12. Fig.14 The first conductive contact 111 is used to connect to the first connection contact 31 on the circuit board 30 .

[0102] In an actual process, forming the first chip 11 includes: providing a first substrate 110; forming a page buffer 112 on the first substrate 110; forming a first bonding layer 114 on the page buffer 112, such as Fig. 9 and Fig.10 As shown;

[0103] The second chip 12 is formed by: providing a second substrate 120; forming a word line driver 122 on the second substrate 120; forming a three-dimensional NAND array 121 on the word line driver 122; forming a second bonding layer 124 on the three-dimensional NAND array 121, such as Fig.11 and Fig.12 As shown;

[0104] The second chip 12 is stacked and bonded with the first chip 11, including: bonding the second bonding layer 124 of the second chip 12 with the first bonding layer 114 of the first chip 11, for details, please refer to Fig.13 .

[0105] Here, the three-dimensional NAND array 121 includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells for storing data. The word line driver 122 is connected to the plurality of word lines WL, and the page buffer 112 is connected to the plurality of bit lines BL.

[0106] In one embodiment, the array storage circuit AC1 further includes a first control circuit 113 and a second control circuit 123, wherein the first control circuit 113 is located in the first chip 11, and the second control circuit 123 is located in the second chip 12. The first control circuit 113 may include but is not limited to analog circuits and logic circuits, and the second control circuit 123 may include but is not limited to drive circuits, read-write circuits, state machines, logic circuits, etc.

[0107] Understandable, such as Fig.14 As shown, after bonding the first chip 11 and the second chip 12, the method further includes: performing a thinning process on the side of the first substrate 110 away from the page buffer 112, and then sequentially depositing a hydrogen barrier layer 116 and a first dielectric layer 117 on the first substrate 110. The hydrogen barrier layer 116 is used to prevent hydrogen from being discharged from the area where the page buffer 112 is located toward the direction where the first conductive contact 111 is located. The material of the hydrogen barrier layer 116 includes but is not limited to silicon nitride, aluminum oxide, etc.; the material of the first dielectric layer 117 includes but is not limited to oxide, nitride, oxynitride, etc.

[0108] A conductive connection column 118 is also formed in the first substrate 110, the hydrogen barrier layer 116 and the first dielectric layer 117, and the conductive connection column 118 is used to form an electrical connection between the first semiconductor structure 10 and the first conductive contact 111. It can be understood that the hydrogen barrier layer 116 is also formed between the conductive connection column 118 and the first substrate 110 and the first dielectric layer 117, and the function of the hydrogen barrier layer 116 is the same as that described in the previous paragraph, which will not be repeated here.

[0109] In the embodiment of the present invention, a page buffer and a first control circuit are formed in the first chip, a word line driver, a second control circuit and a three-dimensional NAND array are formed in the second chip, and then the first chip and the second chip are bonded to form a first semiconductor structure arranged vertically, which is beneficial to reducing the substrate occupied area of ​​the first semiconductor structure and improving the array efficiency of the memory. In addition, the vertical interconnection method effectively shortens the communication distance between the first chip and the second chip, and improves the communication efficiency of the memory.

[0110] When forming the first semiconductor structure, a first chip and a second chip with different structures may be bonded to form the first semiconductor structure. Figures 5 to 7 , the figure shows a schematic diagram of the composition of the first semiconductor structure provided by different embodiments of the present invention.

[0111] In the actual process, a first wafer having a plurality of first chips can be formed on one wafer and a second wafer having a plurality of second chips can be formed on another wafer, and then the first wafer and the second wafer can be bonded and then divided to form a first semiconductor structure. Subsequently, an electrical characteristic sorting test is performed on the first semiconductor structure to select a first semiconductor structure with good performance to wait for fixed connection with a circuit board. It can be understood that a similar method can be used to form a second semiconductor structure, that is, a third wafer having a plurality of peripheral circuit structures is formed on other wafers, and then the third wafer is divided into a plurality of peripheral circuit chips to form a second semiconductor structure. Subsequently, an electrical characteristic sorting test is performed on the second semiconductor structure to select a second semiconductor structure with good performance to wait for fixed connection with a circuit board. The above-mentioned method of forming the first semiconductor structure and the second semiconductor structure can improve the yield of the memory finally formed and reduce the production cost.

[0112] Then, if Fig.15 As shown, step 320 is performed to form a second semiconductor structure 20, wherein the second semiconductor structure 20 at least includes a peripheral circuit 21;

[0113] In some embodiments, Fig.15 As shown, a second semiconductor structure 20 is formed, including:

[0114] Providing a third substrate 210;

[0115] forming a peripheral circuit 21 on the third substrate 210;

[0116] A second conductive contact 211 is formed on the peripheral circuit 21 , and the second conductive contact 211 is used to be connected to the second connection contact 32 on the circuit board 30 .

[0117] Here, the substrate may be a semiconductor substrate; in a specific embodiment, the substrate is a silicon substrate. In the embodiment of the present invention, the materials of the first substrate, the second substrate and the third substrate may be the same or different.

[0118] The peripheral circuit 21 may include, but is not limited to, a voltage generator, a current generator, a fuse protection circuit, an analog circuit, a control logic circuit, and an input / output (I / O) circuit. Preferably, the peripheral circuit includes an analog circuit, a voltage generator, a control logic circuit, and an I / O circuit. The voltage generator may generate various types of word line voltages for each of the address lines to be supplied based on the control of the control logic circuit, and the voltage may be applied to the selected word line through a word line driver.

[0119] Finally, if Fig.16 As shown, step 330 is performed to fix the first semiconductor structure 10 and the second semiconductor structure 20 on the circuit board 30 respectively, wherein the circuit board 30 includes at least a first connecting contact 111 and a second connecting contact 211 that are electrically connected, the first semiconductor structure 10 is fixed on the first connecting contact 111 of the circuit board 30, and the second semiconductor structure 20 is fixed on the second connecting contact 211 of the circuit board 30.

[0120] In the actual process, the circuit board 30 may further include a third connection contact 33, and the third connection contact 33 is located on the opposite side to the first connection contact 31 and the second connection contact 32. It can be understood that the third connection contact 33 can be contact-connected with a printed circuit board (PCB board).

[0121] It is understandable that the circuit board 30 may be a circuit board with a wiring circuit, or may be a substrate formed of silicon (e.g., single crystal silicon), ceramic, glass, or any other suitable material. The material of the first connection contact 111, the second connection contact 211, and the third connection contact 33 includes a conductive material, and the conductive material includes but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof.

[0122] In summary, in the embodiment of the present invention, the first semiconductor structure and the second semiconductor structure are formed separately and then attached to the circuit board. Before attachment, the first semiconductor structure and the second semiconductor structure are selected for electrical characteristics, which can improve the yield of the entire memory. In addition, compared with the prior art, the embodiment of the present invention adopts a method of separately manufacturing the first semiconductor structure and the second semiconductor structure, so that the same number of wafers can produce more memories, which can effectively improve the device yield of a single wafer and reduce the production cost of the memory.

[0123] In addition, in the first semiconductor structure, the three-dimensional NAND array, word line driver and page buffer are arranged vertically, which effectively improves the array efficiency of the memory and reduces the bit cost; and the use of vertical interconnection effectively shortens the communication distance between each other and improves the communication efficiency of the memory.

[0124] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A memory, characterized in that: include: A first semiconductor structure, the first semiconductor structure at least comprising a three-dimensional NAND array and an array access circuit, the array access circuit at least comprising a word line driver and a page buffer; a second semiconductor structure, the second semiconductor structure comprising at least a peripheral circuit; A circuit board, the circuit board at least comprising a first connection contact and a second connection contact which are electrically connected; wherein the first semiconductor structure is fixed on the first connection contact of the circuit board, and the second semiconductor structure is fixed on the second connection contact of the circuit board.

2. The memory according to claim 1, characterized in that: The first semiconductor structure includes a first chip and a second chip that are stacked and bonded; wherein the page buffer is located in the first chip, and the three-dimensional NAND array and the word line driver are located in the second chip.

3. The memory according to claim 2, characterized in that: The first semiconductor structure further includes a first conductive contact, which is located on a side of the first chip away from the second chip; wherein the first conductive contact of the first semiconductor structure is correspondingly connected to the first connection contact of the circuit board.

4. The memory according to claim 2, characterized in that: The first chip includes: a first substrate; the page buffer located on the first substrate; and a first bonding layer located on the page buffer; The second chip includes: a second substrate, the word line driver located on the second substrate; the three-dimensional NAND array located on the word line driver; and a second bonding layer located on the three-dimensional NAND array; The first chip and the second chip are bonded and connected via the first bonding layer and the second bonding layer.

5. The memory according to claim 4, characterized in that: The second substrate includes a first side and a second side arranged opposite to each other in a first direction; the word line driver includes a first sub-driver arranged on the first side and a second sub-driver arranged on the second side; the three-dimensional NAND array includes a plurality of first word lines and a plurality of second word lines; wherein the first sub-driver is located below the plurality of first word lines and connected to the plurality of first word lines, and the second sub-driver is located below the plurality of second word lines and connected to the plurality of second word lines.

6. The memory according to claim 5, characterized in that: The word line driver also includes a third sub-driver arranged on the first side and a fourth sub-driver arranged on the second side; the third sub-driver is located below the multiple second word lines and connected to the multiple second word lines, and the fourth sub-driver is located below the multiple first word lines and connected to the multiple first word lines.

7. The memory according to any one of claims 4 to 6, characterized in that: The first substrate includes a third side and a fourth side arranged opposite to each other in a second direction; the page buffer includes a first sub-buffer arranged on the third side and a second sub-buffer arranged on the fourth side; the three-dimensional NAND array includes a plurality of first bit lines and a plurality of second bit lines extending along the second direction; wherein the first sub-buffer is located above the plurality of first bit lines and connected to the plurality of first bit lines, and the second sub-buffer is located above the plurality of second bit lines and connected to the plurality of second bit lines.

8. The memory according to any one of claims 4 to 6, characterized in that: The first substrate includes a third side and a fourth side arranged opposite to each other in a second direction; the page buffer includes a first sub-buffer and a second sub-buffer arranged at a middle position between the third side and the fourth side; the three-dimensional NAND array includes a plurality of first bit lines and a plurality of second bit lines extending along the second direction; wherein the first sub-buffer is located above the plurality of first bit lines and connected to the plurality of first bit lines, and the second sub-buffer is located above the plurality of second bit lines and connected to the plurality of second bit lines.

9. The memory according to claim 1, characterized in that: The second semiconductor structure includes a third substrate, the peripheral circuit located on the third substrate, and a second conductive contact located on the peripheral circuit; wherein the second conductive contact of the second semiconductor structure is correspondingly connected to the second connection contact of the circuit board.

10. A method for preparing a memory, characterized in that: The method comprises: forming a first semiconductor structure, the first semiconductor structure comprising at least a three-dimensional NAND array and an array access circuit, the array access circuit comprising at least a word line driver and a page buffer; forming a second semiconductor structure, the second semiconductor structure comprising at least a peripheral circuit; The first semiconductor structure and the second semiconductor structure are fixed to a circuit board respectively; wherein the circuit board comprises at least a first connecting contact and a second connecting contact which are electrically connected, the first semiconductor structure is fixed to the first connecting contact of the circuit board, and the second semiconductor structure is fixed to the second connecting contact of the circuit board.

11. The preparation method according to claim 10, characterized in that: The first semiconductor structure includes a first chip, a second chip and a first conductive contact; Forming a first semiconductor structure, comprising: forming the first chip, wherein the first chip includes the page buffer; forming the second chip, wherein the second chip includes a three-dimensional NAND array and the word line driver; Stacking and bonding the second chip to the first chip; The first conductive contact is formed on a surface of the first chip away from the second chip, and the first conductive contact is used to be connected to the first connection contact on the circuit board accordingly.

12. The preparation method according to claim 11, characterized in that: Forming the first chip includes: providing a first substrate; forming a page buffer on the first substrate; forming a first bonding layer on the page buffer; Forming the second chip includes: providing a second substrate; forming a word line driver on the second substrate; forming a three-dimensional NAND array on the word line driver; forming a second bonding layer on the three-dimensional NAND array; The stacking and bonding of the second chip and the first chip includes: bonding a second bonding layer of the second chip and a first bonding layer of the first chip.

13. The preparation method according to claim 10, characterized in that: forming a second semiconductor structure, comprising: providing a third substrate; forming a peripheral circuit on the third substrate; A second conductive contact is formed on the peripheral circuit, and the second conductive contact is used to be connected to the second connection contact on the circuit board accordingly.

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