Storage array fault detection method, device and electronic equipment

Abstract

The present disclosure provides a method, device and electronic device for detecting a storage array fault. The method includes: writing a first voltage and a second voltage to storage cells connected to a plurality of first bit lines and storage cells connected to a plurality of second bit lines in a storage array to be tested, respectively, wherein the first bit line and the second bit line are arranged adjacent to each other in an alternating manner, and the first voltage is greater than the second voltage; sequentially controlling a plurality of word lines to be turned on to read the storage cells, wherein controlling a plurality of word lines to be turned on includes controlling each word line to be turned on for a preset time, and then controlling a sensing amplifier connected to the first bit line or the second bit line to be turned on to read the storage cells, wherein the preset time is greater than the standard sensing delay time corresponding to the sensing amplifier; when the reading result of the storage cell is not equal to the first voltage or the second voltage written therein, it is determined that there is leakage of a coaxial word line dual-bit capacitor in the storage array to be tested. The embodiment of the present disclosure can quickly detect leakage between adjacent storage cells (coaxial word line dual bits) connected to the same word line.

Description

Background Art

[0002] DRAM has a delicate structure and a complex mass production process. In particular, in the DRAM capacitor process, the capacitor columns are prone to tilting against each other, causing adjacent memory cells to easily fail, especially the coaxial word line (Word Line, WL) double-bit (i.e., two adjacent memory cells connected to the same WL) mutual leakage (Cell to Cell leak) problem is difficult to detect.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] The purpose of the present disclosure is to provide a storage array fault detection method, device and electronic device, which are used to overcome the problem of difficulty in detecting coaxial dual-bit leakage due to limitations and defects of related technologies to at least a certain extent.

[0005] According to a first aspect of the present disclosure, a storage array fault detection method is provided, which is used to test a storage array to be tested, comprising: writing a first voltage and a second voltage respectively to storage cells connected to a plurality of first bit lines and storage cells connected to a plurality of second bit lines in the storage array to be tested, the first bit lines and the second bit lines being arranged adjacent to each other in an alternating manner, and the first voltage being greater than the second voltage; sequentially controlling a plurality of word lines to be turned on to read the storage cells, wherein controlling the plurality of word lines to be turned on comprises controlling a sensing amplifier connected to the first bit line or the second bit line to be turned on to read the storage cells after controlling each of the word lines to be turned on for a preset time, the preset time being greater than a standard sensing delay time corresponding to the sensing amplifier; and judging that there is coaxial word line dual-bit capacitor leakage in the storage array to be tested when the reading result of the storage cell is not equal to the first voltage or the second voltage written thereto.

[0006] In an exemplary embodiment of the present disclosure, controlling the sense amplifier connected to the first bit line or the second bit line to turn on to read the memory cell includes: controlling the sense amplifier connected to the second bit line to turn on to read the memory cell connected to the second bit line.

[0007] In an exemplary embodiment of the present disclosure, the first voltage is higher than a power supply voltage of the memory array to be tested.

[0008] In an exemplary embodiment of the present disclosure, before writing the first voltage and the second voltage respectively to the memory cells connected to the plurality of first bit lines and the memory cells connected to the plurality of second bit lines in the memory array to be tested, it also includes: controlling the target charge pump connected to the sense amplifier to turn on to generate the first voltage.

[0009] In an exemplary embodiment of the present disclosure, before writing the first voltage and the second voltage respectively to the memory cells connected to the plurality of first bit lines and the memory cells connected to the plurality of second bit lines in the memory array to be tested, it also includes: controlling the target switch element connecting the first voltage and the sense amplifier to be turned on so as to input the first voltage to the sense amplifier.

[0010] In an exemplary embodiment of the present disclosure, the second voltage is zero voltage or negative voltage.

[0011] In an exemplary embodiment of the present disclosure, the preset time length is greater than or equal to 3ns and less than or equal to 300ns.

[0012] In an exemplary embodiment of the present disclosure, it also includes: after reading the storage cell, writing the second voltage and the first voltage respectively to the storage cells connected to the first bit lines and the storage cells connected to the second bit lines in the storage array to be tested; sequentially controlling the N word lines to be turned on to read the storage cells, wherein controlling the N word lines to be turned on includes controlling each word line to be turned on for a preset time, and then controlling the sensing amplifier connected to the first bit line or the second bit line to be turned on to read the storage cell, and the preset time is greater than the standard sensing delay time corresponding to the sensing amplifier; when the reading result of the storage cell is not equal to the first voltage or the second voltage written thereto, it is determined that there is coaxial word line dual-bit capacitor leakage in the storage array to be tested.

[0013] In an exemplary embodiment of the present disclosure, writing the first voltage and the second voltage respectively to the memory cells connected to the multiple first bit lines and the memory cells connected to the multiple second bit lines in the memory array to be tested includes: turning on the target word line, alternately writing the first voltage and the second voltage to a preset number of consecutive memory cells connected to the target word line, and turning off the target word line.

[0014] In an exemplary embodiment of the present disclosure, the preset number is equal to the burst length of the memory array to be tested, or the preset number is equal to the number of all memory cells connected to the word line, and the writing of the first voltage and the second voltage to the memory cells connected to the multiple first bit lines and the memory cells connected to the multiple second bit lines in the memory array to be tested, respectively, includes: after closing the target word line, opening the next word line of the target word line to alternately write the first voltage and the second voltage to a continuous preset number of memory cells connected to the next word line.

[0015] In an exemplary embodiment of the present disclosure, the preset number is equal to the burst length of the memory array to be tested, and the first voltage and the second voltage are respectively written to the memory cells connected to the plurality of first bit lines and the memory cells connected to the plurality of second bit lines in the memory array to be tested, including: after closing the target word line, opening the target word line to alternately write the first voltage and the second voltage to a preset number of consecutive memory cells connected to the target word line that have not been written to, and closing the target word line; repeating the above steps until all the memory cells connected to the target word line are written to the first voltage or the second voltage.

[0016] In an exemplary embodiment of the present disclosure, sequentially controlling the N word lines to be turned on to read the memory cells includes: turning on a target word line, alternately writing the first voltage and the second voltage to a preset number of consecutive memory cells connected to the target word line, and turning off the target word line, wherein the preset number is equal to the burst length of the memory array to be tested.

[0017] In an exemplary embodiment of the present disclosure, sequentially controlling the N word lines to be turned on to read the memory cells includes: after turning off the target word line, turning on a word line next to the target word line to read the preset number of consecutive memory cells connected to the next word line.

[0018] In an exemplary embodiment of the present disclosure, sequentially controlling the N word lines to be turned on to read the memory cells includes: after turning off the target word line, turning on the target word line to read the preset number of consecutive memory cells connected to the target word line that have not been read; repeating the above steps until all the memory cells connected to the target word line are read.

[0019] According to a third aspect of the present disclosure, there is provided an electronic device, comprising: a memory; and a processor coupled to the memory, wherein the processor is configured to execute any one of the methods described above based on instructions stored in the memory.

[0020] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided, on which a program is stored, and when the program is executed by a processor, the method as described in any one of the above is implemented.

[0021] The disclosed embodiment writes different voltages to adjacent memory cells connected to the same word line, thereby increasing the voltage difference between adjacent memory cells connected to the same word line and prolonging the sensing delay time of the sensing amplifier, thereby being able to detect the coaxial dual-bit inter-capacitor leakage problem and having a high detection efficiency.

[0022] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0024] Figure 1 is a schematic diagram of a memory array to be tested in an exemplary embodiment of the present disclosure.

[0025] Figure 2 The present invention is a flowchart of a storage array fault detection method according to an embodiment of the present invention.

[0026] Figure 3 It is a schematic diagram of the state after the first voltage and the second voltage are written to the storage array in the embodiment of the present disclosure.

[0027] Figure 4 It is a schematic diagram of the read circuit of the memory cell.

[0028] Figure 5 In the embodiment of the present disclosure, Figure 4 Schematic diagram of the process of reading the state of a memory cell by the circuit shown.

[0029] Fig. 6A and Figure 6B Schematic diagrams of the bit line potential change during the reading of data "0" corresponding to normal and abnormal conditions respectively.

[0030] Fig. 7A and Figure 7B Schematic diagrams of the bit line potential change during the reading of data "1" corresponding to normal and abnormal conditions respectively.

[0031] Figure 8 is a block diagram of an electronic device in an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0033] In addition, the accompanying drawings are only schematic diagrams of the present disclosure, and the same reference numerals in the drawings represent the same or similar parts, so their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities, which do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0034] The exemplary embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0035] Figure 1 is a schematic diagram of a memory array to be tested in an exemplary embodiment of the present disclosure.

[0036] refer to Figure 1 , the memory array 100 may include: M bit lines BL1-BLM, N word lines WL1-WLN and M*N memory cells 11, each memory cell 11 is connected to a word line WL* and a bit line BL* ("*" represents any number), a word line WL* is connected to M memory cells 11, and a bit line BL* is connected to N memory cells 11. The M bit lines BL1-BLM extend in the X direction and are arranged in the Y direction; the N word lines WL1-WLN extend in the Y direction and are arranged in the X direction. Wherein, M and N are both positive integers greater than or equal to 2.

[0037] The two memory cells 11 belong to the same active area 12. A bit line contact structure BLC (Bit Line Contact) is provided in the center of the active area 12. The two memory cells 11 located in the same active area 12 are connected to the same bit line through the bit line contact structure BLC. Each memory cell 11 has a capacitor C. There are memory cells 11 connected to the same word line in two adjacent active areas 12 in the Y direction. Figure 1 The memory cell 111 and the memory cell 112 shown in FIG. 1 are connected to the word line WL2 in common, and the memory cell 111 and the memory cell 112 can become coaxial word line dual bits.

[0038] When leakage occurs between the capacitors connecting the memory cells 111 and 112, once the word line WL2 is turned on, both the memory cells 111 and 112 are turned on, and it is difficult to determine whether there is leakage between the memory cells 111 and 112 by separate detection.

[0039] Figure 2 The present invention is a flowchart of a storage array fault detection method according to an embodiment of the present invention. Figure 2 The method shown can be used to detect Figure 1 The leakage phenomenon between the storage unit 111 and the storage unit 112.

[0040] refer to Figure 2 , the method 200 may include:

[0041] Step S1, writing a first voltage and a second voltage into a plurality of memory cells connected to first bit lines and a plurality of memory cells connected to second bit lines in a memory array to be tested, respectively, the first bit lines and the second bit lines being arranged adjacent to each other in an alternating manner, and the first voltage being greater than the second voltage;

[0042] Step S2, sequentially controlling N word lines to be turned on to read the memory cell, wherein controlling the N word lines to be turned on includes controlling each word line to be turned on for a preset time, and then controlling a sense amplifier connected to the first bit line or the second bit line to be turned on to read the memory cell, and the preset time is greater than a standard sense delay time corresponding to the sense amplifier;

[0043] Step S3, when the read result of the memory cell is not equal to the first voltage or the second voltage written therein, it is determined that there is leakage of the coaxial word line dual-bit capacitor in the memory array to be tested.

[0044] Figure 3 1 is a schematic diagram of the state after the first voltage and the second voltage are written to the storage array in the embodiment of the present disclosure. Figure 3 right Figure 2 The method shown is described.

[0045] refer to Figure 3In one embodiment, the first voltage corresponds to data "1" and the second voltage corresponds to data "0". In step S1, data "1" is written to the storage cells connected to the first bit line 31 and data "0" is written to the storage cells connected to the second bit line 32. The first bit line 31 and the second bit line 32 are alternately arranged. Since two adjacent storage cells connected to the same word line are written with different voltages, there is a voltage difference between the capacitors. Once there is capacitor leakage between the two storage cells, the data stored in the storage cells will change. The leakage direction is as follows: Figure 3 Indicated by the arrow.

[0046] In order to improve the detection efficiency and make the possible capacitor leakage more obvious, in one embodiment, the first voltage is set to be higher than the power supply voltage of the memory array to be tested. For example, if the power supply voltage of the memory array to be tested is equal to 1.0V, the first voltage can be set to 1.2V. The difference between the first voltage and the power supply voltage can be set by those skilled in the art according to the actual operating parameters of the memory array to be tested, and the present disclosure is not limited thereto.

[0047] In one embodiment, the method for generating the first voltage may be, for example, through a charge pump or a short circuit. For example, before writing the first voltage and the second voltage respectively to the storage cells connected to the first bit lines and the storage cells connected to the second bit lines in the storage array to be tested, the target charge pump connected to the sense amplifier may be controlled to turn on to generate the first voltage. Alternatively, the target switch element connected to the first voltage and the sense amplifier may be controlled to turn on to input the first voltage to the sense amplifier. Furthermore, the target charge pump may be controlled to turn on to generate the first voltage first, and then the target switch element may be controlled to turn on to input the first voltage to the sense amplifier. There may be many methods for inputting the first voltage into the sense amplifier and then writing it into the storage cell through the sense amplifier, and the present disclosure does not impose any special restrictions on this.

[0048] In order to further increase the voltage difference between the coaxial word line dual bits, the second voltage may be a zero voltage or a negative voltage.

[0049] After the first voltage or the second voltage is written to the memory cell, capacitor leakage begins to occur due to the large voltage difference between adjacent memory cells. At this time, by reading the state of the memory cell, it is possible to determine whether there is capacitor leakage between the coaxial word line dual bits by determining whether the state of the memory cell has changed.

[0050] In an exemplary embodiment of the present disclosure, controlling the sense amplifier connected to the first bit line or the second bit line to turn on to read the memory cell includes: controlling the sense amplifier connected to the second bit line to turn on to read the memory cell connected to the second bit line. That is, reading the memory cell written with "0" to determine whether it is still "0". If leakage occurs, there is a small amount of charge in the capacitor of the memory cell, which will not be "0". Reading the memory cell written with "0" can avoid the situation where the memory cell written with "1" is still read as "1" due to difficulty in detection (see Figure 7 for the specific reason), thereby more accurately determining the state change of the memory cell.

[0051] Figure 4 It is a schematic diagram of the read circuit of the memory cell.

[0052] Figure 5 In the embodiment of the present disclosure, Figure 4 Schematic diagram of the process of reading the state of a memory cell by the circuit shown.

[0053] refer to Figure 4 The storage unit 41 includes M1 and a capacitor C. M1 can be, for example, an N-type transistor. The source of M1 is connected to the capacitor C, the drain is connected to the bit line BL, and the gate is connected to the word line WL. The column selection unit 42, the balance unit 43 and the sense amplifier 44 are sequentially arranged on the bit line BL.

[0054] The column selection unit 42 includes a second switch element M2 . The second switch element M2 is an N-type transistor, a source of which is connected to a local input / output signal line LIO (Local Input / Output), a drain of which is connected to a bit line BL, and a gate of which is connected to a column selection signal line YS (YSelect).

[0055] The balancing unit 43 includes a third switch element M3, a fourth switch element M4 and a fifth switch element M5. The third switch element M3, the fourth switch element M4 and the fifth switch element M5 are all N-type transistors. The gates of the third switch element M3, the fourth switch element M4 and the fifth switch element M5 are all connected to the equalization voltage VEQ (Voltage of Equalizer). The source of the third switch element M3 and the drain of the fourth switch element M4 are both connected to the bit line precharge voltage V BLP (Voltage of BitLine Precharge), the drain of the third switch element M3 is connected to the bit line BL, and the source of the fourth switch element M4 is connected to the complementary bit line / BL.

[0056] The sense amplifier (SA) 44 is a differential amplifier, and its two input terminals are respectively connected to the bit line BL and the complementary bit line / BL, and is used to amplify the voltage difference between the bit line BL and the complementary bit line / BL. The sense amplifier 44 includes a sixth switch element M6, a seventh switch element M7, an eighth switch element M8, and a ninth switch element 444. Among them, the sixth switch element M6 and the seventh switch element M7 are both N-type transistors, and the eighth switch element M8 and the ninth switch element 444 are both P-type transistors. One end of the sixth switch element M6 is connected to the bit line BL through the first node N1, and the other end is connected to the low potential node NCS, and the low potential node NCS is connected to the second voltage Vss, and the control end of the sixth switch element M6 is connected to the complementary bit line / BL. One end of the seventh switch element M7 is connected to the complementary bit line / BL through the second node N2, and the other end is connected to the low potential node NCS, and the control end of the seventh switch element M7 is connected to the bit line BL. One end of the eighth switch element M8 is connected to the bit line BL through the first node N1, and the other end is connected to the high potential node PCS, the high potential node PCS is connected to the second voltage Vary, and the control end of the eighth switch element M8 is connected to the complementary bit line / BL. One end of the ninth switch element M9 is connected to the complementary bit line / BL through the second node N2, and the other end is connected to the high potential node PCS, and the control end of the ninth switch element M9 is connected to the bit line BL.

[0057] refer to Figure 5 Before reading, the equalization voltage VEQ turns on the three switch elements in the balance unit 43, and the bit line BL and the complementary bit line / BL are both equal to the bit line precharge voltage V BLP After the activation signal ACT arrives, the equalization voltage VEQ is turned off (VEQ OFF), allowing a voltage difference to exist between the bit line BL and the complementary bit line / BL. Next, the control word line WL is turned on (WL ON), and M1 in the memory cell 41 is turned on.

[0058] At this time, if the data stored in the memory cell 41 is "0", the capacitor C is at a low level, the bit line BL leaks to the capacitor C through M1, and the voltage on the bit line BL changes from V BLP At this time, if the capacitor of the coaxial word line dual-bit of the storage unit 41 leaks to the capacitor C, the capacitor C will receive the leakage of the bit line BL and the capacitor of the coaxial word line dual-bit at the same time, and will quickly reach a non-zero voltage that can be detected as a non-zero state. At the same time, the bit line BL and the capacitor of the coaxial word line dual-bit leak to the capacitor C at the same time, and the potential drop speed of the bit line BL will be slower than the leakage to the capacitor C alone, and the voltage drop on the bit line BL will not reach the level that can be detected by the sense amplifier 44. This process is called the charge sharing process, and the duration of the charge sharing process is called the sensing delay time (SDT).

[0059] After the charge sharing process, that is, after the control word line WL is turned on for a certain period of time, the sense amplifier 44 can be turned on by the enable signal to start the sense amplification process. Assume that the potential of the bit line BL drops to ΔV and the voltage is V BLP -ΔV. The voltage of the complementary bit line / BL is still V BLP At this time, the two input terminals of the sense amplifier 44 are connected to the bit line BL and the complementary bit line / BL respectively, and the control terminal voltage V BLP is greater than the control terminal voltage V BLP -ΔV.

[0060] Fig. 6A and Figure 6B Schematic diagrams of the bit line potential change during the reading of data "0" corresponding to normal and abnormal conditions respectively.

[0061] refer to Fig. 6A Under normal circumstances, if ΔV is large enough, the opening degree of the sixth switch element M6 is greater than the opening degree of the seventh switch element M7, the voltage of the first node N1 reaches the second voltage Vss faster than the voltage of the second node N2, the ninth switch element M9 controlled by the first node N1 is turned on first, the voltage of the second node N2 is quickly pulled to the first voltage Vary, and the eighth switch element M8 controlled by the second node N2 is turned off. At this time, the first node N1 is connected to the second voltage Vss through the opened sixth switch element M6, that is, the voltage of the bit line BL is equal to the second voltage Vss, the seventh switch element M7 is turned off, and the second node N2 is connected to the first voltage Vary through the opened ninth switch element M9, that is, the voltage of the complementary bit line / BL is pulled to the first voltage Vary. At this point, the voltage difference ΔV caused by the leakage of the bit line BL to the capacitor C is amplified by the sense amplifier 44, the potential of the bit line BL is equal to the second voltage Vss, and the potential of the complementary bit line / BL is equal to the first voltage Vary. This period of time is called tRCD. tRCD is the delay time between RAS (Row Address Strobe) and CAS (Column Address Strobe). CAS and RAS jointly determine memory addressing.

[0062] refer to Figure 6BIn the case of leakage of the coaxial dual-bit capacitor, the leaked capacitor C shares the charge of the bit line BL, resulting in that the potential drop difference ΔV of the bit line BL is not large enough, but becomes smaller and smaller. Once the sense amplifier 44 is enabled, the opening degree of the sixth switch element M6 is not much different from the opening degree of the seventh switch element M7, the first node N1 and the second node N2 reach the second voltage Vss almost at the same time, the sixth switch element M6 and the seventh switch element M7 are both turned off, the eighth switch element M8 and the ninth switch element M9 are turned on at the same time, and the voltages of the first node N1 and the second node N2 are raised at the same time.

[0063] During this process, the leaked capacitor C continues to share charge with the bit line BL, the potential of the first node N1 rises faster than that of the second node N2, the opening degree of the ninth switch element M9 is less than that of the eighth switch element M8, and the first node N1 reaches the first voltage Vary faster than the second node N2. At this time, the ninth switch element M9 is completely turned off, the seventh switch element M7 is completely turned on, and the potential of the second node N2 is pulled to the second voltage Vss.

[0064] In order to detect the coaxial dual-bit capacitor leakage, it is necessary to make ΔV smaller than the sensing capability of the sensing amplifier when the sensing amplifier 44 is enabled. Figure 6B Therefore, in the embodiment of the present disclosure, the preset time length between WL turning on and the sense amplifier 44 turning on is set to be longer than the conventional sense delay time (SDT) of the sense amplifier, that is, Long SDT is set to extend the charge sharing time.

[0065] In an exemplary embodiment of the present disclosure, the preset time length (i.e., the length of Long SDT) may be, for example, greater than or equal to 3 ns and less than or equal to 300 ns. If the preset time length is too small, ΔV cannot be reduced to a level that cannot be sensed by the sense amplifier 44. If the preset time length is too large, the purpose of rapid detection cannot be achieved. The preset time length may be determined by a person skilled in the art based on experiments, and the present disclosure does not impose any special restrictions on this.

[0066] Continue to refer Figure 5, after the sense amplifier 44 pulls the voltage of the bit line BL to the first voltage Vary or the second voltage Vss, the column selection unit 42 is controlled to be turned on (YS ON) through the column selection signal YS, and the voltage of the bit line BL is read to the local signal line LIO. If the potential of the bit line BL is the first voltage Vary, the reading result is "1"; if the potential of the bit line WL is the second voltage Vss, the reading result is "0". After turning off the column selection signal YS (YS OFF), the sense amplifier 44 is controlled to enter the preparation stage (PRE) for the next reading. Turn off the word line WL (WL OFF) and the sense amplifier 44 (SA OFF), control the equalization voltage VEQ to turn on (VEQ ON), so that the bit line BL and the complementary bit line / BL are equal to the bit line precharge voltage V BLP , until the activation signal ACT is received again. This period of time is called tRP (Row Precharge Time). tRP is the time between the precharge command (PRE) and the activation command (ACT) of the next word line in DRAM. It is used to characterize the speed at which the DRAM array recovers to the precharge state, especially the time required for the bit line in the array to charge from a high level or a low level to an intermediate potential.

[0067] By setting a longer charge sharing time, i.e., Long SDT, when the bit line BL and the coaxial word line double-bit capacitance of the memory cell 41 may leak electricity to the memory cell 41, the leakage process can be superimposed on the charge sharing process after WL is turned on, so as to quickly detect the leakage phenomenon.

[0068] In step S3, if the word line WL is turned on and the sense amplifier corresponding to the target memory cell reads a target memory cell, it is found that the target memory cell written with data "0" is read as 1 (that is, the bit line BL is Figure 6B ), it means that the adjacent memory cells connected to the same word line WL have leakage to the target memory cell. At this time, it can be determined that the coaxial dual-bit capacitor leakage phenomenon exists.

[0069] Fig. 7A and Figure 7B Schematic diagrams of the bit line potential change during the reading of data "1" corresponding to normal and abnormal conditions respectively.

[0070] refer to Fig. 7A, when the capacitor C in the storage unit 41 is written with the first voltage, there is no leakage between the capacitors, the word line WL is turned on, and the charge sharing stage is entered. The potential of the bit line BL is raised by the capacitor C, and the potential of the first node N1 is higher than the potential of the second node N2. After the control sense amplifier 44 is turned on, the first node N1 controls the seventh switch element M7 to turn on, and the second node N2 controls the eighth switch element M8 to turn on. The opening degree of the seventh switch element M7 is greater than the opening degree of the sixth switch element M6, and the potential of the bit line BL and the complementary bit line / BL both decrease to a certain extent. However, then, the second node N2 is first pulled to the second voltage Vss through the seventh switch element M7 with a larger opening degree, the eighth switch element M8 is turned on, and the sixth switch element M6 is turned off. The potential of the first node N1 quickly rises to the first voltage Vary, the ninth switch element M9 is turned off, the seventh switch element M7 is turned on, and the potential of the second node N2 is fixed to the second voltage Vss. So far, when the voltage of the bit line BL is read through the column selection signal YS, the first voltage Vary can be read, that is, the reading result is "1".

[0071] refer to Figure 7B When there is leakage between capacitors, after the word line WL is turned on and enters the charge sharing stage, the potential of the bit line BL is raised by the capacitor C. Since the capacitor C leaks to the capacitor of the adjacent storage unit at the same time, the potential of the bit line BL rises faster. Fig. 7A The situation is slow, but it is still higher than the voltage V of the complementary bit line / BL BLC After the control sense amplifier 44 is turned on, the first node N1 controls the seventh switch element M7 to turn on, and the second node N2 controls the eighth switch element M8 to turn on. The opening degree of the seventh switch element M7 is still greater than the opening degree of the sixth switch element M6. Even if the charge sharing process is extended, the potential of the bit line BL is still greater than the potential V of the complementary bit line / BL. BLC As the WL opening time increases, the capacitor C shares more and more charges, the potential of the bit line BL continues to rise, and the difference between the potential of the complementary bit line / BL becomes larger and larger. Therefore, in this case, the reading result of the bit line BL is still "1", and it is not easy to detect the presence of capacitor leakage.

[0072] Therefore, the embodiment of the present disclosure is configured to read the memory cell written with the second voltage to detect the coaxial dual-bit leakage phenomenon.

[0073] After testing half of the memory cells that have been written with the second voltage (ie, data “0”), the data writing scheme may be changed to test the other half of the memory cells.

[0074] In an exemplary embodiment of the present disclosure, method 100 further includes: after reading the memory cells, writing the second voltage and the first voltage respectively to the memory cells connected to the plurality of first bit lines and the memory cells connected to the plurality of second bit lines in the memory array to be tested; sequentially controlling N word lines to be turned on to read the memory cells, wherein controlling the N word lines to be turned on includes controlling each word line to be turned on for a preset time, and then controlling the sense amplifier connected to the first bit line or the second bit line to be turned on to read the memory cells; when the read result of the memory cell is not equal to the first voltage or the second voltage written thereto, determining that there is coaxial word line dual-bit capacitor leakage in the memory array to be tested.

[0075] For example, in the test, "1" is first written to the storage cells connected to the odd-numbered bit lines, and "0" is written to the storage cells connected to the even-numbered bit lines. Then, the storage cells connected to the even-numbered bit lines are read according to the above embodiment. When the reading result of any storage cell is not "0", it is determined that there is coaxial word line dual-bit capacitor leakage.

[0076] After testing all the storage cells connected to the even-numbered bit lines, write "1" to the storage cells connected to the even-numbered bit lines, write "0" to the storage cells connected to the odd-numbered bit lines, and then read the storage cells connected to the odd-numbered bit lines according to the above embodiment. When the reading result of any storage cell is not "0", it is determined that there is coaxial word line dual-bit capacitor leakage.

[0077] The above process may be, for example:

[0078] The first voltage Vary is pulled to a higher potential through a charge pump or a short circuit, and then the entire storage array is processed according to a preset data format (Column stripe, such as Figure 3 The memory cell corresponding to the odd-numbered bit sense amplifier (connected to the bit line) writes data "1" or data "0". The memory cell corresponding to the odd-numbered bit sense amplifier (connected to the bit line) writes data "1", and the memory cell corresponding to the even-numbered bit sense amplifier (connected to the bit line) writes data "0". The memory cell corresponding to the odd-numbered bit sense amplifier and the memory cell corresponding to the even-numbered bit sense amplifier have a higher voltage difference Vary-Vss, where Vss is the second voltage.

[0079] Extend the sensing delay time (Long SDT), and by controlling the word line WL switch of the entire storage array, the sense amplifier continuously performs sensing amplification (charge sharing). During the Long SDT process, the sensing "1" signal leaks the sensing "0" signal, which will cause the "0" signal amplification error. Then turn off the sensing amplifier connected to the odd-bit bit line, and only read the "0" data in the storage cell connected to the even-bit sensing amplifier, and judge whether the "1" signal of the storage cell has leakage to the "0" signal of the storage cell. When used at high temperature, this method can effectively reduce the overkill effect of the "1" data of the storage cell due to insufficient retention time. Next, change the data format for writing, write "0" to the storage cell connected to the odd-bit sensing amplifier, turn off the even-bit sensing amplifier, and only read the "0" data in the storage cell connected to the odd-bit sensing amplifier.

[0080] At this point, the detection of the entire storage array is completed. It can be understood that in the embodiments of the present disclosure, the range of the storage array can be set by those skilled in the art, such as a page or a bank, and the present disclosure does not impose any special restrictions on this. The storage arrays in the memory can all be tested by the above-mentioned test method provided in the embodiments of the present disclosure.

[0081] When testing the memory array, the order of writing data can be preset to write the first voltage or the second voltage to the memory cell.

[0082] In an exemplary embodiment of the present disclosure, the data writing process may include: turning on a target word line, alternately writing a first voltage and a second voltage to a preset number of consecutive memory cells connected to the target word line, and turning off the target word line.

[0083] In one embodiment, the preset number is equal to the burst length (BL) of the memory array to be tested, or the preset number is equal to the number of all memory cells connected by the word line. At this time, after closing the target word line, the next word line of the target word line can be opened to alternately write the first voltage and the second voltage to the continuous preset number of memory cells connected to the next word line.

[0084] When the preset number is equal to the burst length of the memory array to be tested, the process of turning on the next word line of the target word line to alternately write the first voltage and the second voltage to the continuous burst length memory cells connected to the next word line can be called an X-Fast writing mode, that is, fast writing is achieved in the X direction.

[0085] When the preset number is equal to the number of all memory cells connected to the word line, after closing the target word line, the next word line of the target word line is turned on to alternately write the first voltage and the second voltage to a continuous preset number of memory cells connected to the next word line. This is called the Y-Page writing method, that is, realizing full-page writing in the Y direction.

[0086] In another embodiment, the preset number is equal to the burst length of the memory array to be tested, and after closing the target word line, the target word line can be opened to alternately write the first voltage and the second voltage to the continuous burst length memory cells connected to the target word line that have not been written, and then close the target word line; repeat the above steps until all memory cells connected to the target word line are written with the first voltage or the second voltage. This writing method can be called a Y-Fast writing method, that is, fast writing is achieved in the Y direction.

[0087] Similarly, the reading process can also pre-set the reading order.

[0088] In one embodiment, the reading process may include: turning on the target word line, alternately writing the first voltage and the second voltage to a preset number of consecutive memory cells connected to the target word line, and turning off the target word line, where the preset number is equal to the burst length of the memory array to be tested. The burst length is the number of bit lines that can be read simultaneously corresponding to the memory array, for example, the burst length supported by DDR4 is 8 bits, and the maximum burst length supported by DDR5 is 16 bits.

[0089] After closing the target word line, the next word line of the target word line can be opened to read a preset number of continuous storage cells connected to the next word line. This reading method is called X-Fast reading method, which can achieve fast reading in the X direction.

[0090] In another embodiment, after the target word line is turned off, the target word line can be turned on to read a preset number of unread consecutive memory cells connected to the target word line; the above steps are repeated until all memory cells connected to the target word line are read. This reading method is called a Y-Fast reading method, which can achieve fast reading in the Y direction.

[0091] By writing different first voltages and second voltages to the storage cells connected to adjacent bit lines, and expanding the difference between the first voltage and the second voltage, the leakage phenomenon of the coaxial dual-bit capacitor can be made more obvious and the leakage speed can be increased. By increasing the induction delay time, the leakage time can be superimposed on the charge sharing process, and then the potential change ΔV of the bit line BL can be reduced, so that after the sensing amplifier is turned on, ΔV is difficult to be detected. At the same time, it is affected by the leakage phenomenon, and the sensing amplifier is quickly flipped, and the potential of the bit line BL is pulled to the first voltage Vary, and then the abnormal result is quickly detected. By reading the storage cell written with the second voltage (i.e., data "0"), the reading failure when reading the storage cell written with the first voltage (i.e., data "1") can be avoided, and the reading success rate can be improved. Finally, by increasing the voltage difference between adjacent storage cells of the coaxial word line and extending the induction delay time, the chips with potential dual-bit failures can be screened out in advance, and the chip factory yield can be improved.

[0092] In an exemplary embodiment of the present disclosure, an electronic device capable of implementing the above method is also provided.

[0093] It will be appreciated by those skilled in the art that various aspects of the present invention may be implemented as a system, method or program product. Therefore, various aspects of the present invention may be specifically implemented in the following forms, namely: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or a combination of hardware and software, which may be collectively referred to herein as a "circuit", "module" or "system".

[0094] Refer to the following Figure 8 An electronic device 800 according to this embodiment of the present invention will be described. Figure 8 The electronic device 800 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present invention.

[0095] like Figure 8 As shown, the electronic device 800 is in the form of a general computing device. The components of the electronic device 800 may include but are not limited to: the at least one processing unit 810, the at least one storage unit 820, and a bus 830 connecting different system components (including the storage unit 820 and the processing unit 810).

[0096] The storage unit stores program codes, which can be executed by the processing unit 810, so that the processing unit 810 performs the steps according to various exemplary embodiments of the present invention described in the above “Exemplary Method” section of this specification. For example, the processing unit 810 can perform the method shown in the embodiment of the present disclosure.

[0097] The storage unit 820 may include a readable medium in the form of a volatile storage unit, such as a random access memory unit (RAM) 8201 and / or a cache memory unit 8202 , and may further include a read-only memory unit (ROM) 8203 .

[0098] The storage unit 820 may also include a program / utility 8204 having a set (at least one) of program modules 8205, such program modules 8205 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0099] Bus 830 may represent one or more of several types of bus structures, including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

[0100] The electronic device 800 may also communicate with one or more external devices 900 (e.g., keyboards, pointing devices, Bluetooth devices, etc.), may also communicate with one or more devices that enable a user to interact with the electronic device 800, and / or communicate with any device that enables the electronic device 800 to communicate with one or more other computing devices (e.g., routers, modems, etc.). Such communication may be performed via an input / output (I / O) interface 850. In addition, the electronic device 800 may also communicate with one or more networks (e.g., local area networks (LANs), wide area networks (WANs), and / or public networks, such as the Internet) via a network adapter 860. As shown, the network adapter 860 communicates with other modules of the electronic device 800 via a bus 830. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device 800, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, etc.

[0101] Through the description of the above implementation, it is easy for those skilled in the art to understand that the example implementation described here can be implemented by software, or by software combined with necessary hardware. Therefore, the technical solution according to the implementation of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (which can be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to the implementation of the present disclosure.

[0102] In an exemplary embodiment of the present disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the above method of the present specification is stored. In some possible implementations, various aspects of the present invention can also be implemented in the form of a program product, which includes a program code, and when the program product is run on a terminal device, the program code is used to enable the terminal device to execute the steps according to various exemplary embodiments of the present invention described in the above "Exemplary Method" section of the present specification.

[0103] The program product for implementing the above method according to an embodiment of the present invention can adopt a portable compact disk read-only memory (CD-ROM) and include program code, and can be run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited thereto, and in this document, a readable storage medium can be any tangible medium containing or storing a program, which can be used by or in combination with an instruction execution system, an apparatus or a device.

[0104] The program product may use any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0105] Computer readable signal media may include data signals propagated in baseband or as part of a carrier wave, in which readable program code is carried. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Readable signal media may also be any readable medium other than a readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0106] The program code embodied on the readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination of the foregoing.

[0107] Program code for performing the operations of the present invention may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving a remote computing device, the remote computing device may be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., through the Internet using an Internet service provider).

[0108] In addition, the above-mentioned figures are only schematic illustrations of the processes included in the method according to an exemplary embodiment of the present invention, and are not intended to be limiting. It is easy to understand that the processes shown in the above-mentioned figures do not indicate or limit the time sequence of these processes. In addition, it is also easy to understand that these processes can be performed synchronously or asynchronously, for example, in multiple modules.

[0109] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are to be considered exemplary only, and the true scope and concept of the present disclosure are indicated by the claims.

Claims

1. A storage array fault detection method for testing a storage array to be tested, characterized in that: The method comprises: Writing a first voltage and a second voltage into storage cells connected to a plurality of first bit lines and storage cells connected to a plurality of second bit lines in a storage array to be tested, respectively, wherein the first bit lines and the second bit lines are arranged alternately and adjacently, and the first voltage is greater than the second voltage; Controlling the plurality of word lines to be turned on sequentially to read the storage unit, wherein the controlling the plurality of word lines to be turned on comprises: controlling each of the word lines to be turned on for a preset time, and then controlling a sense amplifier connected to the first bit line or the second bit line to be turned on to read the storage unit, wherein the preset time is greater than a standard sense delay time corresponding to the sense amplifier; When the reading result of the memory cell is not equal to the first voltage or the second voltage written therein, determining that there is leakage of the coaxial word line dual-bit capacitor in the memory array to be tested; The sequentially controlling the plurality of word lines to be turned on to read the memory cells comprises: The target word line is turned on, the first voltage and the second voltage are alternately written into a preset number of consecutive memory cells connected to the target word line, and the target word line is turned off, where the preset number is equal to the burst length of the memory array to be tested.

2. The storage array fault detection method according to claim 1, characterized in that: The controlling the sense amplifier connected to the first bit line or the second bit line to turn on to read the memory cell comprises: The sense amplifier connected to the second bit line is controlled to be turned on to read the memory cell connected to the second bit line.

3. The storage array fault detection method according to claim 1, wherein: The first voltage is higher than the power supply voltage of the memory array to be tested.

4. The storage array fault detection method according to claim 3, characterized in that: Before writing the first voltage and the second voltage into the memory cells connected to the first bit lines and the memory cells connected to the second bit lines in the memory array to be tested, respectively, the method further includes: A target charge pump connected to the sense amplifier is controlled to be turned on to generate the first voltage.

5. The storage array fault detection method according to claim 3 or 4, characterized in that: Before writing the first voltage and the second voltage into the memory cells connected to the first bit lines and the memory cells connected to the second bit lines in the memory array to be tested, respectively, the method further includes: A target switch element connecting the first voltage and the sense amplifier is controlled to be turned on, so as to input the first voltage to the sense amplifier.

6. The storage array fault detection method according to claim 1 or 3, characterized in that: The second voltage is zero voltage or negative voltage.

7. The storage array fault detection method according to claim 1, characterized in that: The preset time length is greater than or equal to 3ns and less than or equal to 300ns.

8. The storage array fault detection method according to claim 1, wherein: Also includes: After reading the memory cells, writing the second voltage and the first voltage into the memory cells connected to the plurality of the first bit lines and the memory cells connected to the plurality of the second bit lines in the memory array to be tested, respectively; Controlling the plurality of word lines to be turned on sequentially to read the storage unit, wherein controlling the plurality of word lines to be turned on includes controlling each word line to be turned on for a preset time, and then controlling a sense amplifier connected to the first bit line or the second bit line to be turned on to read the storage unit, wherein the preset time is greater than a standard sense delay time corresponding to the sense amplifier; When the reading result of the memory cell is not equal to the first voltage or the second voltage written therein, it is determined that there is coaxial word line dual-bit capacitor leakage in the memory array to be tested.

9. The storage array fault detection method according to claim 1, wherein: The step of writing the first voltage and the second voltage into the memory cells connected to the first bit lines and the memory cells connected to the second bit lines in the memory array to be tested comprises: A target word line is turned on, the first voltage and the second voltage are alternately written into a preset number of consecutive memory cells connected to the target word line, and the target word line is turned off.

10. The storage array fault detection method according to claim 9, characterized in that: The preset number is equal to the burst length of the memory array to be tested, or the preset number is equal to the number of all memory cells connected to the word lines, and the first voltage and the second voltage are respectively written to the memory cells connected to the first bit lines and the memory cells connected to the second bit lines in the memory array to be tested, including: After the target word line is turned off, a word line next to the target word line is turned on to alternately write the first voltage and the second voltage into a preset number of consecutive memory cells connected to the next word line.

11. The storage array fault detection method according to claim 9, characterized in that: The preset number is equal to the burst length of the memory array to be tested, and the step of writing the first voltage and the second voltage into the memory cells connected to the plurality of first bit lines and the memory cells connected to the plurality of second bit lines in the memory array to be tested, respectively, comprises: After closing the target word line, opening the target word line to alternately write the first voltage and the second voltage into a preset number of consecutive memory cells connected to the target word line and not subjected to a write operation, and closing the target word line; The above steps are repeated until all the memory cells connected to the target word line are written with the first voltage or the second voltage.

12. The storage array fault detection method according to claim 1, wherein: The sequentially controlling the plurality of word lines to be turned on to read the memory cells comprises: After the target word line is turned off, a word line next to the target word line is turned on to read the preset number of continuous memory cells connected to the next word line.

13. The storage array fault detection method according to claim 1, wherein: The sequentially controlling the plurality of word lines to be turned on to read the memory cells comprises: After closing the target word line, opening the target word line to read the preset number of consecutive memory cells connected to the target word line and not read; The above steps are repeated until all the memory cells connected to the target word line are read.

14. An electronic device, characterized in that: include: Memory; as well as A processor coupled to the memory, the processor being configured to execute the storage array failure detection method according to any one of claims 1 to 13 based on instructions stored in the memory.

15. A computer-readable storage medium having a program stored thereon, wherein when the program is executed by a processor, the storage array fault detection method according to any one of claims 1 to 13 is implemented.

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