A silicon carbide power diode with a field plate structure and a method for preparing the same

Abstract

The present invention discloses a silicon carbide power diode with a field plate structure and a preparation method thereof, wherein the power diode is composed of silicon carbide and aluminum oxide. The present invention first uses FP and Al2O3 to realize lateral gradient doping in SiC semiconductor process, and then applies this gradient doping to the JTE structure to solve the problems of low breakdown voltage and narrow doping concentration window in the JTE region in the traditional dual-zone JTE terminal structure. Under the combined action of the high dielectric constant characteristics of Al2O3 and the FP technology, an electric field of appropriate intensity will be generated above the JTE region to regulate the uneven distribution of holes inside the JTE in the longitudinal space, and avoid excessive concentration of holes at the interface between Al2O3 and the JTE region. Therefore, the SiC power diode in the present invention not only has a large breakdown voltage and a wide JTE region doping concentration window, but also has low preparation difficulty and is easy to operate, which greatly improves the working performance of the PiN power diode.

Description

Technical Field

[0001] The invention relates to a power diode, and in particular to a silicon carbide power diode with a field plate structure and a preparation method thereof. Background Art

[0002] The development and breakthroughs in semiconductor material growth and device preparation technology often trigger a new round of industrial revolution and the rise of emerging industries. As the first and second generation semiconductor materials represented by silicon (Si) and gallium arsenide (GaAs) gradually develop to the limit of their material properties, the third generation of new wide bandgap semiconductor materials has emerged. Silicon carbide (SiC) material, as its typical representative, is very suitable for the production of high-voltage, high-power, and high-temperature resistant semiconductor power devices due to its advantages such as large bandgap width, high thermal conductivity, and high critical breakdown electric field. Among the many SiC-based semiconductor power devices, PiN power diodes are widely used in lighting, solar energy, electric vehicles and other fields due to their faster switching speed and stronger large current handling capabilities. They are currently the most widely used SiC-based power devices.

[0003] Faced with such a wide range of applications, the importance of SiC-based PiN power diodes is self-evident. The quality of its device characteristics will affect the performance of the entire power electronics system. In some special fields, such as in high-voltage transmission grids, power semiconductor devices are required to be able to withstand high voltages. However, in the actual devices, the actual withstand voltage of the device is much smaller than the theoretical voltage value when we designed it. The main reason is that there is a certain curvature at the edge of the PN junction. Figure 3 The cross-sectional diagram of a PN junction formed by a planar process is given. A layer of silicon dioxide (SiO2) mask is grown on an n-type SiC substrate, and then a rectangular etching window is etched on the SiO2. Then, p-type impurity ions are implanted in the rectangular etching window, and finally, impurity atoms are implanted into the SiC at high temperature to form a PN junction. The figure shows that during the high-temperature implantation process, on the one hand, the impurity atoms will move vertically downward to form a parallel plane junction, and on the other hand, some impurities will also diffuse laterally, and a cylindrical junction or a spherical junction will appear at the edge of the PN junction. Then, when reverse biased, the surface electric field of the cylindrical junction or the spherical junction will be much larger than the electric field in the body of the device. This phenomenon of the electric field being concentrated at the edge due to the junction bending at the edge of the PN junction is called the curvature effect. The local electric field concentration makes the electric field at that location reach the critical electric field of the device, thereby causing the device to break down early. Therefore, this curvature effect has a very large side effect on the actual withstand voltage of the device.

[0004] In order to make the actual withstand voltage of the device closer to its theoretical design value, it is necessary to solve the problem caused by the curvature effect. The emergence of junction termination technology can effectively alleviate the local electric field concentration effect, which is an effective way to solve this problem. From the 1960s and 1970s to the present, junction termination technology has experienced decades of development. There are many types of junction termination technologies applied to power devices. Among them, the most widely concerned are junction termination extension (JTE) technology and field plate (FP) technology. Therefore, we introduce the above two technologies into this invention to alleviate the local electric field concentration effect and improve the breakdown voltage of the device. In JTE technology, when the reverse bias voltage of the device continues to increase, the depletion region of the main junction will extend to the JTE region. At this time, the JTE region will also be depleted, thereby increasing the width of the depletion region and weakening the local electric field concentration effect. However, the single-region JTE terminal is very sensitive to the ion implantation dose. In order to prevent the JTE end from breaking down prematurely, the ion implantation dose of the JTE must be lower than that of the main junction, but too low an implantation dose will reduce the protection of the main junction. It can be seen that the suitable ion implantation dose window for the single-zone JTE terminal structure is narrow, that is, the doping concentration window of the JTE zone is narrow, which will lead to poor uniformity of products in different batches, making it difficult to apply in large-scale industrial production. To solve this problem, researchers have continuously optimized the structure of JTE technology, and the concept of the traditional dual-zone JTE terminal structure has been proposed. The dual-zone JTE has a different doping concentration distribution compared to the single-zone JTE. The same partition is generally uniformly doped, and generally speaking, the closer to the main junction, the higher the doping concentration. Therefore, the traditional dual-zone JTE terminal structure, due to its longer terminal zone length and multiple partitions with different doping concentrations, further improves the breakdown voltage of the device while reducing the peak electric field of the main junction. In addition, the traditional dual-zone JTE terminal structure is highly operational in the actual process flow and has a wider doping concentration window than the single-zone JTE.

[0005] However, in the uniformly doped dual-zone JTE structure, the breakdown voltage and the JTE zone doping concentration window will also reach a limit value. At this time, we can optimize the results by increasing the length of the terminal zone, but an overly long terminal zone will bring many negative effects, such as increasing the probability of device leakage current, bringing more static power consumption and dynamic power consumption to the device, thereby affecting the reliability and service life of the device. In addition, this structural design will cause the length, thickness and doping concentration of the terminal zone to become variables. Too many variables make it difficult for us to optimize the results. Based on this, we make the originally uniformly doped G-JTE layer a gradient doping area without changing the length of the terminal zone. At this time, the junction terminal area is theoretically equivalent to countless junctions with different concentrations connected together. However, it is difficult to achieve gradient doping of the G-JTE layer through previous technologies, because both ion implantation technology and diffusion technology rely on the diffusion of doped atoms in SiC at high temperatures, and this diffusion is difficult to achieve in SiC. This technology has been mature in Si for a long time, but in SiC, because the diffusion mobility of these doping impurities is smaller than that in Si, it is difficult to use ion implantation or diffusion technology in the G-JTE layer to make the G-JTE layer a graded doping region.

[0006] Faced with the difficulty of gradient doping, we introduced FP terminal technology and high dielectric constant material Al2O3 in this invention to realize gradient doping in the G-JTE layer. The role of Al2O3 in this invention is mainly reflected in two aspects. First, we change the thickness of each part in the Al2O3 region under the action of FP technology to generate an electric field perpendicular to the interface with gradient intensity in the G-JTE layer below, which acts on the spatial distribution of acceptor holes that were originally evenly distributed along the interface, and realizes the effect of lateral gradient of hole distribution in the G-JTE layer. On the other hand, we mainly use the high dielectric constant characteristics of Al2O3 and combine it with FP technology to control the intensity of the electric field generated in the JTE region, avoid excessive concentration of holes at the interface between the G-JTE layer and the Al2O3 region due to excessive electric field, and make the vertical hole distribution in the G-JTE layer more uniform. Therefore, in this invention, we first use FP technology and high dielectric constant material Al2O3 to achieve the gradual doping of the G-JTE layer, and then introduce this gradual doping technology into the JTE terminal structure, so that the SiC power diode in this invention has a larger breakdown voltage and a wider JTE region dose window compared to the traditional dual-zone JTE terminal structure. In addition, due to the presence of a strong electric field in the FP technology, the negative impact of the interface trap charge at the Al2O3 / SiC interface on the device performance will be reduced accordingly, which greatly improves the working performance of the SiC power diode. Summary of the invention

[0007] The purpose of the present invention is to provide a technology for realizing gradual doping of the G-JTE layer, and at the same time solve the problems of low breakdown voltage and narrow doping dose window of the JTE region in the traditional dual-zone JTE terminal structure. The present invention uses field plate terminal technology and Al2O3 to realize gradual doping in the G-JTE layer; to successfully realize gradual doping, on the one hand, we realize lateral gradual doping of holes in the G-JTE layer by changing the thickness of each region in the second Al2O3 region; on the other hand, we need to generate an electric field of appropriate size above the G-JTE layer to make the longitudinal distribution of holes in the JTE terminal structure more uniform.

[0008] The technical solution for achieving the purpose of the present invention is:

[0009] A silicon carbide power diode with a field plate structure, the power diode is a symmetrical cylindrical structure, and from bottom to top there are n + type SiC substrate layer, i-type SiC epitaxial layer and p + Type SiC layer;

[0010] In the p + The edge of the SiC layer is in the shape of concentric circles, extending from the inside to the outside, with two JTE layer ring structures, namely the uniformly doped JTE layer and the gradually doped G-JTE layer;

[0011] Directly above the two JTE layers is an annular structure Al2O3 layer, wherein the Al2O3 layer is also divided into two regions from the inside to the outside, namely, a first Al2O3 region completely covering directly above the JTE layer and a second Al2O3 region completely covering directly above the G-JTE layer;

[0012] The p + A Ti / Au metal top electrode is drawn out above the type SiC layer and the Al2O3 layer; the n + A Ti / Au metal bottom electrode is led out from under the SiC substrate layer.

[0013] Furthermore, the lateral gradient doping of holes in the G-JTE layer is achieved by changing the thickness of each part in the second Al2O3 region.

[0014] Furthermore, the high dielectric constant characteristics of Al2O3 and the FP technology are used to generate a relatively weak electric field above the JTE region, making the holes in the G-JTE layer more uniform in the vertical distribution.

[0015] Furthermore, the second Al2O3 zone is a right-angled trapezoidal annular region with a longitudinal section, and the right-angled waist of the right-angled trapezoid is in contact with the G-JTE layer; the thickness of the second Al2O3 zone gradually decreases from the outside to the inside, and the length of the upper base of the right-angled trapezoid is equal to the thickness of the first Al2O3 zone.

[0016] Furthermore, the thickness of each part in the first Al2O3 region is equal.

[0017] Furthermore, the p + The thicknesses of the i-type SiC layer, JTE layer and G-JTE layer tend to increase gradually, but they are all smaller than the thickness of the i-type SiC epitaxial layer.

[0018] Furthermore, the doping concentration range of the JTE layer annular structure region is 2.3×10 17 cm -3 ~4.5×10 18 cm -3 , the doping concentration window of the JTE layer ring structure area is 42.7.

[0019] The method for preparing the silicon carbide power diode with the field plate structure comprises the following steps:

[0020] S1: in n + An i-type SiC epitaxial layer is epitaxially grown on the i-type SiC substrate layer;

[0021] S2: Then, ion implantation is performed on the i-type SiC epitaxial layer to form a p-type SiC epitaxial layer. + Type SiC layer;

[0022] S3: Then in p + The edge of the SiC layer is also formed into a uniformly doped JTE layer by ion implantation;

[0023] S4: forming a uniformly doped G-JTE layer at the edge of the JTE layer by ion implantation;

[0024] S5: After the ion implantation is completed, the device is annealed;

[0025] S6: epitaxially grow Al2O3 directly above the JTE layer and the G-JTE layer;

[0026] S7: Reactive ion etching is performed on Al2O3 to form a first Al2O3 region directly above the JTE layer; then, a second Al2O3 region in an inclined region is formed directly above the G-JTE layer by changing the content of the experimental gas in the reactive ion etching;

[0027] S8: Finally in p + Ti / Au metal top electrode is deposited on the n-type SiC layer and Al2O3 layer; + A Ti / Au metal bottom electrode is evaporated under the SiC substrate layer to form a silicon carbide power diode with a field plate structure.

[0028] Furthermore, the step S6 specifically includes the following steps:

[0029] S61: After the experimental device is assembled, in order to remove the original air impurities in the reaction chamber, nitrogen with a flow rate of 150 sccm needs to be introduced into the reaction chamber for 10 minutes; after the cleaning is completed, nitrogen and oxygen are introduced to maintain a stable atmosphere in the reaction chamber;

[0030] S62: Take aluminum acetylacetonate as the metal source, oxygen as the reaction gas, and nitrogen as the carrier gas; in the heating stage of the experiment, first weigh 0.05g of aluminum acetylacetonate and place it in a tube furnace, set the temperature to 190°C, and the heating rate to 15°C / min, with the flow rates of oxygen and nitrogen being 5sccm and 100sccm respectively, thereby growing Al2O3 with a ring width of 50μm and a thickness of 12μm directly above the JTE layer and the G-JTE layer.

[0031] Furthermore, the step S7 specifically includes the following steps:

[0032] S71: in a reactive ion etching system, 40 sccm of chlorine gas, 4 sccm of boron trichloride and a pressure of 600 mTorr are applied to the system to etch away a ring region with a ring width of 20 μm and a thickness of 7 μm in the Al2O3 directly above the JTE layer, thereby forming a first Al2O3 region with a ring width of 20 μm and a thickness of 5 μm directly above the JTE layer;

[0033] S72: Then change the content of experimental gas in the system, apply 20sccm of chlorine gas, 6sccm of boron trichloride and a pressure of 600mTorr to the system, and etch away the right-angled triangular ring area with a base of 7μm and a height of 30μm in the Al2O3 just above the G-JTE layer, thereby forming a second Al2O3 region with a right-angled trapezoidal ring area with a ring width of 30μm and a thickness increasing from 5μm to 12μm just above the G-JTE layer.

[0034] The working principle of the silicon carbide power diode with the field plate structure is as follows:

[0035] SiC-based PiN power diodes are based on the PIN junction structure and consist of three layers of semiconductors: highly doped p + Type SiC layer, highly doped n + When a reverse bias is applied to the SiC-based PiN power device, the doping concentration of the i-type SiC epitaxial layer in the drift region is higher than that of the p-type SiC substrate layer. + The depletion region in the diode will expand rapidly in the i-type SiC epitaxial layer as the applied reverse bias increases, resulting in the p + type SiC layer and i-type SiC epitaxial layer + n -The electric field at the junction is too concentrated, and the local electric field is too concentrated, which will cause the electric field at that location to quickly reach the critical electric field value of the device, causing the device to break down prematurely.

[0036] In order to solve the above problems and effectively alleviate the local electric field concentration effect, we introduce the JTE terminal structure in this invention. In the JTE terminal structure, its working mechanism is that when a reverse bias is applied to both ends of the diode, the JTE layer and the G-JTE layer are in a completely depleted state under the action of the reverse bias, and only the immobile ionized acceptor impurity charges are left in the two JTE regions, thereby weakening the electric field concentration phenomenon at the edge of the device main junction.

[0037] On the basis of introducing the JTE terminal structure, we also introduce the FP terminal structure. FP is a metal material covering the oxide layer at the edge of the main junction. When a reverse bias is applied, the depletion region at the main junction in the device is expanded, which also alleviates the electric field concentration effect. Figure 4 As shown in the figure, A shows the boundary shape of the depletion region of the planar junction when no bias is applied to the field plate. When a positive bias is applied to the field plate relative to the N-type substrate, the field plate will attract electrons to move toward the surface. This will cause the depletion region to expand along the surface to shrink, as shown in B in the figure. This will increase the electric field at the junction, causing the breakdown voltage to drop. Conversely, when a negative bias is applied to the field plate, electrons will be repelled and move away from the surface. This will cause the depletion region at the surface to extend outward, as shown in C in the figure. This will reduce the electric field at the junction and increase the breakdown voltage. Therefore, the FP terminal structure is introduced in the invention, on the one hand, to further increase the breakdown voltage and JTE doping concentration window of the device, and more importantly, to achieve the gradual doping of the G-JTE layer, which is quite meaningful.

[0038] In order to successfully realize the gradual doping in the G-JTE layer in this invention, we not only need to introduce the above-mentioned FP terminal structure, but also need to replace the original SiO2 in the diode with Al2O3. The main reason why we do not choose SiO2 is that: when the external electric field is relatively large, due to the relatively small dielectric constant of SiO2, a large electric field will be generated on the JTE layer, which will cause a large number of holes in the G-JTE layer to be attracted to the interface between the G-JTE layer and the second Al2O3 region, making the holes unevenly distributed vertically in the G-JTE layer. In order to avoid the above problems, we use high dielectric constant material Al2O3. Since the electric field is inversely proportional to the dielectric constant, even when the external electric field is relatively large, the electric field generated above the JTE region will be lower than when SiO2 is used as the dielectric layer, which will prevent the holes in the G-JTE layer from being overly concentrated at the interface between the G-JTE layer and the second Al2O3 region, and the holes will be more evenly distributed vertically. In addition, the role of Al2O3 in this invention is also reflected in another aspect. We need to achieve lateral gradient doping of holes in the G-JTE layer by changing the thickness of each part in the second Al2O3 region under the action of FP technology. The Al2O3 layer above the area with relatively high lateral hole concentration in the G-JTE layer is relatively thin, and the Al2O3 layer above the area with relatively low concentration is relatively thick. Because when a negative voltage acts on the thin Al2O3 layer, since the Al2O3 layer there is relatively thin, it can attract a large number of holes to gather in the G-JTE layer, and the hole doping concentration there is relatively high. Conversely, when a negative voltage acts on a thick Al2O3 layer, fewer holes are attracted, and the hole doping concentration there is relatively low. Therefore, in the present invention, we can successfully achieve gradient doping in the G-JTE layer under the joint action of FP terminal technology and Al2O3, and its gradient doping effect is as follows: Figure 5 As shown. Figure 6 In the case of FP is not applied above the G-JTE layer, the hole distribution in the G-JTE layer is uniform. Figure 5 It can be seen that once FP is applied on the G-JTE layer, under the joint action of Al2O3, the originally uniformly doped G-JTE layer becomes a gradient doping area.

[0039] In addition to the above points, in this invention we also need to pay attention to the impact of the interface charge at Al2O3 / SiC on the device performance. The existence of the interface state will seriously affect the performance of the device. For example, the Coulomb scattering generated by the interface state charge makes the effective channel mobility relatively low, thereby increasing the channel resistance and power consumption. Among all the interface charges, the interface charge at Al2O3 / SiC is closest to the interface and has a greater impact on the device. It is caused by defects generated by itself or other reasons. These defects capture electrons under the influence of the outside world to obtain negative electrical properties and capture holes to obtain positive electrical properties. Therefore, the interface charge can be negatively charged or positively charged, which will affect the reliability of the device. Then in order to reduce the negative impact of the interface charge on the device, we also introduce the FP terminal structure. The strong electric field applied to the FP will reduce the negative impact of the interface charge and further improve the working performance of the device.

[0040] By adopting the above technical solution, the present invention has the following beneficial effects:

[0041] (1) Under the combined effect of the JTE terminal structure and the FP terminal structure, the SiC-based PiN power diode in the present invention has a larger breakdown voltage and a wider JTE region doping concentration window than the traditional dual-region JTE terminal structure, making the SiC-based PiN power diode in the present invention more widely used.

[0042] (2) Under the effect of the FP terminal structure, the SiC-based PiN power diode of the present invention transfers the difficulty of gradual doping of the G-JTE layer to the treatment of Al2O3. We solve the trouble of gradual doping in SiC semiconductor technology by changing the thickness of each part in the second Al2O3 region.

[0043] (3) The present invention introduces Al2O3 to replace the original SiO2 layer in the diode, utilizes the high dielectric constant characteristics of Al2O3 and combines the FP technology to generate an electric field of appropriate intensity above the JTE region, which can effectively prevent the holes from being excessively concentrated at the interface between the G-JTE layer and the second Al2O3 region under high electric fields, making the longitudinal distribution of holes in the G-JTE layer more uniform.

[0044] (4) Due to the presence of a strong electric field on the FP terminal structure, the effect of the interface charge at Al2O3 / SiC in the SiC-based PiN power diode of the present invention on the device performance will be weakened, thereby avoiding the effect of the interface charge on the device working state and improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to make the content of the present invention more clearly understood, the present invention is further described in detail below according to specific embodiments and in conjunction with the accompanying drawings, wherein

[0046] Figure 1 This is a cross-sectional view of a silicon carbide power diode with a field plate structure according to the present invention.

[0047] Figure 2 The schematic diagram of the structure of a silicon carbide power diode with a field plate structure according to the present invention.

[0048] Figure 3 Schematic diagram of the curvature effect produced when a PN junction is formed.

[0049] Figure 4 This is a schematic diagram of the FP terminal structure.

[0050] Figure 5 Schematic diagram of hole doping concentration distribution in the silicon carbide power diode of the present invention after using the FP terminal structure.

[0051] Figure 6 Schematic diagram of the hole doping concentration distribution in a traditional dual-zone JTE terminal structure silicon carbide power diode.

[0052] Figure 7 The present invention is a schematic diagram of the preparation process of a silicon carbide power diode with a field plate structure.

[0053] Figure 8 This is the breakdown voltage variation curve of the traditional dual-zone JTE terminal structure silicon carbide power diode.

[0054] Fig. 9 The figure is a breakdown voltage variation curve of a silicon carbide power diode with a field plate structure according to the present invention.

[0055] The numbers in the attached drawings are: n + type SiC substrate layer 1, i-type SiC epitaxial layer 2, p + Type SiC layer 3, JTE layer 4, G-JTE layer 5, first Al2O3 region 6, second Al2O3 region 7, Ti / Au metal top electrode 8, and Ti / Au metal bottom electrode 9. DETAILED DESCRIPTION

[0056] (Example 1)

[0057] The SiC power diode is a symmetrical cylindrical structure, so the device performance on both sides of the vertical center axis is completely consistent. Therefore, in order to avoid a huge amount of calculation during the simulation process, we use the symmetry of the SiC power diode and only study 1 / 2 of the cross section of the structure through the vertical center axis. The device structure cross-section is shown in the figure below. Figure 1 Although the device structure is only a part of the entire SiC power diode, the device performance of the two is completely consistent. It is completely feasible to use the 1 / 2 structure of the vertical center axis section of the entire device to replace the entire SiC power diode for research. Figure 1, a silicon carbide power diode with a field plate structure in this embodiment, the power diode is a symmetrical cylindrical structure, and from bottom to top there are n + type SiC substrate layer 1, i-type SiC epitaxial layer 2 and p + Type SiC layer 3;

[0058] In the p + The edge of the SiC layer 3 is in the shape of concentric circles and extends from the inside to the outside to form two JTE layer ring structures, which are the uniformly doped JTE layer 4 and the gradually doped G-JTE layer 5;

[0059] Directly above the two JTE layers is an annular structure Al2O3 layer, wherein the Al2O3 layer is also divided into two regions from the inside to the outside, namely, a first Al2O3 region 6 completely covering directly above the JTE layer 4 and a second Al2O3 region 7 completely covering directly above the G-JTE layer 5;

[0060] The p + A Ti / Au metal top electrode 8 is drawn out above the type SiC layer 3 and the Al2O3 layer; + A Ti / Au metal bottom electrode 9 is led out from under the SiC substrate layer 1.

[0061] The second Al2O3 region 7 is a right-angled trapezoidal annular region with a longitudinal section, and the right-angled waist of the right-angled trapezoid is in contact with the G-JTE layer 5; the thickness of the second Al2O3 region 7 gradually decreases from the outside to the inside, and the length of the upper base of the right-angled trapezoid is equal to the thickness of the first Al2O3 region 6; the thickness of each part of the first Al2O3 region 6 is equal.

[0062] The p + The thicknesses of the i-type SiC layer 3 , the JTE layer 4 and the G-JTE layer 5 tend to increase gradually, but are all smaller than the thickness of the i-type SiC epitaxial layer 2 .

[0063] A silicon carbide power diode with a field plate structure according to this embodiment comprises the following steps:

[0064] S1: in n + An i-type SiC epitaxial layer 2 is epitaxially grown on the i-type SiC substrate layer 1, specifically, the following steps:

[0065] S11: First, pure hydrogen gas is used to + The type SiC substrate layer 1 is in-situ etched to eliminate the n + Damage or stress on the surface of the SiC substrate layer 1;

[0066] S12: Then, using a chemical vapor deposition system, under the conditions of propane flow rate of 7 mL / min, silane flow rate of 21 mL / min, hydrogen flow rate of 80 L / min, temperature of 1580°C, and pressure of 100 mbar, + An i-type SiC epitaxial layer 2 with a cross-sectional radius of 80 μm and a thickness of 8 μm is epitaxially grown on the i-type SiC substrate layer 1;

[0067] S2: Then, p-type SiC epitaxial layer 2 is formed by ion implantation. + Type SiC layer 3, see the following steps for details:

[0068] S21: firstly, a 2 μm thick SiO2 layer is deposited on the surface of the i-type SiC epitaxial layer 2 by a plasma enhanced chemical vapor deposition device;

[0069] S22: Then, SiO2 is dry-etched using a 1.8 μm thick photoresist as a mask to form an ion implantation mask;

[0070] S23: Aluminum (Al) ions at 450°C are injected into the i-type SiC epitaxial layer 2 through the SiO2 mask window, with an injection energy of 30-150 keV and four injections, ultimately forming a cross-sectional radius of 10 μm, a thickness of 0.65 μm, and a doping concentration of 2.4×10 19 cm -3 p + type SiC layer 3, and remove the SiO2 layer and photoresist on the surface of the i-type SiC epitaxial layer 2;

[0071] S3: Then in p + The edge of the SiC layer 3 is also formed into a uniformly doped JTE layer 4 by ion implantation, as shown in the following steps:

[0072] S31: first, depositing a 2 μm thick SiO2 layer on the surface of the i-type SiC epitaxial layer 2 by a plasma enhanced chemical vapor deposition device;

[0073] S32: Then, using a 1.8 μm thick photoresist as a mask, dry-etching SiO2 to form an ion implantation mask;

[0074] S33: Al ions at 400°C are injected into the i-type SiC epitaxial layer 2 through the SiO2 mask window, with an injection energy of 100-800 keV and 5 injection times, eventually forming a ring with a width of 20 μm, a thickness of 1.25 μm, and a doping concentration of 7×10 18 cm -3 The JTE layer 4 is formed, and the SiO2 layer and the photoresist on the surface of the i-type SiC epitaxial layer 2 are removed;

[0075] S4: Then, an ion implantation method is used to form a uniformly doped G-JTE layer 5 at the edge of the JTE layer 4, as shown in the following steps:

[0076] S41: firstly, a 2 μm thick SiO2 layer is deposited on the surface of the i-type SiC epitaxial layer 2 by a plasma enhanced chemical vapor deposition device;

[0077] S42: Then, using a 1.8 μm thick photoresist as a mask, dry-etching SiO2 to form an ion implantation mask;

[0078] S43: Al ions at 350°C are injected into the i-type SiC epitaxial layer 2 through the SiO2 mask window, with an injection energy of 100-1300 keV and 6 injection times, eventually forming a ring with a width of 30 μm, a thickness of 1.5 μm, and a doping concentration of 2×10 17 cm -3 The G-JTE layer 5 is formed, and the SiO2 layer and the photoresist on the surface of the i-type SiC epitaxial layer 2 are removed;

[0079] S5: After the ion implantation is completed, the device is annealed, as shown in the following steps:

[0080] S51: Put the cleaned device into the clamp pot, slowly push the clamp pot to the middle position of the annealing furnace, and then close the placement port;

[0081] S52: Turn on the mechanical pump to evacuate the cavity, and when the pressure in the cavity is pumped to about 0.2 Pa, turn off the mechanical pump and open the nitrogen valve to introduce nitrogen, so that the pressure in the cavity is slightly higher than the atmospheric pressure, and then close the nitrogen valve to continue the vacuum operation, and evacuate the cavity to about 0.2 Pa, turn off the mechanical pump and introduce nitrogen again. The purpose of repeating the operation is to ensure the purity of the nitrogen in the cavity to prevent oxidation of the sample during annealing;

[0082] S53: After the nitrogen is introduced, turn on the annealing furnace switch, adjust the heating time and the temperature holding time, open the vent valve at the same time, and inject nitrogen into the chamber. The nitrogen flow rate is set to 50 sccm / min, and wait for the temperature to rise to 1450°C;

[0083] S54: Start the cooling procedure, close the annealing furnace after the temperature of the annealing furnace is lower than 600° C., wait for the annealing furnace to cool naturally to room temperature, close the nitrogen valve, open the annealing furnace cavity, complete the annealing work, take out the silicon carbide sample, and proceed to the next experiment;

[0084] S6: epitaxially grow Al2O3 directly above the JTE layer 4 and the G-JTE layer 5, as shown in the following steps:

[0085] S61: After assembling the experimental device, in order to remove the original air impurities in the reaction chamber, it is necessary to open the nitrogen cylinder and introduce nitrogen with a flow rate of 150 sccm into the reaction chamber for 10 minutes. After the cleaning is completed, nitrogen and oxygen are introduced to maintain a stable atmosphere in the reaction chamber;

[0086] S62: Aluminum acetylacetonate is used as the metal source, oxygen is used as the reaction gas, and nitrogen is used as the carrier gas. In the heating stage of the experiment, 0.05 g of aluminum acetylacetonate is first weighed and placed in a tube furnace, the temperature is set to 190°C, and the heating rate is 15°C / min. The flow rates of oxygen and nitrogen are 5 sccm and 100 sccm, respectively, thereby growing Al2O3 with a ring width of 50 μm and a thickness of 12 μm directly above the JTE layer 4 and the G-JTE layer 5;

[0087] S7: Reactive ion etching is performed on Al2O3 to form a first Al2O3 region 6 directly above the JTE layer 4; then, a second Al2O3 region 7 in an inclined region is formed directly above the G-JTE layer 5 by changing the content of the experimental gas in the reactive ion etching, as shown in the following steps:

[0088] S71: in a reactive ion etching system, 40 sccm of chlorine gas, 4 sccm of boron trichloride and a pressure of 600 mTorr are applied to the system to etch away a ring region with a ring width of 20 μm and a thickness of 7 μm in the Al2O3 directly above the JTE layer 4, thereby forming a first Al2O3 region 6 with a ring width of 20 μm and a thickness of 5 μm in the ring region directly above the JTE layer 4;

[0089] S72: Then, the content of the experimental gas in the system is changed, and 20 sccm of chlorine gas, 6 sccm of boron trichloride and a pressure of 600 mTorr are applied to the system to etch away the right-angled triangle annular region with a base of 7 μm and a height of 30 μm in the Al2O3 directly above the G-JTE layer 5, thereby forming a right-angled trapezoidal annular region second Al2O3 region 7 with a ring width of 30 μm and a thickness progressively increasing from 5 μm to 12 μm directly above the G-JTE layer 5;

[0090] S8: Finally in p + Ti / Au metal top electrode 8 is deposited on the SiC layer 3 and the Al2O3 layer; + A Ti / Au metal bottom electrode 9 is evaporated below the SiC substrate layer 1, specifically as follows:

[0091] S81: Raise the bell jar, open the evaporation chamber, tie the weighed Au and Ti metals to the tungsten wire, and clamp the tied tungsten wire to the electrode column of the evaporation table, record the electrode numbers of different metals, and test the contact between the tungsten wire and the electrode, place the silicon carbide sample covered with the electrode mold just above the position where the tungsten wire is tied to the metal, and lower the bell jar;

[0092] S82: Use mechanical pump and molecular pump to evacuate the chamber and pipeline, and reduce the pressure in the chamber to 10 -3 Below Pa;

[0093] S83: Turn on the evaporation switch, select the electrode number to be evaporated, evaporate Au metal first, slowly adjust the voltage knob, when the voltage reaches a certain value, you can see the tungsten filament glowing, continue to increase the voltage until the Au metal on the tungsten filament is completely evaporated, after the Au evaporation is completed, adjust the voltage knob to 0 and wait for two minutes to allow the Au vapor in the chamber to completely disappear, then change the electrode number to evaporate Ti, the experimental steps are the same as Au;

[0094] S84: Turn off the molecular pump and the mechanical pump, turn on the inflation switch, raise the bell jar after inflation is completed, and take out the silicon carbide sample after the electrode is evaporated;

[0095] S85: After all electrodes are evaporated, they need to be annealed to form ohmic contacts. The annealing equipment is a high-temperature tube furnace, the annealing temperature is 880°C, the annealing time is 5 minutes, and the annealing atmosphere is hydrogen. After the annealing is completed, the electrode preparation is completed, thereby forming a silicon carbide power diode with a field plate structure.

[0096] The process for preparing a silicon carbide power diode with a field plate structure according to the present invention is as follows: Figure 7 shown.

[0097] Figure 8 The breakdown voltage variation curve of the traditional dual-zone JTE terminal structure SiC power diode is shown in Figure 2. Fig. 9 The breakdown voltage variation curve of a SiC power diode with a field plate structure in the present invention is shown in the two figures. It can be clearly seen that when both devices are kept at 85% of the theoretical breakdown voltage, the doping concentration range of the JTE region of the conventional dual-region JTE terminal structure SiC power diode is 3.4×10 17 cm -3 ~1.4×10 18 cm -3 , the JTE region doping concentration window is 10.6; while the JTE region doping concentration range of a SiC power diode with a field plate structure in the present invention is 2.3×10 17 cm -3 ~4.5×10 18 cm -3 The JTE region doping concentration window is 42.7, which is nearly 4 times higher than that of the traditional dual-region JTE terminal structure. Therefore, the invention effectively solves the problems of low breakdown voltage and narrow JTE region doping concentration window in the traditional dual-region JTE terminal structure SiC power diode.

[0098] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A silicon carbide power diode with a field plate structure, characterized in that: The power diode is a symmetrical cylindrical structure, with n + type SiC substrate layer (1), i-type SiC epitaxial layer (2) and p + Type SiC layer (3); In the p + The edge of the SiC layer (3) is in the shape of concentric circles and extends from the inside to the outside to form two JTE layer ring structures, which are a uniformly doped JTE layer (4) and a gradually doped G-JTE layer (5); Directly above the two JTE layers is an annular Al2O3 layer, wherein the Al2O3 layer is also divided into two regions from the inside to the outside, namely, a first Al2O3 region (6) completely covering directly above the JTE layer (4) and a second Al2O3 region (7) completely covering directly above the G-JTE layer (5); The p + A Ti / Au metal top electrode (8) is led out from above the type SiC layer (3) and the Al2O3 layer; the n + A Ti / Au metal bottom electrode (9) is led out from below the SiC substrate layer (1); A lateral gradient doping of holes in the G-JTE layer (5) is achieved by changing the thickness of each portion in the second Al2O3 region (7); The second Al2O3 region (7) is a ring-shaped region with a right-angled trapezoidal longitudinal section, and the right-angled waist of the right-angled trapezoid is in contact with the G-JTE layer (5); the thickness of the second Al2O3 region (7) gradually decreases from the outside to the inside, and the length of the upper base of the right-angled trapezoid is equal to the thickness of the first Al2O3 region (6).

2. The silicon carbide power diode with a field plate structure according to claim 1, characterized in that: By utilizing the high dielectric constant characteristics of Al2O3 and the FP technology, a relatively weak electric field is generated above the JTE region, so that the holes in the G-JTE layer (5) are more uniformly distributed in the vertical direction.

3. The silicon carbide power diode with a field plate structure according to claim 1, characterized in that: The thickness of each part in the first Al2O3 region (6) is equal.

4. The silicon carbide power diode with a field plate structure according to claim 1, characterized in that: The p + The thicknesses of the i-type SiC layer (3), the JTE layer (4) and the G-JTE layer (5) tend to increase gradually, but are all smaller than the thickness of the i-type SiC epitaxial layer (2).

5. The silicon carbide power diode with a field plate structure according to claim 1, characterized in that: The doping concentration range of the JTE layer annular structure region is 2.3×10 17 cm -3 ~4.5×10 18 cm -3 , the doping concentration window of the JTE layer ring structure area is 42.

7.

6. A method for preparing a silicon carbide power diode with a field plate structure as claimed in any one of claims 1 to 5, characterized in that The following steps are involved: S1: in n + epitaxially growing an i-type SiC epitaxial layer (2) on an i-type SiC substrate layer (1); S2: Then, ion implantation is performed on the i-type SiC epitaxial layer (2) to form a p-type SiC epitaxial layer. + Type SiC layer (3); S3: Then in p + The edge of the SiC layer (3) is also formed with a uniformly doped JTE layer (4) by ion implantation; S4: forming a uniformly doped G-JTE layer (5) at the edge of the JTE layer (4) by ion implantation; S5: After the ion implantation is completed, the device is annealed; S6: epitaxially growing Al2O3 directly above the JTE layer (4) and the G-JTE layer (5); S7: Reactive ion etching is performed on Al2O3 to form a first Al2O3 region (6) directly above the JTE layer (4); then, a second Al2O3 region (7) in an inclined region is formed directly above the G-JTE layer (5) by changing the content of the experimental gas in the reactive ion etching; S8: Finally in p + A Ti / Au metal top electrode (8) is deposited on the n-type SiC layer (3) and the Al2O3 layer; + A Ti / Au metal bottom electrode (9) is evaporated below the SiC substrate layer (1), thereby forming a silicon carbide power diode with a field plate structure.

7. The method for preparing a silicon carbide power diode with a field plate structure according to claim 6, characterized in that: The step S6 specifically comprises the following steps: S61: After the experimental device is assembled, in order to remove the original air impurities in the reaction chamber, nitrogen gas with a flow rate of 150 sccm needs to be introduced into the reaction chamber for 10 min; after the cleaning is completed, nitrogen gas and oxygen gas are introduced to maintain a stable atmosphere in the reaction chamber; S62: Aluminum acetylacetonate was used as the metal source, oxygen as the reaction gas, and nitrogen as the carrier gas. During the heating stage of the experiment, 0.05 g of aluminum acetylacetonate was first weighed and placed in a tube furnace. The temperature was set to 190 °C, and the heating rate was 15 °C / min. The flow rates of oxygen and nitrogen were 5 sccm and 100 sccm, respectively. Thus, Al2O3 with a ring width of 50 μm and a thickness of 12 μm was grown directly above the JTE layer (4) and the G-JTE layer (5).

8. The method for preparing a silicon carbide power diode with a field plate structure according to claim 6, characterized in that: The step S7 specifically includes the following steps: S71: in a reactive ion etching system, 40 sccm of chlorine gas, 4 sccm of boron trichloride and a pressure of 600 mTorr are applied to the system to etch away a ring region with a ring width of 20 μm and a thickness of 7 μm in the Al2O3 directly above the JTE layer (4), thereby forming a first Al2O3 region (6) with a ring width of 20 μm and a thickness of 5 μm directly above the JTE layer (4); S72: Then, the experimental gas content in the system is changed, and 20 sccm of chlorine, 6 sccm of boron trichloride and a pressure of 600 mTorr are applied to the system to etch away the right-angled triangular annular region with a base of 7 μm and a height of 30 μm in the Al2O3 directly above the G-JTE layer (5), thereby forming a second Al2O3 region (7) in a right-angled trapezoidal annular region with a ring width of 30 μm and a thickness increasing from 5 μm to 12 μm directly above the G-JTE layer (5).

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