Bidirectional mixer

Abstract

A bidirectional mixer comprises: a transmitting module, comprising a first transmitting unit, the first transmitting unit comprising a plurality of first transmitting terminal units, the first transmitting terminal unit comprising a first transmitting end capacitor and a first transmitting end transistor; a receiving module, comprising a first receiving unit, the first receiving unit comprising a plurality of first receiving terminal units, the first receiving terminal unit comprising a first receiving end capacitor and a first receiving end transistor; a transmitting control module, connected to the transmitting module, configured to control the transmitting module to be in a working saturation region or in a non-working cutoff region; a receiving control module, connected to the receiving module, configured to control the receiving module to be in a working saturation region or in a non-working cutoff region; an intermediate frequency port, connected to the transmitting module; and a radio frequency port, connected to the receiving module; wherein the drain of the first transmitting end transistor is connected to the first receiving end capacitor, and the drain of the first receiving end transistor is connected to the first transmitting end capacitor.

Description

Technical Field

[0001] The present disclosure relates to the technical field of communication equipment, and in particular to a bidirectional mixer. Background Art

[0002] Traditional phased array transceiver channels are discrete, with one channel used for the uplink, which is amplified and transmitted by a power amplifier after beamforming through a phase shifter and a variable gain amplifier; the other channel is used for the downlink to achieve directional reception of the receiving array. However, since a large number of channels are required in applications such as base stations, the millimeter-wave phased array system consumes a lot of power, has difficulty in heat dissipation, and has an excessively large chip area.

[0003] The integrated mixing function of discrete transmit and receive channels requires discrete mixers and a matching local oscillator distribution network, which further increases power consumption and area occupancy. In addition, the on-board packaging connections are complex, the weight and volume are large, and it is not easy to promote on a large scale. This has already become a constraint on millimeter-wave phased array technology. Summary of the invention

[0004] The embodiments of the present disclosure provide a bidirectional mixer to at least solve at least one of the above or other technical problems existing in the above-mentioned prior art.

[0005] According to an embodiment of the present disclosure, a bidirectional mixer is provided, comprising: a transmitting module, comprising a first transmitting unit, the first transmitting unit comprising a plurality of first transmitting terminal units, the first transmitting terminal unit comprising a first transmitting end capacitor and a first transmitting end transistor; a receiving module, comprising a first receiving unit, the first receiving unit comprising a plurality of first receiving terminal units, the first receiving terminal unit comprising a first receiving end capacitor and a first receiving end transistor; a transmitting control module, connected to the transmitting module, configured to control the transmitting module to be in a working saturation region or in a non-working cutoff region; a receiving control module, connected to the receiving module, configured to control the receiving module to be in a working saturation region or in a non-working cutoff region; an intermediate frequency port, connected to the transmitting module; and an RF port, connected to the receiving module. The drain of the first transmitting end transistor is connected to the first receiving end capacitor, and the drain of the first receiving end transistor is connected to the first transmitting end capacitor, so as to realize cross coupling between the first receiving terminal unit and the first transmitting terminal unit.

[0006] According to the bidirectional mixer of the above embodiment of the present disclosure, the first sending unit in the sending module and the first receiving unit in the receiving module are connected in a cross-coupling manner, specifically, the first sending terminal unit in the first sending unit and the first receiving terminal unit in the first receiving unit are cross-coupled. Based on this connection mode, the sending control module and the receiving control module are controlled to alternately be in a working saturation state and a non-working cutoff state, so that when the sending control module controls the sending module to be in a working saturation area and the receiving control module controls the receiving module to be in a non-working cutoff area, the external frequency signal flows from the intermediate frequency port through the sending module to the radio frequency port to complete the up-conversion process. When the sending control module controls the sending module to be in a non-working cutoff area and the receiving control module controls the receiving module to be in a working saturation area, the external frequency signal flows from the radio frequency port through the receiving module to the intermediate frequency port to complete the down-conversion process.

[0007] Through this cross-coupling connection method, the bidirectional mixer can work in both the down-conversion receiving channel and the up-conversion transmitting channel, simplifying the complexity of the local oscillator distribution network, improving the integration of the phased array front end, saving power consumption, and in the up-conversion process, the transmitting module is in a saturated working state, that is, the transistors in the transmitting module work in the active area, and in the down-conversion process, the receiving module is in a saturated working state, that is, the transistors in the receiving module, in both the transmitting and receiving modes, the bidirectional mixer has a group of transistors working in the active area, with good frequency conversion gain, linearity and noise coefficient, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a simplified circuit connection diagram of a bidirectional mixer according to an illustrative embodiment of the present disclosure.

[0009] [Reference Signs]

[0010] 1: Sending module;

[0011] 2: receiving module;

[0012] 3: Send control module;

[0013] 4: receiving control module;

[0014] 5: IF port;

[0015] 6: RF port;

[0016] 7: first sending unit;

[0017] 8: second sending unit;

[0018] 9: first receiving unit;

[0019] 10: second receiving unit;

[0020] 11: first sending control unit;

[0021] 12: second sending control unit;

[0022] 13: first receiving control unit;

[0023] 14: second receiving control unit;

[0024] 15: first sending terminal unit;

[0025] 16: a first receiving terminal unit;

[0026] 17: second sending terminal unit;

[0027] 18: second receiving terminal unit;

[0028] NM1: first transistor;

[0029] NM2: second transistor;

[0030] NM3: the third transistor;

[0031] NM4: the fourth transistor;

[0032] NM5: fifth transistor;

[0033] NM6: the sixth transistor;

[0034] NM7: seventh transistor;

[0035] NM8: the eighth transistor;

[0036] NM9: ninth transistor;

[0037] NM10: the tenth transistor;

[0038] NM11: eleventh transistor;

[0039] NM12: twelfth transistor;

[0040] NM13: thirteenth transistor;

[0041] NM14: fourteenth transistor;

[0042] NM15: the fifteenth transistor;

[0043] NM16: sixteenth transistor;

[0044] NM17: seventeenth transistor;

[0045] NM18: eighteenth transistor;

[0046] NM19: nineteenth transistor;

[0047] NM20: twentieth transistor;

[0048] C1: first capacitor;

[0049] C2: second capacitor;

[0050] C3: the third capacitor;

[0051] C4: fourth capacitor;

[0052] C5: fifth capacitor;

[0053] C6: sixth capacitor;

[0054] C7: seventh capacitor;

[0055] C8: the eighth capacitor;

[0056] C9: ninth capacitor;

[0057] C10: tenth capacitor;

[0058] C11: eleventh capacitor;

[0059] C12: twelfth capacitor;

[0060] C13: thirteenth capacitor;

[0061] C14: fourteenth capacitor;

[0062] C15: Fifteenth capacitor;

[0063] C16: sixteenth capacitor;

[0064] R1: first resistor;

[0065] R2: second resistor;

[0066] R3: the third resistor;

[0067] R4: the fourth resistor;

[0068] R5: the fifth resistor;

[0069] R6: the sixth resistor;

[0070] R7: seventh resistor;

[0071] R8: the eighth resistor;

[0072] R9: ninth resistor;

[0073] R10: tenth resistor;

[0074] R11: eleventh resistor;

[0075] R12: twelfth resistor;

[0076] R13: thirteenth resistor;

[0077] R14: fourteenth resistor;

[0078] IF_P: positive intermediate frequency port;

[0079] IF_N: negative intermediate frequency port;

[0080] RF_P: positive RF port;

[0081] RF_N: negative RF port;

[0082] LO_A: the first local oscillator signal terminal;

[0083] LO_B: the second local oscillator signal terminal;

[0084] VB1: first external power supply;

[0085] VB2: second external power supply;

[0086] TX_ENB: external transmit signal;

[0087] RX_ENB: external receive signal. DETAILED DESCRIPTION

[0088] In order to make the purpose, technical scheme and advantages of the present disclosure more clear, the present disclosure is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and fully convey the scope of the present disclosure to those skilled in the art. In the accompanying drawings, for clarity, the sizes and relative sizes of layers and regions may be exaggerated, and the same reference numerals represent the same elements throughout.

[0089] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0090] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0091] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification, and should not be interpreted in an idealized or overly rigid manner.

[0092] In order to facilitate those skilled in the art to understand the technical solution of the present disclosure, the following technical terms are explained.

[0093] In the case of using expressions such as "at least one of A, B, and C, etc.", it should generally be interpreted in accordance with the meaning of the expression generally understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.). In the case of using expressions such as "at least one of A, B, or C, etc.", it should generally be interpreted in accordance with the meaning of the expression generally understood by those skilled in the art (for example, "a system having at least one of A, B, or C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0094] In the process of implementing the present disclosure, it is found that the passive bidirectional mixer in the related art only retains the passive switch field effect transistor in the linear region in the working state, although it can realize the bidirectional mixing function, it has no gain and low output power; the unidirectional active bidirectional mixer in the related art makes the switch transistor in one direction work in the cutoff region, and obtains gain, but the switch tube in the other direction still needs to work in the linear region. In order to compensate for the gain, an additional bidirectional amplifier needs to be added, which will deteriorate the overall linearity. Through analysis, although the existing technology can realize the bidirectional mixing function, the methods for realizing bidirectional mixing have obvious shortcomings.

[0095] Figure 1 It is a simplified circuit connection diagram of a bidirectional mixer according to an illustrative embodiment of the present disclosure.

[0096] The embodiment of the present disclosure provides a bidirectional mixer, such as Figure 1 As shown, the bidirectional mixer includes: a sending module 1, a receiving module 2, a sending control module 3, a receiving control module 4, an intermediate frequency port 5 and a radio frequency port 6.

[0097] The sending module 1 includes a first sending unit 7 , which includes a plurality of first sending terminal units 15 , which includes a first sending terminal capacitor and a first sending terminal transistor. The intermediate frequency port 5 is connected to the sending module 1 .

[0098] The receiving module 2 includes a first receiving unit 9 , which includes a plurality of first receiving terminal units 16 , which includes a first receiving terminal capacitor and a first receiving terminal transistor. The RF port 6 is connected to the receiving module 2 .

[0099] The sending control module 3 is connected to the sending module 1 and is configured to control the sending module 1 to be in a working saturation region or a non-working cut-off region.

[0100] The receiving control module 4 is connected to the receiving module 2 and is configured to control the receiving module 2 to be in a working saturation region or a non-working cut-off region.

[0101] The drain of the first transmitting-end transistor is connected to the first receiving-end capacitor, and the drain of the first receiving-end transistor is connected to the first transmitting-end capacitor, so as to realize cross-coupling between the first receiving terminal unit 16 and the first transmitting terminal unit 15 .

[0102] In some embodiments, when the sending control module 3 controls the sending module 1 to be in the working saturation area and the receiving control module 4 controls the receiving module 2 to be in the non-working cutoff area, the external frequency signal flows from the intermediate frequency port 5 through the sending module 1 to the radio frequency port 6 to complete the up-conversion process; when the sending control module 3 controls the sending module 1 to be in the non-working cutoff area and the receiving control module 4 controls the receiving module 2 to be in the working saturation area, the external frequency signal flows from the radio frequency port 6 through the receiving module 2 to the intermediate frequency port to complete the down-conversion process.

[0103] In detail, the bidirectional mixer is connected by cross-coupling the first sending unit 7 in the sending module 1 and the first receiving unit 9 in the receiving module 2, specifically, by cross-coupling the first sending terminal unit 15 in the first sending unit 7 and the first receiving terminal unit 16 in the first receiving unit 9. Based on this connection mode, the sending control module 3 and the receiving control module 4 control the sending module 1 and the receiving module 2 to be alternately in the working saturation state and the non-working cutoff state, so that when the sending control module 3 controls the sending module 1 to be in the working saturation area and the receiving control module 4 controls the receiving module 2 to be in the non-working cutoff area, the external frequency signal flows from the intermediate frequency port 5 through the sending module 1 to the radio frequency port 6 to complete the up-conversion process; when the sending control module 3 controls the sending module 1 to be in the non-working cutoff area and the receiving control module 4 controls the receiving module 2 to be in the working saturation area, the external frequency signal flows from the radio frequency port 6 to the intermediate frequency port through the receiving module 2 to complete the down-conversion process.

[0104] Furthermore, through this cross-coupling connection mode, the bidirectional mixer can work in both the down-conversion receiving channel and the up-conversion transmitting channel, which simplifies the complexity of the local oscillator distribution network, improves the integration of the phased array front end, saves power consumption, and in the up-conversion process, the transmitting module is in a saturated working state, that is, the transistors in the transmitting module work in the active area, and in the down-conversion process, the receiving module is in a saturated working state, that is, the transistors in the receiving module, that is, in both the transmitting and receiving modes, the bidirectional mixer has a group of transistors working in the active area, has good frequency conversion gain, linearity and noise coefficient, etc., and can be used to reduce the front-end circuit scale of the fifth generation (5G) mobile communication base station.

[0105] Furthermore, if Figure 1 As shown, the first sending unit 7 may include two first sending terminal units 15, and the first receiving unit 9 may include two first receiving terminal units 16, that is, the third transistor NM3 and the fourth transistor NM4 in the first sending terminal unit 15 are first sending end transistors, the seventh transistor NM7 and the eighth transistor NM8 in the first receiving terminal unit 16 are first receiving end transistors, the fifth capacitor C5 and the sixth capacitor C6 in the first sending terminal unit 15 are first sending end capacitors, and the ninth capacitor C9 and the tenth capacitor C10 in the first receiving terminal unit 16 are first sending end capacitors.

[0106] In detail, the drain of the third transistor NM3 is connected to one end of the ninth capacitor C9 close to the outside of the first receiving terminal unit 16, and the drain of the seventh transistor NM7 is connected to one end of the fifth capacitor C5 close to the outside of the first sending terminal unit 15; similarly, the drain of the fourth transistor NM4 is connected to one end of the tenth capacitor C10 close to the outside of the first receiving terminal unit 16, and the drain of the eighth transistor NM8 is connected to one end of the sixth capacitor C6 close to the outside of the first sending terminal unit 15, so as to realize cross-coupling of the two first receiving terminal units 16 and the two first sending terminal units 15, so that the frequency signal in the circuit can include 4 paths when in two directions from the first sending unit 7 to the first receiving unit 9 or from the first receiving unit 9 to the first sending unit 7.

[0107] Further, when the sending control module 3 controls the sending module 1 to be in the working saturation area and the receiving control module 4 controls the receiving module 2 to be in the non-working cutoff area, when the external frequency signal arrives at the cross-coupling from the intermediate frequency port 5 through the sending module 1, since the seventh transistor NM7 and the eighth transistor NM8 are in the non-working cutoff state, the frequency signal does not pass through the branch where the seventh transistor NM7 and the eighth transistor NM8 are located, and directly flows to the RF port 6 through the branch where the third transistor NM3 and the fourth transistor NM4 are located, completing the up-conversion process.

[0108] Similarly, when the sending control module 3 controls the sending module 1 to be in the non-working cutoff area and the receiving control module 4 controls the receiving module 2 to be in the working saturation area, when the external frequency signal arrives at the cross-coupling from the RF port 6 through the receiving module 2, since the third transistor NM3 and the fourth transistor NM4 are in the non-working cutoff state, the frequency signal does not pass through the branch where the third transistor NM3 and the fourth transistor NM4 are located, and directly flows to the intermediate frequency port 5 through the branch where the seventh transistor NM7 and the eighth transistor NM8 are located, completing the down-conversion process.

[0109] In some embodiments, the sending module 1 also includes a second sending unit 8, the second sending unit 8 includes multiple groups of second sending terminal units 17, the second sending terminal unit 17 includes a second sending end capacitor and a second sending end transistor; the receiving module 2 includes a second receiving unit 10, the second receiving unit 10 includes multiple groups of second receiving terminal units 18, the second receiving terminal unit 18 includes a second receiving end capacitor and a second receiving end transistor; the sending control module 3 includes a first sending control unit 11 and a second sending control unit 12; the receiving control module 4 includes a first receiving control unit 13 and a second receiving control unit 14; the intermediate frequency port 5 includes a positive intermediate frequency port IF_P and a negative intermediate frequency port IF_N; the RF port 6 includes a positive RF port RF_P and a negative RF port RF_N.

[0110] In detail, the second transmitting unit 8 is cross-coupled with the second receiving unit 10; the positive intermediate frequency port IF_P and the negative intermediate frequency port IF_N are both connected to the first transmitting unit 7 and the second transmitting unit 8; the positive radio frequency port RF_P and the negative radio frequency port RF_N are both connected to the first receiving unit 9 and the second receiving unit 10.

[0111] In detail, the first transmitting end capacitor is connected to the second transmitting end capacitor to realize a double balanced connection between the first transmitting unit 7 and the second transmitting unit 8; the second receiving end capacitor is connected to the first receiving end capacitor to realize a double balanced connection between the first receiving unit 9 and the second receiving unit 10.

[0112] Furthermore, if Figure 1 As shown, the second sending unit 8 and the second receiving unit 10, like the first sending unit 7 and the first receiving unit 9, also include multiple groups of second sending terminal units 17 and second receiving terminal units 18. Similarly, the second sending terminal capacitor, the second sending terminal transistor, the second receiving terminal capacitor and the second receiving terminal transistor in the second sending terminal unit 17 and the second receiving terminal unit 18 are used to realize cross-coupling of the second sending terminal unit 17 and the second receiving terminal unit 18, thereby realizing cross-coupling of the second sending unit 8 and the second receiving unit 10. This has been described in detail above and will not be repeated here.

[0113] Furthermore, if Figure 1 , the second transmitting end capacitor in the second transmitting terminal unit 17 is the seventh capacitor C7 and the eighth capacitor C8, and the second transmitting end capacitor in the second receiving terminal unit 18 is the eleventh capacitor C11 and the twelfth capacitor C12. The seventh capacitor C7 is connected to the fifth capacitor C5, the eighth capacitor C8 is connected to the sixth capacitor C6, the eleventh capacitor C11 is connected to the tenth capacitor C10, and the twelfth capacitor C12 is connected to the ninth capacitor C9, thereby realizing the double balanced connection of the first transmitting unit 7 and the second transmitting unit 8; the double balanced connection of the first receiving unit 9 and the second receiving unit 10, and then realizing the double balanced connection of the bidirectional mixer.

[0114] Furthermore, the connection mode in which the seventh capacitor C7 is connected to the fifth capacitor C5, the eighth capacitor C8 is connected to the sixth capacitor C6, the eleventh capacitor C11 is connected to the tenth capacitor C10, and the twelfth capacitor C12 is connected to the ninth capacitor C9 can also be replaced by the connection mode in which the seventh capacitor C7 is connected to the sixth capacitor C6, the fifth capacitor C5 is connected to the eighth capacitor C8, the eleventh capacitor C11 is connected to the ninth capacitor C9, and the tenth capacitor C10 is connected to the twelfth capacitor C12, which can also achieve the effect of double balanced connection of the first sending unit 7 and the second sending unit 8, and double balanced connection of the first receiving unit 9 and the second receiving unit 10, thereby realizing the double balanced connection of the bidirectional mixer.

[0115] Furthermore, when the bidirectional mixer undergoes up-conversion, the first transmitting control unit 11 controls and the second transmitting control unit 12 jointly controls the first transmitting unit 7 and the second transmitting unit 8 to be in the working saturation area, the first receiving control unit 13 and the second receiving control unit 14 jointly control the first receiving unit 9 and the second receiving unit 10 to be in the non-working cutoff area, and the external frequency signal passes through the first transmitting unit 7 and the second transmitting unit 8 from the positive intermediate frequency port IF_P and the negative intermediate frequency port IF_N. When passing through the cross-coupling point, it no longer passes through the first receiving unit 9 and the second receiving unit 10 but flows directly to the positive RF port RF_P and the negative RF port RF_N.

[0116] Similarly, when the bidirectional mixer undergoes down-conversion, the first transmission control unit 11 controls and the second transmission control unit 12 jointly controls the first transmission unit 7 and the second transmission unit 8 to be in the non-working cutoff area, the first reception control unit 13 and the second reception control unit 14 jointly control the first reception unit 9 and the second reception unit 10 to be in the working saturation area, and the external frequency signal passes through the first reception unit 9 and the second reception unit 10 from the positive RF port RF_P and the negative RF port RF_N. When passing through the cross-coupling, it no longer passes through the first transmission unit 7 and the second transmission unit 8 but flows directly to the positive intermediate frequency port IF_P and the negative intermediate frequency port IF_N. Due to the presence of parasitic parameters in the circuit, the local oscillator and the RF signal will leak to the intermediate frequency port, and the double balanced connection can make the leakage signals of opposite polarities cancel each other, thereby improving the port isolation.

[0117] In some embodiments, the first sending unit 7 includes: a first transistor NM1, a third resistor R3, a third capacitor C3, a first local oscillation signal terminal LO_A, a fourth transistor NM4, a fifth capacitor C5, a sixth capacitor C6, a fifth resistor R5 and a sixth resistor R6.

[0118] In detail, the source of the first transistor NM1 is grounded; one end of the third resistor R3 is connected to the gate of the first transistor NM1, and the other end of the third resistor R3 is connected to the first sending control unit 11; one end of the third capacitor C3 is connected to the gate of the first transistor NM1; the first local oscillation signal terminal LO_A is connected to the other end of the third capacitor C3; the source of the third transistor NM3 is connected to the drain of the first transistor NM1, and the drain of the third transistor NM3 is connected to the first receiving unit 9; the source of the fourth transistor NM4 is connected to the drain of the first transistor NM1, and the fourth transistor The drain of the transistor NM4 is connected to the first receiving unit 9; one end of the fifth capacitor C5 is connected to the gate of the third transistor NM3, and the other end is connected to the second sending unit 8 and the first receiving unit 9; one end of the sixth capacitor C6 is connected to the gate of the fourth transistor NM4, and the other end is connected to the second sending unit 8 and the first receiving unit 9; one end of the fifth resistor R5 is connected between the fifth capacitor C5 and the gate of the third transistor NM3; one end of the sixth resistor R6 is connected between the sixth capacitor C6 and the gate of the fourth transistor NM4, and the other end is connected to the other end of the fifth resistor R5.

[0119] Furthermore, a second sending control unit is connected between the fifth resistor R5 and the sixth resistor R6; when the signal input to the first local oscillator signal terminal LO_A is a differential signal, the bidirectional mixer is in a bidirectional non-orthogonal mixing mode; when the signal input to the first local oscillator signal terminal LO_A is a single-ended orthogonal signal, the bidirectional mixer is in a bidirectional orthogonal mixing mode.

[0120] In some embodiments, the second sending unit 8 includes: a second transistor NM2, a fourth resistor R4, a fourth capacitor C4, a second local oscillation signal terminal LO_B, a sixth transistor NM6, a seventh capacitor C7, an eighth capacitor C8, a seventh resistor R7 and an eighth resistor R8.

[0121] In detail, the source of the second transistor NM2 is grounded; one end of the fourth resistor R4 is connected to the gate of the second transistor NM2, and the other end of the fourth resistor R4 is connected to the first sending control unit 11; one end of the fourth capacitor C4 is connected to the gate of the second transistor NM2; the second local oscillation signal terminal LO_B is connected to the other end of the fourth capacitor C4; the source of the fifth transistor NM5 is connected to the drain of the second transistor NM2, and the drain of the fifth transistor NM5 is connected to the second receiving unit 10; the source of the sixth transistor NM6 is connected to the drain of the second transistor NM2, and the drain of the sixth transistor NM6 is connected to the second receiving unit 10; One end of the capacitor C7 is connected to the gate of the fifth transistor NM5, and the other end is connected to the fifth capacitor C5 of the first sending unit 7 and the second receiving unit 10; one end of the eighth capacitor C8 is connected to the gate of the sixth transistor NM6, and the other end is connected to the sixth capacitor C6 of the first sending unit 7 and the second receiving unit 10; one end of the seventh resistor R7 is connected between the seventh capacitor C7 and the gate of the fifth transistor NM5; one end of the eighth resistor R8 is connected between the eighth capacitor C8 and the gate of the sixth transistor NM6, and the other end is connected to the other end of the seventh resistor R7; the second sending control unit is connected between the seventh resistor R7 and the eighth resistor R8.

[0122] In some embodiments, the first receiving unit 9 includes: an eleventh transistor NM11, a thirteenth resistor R13, a thirteenth capacitor C13, a first local oscillation signal terminal LO_A, a seventh transistor NM7, an eighth transistor NM8, a ninth capacitor C9, a tenth capacitor C10, a ninth resistor R9 and a tenth resistor R10.

[0123] The source of the eleventh transistor NM11 is grounded; one end of the thirteenth resistor R13 is connected to the gate of the eleventh transistor NM11, and the other end of the thirteenth resistor R13 is connected to the first receiving control unit 13; one end of the thirteenth capacitor C13 is connected to the gate of the eleventh transistor NM11; the first local oscillation signal terminal LO_A is connected to the other end of the thirteenth capacitor C13; the source of the seventh transistor NM7 is connected to the drain of the eleventh transistor NM11, and the drain of the seventh transistor NM7 is connected between the fifth capacitor C5 and the seventh capacitor C7; the source of the eighth transistor NM8 is connected to the drain of the eleventh transistor NM11, and the drain of the seventh transistor NM7 is connected to the sixth capacitor C5. C6 and the eighth capacitor C8; one end of the ninth capacitor C9 is connected to the gate of the seventh transistor NM7, and the other end is connected to the drain of the third transistor NM3 and the second receiving unit 10; one end of the tenth capacitor C10 is connected to the gate of the eighth transistor NM8, and the other end is connected to the drain of the fourth transistor NM4 and the second receiving unit 10; one end of the ninth resistor R9 is connected between the ninth capacitor C9 and the gate of the seventh transistor NM7; one end of the tenth resistor R10 is connected between the tenth capacitor C10 and the gate of the eighth transistor NM8, and the other end is connected to the other end of the ninth resistor R9; the second receiving control unit 14 is connected between the ninth resistor R9 and the tenth resistor R10.

[0124] In some embodiments, the second receiving unit 10 includes: a twelfth transistor NM12,

[0125] a fourteenth resistor R14, a fourteenth capacitor C14, a second local oscillation signal terminal LO_B, a ninth transistor NM9, a tenth transistor NM10, an eleventh capacitor C11, a twelfth capacitor C12, an eleventh resistor R11, and a twelfth resistor R12.

[0126] In detail, the source of the twelfth transistor NM12 is grounded; one end of the fourteenth resistor R14 is connected to the gate of the twelfth transistor NM12, and the other end of the fourteenth resistor R14 is connected to the first receiving control unit 13; one end of the fourteenth capacitor C14 is connected to the gate of the twelfth transistor NM12; the second local oscillation signal terminal LO_B is connected to the other end of the fourteenth capacitor C14; the source of the ninth transistor NM9 is connected to the drain of the twelfth transistor NM12, and the drain of the ninth transistor NM9 is connected between the seventh capacitor C7 and the fifth capacitor C5; the source of the tenth transistor NM10 is connected to the drain of the twelfth transistor NM12, and the drain of the tenth transistor NM10 is connected between the sixth capacitor C6 and the eighth capacitor C8 one end of an eleventh capacitor C11 is connected to the gate of the ninth transistor NM9, and the other end is connected to the tenth capacitor C10 and the drain of the fifth transistor NM5; one end of a twelfth capacitor C12 is connected to the gate of the tenth transistor NM10, and the other end is connected to the ninth capacitor C9 and the drain of the sixth transistor NM6; one end of an eleventh resistor R11 is connected between the eleventh capacitor C11 and the gate of the ninth transistor NM9; a twelfth resistor R12, wherein one end of the twelfth resistor R12 is connected between the twelfth capacitor C12 and the gate of the tenth transistor NM10, and the other end is connected to the other end of the eleventh resistor R11; a second receiving control unit 14 is connected between the eleventh resistor R11 and the twelfth resistor R12.

[0127] In some embodiments, the first transmission control unit 11 includes a fifteenth transistor NM15 and a nineteenth transistor NM19 , and the second transmission control unit 12 includes a sixteenth transistor NM16 and a twentieth transistor NM20 .

[0128] In detail, the drain of the fifteenth transistor NM15 is connected to the third resistor R3 and the fourth resistor R4, the source of the fifteenth transistor NM15 is connected to the first external power supply VB1, and the gate of the fifteenth transistor NM15 is connected to the external transmission signal; the drain of the nineteenth transistor NM19 is connected to the drain of the fifteenth transistor NM15, the source of the nineteenth transistor NM19 is grounded, and the gate of the nineteenth transistor NM19 is connected to the external reception signal; the drain of the sixteenth transistor NM16 is connected between the fifth resistor R5 and the sixth resistor R6, and is connected between the seventh resistor R7 and the eighth resistor R8; the source of the sixteenth transistor NM16 is connected to the second external power supply VB2, and the gate of the sixteenth transistor NM16 is connected to the external transmission signal TX_ENB; the drain of the twentieth transistor NM20 is connected to the drain of the sixteenth transistor NM16, the source of the twentieth transistor NM20 is grounded, and the gate of the twentieth transistor NM20 is connected to the external reception signal RX_ENB.

[0129] In some embodiments, the first receiving control unit 13 includes a thirteenth transistor NM13 and a seventeenth transistor NM17 , and the second receiving control unit 14 includes a fourteenth transistor NM14 and an eighteenth transistor NM18 .

[0130] In detail, the drain of the thirteenth transistor NM13 is connected to the thirteenth resistor R13 and the fourteenth resistor R14, the source of the thirteenth transistor NM13 is connected to the first external power supply VB1, and the gate of the thirteenth transistor NM13 is connected to the external receiving signal RXENB; the drain of the seventeenth transistor NM17 is connected to the drain of the thirteenth transistor NM13, the source of the seventeenth transistor NM17 is grounded, and the gate of the seventeenth transistor NM17 is connected to the external sending signal TX_ENB; the fourteenth transistor NM14 The drain of the eighteenth transistor NM18 is connected between the ninth resistor R9 and the tenth resistor R10, and is connected between the eleventh resistor R11 and the twelfth resistor R12; the source of the fourteenth transistor NM14 is connected to the second external power supply VB2, and the gate of the fourteenth transistor NM14 is connected to the external receiving signal RX_ENB; the drain of the eighteenth transistor NM18 is connected to the drain of the fourteenth transistor NM14, the source of the eighteenth transistor NM18 is grounded, and the gate of the eighteenth transistor NM18 is connected to the external sending signal TX_ENB.

[0131] In some embodiments, the positive intermediate frequency port IF_P is connected between the fifth capacitor C5 and the seventh capacitor C7 through the first capacitor C1; the negative intermediate frequency port IF_N is connected between the sixth capacitor C6 and the eighth capacitor C8 through the second capacitor C2; the positive radio frequency port RF_P is connected between the ninth capacitor C9 and the twelfth capacitor C12; and the negative radio frequency port RF_N is connected between the tenth capacitor C10 and the eleventh capacitor C11.

[0132] In detail, when the external transmission signal TX_ENB is at a high level, the fifteenth transistor NM15, the sixteenth transistor NM16, the seventeenth transistor NM17 and the eighteenth transistor NM18 are in an on state, the thirteenth transistor NM13, the fourteenth transistor NM14, the nineteenth transistor NM19 and the twentieth transistor NM20 are in an off state, providing a bias level for the first transistor NM1, the second transistor NM2, the third transistor NM3, the fourth transistor NM4, the fifth transistor NM5 and the sixth transistor NM6 and pulling the bias of the seventh transistor NM7, the eighth transistor NM8, the ninth transistor NM9, the tenth transistor NM10, the eleventh transistor NM11 and the twelfth transistor NM12 to a low level.

[0133] Further, the intermediate frequency signal is input from the positive intermediate frequency port IF_P and the negative intermediate frequency port IF_N, and in the first transmitting unit 7, passes through the fifth capacitor C5 and the sixth capacitor C6 to the gates of the third transistor NM3 and the fourth transistor NM4 respectively, and the third transistor NM3, the fourth transistor NM4 and the first transistor NM1 convert the local oscillator signal and the intermediate frequency signal from the first local oscillator signal terminal LO_A into an up-converted signal and outputs it from the positive radio frequency port RF_P and the negative radio frequency port RF_N. Similarly, in the second transmitting unit 8, passes through the seventh capacitor C7 and the eighth capacitor C8 to the gates of the fifth transistor NM5 and the sixth transistor NM6 respectively, and the fifth transistor NM5, the sixth transistor NM6 and the second transistor NM2 convert the local oscillator signal and the intermediate frequency signal from the second local oscillator signal terminal LO_B into an up-converted signal and outputs it from the positive radio frequency port RF_P and the negative radio frequency port RF_N.

[0134] Further, when the external receiving signal RX_ENB is at a high level, the fifteenth transistor NM15, the sixteenth transistor NM16, the seventeenth transistor NM17 and the eighteenth transistor NM18 are in a closed state, the thirteenth transistor NM13, the fourteenth transistor NM14, the nineteenth transistor NM19 and the twentieth transistor NM20 are in an open state, providing a bias level for the seventh transistor NM7, the eighth transistor NM8, the ninth transistor NM9, the tenth transistor NM10, the eleventh transistor NM11 and the twelfth transistor NM12 and pulling the bias of the first transistor NM1, the second transistor NM2, the third transistor NM3, the fourth transistor NM4, the fifth transistor NM5 and the sixth transistor NM6 to a low level.

[0135] Further, the RF signal is input from the positive RF port RF_P and the negative RF port RF_N, and in the first receiving unit 9, the RF signal passes through the ninth capacitor C9 and the tenth capacitor C10 to the gates of the seventh transistor NM7 and the eighth transistor NM8 respectively, and the seventh transistor NM7, the eighth transistor NM8 and the eleventh transistor NM11 convert the local oscillator signal and the RF signal from the first local oscillator signal terminal LO_A into down-converted signals and output them from the positive intermediate frequency port IF_P and the negative intermediate frequency port IF_N. Similarly, in the second receiving unit 10, the RF signal passes through the eleventh capacitor C11 and the twelfth capacitor C12 to the gates of the ninth transistor NM9 and the tenth transistor NM10 respectively, and the ninth transistor NM9, the tenth transistor NM10 and the twelfth transistor NM12 convert the local oscillator signal and the RF signal from the second local oscillator signal terminal LO_B into down-converted signals and output them from the positive intermediate frequency port IF_P and the negative intermediate frequency port IF_N.

[0136] Furthermore, when the signal input to the first local oscillator signal terminal LO_A forms a differential signal with the signal input to the second local oscillator signal terminal LO_B, that is, the local oscillator signal voltages have the same amplitude and opposite phases, the bidirectional mixer is in a double-balanced mixing mode and the port isolation is high.

[0137] In detail, the first transistor NM1, the second transistor NM2, the eleventh transistor NM11, and the twelfth transistor NM12 can be stable current sources, and the first resistor R1 and the second resistor R2 can be replaced by other baseband amplifiers or active loads; the first transistor NM1 and the second transistor NM2 can be implemented by other process N-type or P-type devices (such as PMOS transistors and NPN transistors).

[0138] In detail, Figure 1 As shown, it also includes an external power supply VDD, a first resistor R1 and a second resistor R2. The external power supply VDD is connected in series with the first resistor R1 and the second resistor R2 respectively. The first resistor R1 and the second resistor R2 are connected in parallel. The other end of the first resistor R1 is connected between the fifth capacitor C5 and the seventh capacitor C7.

[0139] In detail, Figure 1 As shown, the fifteenth capacitor C15, the sixteenth capacitor C16 and the electromagnetic coupler L1-L2 are also included. The fifteenth capacitor C15, the sixteenth capacitor C16 and the electromagnetic coupler L1-L2 are all connected between the positive radio frequency port RF_P and the negative radio frequency port RF_N.

[0140] It should also be noted that the directional terms mentioned in the embodiments, such as "upper", "lower", "front", "back", "left", "right", etc., are only reference directions of the drawings and are not intended to limit the scope of protection of the present disclosure. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure, and the shapes and sizes of the components in the drawings do not reflect the actual size and proportion, but only illustrate the contents of the embodiments of the present disclosure.

[0141] Unless otherwise indicated, the numerical parameters in this specification and the appended claims are approximate values ​​and can vary according to the desired properties obtained through the content of the present disclosure. Specifically, all numbers used in the specification and claims to express the content of the composition, reaction conditions, etc., should be understood to be modified by the term "about" in all cases. In general, the meaning of the expression is to include a variation of ±10% in some embodiments, ±5% in some embodiments, ±1% in some embodiments, and ±0.5% in some embodiments by a specific number.

[0142] The ordinal numbers used in the specification and claims, such as "first", "second", "third", etc., to modify the corresponding elements, do not themselves mean that the elements have any ordinal numbers, nor do they represent the order of one element and another element, or the order in the manufacturing method. The use of these ordinal numbers is only used to clearly distinguish a component with a certain name from another component with the same name.

[0143] In addition, unless the steps are specifically described or must occur in sequence, the order of the above steps is not limited to the above list, and can be changed or rearranged according to the required design. And the above embodiments can be mixed and matched with each other or with other embodiments based on design and reliability considerations, that is, the technical features in different embodiments can be freely combined to form more embodiments.

[0144] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above description is only a specific embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A bidirectional mixer, comprising: A sending module (1) comprising a first sending unit (7), wherein the first sending unit (7) comprises a plurality of groups of first sending terminal units (15), and the first sending terminal units (15) comprise a first sending end capacitor and a first sending end transistor; A receiving module (2) comprising a first receiving unit (9), wherein the first receiving unit (9) comprises a plurality of groups of first receiving terminal units (16), and the first receiving terminal units (16) comprise a first receiving end capacitor and a first receiving end transistor; A sending control module (3), connected to the sending module (1), and configured to control the sending module (1) to be in a working saturation region or in a non-working cut-off region; A receiving control module (4), connected to the receiving module (2), and configured to control the receiving module (2) to be in a working saturation region or a non-working cut-off region; An intermediate frequency port (5) connected to the sending module (1); as well as A radio frequency port (6) connected to the receiving module (2); The drain of the first transmitting-end transistor is connected to the first receiving-end capacitor, and the drain of the first receiving-end transistor is connected to the first transmitting-end capacitor, so as to achieve cross-coupling between the first receiving terminal unit (16) and the first transmitting terminal unit (15); Wherein, when the sending control module (3) controls the sending module (1) to be in a working saturation region and the receiving control module (4) controls the receiving module (2) to be in a non-working cut-off region, the external frequency signal flows from the intermediate frequency port (5) through the sending module (1) to the radio frequency port (6), thereby completing the up-conversion process; when the sending control module (3) controls the sending module (1) to be in a non-working cut-off region and the receiving control module (4) controls the receiving module (2) to be in a working saturation region, the external frequency signal flows from the radio frequency port (6) through the receiving module (2) to the intermediate frequency port (5), thereby completing the down-conversion process.

2. The bidirectional mixer according to claim 1, wherein: The transmitting module (1) further comprises a second transmitting unit (8), the second transmitting unit (8) comprising a plurality of groups of second transmitting terminal units (17), the second transmitting terminal unit (17) comprising a second transmitting end capacitor and a second transmitting end transistor, the first transmitting end capacitor being connected to the second transmitting end capacitor to achieve a double balanced connection between the first transmitting unit (7) and the second transmitting unit (8); The receiving module (2) comprises a second receiving unit (10), the second receiving unit (10) comprises a plurality of groups of second receiving terminal units (18), the second receiving terminal unit (18) comprises a second receiving end capacitor and a second receiving end transistor, the second receiving end capacitor is connected to the first receiving end capacitor to achieve a double balanced connection between the first receiving unit (9) and the second receiving unit (10); The transmission control module (3) comprises a first transmission control unit (11) and a second transmission control unit (12); The receiving control module (4) comprises a first receiving control unit (13) and a second receiving control unit (14); The intermediate frequency port (5) comprises a positive intermediate frequency port (IF_P) and a negative intermediate frequency port (IF_N); and The radio frequency port (6) comprises a positive radio frequency port (RF_P) and a negative radio frequency port (RF_N); The second transmitting unit (8) is cross-coupled with the second receiving unit (10); the positive intermediate frequency port (IF_P) and the negative intermediate frequency port (IF_N) are both connected to the first transmitting unit (7) and the second transmitting unit (8); and the positive radio frequency port (RF_P) and the negative radio frequency port (RF_N) are both connected to the first receiving unit (9) and the second receiving unit (10).

3. The bidirectional mixer according to claim 2, wherein: The first sending unit (7) comprises: A first transistor (NM1), wherein a source of the first transistor (NM1) is grounded; a third resistor (R3), wherein one end of the third resistor (R3) is connected to the gate of the first transistor (NM1), and the other end of the third resistor (R3) is connected to the first sending control unit (11); a third capacitor (C3), wherein one end of the third capacitor (C3) is connected to the gate of the first transistor (NM1); A first local oscillator signal terminal (LO_A) is connected to the other end of the third capacitor (C3); a third transistor (NM3), wherein a source of the third transistor (NM3) is connected to a drain of the first transistor (NM1), and a drain of the third transistor (NM3) is connected to the first receiving unit (9); a fourth transistor (NM4), wherein a source of the fourth transistor (NM4) is connected to a drain of the first transistor (NM1), and a drain of the fourth transistor (NM4) is connected to the first receiving unit (9); a fifth capacitor (C5), wherein one end of the fifth capacitor (C5) is connected to the gate of the third transistor (NM3), and the other end of the fifth capacitor (C5) is connected to the second sending unit (8) and the first receiving unit (9); a sixth capacitor (C6), wherein one end of the sixth capacitor (C6) is connected to the gate of the fourth transistor (NM4), and the other end of the sixth capacitor (C6) is connected to the second sending unit (8) and the first receiving unit (9); a fifth resistor (R5), wherein one end of the fifth resistor (R5) is connected between the fifth capacitor (C5) and the gate of the third transistor (NM3); and a sixth resistor (R6), wherein one end of the sixth resistor (R6) is connected between the sixth capacitor (C6) and the gate of the fourth transistor (NM4), and the other end is connected to the other end of the fifth resistor (R5); Wherein, the second sending control unit is connected between the fifth resistor (R5) and the sixth resistor (R6).

4. The bidirectional mixer according to claim 3, wherein: The second sending unit (8) comprises: a second transistor (NM2), wherein a source of the second transistor (NM2) is grounded; a fourth resistor (R4), wherein one end of the fourth resistor (R4) is connected to the gate of the second transistor (NM2), and the other end of the fourth resistor (R4) is connected to the first sending control unit (11); a fourth capacitor (C4), wherein one end of the fourth capacitor (C4) is connected to the gate of the second transistor (NM2); A second local oscillator signal terminal (LO_B) is connected to the other end of the fourth capacitor (C4); a fifth transistor (NM5), wherein a source of the fifth transistor (NM5) is connected to a drain of the second transistor (NM2), and a drain of the fifth transistor (NM5) is connected to the second receiving unit (10); a sixth transistor (NM6), wherein a source of the sixth transistor (NM6) is connected to a drain of the second transistor (NM2), and a drain of the sixth transistor (NM6) is connected to the second receiving unit (10); a seventh capacitor (C7), wherein one end of the seventh capacitor (C7) is connected to the gate of the fifth transistor (NM5), and the other end of the seventh capacitor (C7) is connected to the fifth capacitor (C5) of the first sending unit (7) and the second receiving unit (10); an eighth capacitor (C8), wherein one end of the eighth capacitor (C8) is connected to the gate of the sixth transistor (NM6), and the other end of the eighth capacitor (C8) is connected to the sixth capacitor (C6) of the first sending unit (7) and the second receiving unit (10); a seventh resistor (R7), wherein one end of the seventh resistor (R7) is connected between the seventh capacitor (C7) and the gate of the fifth transistor (NM5); and an eighth resistor (R8), wherein one end of the eighth resistor (R8) is connected between the eighth capacitor (C8) and the gate of the sixth transistor (NM6), and the other end is connected to the other end of the seventh resistor (R7); The second transmission control unit is connected between the seventh resistor (R7) and the eighth resistor (R8); when the signal input from the first local oscillator signal terminal (LO_A) and the signal input from the second local oscillator signal terminal (LO_B) form a differential signal, the bidirectional mixer is in a double-balanced mixing mode.

5. The bidirectional mixer according to claim 4, wherein: The first receiving unit (9) comprises: an eleventh transistor (NM11), wherein a source of the eleventh transistor (NM11) is grounded; a thirteenth resistor (R13), wherein one end of the thirteenth resistor (R13) is connected to the gate of the eleventh transistor (NM11), and the other end of the thirteenth resistor (R13) is connected to the first receiving control unit (13); a thirteenth capacitor (C13), wherein one end of the thirteenth capacitor (C13) is connected to the gate of the eleventh transistor (NM11); The first local oscillator signal terminal (LO_A) is connected to the other end of the thirteenth capacitor (C13); a seventh transistor (NM7), wherein a source of the seventh transistor (NM7) is connected to a drain of the eleventh transistor (NM11), and a drain of the seventh transistor (NM7) is connected between the fifth capacitor (C5) and the seventh capacitor (C7); an eighth transistor (NM8), wherein a source of the eighth transistor (NM8) is connected to a drain of the eleventh transistor (NM11), and a drain of the seventh transistor (NM7) is connected between the sixth capacitor (C6) and the eighth capacitor (C8); a ninth capacitor (C9), wherein one end of the ninth capacitor (C9) is connected to the gate of the seventh transistor (NM7), and the other end of the ninth capacitor (C9) is connected to the drain of the third transistor (NM3) and the second receiving unit (10); a tenth capacitor (C10), wherein one end of the tenth capacitor (C10) is connected to the gate of the eighth transistor (NM8), and the other end of the tenth capacitor (C10) is connected to the drain of the fourth transistor (NM4) and the second receiving unit (10); a ninth resistor (R9), wherein one end of the ninth resistor (R9) is connected between the ninth capacitor (C9) and the gate of the seventh transistor (NM7); and a tenth resistor (R10), wherein one end of the tenth resistor (R10) is connected between the tenth capacitor (C10) and the gate of the eighth transistor (NM8), and the other end is connected to the other end of the ninth resistor (R9); The second receiving control unit (14) is connected between the ninth resistor (R9) and the tenth resistor (R10).

6. The bidirectional mixer according to claim 5, wherein: The second receiving unit (10) comprises: A twelfth transistor (NM12), wherein a source of the twelfth transistor (NM12) is grounded; a fourteenth resistor (R14), wherein one end of the fourteenth resistor (R14) is connected to the gate of the twelfth transistor (NM12), and the other end of the fourteenth resistor (R14) is connected to the first receiving control unit (13); a fourteenth capacitor (C14), wherein one end of the fourteenth capacitor (C14) is connected to the gate of the twelfth transistor (NM12); The second local oscillator signal terminal (LO_B) is connected to the other end of the fourteenth capacitor (C14); a ninth transistor (NM9), wherein a source of the ninth transistor (NM9) is connected to a drain of the twelfth transistor (NM12), and a drain of the ninth transistor (NM9) is connected between the seventh capacitor (C7) and the fifth capacitor (C5); a tenth transistor (NM10), wherein a source of the tenth transistor (NM10) is connected to a drain of the twelfth transistor (NM12), and a drain of the tenth transistor (NM10) is connected between the sixth capacitor (C6) and the eighth capacitor (C8); an eleventh capacitor (C11), wherein one end of the eleventh capacitor (C11) is connected to the gate of the ninth transistor (NM9), and the other end of the eleventh capacitor (C11) is connected to the tenth capacitor (C10) and the drain of the fifth transistor (NM5); a twelfth capacitor (C12), wherein one end of the twelfth capacitor (C12) is connected to the gate of the tenth transistor (NM10), and the other end is connected to the ninth capacitor (C9) and the drain of the sixth transistor (NM6); an eleventh resistor (R11), wherein one end of the eleventh resistor (R11) is connected between the eleventh capacitor (C11) and the gate of the ninth transistor (NM9); and a twelfth resistor (R12), wherein one end of the twelfth resistor (R12) is connected between the twelfth capacitor (C12) and the gate of the tenth transistor (NM10), and the other end is connected to the other end of the eleventh resistor (R11); The second receiving control unit (14) is connected between the eleventh resistor (R11) and the twelfth resistor (R12).

7. The bidirectional mixer according to claim 6, wherein: The first sending control unit (11) comprises: a fifteenth transistor (NM15), wherein a drain of the fifteenth transistor (NM15) is connected to the third resistor (R3) and the fourth resistor (R4), a source of the fifteenth transistor (NM15) is connected to a first external power supply (VB1), and a gate of the fifteenth transistor (NM15) is connected to an external transmission signal; a nineteenth transistor (NM19), wherein a drain of the nineteenth transistor (NM19) is connected to a drain of the fifteenth transistor (NM15), a source of the nineteenth transistor (NM19) is grounded, and a gate of the nineteenth transistor (NM19) is connected to an external receiving signal; The second sending control unit (12) comprises: a sixteenth transistor (NM16), wherein a drain of the sixteenth transistor (NM16) is connected between the fifth resistor (R5) and the sixth resistor (R6), and is connected between the seventh resistor (R7) and the eighth resistor (R8); a source of the sixteenth transistor (NM16) is connected to a second external power supply (VB2), and a gate of the sixteenth transistor (NM16) is connected to an external transmission signal (TX_ENB); A twentieth transistor (NM20), wherein a drain of the twentieth transistor (NM20) is connected to a drain of the sixteenth transistor (NM16), a source of the twentieth transistor (NM20) is grounded, and a gate of the twentieth transistor (NM20) is connected to an external receiving signal (RX_ENB).

8. The bidirectional mixer according to claim 7, wherein: The first receiving control unit (13) comprises: a thirteenth transistor (NM13), wherein a drain of the thirteenth transistor (NM13) is connected to the thirteenth resistor (R13) and the fourteenth resistor (R14), a source of the thirteenth transistor (NM13) is connected to a first external power supply (VB1), and a gate of the thirteenth transistor (NM13) is connected to an external receiving signal (RX_ENB); a seventeenth transistor (NM17), wherein a drain of the seventeenth transistor (NM17) is connected to a drain of the thirteenth transistor (NM13), a source of the seventeenth transistor (NM17) is grounded, and a gate of the seventeenth transistor (NM17) is connected to an external transmission signal (TX_ENB); The second receiving control unit (14) comprises: a fourteenth transistor (NM14), wherein a drain of the fourteenth transistor (NM14) is connected between the ninth resistor (R9) and the tenth resistor (R10), and is connected between the eleventh resistor (R11) and the twelfth resistor (R12); a source of the fourteenth transistor (NM14) is connected to a second external power supply (VB2), and a gate of the fourteenth transistor (NM14) is connected to an external receiving signal (RX_ENB); An eighteenth transistor (NM18), wherein a drain of the eighteenth transistor (NM18) is connected to a drain of the fourteenth transistor (NM14), a source of the eighteenth transistor (NM18) is grounded, and a gate of the eighteenth transistor (NM18) is connected to an external transmission signal (TX_ENB).

9. The bidirectional mixer according to claim 7, wherein: The positive intermediate frequency port (IF_P) is connected between the fifth capacitor (C5) and the seventh capacitor (C7); The negative intermediate frequency port (IF_N) is connected between the sixth capacitor (C6) and the eighth capacitor (C8); The positive radio frequency port (RF_P) is connected between the ninth capacitor (C9) and the twelfth capacitor (C12); The negative radio frequency port (RF_N) is connected between the tenth capacitor (C10) and the eleventh capacitor (C11).

Images