Thin film transistor and manufacturing method thereof, and display panel

Abstract

The present invention discloses a thin film transistor and a manufacturing method thereof, and a display panel. The thin film transistor includes a substrate and a first gate layer, a first insulating layer, an active layer and a source-drain electrode layer sequentially formed on the substrate. An amorphous metal oxide layer is deposited on the surface of the active layer. The amorphous metal oxide layer is formed by ion bombardment of metal oxygen bonding bonds on the surface of the active layer during the deposition process. The present invention deposits an amorphous metal oxide layer on the surface of the active layer, and utilizes ions in the metal oxide deposition process to bombard the metal oxygen bonding bonds of the active layer to promote the segregation of oxygen ions, so that the surface of the active layer has a high oxygen vacancy concentration, and the carrier concentration on the surface of the active layer is increased, thereby improving the field effect mobility of the thin film transistor. The amorphous metal oxide layer can also improve the influence of positive polarized light on the thin film transistor.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a thin film transistor and a manufacturing method thereof, and a display panel. Background Art

[0002] Oxide TFT technology is widely used in display fields such as OLED (Organic Light-Emitting Diode) and AMLCD (Active-matrix Liquid Crystal Display). Display panels on the market are gradually developing towards high PPI (Pixels Per Inch), high frequency, and large size, which puts higher requirements on the field effect mobility of thin film transistors.

[0003] How to improve the field effect mobility of thin film transistors is a technical problem that needs to be solved urgently. Summary of the invention

[0004] In view of the above-mentioned deficiencies in the prior art, an object of the present invention is to provide a thin film transistor and a manufacturing method thereof, and a display panel, which can improve the field effect mobility of the thin film transistor.

[0005] To achieve the above-mentioned purpose, the present invention first provides a thin film transistor, including a substrate and a first gate layer, a first insulating layer, an active layer and a source-drain layer formed in sequence on the substrate, an amorphous metal oxide layer is deposited on the surface of the active layer, and the amorphous metal oxide layer is formed by ion bombardment of metal-oxygen bonds on the surface of the active layer during the deposition process.

[0006] Optionally, it further includes a second insulating layer and a second gate layer, the second insulating layer is located on the active layer and the source and drain layer, and the second gate layer is located on the second insulating layer.

[0007] Optionally, the source-drain electrode layer includes a source electrode and a drain electrode, a source connection region and a drain connection region are formed at two ends of the active layer, and the source electrode and the drain electrode are connected to the source connection region and the drain connection region respectively.

[0008] Optionally, a distance between the source and the drain is less than or equal to 3 micrometers.

[0009] Optionally, the thickness of the active layer is 3 nanometers to 20 nanometers.

[0010] The present invention also provides a method for manufacturing a thin film transistor, comprising:

[0011] forming a first gate layer, a first insulating layer and an active layer in sequence on the substrate;

[0012] Depositing an amorphous metal oxide layer on the surface of the active layer, wherein during the deposition of the amorphous metal oxide layer, metal oxygen bonds on the surface of the active layer are bombarded by ions;

[0013] A source-drain layer is formed on the active layer.

[0014] Optionally, after the step of forming a source-drain electrode layer on the active layer, the method further comprises:

[0015] forming a second insulating layer on the active layer and the source-drain electrode layer;

[0016] A second gate layer is formed over the second insulating layer.

[0017] Optionally, the step of sequentially forming a first gate layer, a first insulating layer and an active layer on the substrate includes:

[0018] Depositing a first gate layer on the substrate and patterning the first gate layer;

[0019] Depositing a first insulating layer on the first gate layer;

[0020] A metal oxide semiconductor material is deposited on the first insulating layer to form an active layer.

[0021] Optionally, the source-drain electrode layer includes a source electrode and a drain electrode, and the step of forming the source-drain electrode layer on the active layer includes:

[0022] A source connection region and a drain connection region are respectively formed at two ends of the active layer;

[0023] A source electrode and a drain electrode are formed on the active layer, respectively, and the source electrode and the drain electrode are connected to the source connection region and the drain connection region, respectively.

[0024] The present invention further provides a display panel, comprising the above-mentioned thin film transistor, or a thin film transistor manufactured by the above-mentioned thin film transistor manufacturing method.

[0025] Compared with the prior art, the present invention has the following effects: the present invention deposits an amorphous metal oxide layer on the surface of the active layer, utilizes ions in the metal oxide deposition process to bombard the metal oxygen bonding bonds of the active layer, promotes the segregation of oxygen ions, makes the surface of the active layer have a high oxygen vacancy concentration, increases the carrier concentration on the surface of the active layer, thereby increasing the field effect mobility of the thin film transistor, and the amorphous metal oxide layer can also improve the influence of positive polarized light on the thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0027] Figure 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention;

[0028] Figure 2 Schematic diagram of the structure of the source-drain layer and the active layer in an embodiment of the present invention;

[0029] Figure 3 The steps of the method for manufacturing a thin film transistor according to an embodiment of the present invention are as follows Figure 1 ;

[0030] Figure 4 The steps of the method for manufacturing a thin film transistor according to an embodiment of the present invention are as follows Figure 2 ;

[0031] Figure 5 The steps of the method for manufacturing a thin film transistor according to an embodiment of the present invention are as follows Figure 3 . DETAILED DESCRIPTION

[0032] The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments of the present invention that can be implemented. In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc. is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0033] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0034] An embodiment of the present invention provides a thin film transistor, such as Figure 1 As shown, it includes a substrate 1 and a first gate layer 2, a first insulating layer 3, an active layer 4 and a source-drain layer 5 formed in sequence on the substrate 1. An amorphous metal oxide layer 41 is deposited on the surface of the active layer 4. The amorphous metal oxide layer 41 is formed by ion bombardment of metal-oxygen bonds on the surface of the active layer 4 during the deposition process.

[0035] By adopting the above structure, an amorphous metal oxide layer 41 is deposited on the surface of the active layer 4. The ions in the metal oxide deposition process are used to bombard the metal-oxygen bonds of the active layer 4, thereby promoting the segregation of oxygen ions, so that the surface of the active layer 4 has a high oxygen vacancy concentration, and the carrier concentration on the surface of the active layer 4 is increased, thereby improving the field effect mobility of the thin film transistor. The amorphous metal oxide layer 41 can also improve the influence of positive polarized light on the thin film transistor.

[0036] In this embodiment, the carrier concentration of the active layer 4 can reach 10 19 / cm 3 The carrier concentration of the active layer 4 in the prior art is much higher than that of the active layer 4. The carrier mobility of the active layer 4 in this embodiment can reach 10 cm 2 / (V·s) or more, which can ensure that the active layer 4 supports carrier migration at a faster speed without undergoing a high conductivity treatment process, thereby ensuring that the thin film transistor has a fast response speed.

[0037] The active layer 4 of the present embodiment includes indium and / or at least one of tin, zinc, gallium, tantalum and bismuth and a metal oxide semiconductor composed thereof. The thin film transistor of the present embodiment has excellent piezoelectric, photoelectric, gas-sensitive and pressure-sensitive properties and has broad development prospects in the semiconductor field. The active layer 4 composed of a metal oxide semiconductor and an oxide composed of a rare earth element (at least one of praseodymium oxide, terbium oxide, dysprosium oxide and ytterbium oxide) can greatly improve the carrier concentration and carrier migration efficiency of the active layer 4.

[0038] In one embodiment, the thin film transistor further includes a second insulating layer 6 and a second gate layer 7, the second insulating layer 6 is located on the active layer 4 and the source-drain electrode layer 5, and the second gate layer 7 is located on the second insulating layer 6. The thin film transistor of this embodiment includes a first gate layer 2 and a second gate layer 7, and the use of such a dual-gate structure can further improve the field effect mobility of the thin film transistor.

[0039] The material of the first gate layer 2 and the second gate layer 7 is one or a composite material of Al, Mo, Cu or Ag.

[0040] In one embodiment, Figure 2 As shown, the source-drain layer 5 includes a source 51 and a drain 52 , and a source connection region 401 and a drain connection region 402 are formed at two ends of the active layer 4 , and the source 51 and the drain 52 are connected to the source connection region 401 and the drain connection region 402 respectively.

[0041] In one embodiment, the material of the source and the drain includes at least one of metal materials such as gold (Au), titanium (Ti), aluminum (Al), palladium (Pd), platinum (Pt), nickel (Ni), molybdenum (Mo), copper (Cu), and semiconductor materials with good conductivity such as ITO, FTO, AZO, etc.; the thickness of the source and the drain is 10 nanometers to 300 nanometers.

[0042] In one embodiment, the distance between the source electrode 51 and the drain electrode 52 is less than or equal to 3 micrometers. This can make the channel length of the active layer 4 smaller, effectively increase the on-state current of the thin film transistor, and the size of the thin film transistor can be designed to be smaller.

[0043] In one embodiment, the thickness of the active layer 4 is 3 nanometers to 20 nanometers, which can ensure the carrier concentration and carrier migration efficiency.

[0044] In one embodiment, the substrate 1 includes at least one of a heavily doped Si substrate 1, ITO glass, FTO glass, AZO glass and other commonly used hard conductive materials, and a flexible substrate 1 material with a conductive layer covering the surface.

[0045] In one embodiment, the materials of the first insulating layer 3 and the second insulating layer 6 may include Ta 2 O 5 、SiO 2 、Al 2 O 3 , HfO 2 One of the commonly used dielectric materials such as silicon nitride, etc.

[0046] The embodiment of the present invention provides a method for manufacturing a thin film transistor, which is used to manufacture the thin film transistor provided in the above embodiment. Figure 3As shown, it includes step S1, step S2 and step S3, which are specifically as follows:

[0047] Step S1 , forming a first gate layer 2 , a first insulating layer 3 and an active layer 4 in sequence on a substrate 1 .

[0048] Step S2 deposits an amorphous metal oxide layer 41 on the surface of the active layer 4, wherein during the deposition of the amorphous metal oxide layer 41, ions bombard the metal oxygen bonds on the surface of the active layer 4. Specifically, the amorphous metal oxide layer 41 can be sputtered on the surface of the active layer 4 by a sputtering process.

[0049] Step S3 , forming a source-drain electrode layer 5 on the active layer 4 .

[0050] Through the above steps, an amorphous metal oxide layer 41 is deposited on the surface of the active layer 4. The ions in the metal oxide deposition process are used to bombard the metal-oxygen bonds of the active layer 4, thereby promoting the segregation of oxygen ions, so that the surface of the active layer 4 has a high oxygen vacancy concentration, and the carrier concentration on the surface of the active layer 4 is increased, thereby improving the field effect mobility of the thin film transistor. The amorphous metal oxide layer 41 can also improve the impact of positive polarized light on the thin film transistor.

[0051] In one embodiment, after step S3, steps S4 and S5 are further included:

[0052] Step S4 , forming a second insulating layer 6 on the active layer 4 and the source-drain electrode layer 5 .

[0053] Step S5 , forming a second gate layer 7 on the second insulating layer 6 .

[0054] Through the above steps, two gates can be formed on the thin film transistor. This dual-gate structure can further improve the field effect mobility of the thin film transistor.

[0055] In one embodiment, Figure 4 As shown, step S1 specifically includes:

[0056] Step S11, depositing a first gate layer 2 on the substrate 1, and patterning the first gate layer 2. The first gate layer 2 can be formed by a physical vapor deposition process (Physical Vapor Deposition, PVD). Physical vapor deposition refers to the process of transferring atoms or molecules from a source to the surface of a substrate by a physical process to achieve material transfer. Its function is to allow certain particles with special properties (high strength, wear resistance, heat dissipation, corrosion resistance, etc.) to be sprayed on a lower-performance matrix, so that the matrix has better performance. In the embodiment of the present invention, the basic methods of the PVD process are: vacuum evaporation, sputtering, ion plating (hollow cathode ion plating, hot cathode ion plating, arc ion plating, active reaction ion plating, radio frequency ion plating, DC discharge ion plating), etc.

[0057] Step S12, depositing a first insulating layer 3 on the first gate layer 2. Specifically, PECVD (Plasma Enhanced Chemical Vapor Deposition) can be used to deposit the first insulating layer 3. PECVD uses microwaves or radio frequencies to ionize the gas containing the atoms of the film components to form plasma locally. The plasma is highly chemically active and easily reacts, thereby depositing the desired film.

[0058] Step S13 , depositing a metal oxide semiconductor material on the first insulating layer 3 to form an active layer 4 .

[0059] In one embodiment, Figure 5 As shown, the source-drain electrode layer 5 includes a source electrode 51 and a drain electrode 52, and step S3 includes:

[0060] Step S31 , forming a source connection region 401 and a drain connection region 402 at two ends of the active layer 4 , respectively.

[0061] Step S32 , forming a source electrode 51 and a drain electrode 52 on the active layer 4 , and connecting the source electrode 51 and the drain electrode 52 to the source connection region 401 and the drain connection region 402 , respectively.

[0062] In one embodiment, in step S1, the first insulating layer 3 and the first gate layer 2 are deposited by plasma enhanced chemical vapor deposition and physical vapor deposition, respectively. The first insulating layer 3 is a silicon oxide layer, or a composite layer of a silicon nitride layer and a silicon oxide layer. The material of the first gate layer 2 is one or more of metals such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti).

[0063] Specifically, before depositing the first gate layer 2, the first insulating layer 3 is subjected to high temperature annealing treatment in a high temperature furnace, and the annealing temperature is 150°C to 450°C, so as to repair the defects existing on the surface of the active layer 4 of the metal oxide material, thereby improving the electrical properties and stability of the thin film transistor. In this embodiment, the insulating layer and the first gate layer 2 are patterned by a yellow light process and an etching process in sequence, wherein when the insulating layer and the first gate layer 2 are etched by the etching process, the insulating layer and the first gate layer 2 can be etched by a wet etching process and a dry etching process, respectively.

[0064] Similarly, the second insulating layer 6 and the second gate layer 7 can also be manufactured by the above method, which will not be described in detail here.

[0065] An embodiment of the present invention further provides a display panel, comprising the above-mentioned thin film transistor, or a thin film transistor manufactured by the above-mentioned thin film transistor manufacturing method.

[0066] In the display panel of this embodiment, the thin film transistor includes a substrate 1 and a first gate layer 2, a first insulating layer 3, an active layer and a source-drain layer 5 formed in sequence on the substrate 1. An amorphous metal oxide layer 41 is deposited on the surface of the active layer 4. The amorphous metal oxide layer 41 is formed by ion bombardment of the metal-oxygen bonding bonds on the surface of the active layer 4 during the deposition process.

[0067] In this way, an amorphous metal oxide layer 41 is deposited on the surface of the active layer 4. The ions in the metal oxide deposition process are used to bombard the metal-oxygen bonds of the active layer 4, thereby promoting the segregation of oxygen ions. This allows the surface of the active layer 4 to have a high oxygen vacancy concentration, thereby increasing the carrier concentration on the surface of the active layer 4 and thereby increasing the field effect mobility of the thin film transistor. The amorphous metal oxide layer 41 can also improve the effect of positive polarized light on the thin film transistor.

[0068] The thin film transistor of the display panel in the present invention can be obtained by the following method steps:

[0069] (1) A first gate layer 2, a first insulating layer 3 and an active layer 4 are formed in sequence on a substrate 1.

[0070] Specifically, a first gate layer 2 is deposited on the substrate 1 and patterned. The first gate layer 2 can be formed by a physical vapor deposition process (PVD). Physical vapor deposition refers to the process of transferring atoms or molecules from a source to the surface of a substrate by a physical process to achieve material transfer. Its function is to allow certain particles with special properties (high strength, wear resistance, heat dissipation, corrosion resistance, etc.) to be sprayed on a matrix with lower performance, so that the matrix has better performance. In the embodiment of the present invention, the basic methods of the PVD process are: vacuum evaporation, sputtering, ion plating (hollow cathode ion plating, hot cathode ion plating, arc ion plating, active reaction ion plating, radio frequency ion plating, DC discharge ion plating), etc.

[0071] The first insulating layer 3 is deposited on the first gate layer 2. Specifically, PECVD (Plasma Enhanced Chemical Vapor Deposition) can be used to deposit the first insulating layer 3. PECVD uses microwaves or radio frequencies to ionize the gas containing the atoms of the film components to form plasma locally. The plasma has strong chemical activity and is easy to react, thereby depositing the desired film.

[0072] The first insulating layer 3 and the first gate layer 2 can be deposited by plasma enhanced chemical vapor deposition and physical vapor deposition, respectively. The first insulating layer 3 is a silicon oxide layer, or a composite layer of a silicon nitride layer and a silicon oxide layer. The material of the first gate layer 2 is one or more of metals such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti).

[0073] In addition, before depositing the first gate layer 2, the first insulating layer 3 is subjected to high temperature annealing treatment using a high temperature furnace, and the annealing temperature is 150°C to 450°C, so as to repair the defects existing on the surface of the active layer 4 of the metal oxide material, thereby improving the electrical properties and stability of the thin film transistor. In this embodiment, the insulating layer and the first gate layer 2 are patterned using a yellow light process and an etching process in sequence, wherein when the insulating layer and the first gate layer 2 are etched using an etching process, the insulating layer and the first gate layer 2 can be etched using a wet etching process and a dry etching process, respectively.

[0074] A metal oxide semiconductor material is deposited on the first insulating layer 3 to form an active layer 4 .

[0075] (2) An amorphous metal oxide layer 41 is deposited on the surface of the active layer 4, wherein during the deposition of the amorphous metal oxide layer 41, ions bombard the metal oxygen bonding bonds on the surface of the active layer 4. Specifically, the amorphous metal oxide layer 41 can be sputtered on the surface of the active layer 4 by a sputtering process. Ions bombarding the metal oxygen bonding bonds on the surface of the active layer 4 can promote the segregation of oxygen ions, so that the surface of the active layer 4 has a high oxygen vacancy concentration, and the carrier concentration of the interface layer is increased, thereby improving the field effect mobility of the thin film transistor device.

[0076] (3) Forming a source-drain electrode layer 5 on the active layer 4. Specifically, forming a source connection region and a drain connection region at both ends of the active layer 4. Forming a source electrode and a drain electrode on the active layer 4, and connecting the source electrode and the drain electrode to the source connection region and the drain connection region, respectively.

[0077] (4) A second insulating layer 6 is formed on the active layer 4 and the source-drain electrode layer 5 .

[0078] (5) A second gate layer 7 is formed on the second insulating layer 6. The thin film transistor is formed with two gates. This double-gate structure can further improve the field effect mobility of the thin film transistor.

[0079] The display panel of this embodiment adopts the thin film transistor provided by the above embodiment, which has a higher field effect mobility and can meet the development trend of high PPI (pixel density), high frequency and large size of the display panel.

[0080] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A thin film transistor, characterized in that: The invention comprises a substrate and a first gate layer, a first insulating layer, an active layer and a source-drain layer sequentially formed on the substrate. An amorphous metal oxide layer is deposited on the surface of the active layer. The amorphous metal oxide layer is formed after metal-oxygen bonding bonds on the surface of the active layer are bombarded with ions to segregate oxygen ions during the deposition of the active layer.

2. The thin film transistor according to claim 1, characterized in that: It also includes a second insulating layer and a second gate layer, wherein the second insulating layer is located on the active layer and the source-drain electrode layer, and the second gate layer is located on the second insulating layer.

3. The thin film transistor according to claim 1, characterized in that: The source-drain electrode layer includes a source electrode and a drain electrode. A source connection region and a drain connection region are formed at two ends of the active layer. The source electrode and the drain electrode are connected to the source connection region and the drain connection region respectively.

4. The thin film transistor according to claim 3, characterized in that: The distance between the source electrode and the drain electrode is less than or equal to 3 micrometers.

5. The thin film transistor according to any one of claims 1 to 4, characterized in that: The thickness of the active layer is 3 nanometers to 20 nanometers.

6. A method for manufacturing a thin film transistor, characterized in that: include: A first gate layer, a first insulating layer and an active layer are sequentially formed on the substrate; wherein an amorphous metal oxide layer is deposited on the surface of the active layer, and the amorphous metal oxide layer is formed after metal-oxygen bonding bonds on the surface of the active layer are bombarded with ions to segregate oxygen ions during the deposition of the active layer; A source-drain layer is formed on the active layer.

7. The method for manufacturing a thin film transistor according to claim 6, characterized in that: After the step of forming a source-drain electrode layer on the active layer, the method further comprises: forming a second insulating layer on the active layer and the source-drain electrode layer; A second gate layer is formed on the second insulating layer.

8. The method for manufacturing a thin film transistor according to claim 6, characterized in that: The step of sequentially forming a first gate layer, a first insulating layer and an active layer on the substrate comprises: Depositing a first gate layer on the substrate and patterning the first gate layer; Depositing a first insulating layer on the first gate layer; A metal oxide semiconductor material is deposited on the first insulating layer to form an active layer.

9. The method for manufacturing a thin film transistor according to claim 6, characterized in that: The source-drain electrode layer includes a source electrode and a drain electrode, and the step of forming the source-drain electrode layer on the active layer includes: forming a source connection region and a drain connection region at two ends of the active layer respectively; A source electrode and a drain electrode are formed on the active layer, respectively, and the source electrode and the drain electrode are connected to the source connection region and the drain connection region, respectively.

10. A display panel, characterized in that: A thin film transistor comprising the thin film transistor according to any one of claims 1 to 5, or a thin film transistor manufactured by the thin film transistor manufacturing method according to any one of claims 6 to 9.

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