Method of manufacturing a semiconductor device and corresponding semiconductor device

Abstract

The present disclosure relates to a method of manufacturing a semiconductor device, such as a QFN / BGA flip chip type package, and a corresponding semiconductor device. For example, the method includes disposing one or more semiconductor chips or dies on a leadframe, the semiconductor chips or dies having a first side facing the leadframe and electrically coupled with the leadframe and a second side facing away from the leadframe. The method further includes molding a package on the semiconductor chips disposed on the leadframe, wherein the package has an outer surface opposite the leadframe and includes a laser direct structuring (LDS) material. A laser direct structuring process is applied to the LDS material of the package to provide a metal via between the outer surface of the package and the second side of the semiconductor chips and to provide a metal pad at the outer surface of the package.

Description

[0001] Priority Statement

[0002] This application claims priority to Italian Patent Application No. 102020000031244, filed on 17 December 2020, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0003] This invention relates to semiconductor devices. Specifically, one or more embodiments can be applied to semiconductor devices such as integrated circuits (ICs). Background Technology

[0004] Semiconductor devices (e.g., QFN flat packages with peripheral pads on the bottom of the package to provide electrical connections via flip-chip mounting on a substrate such as a printed circuit board (PCB)) have spurred growing interest in a wide range of applications.

[0005] Good heat dissipation contributes to the full performance of these devices. To further enhance heat dissipation, exposed pads are now commonly used in standard QFN packages.

[0006] However, this method has been observed to encounter various reliability issues related to power consumption. This is particularly evident in flip-chip semiconductor devices.

[0007] There is a need in the field for improved methods to overcome these shortcomings. Summary of the Invention

[0008] One or more embodiments may relate to a method.

[0009] One or more embodiments may relate to corresponding semiconductor devices.

[0010] One or more embodiments involve molding dies and lead frames in devices using laser direct forming (LDS) materials (e.g., molding compounds with chromium oxide particulate fillers).

[0011] One or more embodiments benefit from the proven ability of laser direct forming (LDS) technology to form vias and traces.

[0012] One or more embodiments may demonstrate vias and heat-dissipating molding compounds (with chromium oxide particles) filled with detectable metal (e.g., copper).

[0013] One or more embodiments can facilitate high heat dissipation in semiconductor devices, possibly via double-sided heat dissipation.

[0014] One or more embodiments are compatible with those devices that benefit from good heat dissipation, such as in the flip-chip version.

[0015] For example, this can be the case in power devices where fully developing the package leads as input / output (I / O) nodes is a desirable feature, and heat dissipation is primarily entrusted to the semiconductor material (silicon) on the back side through the exposed pads on top.

[0016] One or more embodiments benefit from top thermal pads created by LDS activation and metal (e.g., Cu) plating, which provide improved heat dissipation compared to standard flip-chip solutions. Attached Figure Description

[0017] One or more embodiments will now be described by way of example only with reference to the accompanying drawings, wherein:

[0018] Figure 1 This is a cross-sectional view of a semiconductor device according to an embodiment of this specification;

[0019] Figure 2 and Figure 3 This is a cross-sectional view of a semiconductor device illustrating possible options for implementing embodiments of this specification; and

[0020] Figures 4A to 4G This describes the possible assembly processes that form the embodiments of this specification.

[0021] It should be understood that, for clarity and ease of understanding, the accompanying drawings may not be drawn to the same scale. Detailed Implementation

[0022] In the following description, various specific details are shown to provide a thorough understanding of various examples of embodiments according to the specification. Embodiments may be obtained without one or more specific details, or using other methods, components, materials, etc. In other instances, known structures, materials, or operations are not described in detail so as not to obscure various aspects of the embodiments.

[0023] References to "embodiment" or "an embodiment" within the framework of this specification are intended to indicate that a particular configuration, structure, or feature described with respect to that embodiment is included in at least one embodiment. Therefore, wording such as "in one embodiment" appearing throughout this specification is not necessarily intended to refer precisely to one and the same embodiment. Furthermore, specific constructions, structures, or features may be combined in any suitable manner in one or more embodiments.

[0024] The headings / references used herein are provided for convenience only and are not intended to limit the scope of protection or the scope of the embodiments.

[0025] Furthermore, in all the accompanying drawings, similar reference numerals are used to indicate similar parts or elements unless the context otherwise indicates, and for the sake of brevity, the corresponding descriptions will not be repeated for each drawing.

[0026] Various types of conventional semiconductor devices include lead frames on which one or more semiconductor chips or dies are mounted.

[0027] The lead frame (or lead frame) is currently used to refer to a metal frame that provides support for a semiconductor chip or die, as well as electrical leads that couple the semiconductor chip or die to other electrical components or contacts.

[0028] Essentially, a leadframe comprises an array of conductive structures (leads) extending inward from a peripheral location along the direction of a semiconductor chip or die, thereby forming an array of conductive structures from die pads on which at least one semiconductor chip or die is attached. This can be achieved using die attachment adhesives (e.g., die attachment films or DAF).

[0029] Electrical coupling between the leads in the lead frame and the semiconductor chip or die can be achieved by wires forming a lead bonding pattern around the chip or die.

[0030] The device is packaged using an insulating package, which is formed by molding a compound such as epoxy resin onto a lead frame and a semiconductor chip attached to the lead frame.

[0031] Flat leadless (QFN) type semiconductor devices can be electrically connected to external circuit devices (e.g., printed circuit boards or PCBs) via ball grid arrays (BGAs). The resulting arrangement is called a QFN / BGA arrangement.

[0032] In a conventional QFN / BGA layout, if a semiconductor chip mounted on a leadframe has pads on its top or front side that are connected to the leadframe via a wire bonding pattern, exposed die pads can be provided for heat dissipation.

[0033] A flip-chip type semiconductor device involves interconnection with external circuitry via solder bumps deposited on chip pads formed on the top or front side of a semiconductor chip or die. The chip is flipped so that its front side faces down to couple with the external circuitry (e.g., a printed circuit board or PCB). The pads on this surface are aligned with corresponding pads on the external circuitry (e.g., the PCB). Solder reflow completes the interconnection.

[0034] Therefore, in traditional flip-chip type semiconductor devices (which may use QFN / BGA configurations), the semiconductor chip is typically mounted in an inverted package (bottom side up and top side down). Since the bottom or back of the chip or die is not in contact with a metal plate, the heat dissipation of the device is inevitably poor, relying solely on metal (e.g., copper) pillars for heat dissipation, and the die area coupled to the lead frame for heat transfer is very small, resulting in poor heat dissipation performance.

[0035] For this reason, flip-chip packaging is primarily used for devices with (very) low heat dissipation expectations and / or for applications where reduced heat dissipation is not considered a critical feature.

[0036] One or more embodiments may utilize laser direct forming technology used in the manufacture of semiconductor devices.

[0037] Laser direct molding (LDS) is a technology used in various fields that can involve molding resins containing additives (e.g., injection molding).

[0038] A laser beam can be applied to the surface of a part being molded to transfer a desired pattern onto it. A metallization process involving metals such as copper (such as electroless plating) can then be used to deposit the desired conductive pattern onto the laser-activated surface. LDS processes are also known for providing vias or contact pads.

[0039] Figure 1 This is a diagram of a semiconductor device 10 that can be manufactured according to the embodiments described herein.

[0040] As with other conventional methods in the art, a device such as semiconductor device 10 can be fabricated as part of an array (e.g., a string or bar) of similar devices that are ultimately separated via “segmentation”. The accompanying drawings illustrate the steps applied to produce one such device. It should be understood that these steps can be applied simultaneously to fabricate multiple devices 10.

[0041] like Figure 1 As shown, the semiconductor device 10 includes a lead frame 12, on which one or more semiconductor chips or dies 14 are mounted: for simplicity, a single chip or die 14 is shown here.

[0042] The lead frame 12 can be of the pre-molded type, with its insulating compound molded on the basic metal structure of the lead frame, which is etched from metal (e.g., copper) strip or roll.

[0043] As shown in 12A, the lead frame 12 may be electroplated on its bottom or back surface.

[0044] The chip or die 14 may be mounted on the lead frame 12 via bump 16, with the chip or die inverted (referred to in the art as a "flip chip"), i.e., with its bottom or back side (which may be metallized at 14A) facing up and its top or front side facing down.

[0045] Package 18 can be molded onto lead frame 12 and semiconductor chip 14 attached thereon.

[0046] In one or more embodiments, the package 18 is provided using a laser-directly formed (LDS) material.

[0047] For example, the material may include a thermoplastic material doped with a compound that can be activated by a laser. Subsequent metallization (e.g., forming layers of copper, nickel, and gold in a chemical copper plating bath) helps to provide a conductive structure at the location where the LDS material is laser activated. LDS technology has proven suitable for providing vias or contact pads.

[0048] Figure 1 Device 10 is shown, wherein LDS molding compound 18 can be molded on die 14 having back metallization (or metallization layer) 14A.

[0049] The laser beam energy and LDS processing exemplified by LB can be applied to form one or more (conductive and thermally conductive) metallized vias 180 that extend down through the molding compound to the die 14 (the bottom or back metallization A) and to form thermal pads 182 on top of the package of device 10.

[0050] For example, electroless plating and electroplating of Cu help to grow thermal pads 182 on the top of the package, creating a connection with the outside world for heat dissipation. For example, an additional heat sink (not visible in the figure) can be added on top of the thermal pads 182.

[0051] Figure 2 and Figure 3 Implementation shown Figure 1 Different options for the layout shown.

[0052] Unless the context otherwise indicates, Figure 2 and Figure 3 In the middle, similar to already combined Figure 1 Parts or elements discussed are denoted by similar reference symbols, so for simplicity, the corresponding descriptions are not repeated.

[0053] like Figure 2 As shown, a sacrificial via 184 (which is removed during the final splitting step) can be provided on the external guide rail to allow current continuity to reach the top exposed pad 182 and to grow a thicker copper layer on top of the thermal pad 182.

[0054] like Figure 3 As shown, some leads in lead frame 12 can be used to connect to the top-exposed pad 182 through via 186, again allowing thicker copper to grow on top of the thermal pad 182.

[0055] Figures 4A to 4G The possible assembly process in the embodiments of this specification is shown.

[0056] Those skilled in the art should understand that Figures 4A to 4GSpecific steps illustrated in the example may be omitted or replaced by other steps, or additional steps may be added. Furthermore, one or more steps in the process may differ from... Figures 4A to 4G The execution will proceed in the order shown in the example.

[0057] Figure 4A An example is growing pillars 16 (e.g., copper) on the front or top surface of a semiconductor chip or die 14, wherein the semiconductor chip or die 14 is metallized at its bottom or back surface 14A.

[0058] Figure 4B This is an example of leader frame 12, as follows: Figure 4C The example shows a semiconductor chip or die 14 (inverted) attached to the lead frame 12.

[0059] Figure 4D Is Figure 4C An example of the steps for molding LDS molding compound 18 (i.e., molding compound including laser-activated material used in LDS technology) on the structure shown (e.g., after reflow and flux cleaning).

[0060] As those skilled in the art will understand, these steps can be performed in any suitable manner.

[0061] like Figure 4E As shown, after possible electroplating (e.g., tin plating) at 12A (if there is no pre-plating of LF), then as Figure 4F As shown, LDS treatment is applied to molding compound 18.

[0062] like Figure 4F As shown, the LDS treatment of molding compound 18 may include laser activation and metallization (e.g., electroless plating and electroplating of Cu) as illustrated by LB, in order to form vias 180 and exposed pads 182.

[0063] For illustrative purposes only, Figure 4F (and Figure 4G () indicates: On the left side of the diagram is Figure 2 The options shown (in) Figure 4G During the final segmentation step, sacrificial via 184 is removed, while on the right side of the figure is... Figure 3 The option shown is that the leads in the lead frame 12 are used to connect to the top exposed pad 182 through the via 186.

[0064] As mentioned above, this representation is for illustrative purposes only, and any of these options will be expected to be applied in any industrial assembly process implemented for a particular device.

[0065] Figure 4G This is an example of the final segmentation step, which is performed in a conventional manner via a sawing tool S, for example, to segment such a strip into individual semiconductor devices 10.

[0066] In short, the methods illustrated herein may include: arranging at least one semiconductor chip or die (e.g., 14) on a leadframe (e.g., 12), the semiconductor chip or die having a first side facing and electrically coupled to the leadframe (e.g., via metal, such as copper pillar 16) and a second side away from the leadframe; molding (insulating) a package (e.g., 18) on the at least one semiconductor chip or die arranged on the leadframe, wherein the package has an outer surface opposite the leadframe and includes a laser-directly formed LDS material; and applying a laser-directly formed process (e.g., LB, CP) to the LDS material of the package to provide at least one metal via (e.g., 180) between the outer surface of the package and the second side of the at least one semiconductor chip or die, and providing metal pads (e.g., 182) at the outer surface of the package.

[0067] In the method illustrated herein, the laser direct forming process for LDS material applied to a package may include: applying laser beam energy (e.g., LB) to the outer surface of the package to drill at least one laser-activated hole between the outer surface of the package and a second side of at least one semiconductor chip or die, and providing laser activation of the outer surface of the package; growing (e.g., CP) a metal material in the at least one laser-activated hole to provide the at least one metal via between the outer surface of the package and the second side of at least one semiconductor chip or die, and forming a metal material at the outer surface of the package to provide the metal pads at the outer surface of the package.

[0068] The methods illustrated herein may include forming a metallization (e.g., 14A) on a second side of at least one semiconductor chip or die, wherein at least one metal via is coupled (electrically and / or thermally) to the metallization layer.

[0069] The methods illustrated herein may include electrically coupling a first side of at least one semiconductor chip or die to a lead frame via a metal pillar (e.g., 16).

[0070] The methods illustrated herein may include applying a laser direct forming process (LB, CP) to the LDS material of the package to provide at least one metal via (e.g., 184, 186) between the outer surface of the package and the lead frame, wherein the at least one metal via facilitates the formation of the metal pad at the outer surface of the package.

[0071] The method illustrated herein may include: applying a laser direct forming process to the LDS material of the package to provide at least one sacrificial metal via (e.g., 184) between the outer surface of the package and the lead frame, wherein the at least one sacrificial metal via facilitates the formation of the metal pad at the outer surface of the package, and after the metal pad is formed at the outer surface of the package, removing (e.g., S) the at least one sacrificial metal via.

[0072] The device (e.g., 10) illustrated herein may include: a lead frame (e.g., 12) on which at least one semiconductor chip or die (e.g., 14) is disposed, the semiconductor chip or die having a first side facing and electrically coupled to the lead frame (e.g., via a post such as 16) and a second side away from the lead frame; a package (e.g., 18) molded on the at least one semiconductor chip or die disposed on the lead frame, wherein the package has an outer surface opposite to the lead frame and includes a laser-direct-formed LDS material; at least one metal via (e.g., 180) formed in the LDS material of the package between the outer surface of the package and the second side of the at least one semiconductor chip or die; and a metal pad (e.g., 182) formed on the outer surface of the LDS material of the package.

[0073] The device, as illustrated herein, may include a metallic material: in at least one laser-activated via drilled in the LDS material of the package to provide the at least one metallic via between the outer surface of the package and a second side of at least one semiconductor chip or die; and grown on the outer surface of the LDS material of the package to provide the metallic pads on the outer surface of the package.

[0074] Devices as illustrated herein may include a metallization (e.g., 14A) located on a second side of at least one semiconductor chip or die, wherein at least one metal via (electrically and / or thermally) is coupled to the metallization.

[0075] Devices as illustrated herein may include metal pillars (e.g., 16) that electrically couple a first side of at least one semiconductor chip or die to a lead frame.

[0076] Devices as illustrated herein may include at least one metal via (e.g., 186) formed in the LDS material of the package between the outer surface of the package and the lead frame.

[0077] It should be understood that sacrificial vias such as 184 will no longer be visible in individual devices 10 after the split (see [reference]). Figure 4G (S in the middle).

[0078] Without prejudice to the fundamental principles, details and embodiments may vary, even significantly, relative to what is described by example, without departing from the scope of the embodiments.

Claims

1. A method comprising: At least one semiconductor die is disposed on a lead frame, the at least one semiconductor die having a first side facing the lead frame and electrically coupled to the lead frame and a second side away from the lead frame; A package is molded on the at least one semiconductor die disposed on the lead frame, wherein the package has an outer surface opposite to the lead frame and comprises laser direct-formed LDS material. The LDS material of the package is subjected to a laser direct forming process so as to: At least one metal via is provided between the outer surface of the package and the second side of the at least one semiconductor die, and Metal pads are provided on the outer surface of the package. The laser direct forming process for the LDS material used in the package includes: Laser energy is applied to the outer surface of the package to drill at least one laser-activated hole between the outer surface of the package and the second side of the at least one semiconductor die, and to provide laser activation of the outer surface of the package. as well as To form metallic materials: In the at least one laser-activated hole, at least one metal via is provided between the outer surface of the package and the second side of the at least one semiconductor die, and The metal pads are provided on the outer surface of the package.

2. The method according to claim 1, further comprising: A metallization is formed on the second side of the at least one semiconductor die, wherein at least one metal via is coupled to the metallization.

3. The method according to claim 1, further comprising: The at least one metal via is coupled to a metallization formed on the second side of the at least one semiconductor die.

4. The method according to claim 1, further comprising: The first side of the at least one semiconductor die is electrically coupled to the lead frame via a metal pillar.

5. The method according to claim 1, further comprising: A laser direct forming process is applied to the LDS material of the package to provide at least one metal via between the outer surface of the package and the lead frame, wherein the at least one metal via facilitates the formation of the metal pad at the outer surface of the package.

6. The method according to claim 5, further comprising: A laser direct forming process is applied to the LDS material of the package to provide at least one sacrificial metal via between the outer surface of the package and the lead frame, wherein the at least one sacrificial metal via facilitates the formation of the metal pad at the outer surface of the package. as well as After the metal pads are formed on the outer surface of the package, the at least one sacrificial metal via is removed.

7. A device comprising: A lead frame having at least one semiconductor die disposed thereon, the at least one semiconductor die having a first side facing the lead frame and electrically coupled to the lead frame and a second side away from the lead frame; A package located on the at least one semiconductor die disposed on the lead frame, wherein the package has an outer surface opposite to the lead frame and comprises laser-direct-formed LDS material; At least one metal via is formed in the LDS material of the package, located between the outer surface of the package and the second side of the at least one semiconductor die; as well as Metal pads are formed on the outer surface of the LDS material of the package. The device also includes metallic materials: Located in at least one laser-activated hole drilled in the LDS material of the package, to provide the at least one metal via between the outer surface of the package and the second side of the at least one semiconductor die; as well as The metal pads are located on the outer surface of the LDS material of the package to provide the outer surface of the package.

8. The device of claim 7, comprising a metallization located on the second side of the at least one semiconductor die, wherein the at least one metal via is coupled to the metallization.

9. The device according to claim 8, further comprising: At least one metal via is formed in the LDS material of the package, located between the outer surface of the package and the lead frame.

10. The device according to claim 9, further comprising: The metal pillar is electrically coupled to the first side of the at least one semiconductor die via the lead frame.

11. The device according to claim 7, further comprising: The metal pillar is electrically coupled to the first side of the at least one semiconductor die via the lead frame.

12. The device according to claim 7, further comprising: At least one metal via is located in the LDS material of the package, between the outer surface of the package and the lead frame.

13. The device according to claim 7, further comprising: A metal pillar electrically couples the first side of the at least one semiconductor die to the lead frame.

14. The device of claim 7, further comprising at least one metal via located in the LDS material of the package, between the outer surface of the package and the lead frame.

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