A method for screening potential failure of wafer group chips

Abstract

The present invention provides a method for screening potential failure of wafer group chips. For all chips of N wafers in a wafer group, ASCII coded characters are used to mark valid chips and failed chips, chip coordinates are created for each chip in the N wafers in the wafer group, all chip coordinates are summarized, and the percentage of the number of failed chips under the same horizontal coordinate of the wafer group to the number N of wafers in the wafer group is counted, so as to realize transposition processing of characteristic areas with concentrated failed chip trend under the N wafers in the wafer group, thereby improving the efficiency of identifying failed chips and the reliability of overall chip products.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor product manufacturing, and in particular to a method for screening potential failures of wafer group chips. Background Art

[0002] The production of integrated circuits takes several weeks and requires hundreds of independent processes, repeating dozens of core processes such as cleaning, photoresist coating, exposure, development, etching, doping, annealing, etc. In the current production process, process control and production are carried out in batches of wafer groups (a batch of wafers is called a lot, and a wafer is called a wafer). Usually a wafer group consists of 25 wafers. Under certain processes, wafers in one or more wafer groups will be operated on the same equipment at the same time.

[0003] Wafer testing (Chip Probing, abbreviated as CP in English), also known as mid-test, is a wafer-level screening test. It performs functional screening tests on wafers before chip reduction and packaging to confirm that the chip functions on the wafer meet the design definition, usually including voltage, current, timing and function verification.

[0004] Chip functional testing is usually completed by an integrated circuit automatic tester (ATE). During the test, the probe equipment on the ATE outputs a binary code file that can represent the distribution of the functional test results of the wafer chip on the wafer, which is generally represented by a wafer test result map (ChipProbe Map, Map for short). In the wafer test result map, different Bin values ​​are used to mark qualified chips that pass the test and unqualified chips that fail the test according to the set Bin value relationship.

[0005] During the packaging stage, the packaging and testing equipment converts the wafer test result map CP-Map into a packaging result map (Final Test Map, FT-Map for short) and selects qualified marked chips for packaging and testing operations.

[0006] The production and manufacturing of integrated circuits belongs to micro-manufacturing. Minor abnormal jitters in processes and equipment will cause regional continuous failures. Under the current production conditions, chip testing is a balance between cost, efficiency and other aspects. Generally, only characteristic temperature, voltage, frequency and other conditions are selected for testing. The first representation of production monitoring is the wafer test yield. When the wafer test yield meets the monitoring conditions, it is released. Although the detection rate of the test system can be improved by traversing test temperature, test voltage, test vector and other conditions, the testing cost required to do so is extremely high. Moreover, the current test scheme lacks detection means for common failure areas and trend failures of different wafers in the wafer group. In the field of high-reliability applications, there is an urgent need for a test method to characterize and screen out failed chips affected by the same factors between wafers in the same batch of wafers, so as to improve the reliability of the final chip product. Summary of the invention

[0007] In view of the deficiencies in the above-mentioned prior art, the purpose of the present invention is to provide a method for screening potential failures of wafer group chips. For all chips in a wafer group of N wafers, ASCII coded characters are used to mark valid chips and failed chips, chip coordinates are created for each chip in the N wafers of the wafer group, all chip coordinates are summarized, and the percentage of the number of failed chips at the same horizontal coordinate of the wafer group to the number of wafers in the wafer group N is counted, so as to realize transposition processing of characteristic areas with concentrated failed chip trend under the N wafers of the wafer group, thereby improving the efficiency of identifying failed chips and the reliability of the overall chip product.

[0008] In order to achieve the above technical purpose, the technical solution adopted by the present invention is:

[0009] A method for screening potential failures of wafer assembly chips, characterized in that the screening method comprises the following specific steps:

[0010] Step 1: The wafer group consists of N wafers, where N ≥ 2. Use ASCII coded characters to define the Map text files represented by valid chips, default chips, and failed chips, and define the Map text file suffix;

[0011] Step 2: Use custom Map tool software to define the wafer Map coordinate system, wafer group wafer test probe Map data, the first wafer group test Map text file, and the second wafer group test Map text file, and set the wafer group test probe Map data directory item, the first wafer group test Map text file directory item, and the second wafer group test Map text file directory item;

[0012] Step 3: Start the ATE instrument to collect wafer group wafer test probe Map data, and store the wafer group wafer test probe Map data in the wafer group test probe Map data directory item;

[0013] Step 4: Use the custom Map tool software to select the wafer group test probe Map data directory item, and use the Map tool software to identify the wafer group test probe Map data one by one, transpose and output them into the first wafer group test Map text file, and store them in the first wafer group test Map text file directory item;

[0014] Step 5: Select the first wafer group test Map text file directory item, and call the wafer group statistical algorithm by the Map tool software to read the Map text file in the first wafer group test Map text file directory item one by one, use ASCII coded characters to mark the valid chips and failed chips in all chips of the N wafers in the wafer group, take the wafer MAP coordinate system coordinate origin (0, 0) as the starting point, take the number of rows and columns of the wafer MAP chip as the coordinate parameters, create chip coordinates for each chip in the N wafers in the wafer group, summarize all chip coordinates, count the percentage of the number of failed chips to the number of wafers in the wafer group N at the same horizontal coordinate of the wafer group, and compare the ratio with the set threshold value. If the percentage value is greater than the set threshold value, record the coordinate in the abnormal failure coordinate set {Q};

[0015] Step 6: Use the Map tool software again to read the first wafer group test Map text file corrected in step 5 one by one, obtain the valid chip mark characters and failed chip mark characters of all chips in the wafer group N, and modify the valid chip mark characters in the abnormal failure coordinate set {Q} to the failed chip mark characters;

[0016] Step 7: Use Map tool software to transpose and output the first wafer group test Map text file corrected in the above step 6 into a second wafer group test Map text file, and store it in the second wafer group test Map text file directory item. The second wafer group test Map text file is used for back-end packaging of wafer testing.

[0017] Preferably, the coordinate system is a Cartesian coordinate system, wherein the vertical coordinates are columns and the horizontal coordinates are rows.

[0018] The present invention is based on all chips of N wafers in a wafer group, uses ASCII coded characters to mark valid chips and failed chips, creates chip coordinates for each chip in the N wafers in the wafer group, summarizes all chip coordinates, counts the percentage of the number of failed chips to the number of wafers in the wafer group N under the same horizontal coordinate of the wafer group, and compares the ratio with a set threshold value. If the ratio is greater than the set threshold value, the coordinate is recorded in an abnormal failure coordinate set {Q}, and the valid chip marking characters in the abnormal failure coordinate set {Q} of each wafer in the wafer group are modified to failed chip marking characters, thereby realizing transposition processing of a characteristic area with a concentrated failed chip trend under the N wafers in the wafer group, and improving the efficiency of identifying failed chips and the reliability of the overall chip product. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0020] Figure 1 It is a coordinate system Map plane diagram specifically implemented in the present invention.

[0021] Figure 2 It is a flow chart of a method for screening potential failures of wafer assembly chips implemented in the present invention.

[0022] Figure 3 It is a plan view of a statistical result Map of the number of failed chip coordinates of a wafer group and the percentage of the wafer group according to a specific implementation of the present invention.

[0023] Figure 4 It is a map plan view of an example of chip potential failure screening process for a wafer in a wafer group implemented in the present invention. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0026] See also Figure 1 , a coordinate system Map plane diagram of a specific implementation of the present invention. In the wafer test result map, the default chip 100 means that there is no chip in the area, the failed chip 200 means that the chip is a failed chip, and the valid chip 300 means that the chip is a valid chip. The origin (0, 0) of the wafer MAP coordinate system is 400, its vertical coordinate is 500, and its horizontal coordinate is 600.

[0027] See also Figure 2 , a flowchart of a method for screening potential failures of wafer stack chips implemented in the present invention. The specific steps of the method for screening potential failures of wafer stack chips are as follows:

[0028] Step 1 S1: The wafer group consists of N wafers, where N ≥ 2. ASCII encoding characters are used to define the valid chip as the character "A", the default chip as the character black dot ".", the failed chip as the character "F", and the Map text file suffix is ​​defined as ".Map".

[0029] Step 2 S2: Use custom Map tool software to define the wafer Map coordinate system, define the wafer group wafer test probe Map data as Lot_Wafer_Cp.Dat, define the first wafer group test Map text file as Lot_Wafer_Cp.Map, define the second wafer group test Map text file as Lot_Wafer_Ft.Map, and set the wafer group test probe Map data directory item as Cp_Data, set the first wafer group test Map text file directory item Cp_Map and the second wafer group test Map text file directory item Ft_Map.

[0030] Step 3 S3: Start the ATE instrument to collect the wafer group wafer test probe Map data Lot_Wafer_Cp.Dat, and store the wafer group wafer test probe Map data Lot_Wafer_Cp.Dat in the wafer group test probe Map data directory item Cp_Data.

[0031] Step 4 S4: Use the custom Map tool software to select the wafer group test probe Map data directory item Cp_Data, and use the Map tool software to recognize the wafer group test probe Map data Lot_Wafer_Cp.Dat one by one, transpose and output the first wafer group test Map text file Lot_Wafer_Cp.Map, and store it in the first wafer group test Map text file directory item Cp_Map.

[0032] Step 5 S5: Select the first wafer group test Map text file directory item Cp_Map, and the Map tool software calls the wafer group statistical algorithm to read the Map text file Lot_Wafer_Cp in the first wafer group test Map text file directory item Cp_Map one by one. During the Map process, use ASCII coded characters to mark the valid chips in all the chips of the N wafers in the wafer group as the character "A" and the failed chips as the character "F", take the wafer MAP coordinate system coordinate origin (0, 0) 400 as the starting point, take the number of rows N and the number of columns M of the wafer MAP chip as the coordinate parameters, and create chip coordinates for each chip in the N wafers in the wafer group;

[0033] In this specific embodiment, the chip coordinates of each chip in the N wafers of the wafer group are created as follows:

[0034] Column: (M,0),(M,1),(M,2)…(M,N-2),(M,N-1),(M,N)

[0035] Rows: (M-1,0),(M-1,1),(M-1,2)…(M-1,N-2),(M-1,N-1),(M-1,N)

[0036] …

[0037] (1,0),(1,1),(1,2)…(1,N-2),(1,N-1),(1,N)

[0038] (0,0),(0,1),(0,2)…(0,N-2),(0,N-1),(0,N)

[0039] Summarize all chip coordinates, count the percentage of failed chips at the same horizontal coordinate of the wafer group to the number of wafers in the wafer group N, and compare each ratio with the set threshold. If it is greater than the set threshold, record the coordinate in the abnormal failure coordinate set {Q}.

[0040] Step 6 S6: Re-use the Map tool software to read the first wafer group test Map text file Lot_Wafer_Cp.Map corrected in step 5 one by one, obtain the valid chip marking character "A" and the failed chip marking character "F" in all chips of the N wafers in the wafer group, and modify the valid chip marking character "A" in the abnormal failure coordinate set {Q} to the failed chip marking character "F".

[0041] Step 7 S7: Use Map tool software to transpose and output the first wafer group test Map text file Lot_Wafer_Cp.Map corrected in the above step 6 into the second wafer test Map text file Lot_Wafer_Ft.Map, and store it in the second wafer test Map text file directory item Ft_Map. The second wafer test Map text file Lot_Wafer_Ft.Map is used for back-end packaging of wafer testing.

[0042] See also Figure 3, the wafer group chip coordinate yield statistics result Map plane diagram of the specific implementation of the present invention. In the wafer Map diagram of this specific embodiment, A100 is the default chip area; A200 is the effective chip area; A300 is the concentrated trend failure chip area, that is, the coordinate position area where the wafer chip failure percentage value is greater than the set threshold. In this specific embodiment, the threshold range is set to 0-100%, and the threshold set in this specific embodiment is 60%. The percentage value of failed chips in the effective chip area of ​​the wafer group in the A200 effective chip area is R1, where R1 <60%; and the percentage value of failed chips in the A300 effective chip area is R2, where 60% ≤ R2 ≤ 100%.

[0043] See also Figure 4 , which is a map plane diagram of an example of chip potential failure screening process of a wafer in a wafer group implemented in the present invention. In the wafer map diagram of this specific embodiment, B100 is the effective chip area, which is displayed in dark gray; B200 is the failed chip area, which is displayed in white; the black area displayed by B300 means that according to the wafer group chip potential failure screening method of the present invention, the effective chip is transposed to the area of ​​the failed chip, that is, the effective chip mark character "A" on the abnormal failure coordinate set {Q} is read using the Map tool software, and the effective chip mark character "A" is modified to the failed chip mark character "F".

[0044] The above is a detailed introduction to a method for screening potential failures of wafer group chips provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

[0045] It should be noted that each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0046] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device that includes a series of elements is inherent to the elements, or also includes elements inherent to these processes, methods, articles or devices. In the absence of further restrictions, the elements defined by the sentence "including a..." do not exclude the presence of other identical elements in the process, method, article or device that includes the elements.

[0047] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for screening potential failure of wafer assembly chips, characterized in that: The screening method comprises the following specific steps: Step 1: The wafer group consists of N wafers, where N ≥ 2. Use ASCII coded characters to define the Map text files represented by valid chips, default chips, and failed chips, and define the Map text file suffix; Step 2: Use custom Map tool software to define the wafer Map coordinate system, wafer group wafer test probe Map data, the first wafer group test Map text file, and the second wafer group test Map text file, and set the wafer group test probe Map data directory item, the first wafer group test Map text file directory item, and the second wafer group test Map text file directory item; Step 3: Start the ATE instrument to collect wafer group wafer test probe Map data, and store the wafer group wafer test probe Map data in the wafer group test probe Map data directory item; Step 4: Use the custom Map tool software to select the wafer group test probe Map data directory item, and use the Map tool software to identify the wafer group test probe Map data one by one, transpose and output them into the first wafer group test Map text file, and store them in the first wafer group test Map text file directory item; Step 5: Select the first wafer group test Map text file directory item, and call the wafer group statistical algorithm by the Map tool software to read the Map text file in the first wafer group test Map text file directory item one by one, use ASCII coded characters to mark the valid chips and failed chips in all chips of the N wafers in the wafer group, take the wafer MAP coordinate system coordinate origin (0, 0) as the starting point, take the number of rows and columns of the wafer MAP chip position as the coordinate parameters, create chip coordinates for each chip in the N wafers in the wafer group, summarize all chip coordinates, count the percentage value of the number of failed chips at the same horizontal chip coordinate of the wafer group and the number of wafers in the wafer group N, and compare the percentage value with the set threshold value one by one. If the percentage value of the chip coordinate is greater than the set threshold value, record the chip coordinate in the abnormal failure coordinate set {Q}; Step 6: Use the Map tool software again to read the first wafer group test Map text file corrected in step 5 one by one, obtain the valid chip mark characters and failed chip mark characters of all chips in the wafer group N, read the valid chip mark characters in the abnormal failure coordinate set {Q}, and modify the valid chip mark characters to failed chip mark characters; Step 7: Use Map tool software to transpose and output the first wafer group test Map text file corrected in the above step 6 into a second wafer group test Map text file, and store it in the second wafer group test Map text file directory item. The second wafer group test Map text file is used for back-end packaging of wafer testing.

2. The method for screening potential failure of wafer group chips according to claim 1, characterized in that: The coordinate system is a Cartesian coordinate system, in which the vertical coordinates are columns and the horizontal coordinates are rows.

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