A storage unit resistant to power consumption attacks based on digital mechanism

Abstract

The present invention discloses a power consumption attack resistant storage unit based on a digital mechanism, the storage unit is composed of a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first inverter, a second inverter, a third inverter, a first transmission gate and a second transmission gate. The power consumption attack resistant storage unit based on a digital mechanism of the present invention can improve the ability of the unit circuit to resist side channel attacks, can greatly improve the stability of the unit while sacrificing a smaller unit area, and reduces the power consumption of the unit.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a power consumption attack resistant storage unit based on a digital mechanism. Background Art

[0002] Nowadays, Side Channel Attack (SCA) has become a serious threat to security systems because it can extract confidential data by analyzing the current consumed by the system power layer. Static random access memory (SRAM), as a key component of these security systems, is the main target of attack. Figure 1 As shown in Figure 1, the traditional SRAM cell composed of 6 transistors (referred to as 6T cell) has been proven to be vulnerable to side channel attacks. When a traditional 6T cell is written, the power consumption generated by the write operation varies depending on the data stored inside the cell. The attacker obtains the original data information stored inside the cell by analyzing the correlation between the write power consumption and the internal storage data.

[0003] As different side channel attack methods emerge one after another, a series of anti-side channel attack technologies have also emerged. The existing technologies mainly include the following solutions:

[0004] like Figure 2 The figure shows a 7T structure proposed by Robert Giterman in 2019 to resist power consumption attacks. It adds a "balance tube" ( Figure 2 The write operation of the 7T structure is divided into two stages: the balance stage and the write stage. The balance stage enables the "balance tube" to pull the two storage nodes to the same level, thus eliminating the correlation between the original storage data and the write power consumption and achieving the purpose of resisting side channel attacks. However, the 7T structure has the problems of large write power consumption, obvious delay in write operation, and low write speed.

[0005] like Figure 3 Shown is V. An 8T structure that is resistant to side channel attacks was proposed in 2012. Two NMOS transistors are added between the two coupled inverters of this structure ( Figure 3 The NMOS transistors N5 and N6 in the structure are used to cut off the feedback. The write operation of this structure is also divided into two stages. In the balance stage, the CUT signal is pulled low, and the positive feedback between the two storage nodes Q and QN is broken. At this time, since the bit lines BL / BLB are at a low level, the levels of the two storage nodes are simultaneously pulled down to '0', thus eliminating the influence of the original data, resulting in a reduction in the correlation between the write power consumption and the internal original data, thereby achieving the purpose of resisting side channel attacks.

[0006] Existing anti-side channel attack technologies still have problems such as high power consumption, low write speed, interference from half-selection problems, and low noise tolerance. Summary of the invention

[0007] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a power consumption attack resistant storage unit based on a digital mechanism, which is used to solve the problems of high power consumption, low write speed, interference from half-selection problem and low noise tolerance of static random storage units in the prior art.

[0008] To achieve the above-mentioned purpose and other related purposes, the present invention provides a power consumption attack resistant storage unit based on a digital mechanism, comprising:

[0009] A first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first inverter, a second inverter, a third inverter, a first transmission gate, and a second transmission gate;

[0010] The source of the first PMOS transistor is connected to a power supply, the drain of the first PMOS transistor is connected to the source of the second PMOS transistor, the gate of the first PMOS transistor is connected to the output of the first inverter, the input of the third inverter, the gate of the second NMOS transistor, and the input of the second inverter; the gate of the second PMOS transistor is connected to a first write word line, the drain of the second PMOS transistor is respectively connected to the drain of the first NMOS transistor, the input of the first inverter, and the output of the second inverter; the gate of the first NMOS transistor is connected to a second write word line, the drain of the second NMOS transistor is connected to the source of the first NMOS transistor, and the source of the second NMOS transistor is grounded; the output of the third inverter is connected to the first bit line through the first transmission gate; the input of the second inverter is connected to the second bit line through the second transmission gate;

[0011] The first control end of the first transmission gate is connected to the first read word line, and the second control end of the first transmission gate is connected to the second read word line; the first control end of the second transmission gate is connected to the first write bit line, and the second control end of the second transmission gate is connected to the second write bit line.

[0012] In an optional embodiment, the first write word line and the second write word line are used to provide a pair of opposite control signals.

[0013] In an optional embodiment, the first read word line and the second read word line are used to provide a pair of opposite control signals.

[0014] In an optional embodiment, the first write bit line and the second write bit line are used to provide a pair of opposite control signals.

[0015] In an optional embodiment, the first transmission gate is a CMOS transmission gate.

[0016] In an optional embodiment, the second transmission gate is a CMOS transmission gate.

[0017] In an optional embodiment, the first inverter, the second inverter, and the third inverter are CMOS inverters.

[0018] In an optional embodiment, in the holding phase, the first bit line and the second bit line are both precharged to a high level, the first write bit line is a low level, the second write bit line is a high level, the first read word line is a low level, the second read word line is a high level, the first write word line is a low level, and the second write word line is a high level.

[0019] In an optional embodiment, in the data reading phase, the first bit line is precharged to a high level, the first read word line is a high level, the second read word line is a low level, the first write word line is a low level, and the second write word line is a high level.

[0020] In an optional embodiment, in the data writing stage, the first write bit line is high, the second write bit line is low, the first write word line is high, the second write word line is low, and the second bit line is high or low.

[0021] The power consumption attack resistant storage unit based on digital mechanism of the present invention is composed of a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first inverter, a second inverter, a third inverter, a first transmission gate and a second transmission gate, which can improve the stability of the storage unit and improve the unit's ability to resist side channel attacks, and can greatly improve the unit's write speed while sacrificing a smaller unit area, and reduce the unit's power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a structural schematic diagram of a 6T circuit in the prior art.

[0023] Figure 2 It is a schematic diagram of the structure of a 7T circuit in the prior art.

[0024] Figure 3 It is a structural diagram of an 8T circuit in the prior art.

[0025] Figure 4 A schematic diagram of the structure of a power consumption attack resistant storage unit based on a digital mechanism provided in an embodiment of the present invention;

[0026] Figure 5A timing waveform diagram of a digital mechanism-based power consumption attack resistant storage unit circuit provided in an embodiment of the present invention.

[0027] Among them: 0.5ns-1.5ns is the write "0" operation, 1.5ns-2.5ns is the read "0" operation, 2.5sn-3.5ns is the write "1" operation, 3.5ns-4.5ns is the read "1" operation, 4.5ns-5.5ns is the hold (the simulation conditions are: Corner: TT; Temperature: 27℃; VDD: 0.9V). DETAILED DESCRIPTION

[0028] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0029] See also Figure 1-5 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0030] like Figure 4As shown, this embodiment provides a power consumption attack resistant storage unit based on a digital mechanism, which is a unit circuit structure that can be applied to an ultra-low voltage system and improves the unit's ability to resist side channel attacks (SCA). The power consumption attack resistant storage unit based on a digital mechanism includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first inverter 10, a second inverter 20, a third inverter 30, a first transmission gate 40 and a second transmission gate 50. The source of the first PMOS transistor is connected to a power supply, the drain of the first PMOS transistor is connected to the source of the second PMOS transistor, the gate of the first PMOS transistor is connected to the output end of the first inverter 10, the input end of the third inverter 30, the gate of the second NMOS transistor, and the input end of the second inverter 20; the gate of the second PMOS transistor is connected to the first write word line, and the drain of the second PMOS transistor is respectively connected to the drain of the first NMOS transistor, the input end of the first inverter 10 and the output end of the second inverter 20; the first NMOS transistor is connected to the drain of the first NMOS transistor, the input end of the first inverter 10 and the output end of the second inverter 20. The gate of the body transistor is connected to the second write word line, the drain of the second NMOS transistor is connected to the source of the first NMOS transistor, and the source of the second NMOS transistor is grounded; the output end of the third inverter 30 is connected to the first bit line through the first transmission gate 40; the input end of the second inverter 20 is connected to the second bit line through the second transmission gate 50; the first control end of the first transmission gate 40 is connected to the first read word line, and the second control end of the first transmission gate 40 is connected to the second read word line; the first control end of the second transmission gate 50 is connected to the first write bit line, and the second control end of the second transmission gate 50 is connected to the second write bit line.

[0031] like Figure 4 As shown, the first inverter 10, the second inverter 20, and the third inverter 30 are all CMOS inverters composed of a PMOS transistor and an NMOS transistor, and the first transmission gate 40 and the second transmission gate 50 are CMOS transmission gates composed of a PMOS transistor and an NMOS transistor in parallel. It can be understood that, in other embodiments, the first inverter 10, the second inverter 20, and the third inverter 30 can also be replaced by inverters such as NMOS inverters, PMOS inverters, and TTL inverters, and the first transmission gate 40 and the second transmission gate 50 can also be selected as transmission gates composed of a pair of transistors with opposite polarities.

[0032] Specifically, Figure 4The power consumption attack resistant storage cell based on digital structure shown is a 14T digital structure SRAM storage cell, hereinafter referred to as DIGIT-14T. The DIGIT-14T includes: seven NMOS transistors and seven PMOS transistors; the seven NMOS transistors are sequentially recorded as N1 to N7, and the seven PMOS transistors are sequentially recorded as P1 to P7; the drain of the PMOS transistor P1 (as the first PMOS transistor) is connected to the source of the PMOS transistor P2 (as the second PMOS transistor), and the PMOS transistors P1 and P2 serve as pull-up transistors, the source of the NMOS transistor N1 (as the first NMOS transistor) is connected to the drain of the NMOS transistor N2 (as the second NMOS transistor), and the NMOS transistors N1 and N2 serve as pull-down transistors; the NMOS transistor N3 and the PMOS transistor P3 form a CMOS inverter (as the first inverter 10), the NMOS transistor N4 and the PMOS transistor P4 form another CMOS inverter (as the second inverter 20), and the two inverters are cross-coupled; the NMOS transistor N6 and the PMOS transistor P6 form a CMOS The main storage node QN is connected to the read bit line RBL (as the first read bit line) through the third inverter 30 and the first transmission gate 40; wherein: the PMOS transistor P2 and the NMOS transistor N1 are respectively controlled by the write word line WWLB (as the second write word line) and WWL (as the first write word line); the PMOS transistor P6 and the NMOS transistor N6 are respectively controlled by the write bit line WBLB (as the second write bit line) and WBL (as the first write bit line); the NMOS transistor N7 and the PMOS transistor P7 are respectively controlled by the word line RWL (as the first read word line) and RWLB (as the second read word line).

[0033] The bit line BLB is electrically connected to the drains of the NMOS transistor N6 and the PMOS transistor P6, respectively; the write bit line WBL is electrically connected to the gate of the NMOS transistor N6, and the write bit line WBLB is electrically connected to the gate of the PMOS transistor N6; the bit line RBL is electrically connected to the sources of the NMOS transistor N7 and the PMOS transistor P7, respectively; the read word line RWL is electrically connected to the gate of the NMOS transistor N7; the read word line RWLB is electrically connected to the gate of the PMOS transistor P7; the power supply VDD is electrically connected to the source of the PMOS transistor P1, the source of the PMOS transistor P3, the source of the PMOS transistor P4, and the source of the PMOS transistor P5; the source of the NMOS transistor N2, the source of the NMOS transistor N3, the source of the NMOS transistor N4, and the source of the NMOS transistor N5 are grounded.

[0034] The drain of the PMOS transistor P1 is electrically connected to the source of the PMOS transistor P2, and the gate of the PMOS transistor P1 is electrically connected to the gate of the NMOS transistor N2, the drain of the PMOS transistor P3, the drain of the NMOS transistor N3, the gate of the PMOS transistor P4, the gate of the NMOS transistor N4, the gate of the PMOS transistor P5, the gate of the NMOS transistor N5, the gate of the NMOS transistor N2, the source of the NMOS transistor N6, and the source of the PMOS transistor P6; the drain of the PMOS transistor P2 is electrically connected to the drain of the NMOS transistor N1, the gate of the PMOS transistor P3, the gate of the NMOS transistor N3, the drain of the PMOS transistor P4, and the drain of the NMOS transistor N4, and the gate of the PMOS transistor P2 is electrically connected to the write word line WWLB; the source of the NMOS transistor N1 is electrically connected to the drain of the NMOS transistor N2, and the gate of the NMOS transistor N1 is electrically connected to the write word line WWL.

[0035] The working principle of the DIGIT-14T memory cell provided in the embodiment of the present invention is as follows: the write bit lines WBL and WBLB are always a pair of opposite control signals, the read word lines RWL and RWLB are always a pair of opposite control signals, and the write word lines WWL and WWLB are always a pair of opposite control signals.

[0036] In the holding stage, the bit lines RBL and BLB are precharged to a high level, the write bit lines WBL and WBLB are low and high respectively, the read word lines RWL and RWLB are low and high respectively, the write word lines WWL and WWLB are low and high respectively, the internal circuit maintains its initial state and the circuit does not work.

[0037] When in the data reading stage, the bit line RBL is precharged to a high level, the read word lines RWL and RWLB are high and low respectively, the write word lines WWL and WWLB are low and high respectively, the write bit lines WBL and WBLB are low and high respectively, and the NMOS transistor N7 and the PMOS transistor P7 constituting the first transmission gate 40 are turned on; if the data stored in the unit circuit is '0', then "Q=0, QN=1"; then RBL is discharged to the ground through the discharge path: the first transmission gate 40 and the NMOS transistor N5 constituted by the NMOS transistor N7 and the PMOS transistor P7, so that the voltage of the bit line RBL is reduced; if the data stored in the unit circuit is '1', then "Q=1, QN=0", then the power supply VDD charges the bit line RBL through the charging path: the second transmission gate 50 constituted by the PMOS transistor P5, the PMOS transistor P7 and the NMOS transistor N7, so that the voltage of the bit line RBL is increased.

[0038] In the data writing phase, the write bit lines WBL and WBLB are high and low respectively, and the write word lines WWL and WWLB are high and low respectively. If the bit line BLB is high, then the second transmission gate 50 composed of NMOS transistor N6 and PMOS transistor P6 writes '1' to the storage node QN; if the bit line BLB is low, then the second transmission gate 50 composed of NMOS transistor N6 and PMOS transistor P6 writes '0' to the storage node QN. In the writing process, because the PMOS transistor P1, PMOS transistor P2, NMOS transistor N1, and NMOS transistor N2 form an inverter between the two storage nodes Q and QN, the storage node data is more easily flipped, so that the writing capacity of the storage unit is greatly improved.

[0039] The memory cell uses a digital structure in both the read and write paths, and the read and write operations are performed in a digital manner, which greatly improves the memory cell's ability to resist interference and can operate stably at extremely low voltages. Although the number of transistors in a single cell has increased by 1.3 times compared to the traditional 6T, considering the entire system, the digital operation method eliminates the analog part in the traditional SRAM circuit, which to some extent makes up for the area consumption caused by the increase in the number of transistors in a single cell.

[0040] The principle of the DIGIT-14T storage unit's resistance to side channel attacks provided in this embodiment is as follows: Figure 1 The 6T structure shown in FIG. 1 is composed of only two positive feedback loops formed by inverters. Such a structure enables the 6T SRAM to have good retention capability, that is, a higher retention noise margin. The DIGIT-14T of this embodiment also has such a structure. Figure 4The cross-coupling structure of the first inverter 10 composed of the PMOS transistor P3 and the NMOS transistor N3 and the first inverter 10 composed of the PMOS transistor P4 and the NMOS transistor N4. However, for 6T, a good feedback loop makes it difficult to rewrite data. Figure 1 As shown, when the data stored in the storage node Q is "0", if "0" is still written the next time, that is, BL = 0, BLB = 1, and the data in the feedback loop is not changed, the operation is easy and the power consumption is very small; if "1" is written to the storage node Q the next time, that is, BL = 1, BLB = 0, the data in the feedback loop needs to be changed. At this time, there is a voltage difference between BL and the storage node Q, and a current is generated through N1, and BL will increase the voltage of the storage node Q. However, although the level of the storage node QN has dropped at this time, it has not reached "0", so that P1 is still closed and N2 is still open, so a feedback effect is generated, and N2 will pull down the level of the storage node Q to keep the original stored data in the feedback loop unchanged. Although the data of the storage node Q can be rewritten in the end due to the strong pull of BL and BLB, in this process, due to the influence of the feedback loop, the operation is more difficult. The operation mode of this analog circuit will consume more power, making the power consumption of rewriting the data to "1" much higher than the power consumption of writing "0". In the DIGIT-14T of the present embodiment, the storage node Q is directly rewritten by adding PMOS transistor P1, PMOS transistor P2, NMOS transistor N1, and NMOS transistor N2. Although the storage nodes Q and QN are still restricted by the feedback loop, the PMOS transistor P1, PMOS transistor P2, NMOS transistor N1, and NMOS transistor N2 are digital writing methods and will not be affected by the storage node QN and reduce the writing effect. Therefore, when rewriting data, DIGIT-14T is less affected by the original data and consumes less power.

[0041] Currently, the SRAM cell structure with the best resistance to power consumption attacks is Figure 2 The 7T structure in the DIGIT-14T achieves the effect of similar power consumption whether writing "1" or "0" by cutting off the feedback loop for data balance in the first stage and rewriting the data in the second stage. In fact, this amplifies the power consumption, and whether the data is rewritten or not, a large write power consumption will be generated. At the same time, because the write operation is divided into two stages, the write operation of the 7T structure will have a significant delay, resulting in a lower write speed. Although 7T has the advantage of a small number of transistors, in order to achieve a balanced effect, under the same process, such as the 28nm process, the gate width of the P3 tube is ten times that of the transistor in the DIGIT-14T.

[0042] The DIGIT-14T of this embodiment has high security, which is not only reflected in its resistance to power consumption attacks, but also in its immunity to half-selection problems and its extremely high noise tolerance. Figure 4As shown, firstly, compared with other storage units that only need to turn on the word line switch to select during write operation, this unit needs to turn on the write word lines WWL, WWLB and the write bit lines WBL, WBLB at the same time during write operation. Data can only be written effectively when the row and column are valid signals at the same time, thus avoiding the problem of half-row selection during traditional 6T write operation. At the same time, during read operation, the second transmission gate 50 (composed of NMOS transistor N6 and PMOS transistor P6) connected to the bit line BLB is connected to the third inverter 30 (composed of NMOS transistor N5 and PMOS transistor P5). Since the third inverter 30 transmits the level unidirectionally, the fluctuation on the bit line during half-column selection cannot affect the storage node. Secondly, the use of the third inverter 30 also makes the read noise tolerance of DIGIT-14T as high as the static noise tolerance of the feedback loop (see the simulation comparison table in Table 1). Therefore, the DIGIT-14T of this embodiment has many advantages such as low power consumption, fast speed, simple timing and small area.

[0043] During simulation, since the DIGIT-14T circuit structure of this embodiment does not need to use MOS transistors of special sizes to maintain better performance, the smallest transistors in the 28nm process library can be used to build the structure. The gate length of all MOS transistors is 30nm, and the gate width of all MOS tubes is 100nm.

[0044] Figure 5 The timing waveform diagram of the simulation of the DIGIT-14T circuit of this embodiment is shown, wherein: 0.5ns-1.5ns is the write "0" operation, 1.5ns-2.5ns is the read "0" operation, 2.5ns-3.5ns is the write "1" operation, 3.5ns-4.5ns is the read "1" operation, and 4.5ns-5.5ns is the hold (simulation conditions are: Corner: TT; Temperature: 27°C; VDD: 0.9V).

[0045] Table 1 is a simulation comparison table of write time, write "0" power consumption, write "1" power consumption, anti-attack capability (difference in power consumption between writing "1" and writing "0"), read noise margin RSNM and hold noise margin HSNM of the prior art SRAM unit circuit and the DIGIT-14T circuit provided in this embodiment (simulation conditions are: Corner: TT; Temperature: 27°C; VDD: 0.9V).

[0046] Table 1 Simulation comparison table

[0047]

[0048] It can be seen that the DIGIT-14T provided in the embodiment of the present invention can improve the ability of the unit circuit to resist side channel attacks, can greatly improve the stability of the unit at the expense of a smaller unit area, and reduce the power consumption of the unit.

[0049] It should be noted that the DIGIT-14T SRAM storage unit provided in the embodiment of the present invention is constructed using the smallest MOS transistors available in the process library. However, if other sizes are selected, or other transistors (such as TFET, etc.) are used to replace the tubes in the DIGIT-14T, the function of the SRAM storage unit can still be realized to a certain extent. At the same time, in order to ensure good performance, the DIGIT-14T provided in the embodiment of the present invention adopts a transmission gate, a pair of write word lines, a pair of write bit lines, and other circuit structures that conform to CMOS logic. However, if these paired components are replaced with a single MOS transistor, the original function of the circuit can also be realized to a certain extent.

[0050] In the description herein, many specific details, such as examples of components and / or methods, are provided to provide a complete understanding of embodiments of the present invention. However, those skilled in the art will recognize that embodiments of the present invention may be practiced without one or more of the specific details or with other devices, systems, components, methods, components, materials, parts, etc. In other cases, well-known structures, materials, or operations are not specifically shown or described in detail to avoid obscuring aspects of embodiments of the present invention.

[0051] It should also be understood that one or more of the elements shown in the figures may also be implemented in a more separate or more integrated manner, or even removed because they are inoperable in certain circumstances or provided because they may be useful depending on the application.

[0052] In addition, unless otherwise explicitly indicated, any marking arrows in the drawings should be regarded as exemplary only and not limiting. In addition, unless otherwise indicated, the term "or" used herein is generally intended to mean "and / or". In the case where the term is not clear because it is anticipated that the ability to separate or combine is provided, the combination of components or steps will also be regarded as indicated.

[0053] The above description of the illustrated embodiments of the present invention (including the contents described in the Abstract) is not intended to be an exhaustive list or to limit the present invention to the precise form disclosed herein. Although specific embodiments of the present invention and examples of the present invention are described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the present invention as will be recognized and appreciated by those skilled in the art. As noted, these modifications may be made to the present invention in accordance with the above description of the embodiments described in the present invention, and these modifications will be within the spirit and scope of the present invention.

[0054] Systems and methods have been generally described herein as details that aid in understanding the present invention. In addition, various specific details have been given to provide an overall understanding of embodiments of the present invention. However, those skilled in the relevant art will recognize that embodiments of the present invention may be practiced without one or more of the specific details, or may be practiced using other devices, systems, accessories, methods, components, materials, parts, etc. In other cases, well-known structures, materials, and / or operations are not specifically shown or described in detail to avoid confusion with various aspects of embodiments of the present invention.

[0055] Thus, although the invention has been described herein with reference to specific embodiments thereof, freedom of modification, various changes and substitutions are also within the foregoing disclosure, and it should be understood that in some cases, some features of the invention will be employed without the corresponding use of other features without departing from the scope and spirit of the proposed invention. Thus, many modifications may be made to adapt a particular environment or material to the essential scope and spirit of the invention. The invention is not intended to be limited to the specific terms used in the claims below and / or the specific embodiments disclosed as the best mode contemplated for carrying out the invention, but the invention will include any and all embodiments and equivalents falling within the scope of the appended claims. Thus, the scope of the invention will be determined solely by the appended claims.

Claims

1. A power consumption attack resistant storage unit based on a digital mechanism, characterized in that: include: A first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first inverter, a second inverter, a third inverter, a first transmission gate, and a second transmission gate; The source of the first PMOS transistor is connected to a power supply, the drain of the first PMOS transistor is connected to the source of the second PMOS transistor, the gate of the first PMOS transistor is connected to the output of the first inverter, the input of the third inverter, the gate of the second NMOS transistor, and the input of the second inverter; the gate of the second PMOS transistor is connected to a first write word line, the drain of the second PMOS transistor is respectively connected to the drain of the first NMOS transistor, the input of the first inverter, and the output of the second inverter; the gate of the first NMOS transistor is connected to a second write word line, the drain of the second NMOS transistor is connected to the source of the first NMOS transistor, and the source of the second NMOS transistor is grounded; the output of the third inverter is connected to the first bit line through the first transmission gate; the input of the second inverter is connected to the second bit line through the second transmission gate; The first control end of the first transmission gate is connected to the first read word line, and the second control end of the first transmission gate is connected to the second read word line; the first control end of the second transmission gate is connected to the first write bit line, and the second control end of the second transmission gate is connected to the second write bit line.

2. The power consumption attack resistant storage unit based on digital mechanism according to claim 1, characterized in that: The first write word line and the second write word line are used to provide a pair of opposite control signals.

3. The digital mechanism-based power consumption attack resistant storage unit according to claim 1, characterized in that: The first read word line and the second read word line are used to provide a pair of opposite control signals.

4. The power consumption attack resistant storage unit based on digital mechanism according to claim 1, characterized in that: The first write bit line and the second write bit line are used to provide a pair of opposite control signals.

5. The power consumption attack resistant storage unit based on digital mechanism according to claim 1, characterized in that: The first transmission gate is a CMOS transmission gate.

6. The power consumption attack resistant storage unit based on digital mechanism according to claim 1, characterized in that: The second transmission gate is a CMOS transmission gate.

7. The power consumption attack resistant storage unit based on digital mechanism according to claim 1, characterized in that: The first inverter, the second inverter, and the third inverter are CMOS inverters.

8. The power consumption attack resistant storage unit based on digital mechanism according to claim 1, characterized in that: In the holding stage, the first bit line and the second bit line are both precharged to a high level, the first write bit line is a low level, the second write bit line is a high level, the first read word line is a low level, the second read word line is a high level, the first write word line is a low level, and the second write word line is a high level.

9. The power consumption attack resistant storage unit based on digital mechanism according to claim 1, characterized in that: In the data reading phase, the first bit line is precharged to a high level, the first read word line is a high level, the second read word line is a low level, the first write word line is a low level, and the second write word line is a high level.

10. The power consumption attack resistant storage unit based on digital mechanism according to claim 1, characterized in that: In the data writing phase, the first write bit line is at a high level, the second write bit line is at a low level, the first write word line is at a high level, the second write word line is at a low level, and the second bit line is at a high level or a low level.

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