A phase calibration circuit structure

Abstract

The present invention discloses a phase calibration circuit structure, which belongs to the field of integrated circuits, and includes a voltage-controlled delay chain, a first modulation loop, a second modulation loop and a phase detector; wherein the output signal of the phase detector is sent to the second modulation loop through a first-level buffer, and then sent to the first modulation loop through another level of buffer; the first modulation loop adjusts the voltage-controlled delay chain through a digital module detection circuit state value, and modulates the phase difference between two clocks to between two set phase difference values; the second modulation loop adjusts the voltage-controlled delay chain through a feedback circuit output control voltage, and modulates the phase difference between two clocks to between two set phase difference values. The second modulation loop is introduced to avoid the calibrated phase from falling on the set phase edge, thereby improving the accuracy and reliability of the circuit phase calibration.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a phase calibration circuit structure. Background Art

[0002] With the rapid development of integrated circuits, the sending and receiving of high-speed signals, multi-channel analog-to-digital converters, digital-to-analog converters and other data processing systems, the phase relationship between clock and data directly determines whether the data can be transmitted normally. It is necessary to design a calibration circuit to generate a specific phase clock or clock sequence, and the accuracy of the clock signal phase directly affects the overall performance of the data processing system.

[0003] Traditional voltage-controlled delay circuits generally have only one control voltage. In order to ensure the accuracy and reliability of phase calibration, it is usually necessary to design complex digital logic or counter circuits. Complex digital logic or counters are used to detect the edge position of the set phase, and then the digital circuit gives a suitable control signal to lock the phase in the middle position, thereby improving the stability of phase locking. Summary of the invention

[0004] The purpose of the present invention is to provide a phase calibration circuit structure to solve the problems in the background technology.

[0005] In order to solve the above technical problems, the present invention provides a phase calibration circuit structure, including a voltage-controlled delay chain, a first modulation loop, a second modulation loop and a phase detector; wherein,

[0006] The output signal of the phase detector is sent to the second modulation circuit via a first-stage buffer, and then sent to the first modulation circuit via another-stage buffer;

[0007] The first modulation loop adjusts the voltage-controlled delay chain through the digital module detection circuit state value, and modulates the phase difference between the two clocks to between the two set phase difference values; the second modulation loop adjusts the voltage-controlled delay chain through the feedback circuit output control voltage, and modulates the phase difference between the two clocks to between the two set phase difference values.

[0008] Optionally, the first modulation loop includes a first filter, a first comparator, a second comparator, a NAND gate, a digital module and a bias circuit;

[0009] The first filter performs filtering processing on the output signal of the phase detector, and quantizes the clock phase difference signal to a specific voltage value V OUT1 , and sent to the negative terminal of the first comparator and the positive terminal of the second comparator respectively;

[0010] The positive terminal of the first comparator is connected to the voltage value V selected by the circuit K+1 , the negative terminal of the second comparator is connected to the voltage value V selected by the circuitK-1 , the two comparators compare the specific voltage value with the two selected voltage values, and obtain the comparison result and input it into the NAND gate;

[0011] The NAND gate performs NAND processing on the output results of the two comparators, and the output result is used as the state value of the circuit lock;

[0012] The digital module detects the circuit lock state value and outputs a corresponding control signal according to the detection result;

[0013] The bias circuit outputs a corresponding control voltage V according to the control signal CTRL1 , adjust the delay size of the voltage-controlled delay chain.

[0014] Optionally, the second modulation loop includes a second filter, an operational amplifier and two MOS transistors;

[0015] The second filter is used to quantize the output signal of the phase detector to a specific voltage value V OUT2 ;

[0016] The operational amplifier quantizes the voltage value V OUT2 and set voltage value V K The difference between the two is amplified and the output result is used as the control voltage V of the voltage-controlled delay chain. CTRL2 , adjust the delay size of the voltage-controlled delay chain.

[0017] Optionally, the voltage-controlled delay chain includes a plurality of voltage-controlled delay units connected in series, each of which is composed of a V CTRL1 and V CTRL2 Two control voltages adjust the output delay.

[0018] Optionally, two input ends of the phase detector are respectively connected to the input clock and the output end of the voltage-controlled delay chain, and the phase detector is used to compare the phases of the input clock signal and the delayed clock signal, and output a comparison result signal.

[0019] Optionally, the first filter and the second filter are respectively formed by connecting a resistor and a capacitor in parallel.

[0020] The phase calibration circuit structure provided by the present invention includes a voltage-controlled delay chain, a first modulation loop, a second modulation loop and a phase detector. The first modulation loop includes a first filter, two comparators, a NAND gate, a digital module and a bias circuit; the second modulation loop includes a second filter, an operational amplifier and two MOS transistors. In the first modulation loop, the first filter quantizes the phase difference between the two clocks to a voltage value, compares the quantized voltage value with the two set voltage values, and sends the comparison result to the NAND gate. The digital module detects the output state value of the NAND gate, sends a corresponding control signal according to the state value, and the control signal adjusts the output voltage of the bias circuit. The output voltage is sent to the voltage-controlled delay chain, and the clock output delay is adjusted until the quantized voltage value falls between the two set voltage values, completing the circuit locking; the second modulation loop compares another quantized voltage value with the set third voltage value, outputs a control voltage through a feedback circuit, and the control voltage is sent to the voltage-controlled delay chain to adjust the clock output delay until the quantized voltage value is equal to the set third voltage value, and the third voltage value is half of the sum of the two voltage values ​​set in the first modulation loop. The introduction of the second modulation loop is mainly to avoid the calibrated phase falling on the edge of the set phase. When another quantized voltage value is equal to the set third voltage through feedback, it means that the calibrated phase falls between the two set phases, which improves the accuracy and reliability of the circuit phase calibration. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic diagram of the phase calibration circuit structure provided by the present invention;

[0022] Figure 2 It is a schematic diagram of the circuit quantization voltage provided by the present invention under a reset signal;

[0023] Figure 3 It is a schematic diagram showing whether the circuit provided by the present invention is locked. DETAILED DESCRIPTION

[0024] The following is a further detailed description of a phase calibration circuit structure proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the accompanying drawings are in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0025] The present invention provides a phase calibration circuit structure, the overall schematic diagram of which is as follows: Figure 1As shown, it includes a voltage controlled delay line (VCDL), a first modulation loop, a second modulation loop and a phase detector PD; the two input ends of the phase detector PD are respectively connected to the input clock CLK and the output end DCLK of the voltage controlled delay line, for comparing the phases of the input clock signal CLK and the delayed clock signal DCLK, and outputting a comparison result signal. The output signal of the phase detector PD is sent to the second modulation loop through a first-level buffer, and then sent to the first modulation loop through a first-level buffer; the first modulation loop adjusts the voltage controlled delay line through a digital module detection circuit state value, and modulates the phase difference between the two clocks to between the two set phase difference values; the second modulation loop adjusts the voltage controlled delay line through a feedback circuit output control voltage, and modulates the phase difference between the two clocks to between the two set phase difference values.

[0026] The first modulation loop includes a filter, a first comparator, a second comparator, a NAND gate, a digital module DIG BLOCK and a bias circuit BIAS; the filter performs filtering processing on the output signal of the phase detector PD, and quantizes the clock phase difference signal to a specific voltage value V OUT1 ; The voltage value V OUT1 The positive terminal of the first comparator is connected to the voltage value V selected by the circuit. K+1 , the negative terminal of the second comparator is connected to the voltage value V selected by the circuit K-1 , where the voltage value V K+1 Greater than V K-1 , voltage value V K+1 and voltage value V K-1 Represents different phase difference values; the first comparator is for voltage value V K+1 and V OUT1 For comparison, the second comparator compares the voltage value V K-1 and V OUT1For comparison, the first comparator and the second comparator send the output results to the NAND gate; the NAND gate receives the output results of the two comparators, provides the corresponding state value STATE according to the input signal, and the state value STATE output signal is sent to the digital module DIGBLOCK; the digital module DIG BLOCK detects the state value STATE of the internal signal of the circuit to determine whether the phase calibration of the circuit is locked. When the state value STATE is detected to be 0, it means that the phase calibration is locked, and the output signal is maintained and no longer changes; when the state value STATE is detected to be 1, it means that the phase calibration is not locked temporarily, and the output control signal is changed successively until the phase calibration is locked. The detection cycle of the digital module DIG BLOCK is determined by the RESET signal. When the rising edge of the RESET signal arrives, the digital module DIG BLOCK starts to detect the state value STATE and outputs the corresponding control signal according to the detected state value STATE, where V OUT1 and V OUT2 At each RESET falling edge, V OUT1 The time to stabilize must be greater than V OUT2 Stable time, specific signal changes such as Figure 2 As shown, this is mainly to reduce the interference of the second modulation loop on the first modulation loop; the bias circuit BIAS outputs a corresponding control voltage according to the received control signal CTRL SIGNAL.

[0027] Please continue reading Figure 1 The second modulation loop includes a filter, an operational amplifier AMP and two MOS transistors; the filter filters the output signal of the phase detector PD and quantizes the clock phase difference signal to a specific voltage value V OUT2 ; The voltage value V OUT2 Connect the positive terminal of the operational amplifier AMP and the negative terminal to the voltage value V selected by the circuit. K The output voltage of the operational amplifier AMP is used as the control voltage V of the voltage-controlled delay chain. CTRL2 ; The phase of the circuit lock is biased towards V K-1 When the voltage represents the phase, the output voltage after filtering and stabilization is V OUT2 Prefer V K-1 , at this time V OUT2 The value is less than the voltage value V K , control voltage V CTRL2 As the output voltage of the operational amplifier AMP decreases, the output clock delay of the voltage-controlled delay chain increases, and the voltage of the output signal of the phase detector PD increases after filtering, that is, V OUT2 The voltage value increases, and the circuit undergoes self-feedback to make the voltage value V OUT2 Gradually increases to the voltage value V KWhen the entire circuit becomes stable, the voltage value V OUT1 =V OUT2 =V K =0.5*(V K+1 +V K-1 ); instead, the circuit locks the phase toward V K+1 When the voltage represents the phase, the output voltage after filtering and stabilization is V OUT2 Prefer V K+1 , at this time V OUT2 The value is greater than the voltage value V K , control voltage V CTRL2 As the output voltage of the operational amplifier AMP increases, the output clock delay of the voltage-controlled delay chain decreases, and the voltage of the output signal of the phase detector PD after filtering decreases, that is, V OUT2 The voltage value decreases, and the circuit self-feeds back to make the voltage value V OUT2 Gradually decreases to the voltage value V K When the entire circuit becomes stable, the voltage value V OUT1 =V OUT2 =V K =0.5*(V K+1 +V K-1 ).

[0028] The voltage-controlled delay chain includes a plurality of voltage-controlled delay cells connected in series, each of which is controlled by a control voltage V CTRL1 and V CTRL2 Adjust the output delay; the clock output delay of the voltage-controlled delay chain decreases as the control voltage increases, and increases as the control voltage decreases; the control voltage V CTRL1 Mainly regulated by the first modulation loop, the size change is determined by the digital module DIG BLOCK according to the state value STATE of the detected phase; the control voltage V CTRL2 It is mainly regulated by the second modulation loop, and the size change is determined by the self-generated feedback circuit. However, when the phase calibration is locked and the entire circuit is stable, no matter what the locked phase is, the control voltage V CTRL2 are all stable at a fixed value.

[0029] Figure 3 The simulation results of the circuit state value are shown, and the filtered voltage value V OUT1 At the same time, it is less than or greater than the selected voltage value V K+1 and V K-1 When the output state value of the NAND gate is high, the voltage value after filtering V OUT1 Greater than the selected voltage value V K-1 and is less than the selected voltage value V K+1When the output state value of the NAND gate is low level; when the digital module detects that the output state of the NAND gate is low level, it determines that the phase calibration is locked; the second modulation loop accurately calibrates the position of the phase to the middle position of the two selected phase difference values.

[0030] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A phase calibration circuit structure, characterized in that: It includes a voltage-controlled delay chain, a first modulation circuit, a second modulation circuit and a phase detector; wherein, The two input ends of the phase detector are respectively connected to the input clock and the delayed clock signal output by the voltage-controlled delay chain. The phase detector is used to compare the phases of the input clock signal and the delayed clock signal and output a comparison result signal. The output signal of the phase detector is sent to the second modulation loop through a first-stage buffer and then sent to the first modulation loop through another-stage buffer. The first modulation loop adjusts the voltage-controlled delay chain by detecting the circuit state value through the digital module, modulates the phase difference between the two clocks to between the two set phase difference values, and completes circuit locking; the second modulation loop adjusts the voltage-controlled delay chain by outputting a control voltage through the feedback circuit, and modulates the phase difference between the two clocks to between the two set phase difference values; The first modulation loop includes a first filter, a first comparator, a second comparator, a NAND gate, a digital module and a bias circuit; the first filter filters the output signal of the phase detector and quantizes the clock phase difference signal to a specific voltage value V OUT1 , and sent to the negative terminal of the first comparator and the positive terminal of the second comparator respectively; The positive terminal of the first comparator is connected to the voltage value V selected by the circuit K+1 , the negative terminal of the second comparator is connected to the voltage value V selected by the circuit K-1 , the two comparators compare the specific voltage value with the two selected voltage values, and obtain the comparison result and input it into the NAND gate; The NAND gate performs NAND processing on the output results of the two comparators, and the output result is used as the state value of the circuit lock; The digital module detects the circuit lock state value and outputs a corresponding control signal according to the detection result; The bias circuit outputs a corresponding control voltage V according to the control signal CTRL1 , adjusting the delay size of the voltage-controlled delay chain; The second modulation loop includes a second filter, an operational amplifier and two MOS transistors; the second filter is used to quantize the output signal of the phase detector to a specific voltage value V OUT2 ; The operational amplifier quantizes the voltage value V OUT2 and set voltage value V K The difference between the two is amplified and the output result is used as the control voltage V of the voltage-controlled delay chain. CTRL2 , adjust the delay size of the voltage-controlled delay chain.

2. The phase calibration circuit structure according to claim 1, characterized in that: The voltage-controlled delay chain includes a plurality of voltage-controlled delay units connected in series, each of which is composed of a V CTRL1 and V CTRL2 Two control voltages adjust the output delay.

3. The phase calibration circuit structure according to claim 1, characterized in that: The first filter and the second filter are respectively formed by connecting a resistor and a capacitor in parallel.

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