Signal width repair circuit, method and electronic device

Abstract

The present disclosure relates to a signal width repair circuit, method and electronic device, and relates to the field of integrated circuit technology. The signal width repair circuit includes: a delay unit, which is used to access an input signal and delay the input signal for a preset time to obtain a delayed signal, and the input signal is a low-level signal; a signal reconstruction unit, which is used to access the input signal and the delayed signal, and perform repair processing on the input signal and the delayed signal to obtain a repair signal; a signal selection unit, which is used to access the input signal and the repair signal, and select and output the input signal and the repair signal to obtain a target signal whose width meets the preset width; wherein the preset time is equal to or greater than the duration of the preset width. The present disclosure provides a method for repairing the width of a signal so that the repaired signal width meets the use requirements of the next level circuit.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a signal width repair circuit, a signal width repair method, and an electronic device. Background Art

[0002] In the application field of integrated circuits, the normal operation of the next-level circuit depends on whether the signal generated by the previous-level circuit meets the minimum usage requirements.

[0003] However, during the transmission of the signal in the previous level circuit, the width of the signal finally generated by the previous level circuit may not meet the minimum usage requirements of the next level circuit due to time mismatch between the signals or the signal transmission path is too long, thereby affecting the normal use of the next level circuit.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to provide a signal width repair circuit, a signal width repair method and an electronic device, so as to provide a method for repairing the width of a signal so that the repaired signal width meets the use requirements of the next level circuit.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present invention.

[0007] According to a first aspect of the present disclosure, there is provided a signal width repair circuit, comprising:

[0008] A delay unit, used for receiving an input signal and delaying the input signal for a preset time to obtain a delayed signal, wherein the input signal is a low level signal;

[0009] A signal reconstruction unit, used for accessing the input signal and the delayed signal, and performing repair processing on the input signal and the delayed signal to obtain a repaired signal;

[0010] A signal selection unit is used to access the input signal and the repair signal, and select and output the input signal and the repair signal to obtain a target signal whose width meets a preset width; wherein the preset time is equal to or greater than the duration of the preset width.

[0011] Optionally, the signal reconstruction unit includes a first NAND gate, a second NAND gate and a first NOT gate; wherein,

[0012] The input terminals of the first NAND gate are respectively connected to the input signal and the output signal of the second NAND gate;

[0013] The input ends of the second NAND gate are respectively connected to the system reset signal, the delay signal and the output signal of the first NAND gate;

[0014] The input end of the first NOT gate is connected to the output end of the first NAND gate, the output end of the first NOT gate outputs the repair signal, and the width of the repair signal satisfies the preset width.

[0015] Optionally, the signal selection unit is a first multiplexer;

[0016] The input end of the first multiplexer is connected to the input signal and the repair signal respectively, the control end of the first multiplexer is connected to the repair signal, and the output end of the first multiplexer is used to output the target signal;

[0017] The first multiplexer is used for selecting to output the repair signal when the repair signal is a 0 signal, and for selecting to output the input signal when the repair signal is a 1 signal.

[0018] Optionally, the input signal is connected to input terminal 1 of the first multiplexer, and the repair signal is connected to input terminal 0 of the first multiplexer.

[0019] Optionally, it further includes: a first buffer; wherein,

[0020] The first buffer is arranged on an input line of the first multiplexer for receiving the input signal.

[0021] Optionally, the signal selection unit includes a second multiplexer and a signal width detection unit; wherein,

[0022] The input end of the signal width detection unit is connected to the input signal and the delayed signal respectively, and the output end of the signal width detection unit is connected to the control end of the second multiplexer;

[0023] The input end of the second multiplexer is respectively connected to the input signal and the repair signal, and the output end of the second multiplexer is used to output the target signal;

[0024] The signal selection unit is used to select and output the input signal when the output signal of the signal width detection unit is a 0 signal, and to select and output the repair signal when the output signal of the signal width detection unit is a 1 signal.

[0025] Optionally, the input signal is connected to input terminal 0 of the second multiplexer, and the repair signal is connected to input terminal 1 of the second multiplexer.

[0026] Optionally, the signal width detection unit is an AND gate.

[0027] Optionally, it further includes: a second buffer; wherein,

[0028] The second buffer is arranged on an input line of the second multiplexer for receiving the input signal.

[0029] Optionally, the delay unit includes at least one inverter string, and the inverter string includes a plurality of inverters connected in series.

[0030] Optionally, the delay unit further includes a plurality of switches, a plurality of inverter strings in the delay unit are connected in series, and each of the switches is connected in parallel with one of the inverter strings.

[0031] Optionally, the delay unit includes four inverter strings connected in series, and the delay times of the four inverter strings are 0.1ns, 0.2ns, 0.2ns, and 0.5ns, respectively.

[0032] Optionally, the preset time is 0.1ns-1.0ns.

[0033] Optionally, the inverter has a width-to-length ratio of 1-2.

[0034] According to a second aspect of the present disclosure, a signal width repair method is provided, which is used in a signal width repair circuit, wherein the signal width repair circuit includes a delay unit, a signal reconstruction unit, and a signal selection unit; the signal width repair method includes:

[0035] Control the delay unit to access an input signal, and delay the input signal by a preset time through the delay unit to obtain a delayed signal, wherein the input signal is a low level signal;

[0036] Controlling the signal reconstruction unit to access the input signal and the delayed signal, and performing repair processing on the input signal and the delayed signal through the signal reconstruction unit to obtain a repaired signal;

[0037] Control the signal selection unit to access the input signal and the repair signal, and select and output the input signal and the repair signal through the signal selection unit to obtain a target signal whose width meets a preset width; wherein the preset time is equal to or greater than the duration of the preset width.

[0038] According to a third aspect of the present disclosure, there is provided an electronic device, comprising: the signal width repair circuit as described above.

[0039] The technical solution provided by the present disclosure may have the following beneficial effects:

[0040] The signal width repair circuit provided by the exemplary embodiment of the present disclosure is mainly used for processing the case where the input signal is a low-level signal. By connecting the input signal and the delayed signal in the signal reconstruction unit, the input signal can be repaired to obtain a repaired signal; and then the input signal and the repaired signal are selectively output through the signal selection unit, so that a target signal whose width meets the preset width can be obtained, so as to achieve the purpose of repairing the width of the input signal, so that the signal passing through the signal width repair circuit finally meets the preset width usage requirements.

[0041] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0043] Figure 1 The structure diagram of a logic circuit in the prior art is schematically shown;

[0044] Figure 2 Schematically shows Figure 1 The waveform diagram corresponding to the logic circuit in;

[0045] Figure 3 The schematic diagram shows a structure of a long-distance transmission circuit in the prior art;

[0046] Figure 4 Schematically shows Figure 3 The waveform diagram corresponding to the long-distance transmission circuit in;

[0047] Figure 5 A schematic diagram of the structure of a signal width repair circuit according to an exemplary embodiment of the present disclosure is schematically shown;

[0048] Figure 6 A schematic diagram of the structure of a signal reconstruction unit in a width repair circuit according to an exemplary embodiment of the present disclosure is schematically shown;

[0049] Figure 7A schematic diagram schematically shows a waveform of a signal passing through a signal reconstruction unit provided by an exemplary embodiment of the present disclosure;

[0050] Figure 8 A schematic diagram of the structure of a signal width repair circuit when the signal selection unit of an exemplary embodiment of the present disclosure is a first multiplexer is shown;

[0051] Fig. 9 Schematically shows Figure 8 The signal waveform diagram corresponding to the signal width repair circuit shown;

[0052] Fig.10 A schematic diagram of the structure of another signal width repair circuit when the signal selection unit of the exemplary embodiment of the present disclosure is a second multiplexer and a signal width detection unit;

[0053] Fig.11 Schematically shows Fig.10 The signal waveform diagram corresponding to the signal width repair circuit shown;

[0054] Fig.12 A schematic diagram schematically shows waveform changes of waveforms of different widths after passing through a signal width repair circuit of an exemplary embodiment of the present disclosure;

[0055] Fig.13 A schematic diagram of the structure of a delay unit according to an exemplary embodiment of the present disclosure is shown;

[0056] Fig.14 Schematically shows a structural diagram of another delay unit according to an exemplary embodiment of the present disclosure;

[0057] Fig.15 The structure diagram of a signal width repair circuit for a high-level signal according to an exemplary embodiment of the present disclosure is schematically shown;

[0058] Fig.16 A flow chart of a signal width repairing method according to an exemplary embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0059] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.

[0060] In addition, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known structures, methods, devices, implementations, materials or operations are not shown or described in detail to avoid blurring the various aspects of the present disclosure.

[0061] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or these functional entities or parts of functional entities may be implemented in one or more software hardened modules, or these functional entities may be implemented in different networks and / or processor devices and / or microcontroller devices.

[0062] During the transmission of signals in an integrated circuit, if there is a time difference between two signals input into a circuit, the width of the signal output from the circuit may become narrower and may even fail to meet actual needs, for example, fail to meet the minimum signal width usage requirement of the next-level circuit.

[0063] For example, Figure 1 and Figure 2 As shown, when signal A and signal B pass through the logic gate circuit 100, there is a time difference of length α between signal A and signal B. B T A The delay α causes the width T of the output signal C generated after the two signals pass through the logic gate circuit 100. C Than the width of signal A A The narrow α length makes it possible that signal C cannot meet the minimum usage requirement of the next-stage circuit, thus affecting the normal use of the next-stage circuit.

[0064] There is another situation, such as Figure 3 and Figure 4 As shown, after the signal D is transmitted through the long-distance line 300, the signal D will be attenuated, the width of the output signal E will be narrowed, and it may even be distorted. There is also a situation where the minimum use requirement of the next level circuit cannot be met, thereby affecting the normal use of the next level circuit. Figure 4 As shown, the width T of signal E E Significantly smaller than the width T of signal D D .

[0065] Based on this, this exemplary embodiment provides a signal width repair circuit, which can perform width expansion processing on signals whose width is smaller than actual usage requirements so that the signal width meets the actual usage requirements; it will not have any impact on signals whose width meets or even exceeds the actual usage requirements.

[0066] Reference Figure 5 , schematically shows a structural diagram of a signal width repair circuit according to an exemplary embodiment of the present disclosure. Figure 5 As shown, the signal width repair circuit includes: a delay unit 510, a signal reconstruction unit 520 and a signal selection unit 530; wherein,

[0067] The delay unit 510 is used to access the input signal and delay the input signal for a preset time to obtain a delayed signal, where the input signal is a low-level signal; the delayed signal is obtained through the input signal, and in the subsequent signal processing process, the input signal and the delayed signal can be used to achieve the purpose of repairing the signal width.

[0068] It should be noted that the input signal here may be the signal C or signal E with a narrow signal width mentioned above, that is, a signal whose width cannot meet actual usage requirements.

[0069] The signal reconstruction unit 520 is used to access the input signal and the delayed signal, and perform repair processing on the input signal and the delayed signal to obtain a repaired signal; in this exemplary embodiment, the width of the obtained repaired signal is equal to or greater than a preset width.

[0070] The signal selection unit 530 is used to receive the input signal and the repair signal, and selectively output the input signal and the repair signal to obtain a target signal whose width meets a preset width; wherein the preset time is equal to or greater than the duration of the preset width. By selectively outputting the input signal and the repair signal, a target signal whose width meets the preset width can be obtained.

[0071] The signal width repair circuit provided by the exemplary embodiment of the present disclosure is mainly used for processing the case where the input signal is a low-level signal. By connecting the input signal and the delayed signal in the signal reconstruction unit, the input signal can be repaired to obtain a repaired signal; and then the input signal and the repaired signal are selectively output through the signal selection unit, so that a target signal whose width meets the preset width can be obtained, so as to achieve the purpose of repairing the width of the input signal, so that the signal passing through the signal width repair circuit finally meets the preset width usage requirements.

[0072] The specific structure and function of the signal width repair circuit provided by the exemplary embodiment of the present disclosure will be further described below:

[0073] Reference Figure 6 , schematically shows a structural diagram of a signal reconstruction unit according to an exemplary embodiment of the present disclosure. In this exemplary embodiment, the signal reconstruction unit 520 may include a first NAND gate 521, a second NAND gate 522 and a first NOT gate 523; wherein,

[0074] The input terminals of the first NAND gate 521 are respectively connected to the input signal IN and the output signal Y1 of the second NAND gate 522 ; the first NAND gate 521 is a two-input NAND gate.

[0075] The input ends of the second NAND gate 522 are respectively connected to the system reset signal RST, the delay signal DL and the output signal Y2 of the first NAND gate 521; the delay signal DL is obtained by delaying the input signal IN for a preset time, and the second NAND gate 522 is a three-input NAND gate.

[0076] The input end of the first NOT gate 523 is connected to the output end of the first NAND gate 521 , that is, the input end of the first NOT gate 523 is connected to the output signal Y2 of the first NAND gate 521 ; the output end of the first NOT gate 523 outputs the repair signal RP, and the width of the repair signal RP meets the preset width.

[0077] Reference Figure 7 , schematically shows a waveform diagram of a signal passing through a signal reconstruction unit provided by an exemplary embodiment of the present disclosure. Figure 7 As shown, the signal reconstruction unit 520 provided by the exemplary embodiment of the present disclosure is a low enable unit, and the signals input therein are all low level signals. Before the system reset signal RST is reset, that is, before the system reset signal RST inputs a low level signal to the second NAND gate 522, the repair signal RP output by the signal reconstruction unit 520 is unknown, and specifically, the previous signal is kept unchanged, as shown in Table 1.

[0078] When the system reset signal RST is a low level signal input to the second NAND gate 522, RST becomes a 0 signal; when RST is a 0 signal, the output signal Y1 of the second NAND gate 522 becomes a 1 signal; since the input signal IN and the output signal Y1 of the second NAND gate 522 are both 1 signals, after passing through the first NAND gate 521, the output signal Y2 of the first NAND gate 521 is a 0 signal, and finally, the output signal Y2, which is a 0 signal, passes through the first NOT gate 523, so that the repair signal RP becomes a 1 signal.

[0079] Next, when the input signal IN to the first NAND gate 521 is a low level signal, that is, the input signal IN becomes a 0 signal; at this time, the output signal Y2 of the first NAND gate 521 becomes a 1 signal, and then, after passing through the first NOT gate 523, the repair signal RP becomes a 0 signal. In this case, the repair signal RP is not affected by the delay signal DL, that is, the delay signal DL can be arbitrary.

[0080] When the delay signal DL is a low-level signal input to the second NAND gate 522, the delay signal DL becomes a 0 signal; at this time, the output signal Y1 of the second NAND gate 522 becomes a 1 signal. When the input signal IN becomes a 1 signal, the first NAND gate 521 will flip the signal, and the output signal Y2 will become a 0 signal, thereby making the final repair signal RP become a 1 signal.

[0081] like Figure 7 As shown in the figure, the time period between the start time when the input signal IN is a low level signal and the start time when the delay signal DL is a low level signal is recorded as T DL , T DL It is the delay time of the delay signal DL, that is, the preset time. DL It is also the duration of the width of the output repair signal RP; since the preset time is equal to or greater than the duration of the preset width, the width of the repair signal RP meets the preset width requirement.

[0082] Table 1

[0083] RST IN DL RP 1 1 1 Keep 0 1 1 1 1 0 Any 0 1 1 0 1

[0084] In an exemplary embodiment of the present disclosure, the signal selection unit 530 may be a first multiplexer 531. Figure 8 , schematically shows a structural diagram of a signal width repair circuit when the signal selection unit of an exemplary embodiment of the present disclosure is a first multiplexer.

[0085] like Figure 8 As shown, the input terminals 5311 and 5312 of the first multiplexer 531 are connected to the input signal IN and the repair signal RP, respectively, that is, the input terminal 5311 of the first multiplexer 531 is connected to the output terminal of the signal reconstruction unit 520. The control terminal 5313 of the first multiplexer 531 is connected to the repair signal RP, and the output terminal of the first multiplexer 531 is used to output the target signal OUT; wherein, the first multiplexer 531 can be used to select to output the repair signal RP when the repair signal RP is a 0 signal, and select to output the input signal IN when the repair signal RP is a 1 signal.

[0086] In this exemplary embodiment, the input signal IN is connected to the 1 input terminal of the first multiplexer 531, that is, the input terminal 5312 of the first multiplexer 531 is the 1 input terminal, and the repair signal RP is connected to the 0 input terminal of the first multiplexer 531, that is, the input terminal 5311 of the first multiplexer 531 is the 0 input terminal. When the repair signal RP is a 0 signal, the first multiplexer 531 will select to output the repair signal RP; when the repair signal RP is a 1 signal, the first multiplexer 531 will select to output the input signal IN. For specific waveform diagrams, please refer to Fig. 9 shown.

[0087] Fig. 9 1 shows the corresponding waveforms of the input signal IN, the delayed signal DL, the repair signal RP and the target signal OUT. Fig. 9 As shown, when the width of the input signal IN is less than the preset width, the waveforms of the corresponding delayed signal DL, the repair signal RP and the target signal OUT are as shown in area 1 901. If the delayed signal DL is the input signal IN delayed by Tmin, the width of the repair signal RP is also Tmin. When the repair signal RP is a 0 signal, the waveforms of the target signal OUT output by the first multiplexer 531 are the same as the repair signal RP, and the width of the target signal OUT is Tmin, which meets the preset width requirement.

[0088] When the width of the input signal IN is greater than the preset width, the waveforms of the corresponding delayed signal DL, repair signal RP and target signal OUT are as shown in area 2 902. If the delayed signal DL is the input signal IN delayed by Tmin, the waveform of the repair signal RP is the same as the input signal IN, and the duration of the width of the repair signal RP is greater than the duration of the preset width Tmin. When the repair signal RP is a 0 signal, the waveform of the target signal OUT output by the first multiplexer 531 is the same as that of the repair signal RP, and the duration of the width of the target signal OUT is greater than Tmin, meeting the preset width requirement.

[0089] like Figure 8 As shown, a signal width repair circuit provided in this exemplary embodiment is also provided with a first buffer 540; wherein the first buffer 540 is arranged on the input line of the first multiplexer 531 for accessing the input signal IN, and the first buffer 540 is used to enhance the input signal IN to avoid distortion of the input signal IN.

[0090] In the exemplary embodiments of the present disclosure, referring to Fig.10, schematically shows a structural diagram of another signal width repair circuit when the signal selection unit of an exemplary embodiment of the present disclosure is a second multiplexer and a signal width detection unit. The signal selection unit 530 can also be composed of a second multiplexer 532 and a signal width detection unit 533.

[0091] like Fig.10 As shown, the input end of the signal width detection unit 533 is respectively connected to the input signal IN and the delayed signal DL, and the output end of the signal width detection unit 533 is connected to the control end of the second multiplexer 532; the input end of the second multiplexer 532 is respectively connected to the input signal IN and the repair signal RP, and the output end of the second multiplexer 532 is used to output the target signal OUT.

[0092] In this exemplary embodiment, the signal selection unit 530 can be used to select to output the input signal IN when the output signal DS of the signal width detection unit 533 is a 0 signal; and select to output the repair signal RP when the output signal DS of the signal width detection unit 533 is a 1 signal.

[0093] In practical applications, the signal width detection unit 533 can be an AND gate. It should be noted that the signal width detection unit 533 can also be other structures to output the repair signal RP when the width of the input signal IN cannot meet the preset width requirement; when the width of the input signal IN meets the preset width requirement, the input signal IN is output. This exemplary embodiment does not make any special limitation on this.

[0094] In this exemplary embodiment, the input signal IN is connected to the 0 input terminal of the second multiplexer 532, that is, the input terminal 5322 of the second multiplexer 532 connected to the input signal IN is the 0 input terminal, and the repair signal RP is connected to the 1 input terminal of the second multiplexer 532, that is, the input terminal 5321 of the second multiplexer 532 connected to the repair signal RP is the 1 input terminal.

[0095] Reference Fig.11 , showing Fig.10 The waveform corresponding to the signal width repair circuit shown. Fig.11 The corresponding waveforms of the input signal IN, the delay signal DL, the repair signal RP, the output signal DS of the width detection unit and the target signal OUT are shown in FIG. When the width of the input signal IN is less than the preset width, the waveforms of the corresponding delay signal DL, the repair signal RP, the output signal DS of the width detection unit and the target signal OUT are shown in area 1101. If the delay signal DL is the input signal IN delayed by Tmin, the width of the repair signal RP is also Tmin; the output signal DS at this stage is a multi-segment signal. Fig.11As shown, when the output signal DS is a 0 signal, the input signal IN is selected to be output, and since the corresponding input signal IN is a low-level signal 0, the output target signal OUT is also a low-level signal 0; when the output signal DS is a 1 signal, the repair signal RP is selected to be output, and the corresponding repair signal RP is a low-level signal 0. Finally, the width of the low-level stage of the output target signal OUT is Tmin, which meets the preset width requirement.

[0096] When the width of the input signal IN is greater than the preset width, the waveforms of the corresponding delay signal DL, the repair signal RP, the output signal DS of the width detection unit and the target signal OUT are as shown in area 2 1102. If the delay signal DL is the input signal IN delayed by Tmin, the waveform of the repair signal RP is the same as the input signal IN, and the duration of the width of the repair signal RP is greater than the duration Tmin of the preset width; accordingly, the low level stage width of the output signal DS is the total width of the input signal IN and the delay signal DL after superposition, and the total width is greater than the width of the input signal IN. Fig.11 As shown, when the output signal DS is a 0 signal, the input signal IN is selected for output, and the final target signal OUT is obtained to be the same as the input signal IN, and the width of the low level stage is Tmin, which meets the preset width requirement.

[0097] pass Fig. 9 and Fig.11 It can be seen that when the width of the input signal IN is greater than the preset width, the input signal IN will maintain its original waveform unchanged after passing through the signal width repair circuit provided by this exemplary embodiment. Fig.12 As shown, the input signal IN has three waveforms of different widths: waveform one 1201, waveform two 1202 and waveform three 1203, wherein the duration of the width of waveform one 1201 and waveform two 1202 is less than Tmin, and the duration of the width of waveform three 1203 is greater than Tmin; in the target signal OUT finally obtained, the width of the target signal OUT corresponding to waveform one 1201 and waveform two 1202 is expanded to Tmin, while the target signal OUT corresponding to waveform three 1203 maintains the original waveform.

[0098] like Fig.10 As shown, another signal width repair circuit provided by this exemplary embodiment is also provided with a second buffer 550; wherein the second buffer 550 is arranged on the input line of the second multiplexer 532 for accessing the input signal IN, and the second buffer 550 is used to enhance the input signal IN to avoid distortion of the input signal IN.

[0099] Reference Fig.13, schematically shows a structural diagram of a delay unit according to an exemplary embodiment of the present disclosure. Optionally, the delay unit 510 may include at least one inverter string 511, and an inverter string 511 may include a plurality of inverters 5111 connected in series. The purpose of delaying the input signal IN can be achieved by using a plurality of inverters 5111.

[0100] In practical applications, different numbers of inverters 5111 can delay the input signal IN for different times. Therefore, the number of inverters 5111 can be selected according to the size of the preset time.

[0101] In this exemplary embodiment, in order to obtain a delay unit 510 with adjustable delay time, multiple inverter strings 511 can be connected in series, and multiple switches 512 are provided, each switch 512 is connected in parallel with an inverter string 511, such as Fig.14 According to the preset time required for delay, the inverter strings 511 that need to be connected can be selected, and the inverter strings 511 that do not need to be connected can be short-circuited by closing the corresponding switches 512 .

[0102] Optionally, in this exemplary embodiment, the delay unit 510 includes four inverter strings 511 connected in series, and the delay times of the four inverter strings 511 are 0.1ns, 0.2ns, 0.2ns, and 0.5ns, respectively. Then the range of the preset time selected and combined by the four inverter strings 511 may include 0.1ns-1.0ns, and the specific combination is shown in Table 2.

[0103] Table 2

[0104] 0.1ns 0.2ns 0.2ns 0.5ns Preset time √ 0.1ns √ 0.2ns √ √ 0.3ns √ √ 0.4ns √ 0.5ns √ √ 0.6ns √ √ 0.7ns √ √ √ 0.8ns √ √ √ 0.9ns √ √ √ √ 1.0ns

[0105] The √ represents the selected inverter string.

[0106] In practical applications, the smaller the width-to-length ratio of the inverter 5111 is, the smaller the current passing through it is, and the time required for transmission will be longer. Therefore, the delay time of the input signal IN will also be longer. Selecting a suitable width-to-length ratio is also a method for obtaining the preset time delay signal DL. In this exemplary embodiment, the width-to-length ratio of the inverter 5111 is set between 1 and 2.

[0107] As mentioned above, the above-mentioned signal width repair circuit provided by this exemplary embodiment is mainly applicable to the case where the input signal IN is a low-level signal. However, when the input signal IN is a high-level signal, it can be as follows Fig.15As shown, a second NOT gate 560 is set on the line of the input signal IN, and a third NOT gate 570 is set on the output target signal OUT, that is, before the input signal IN enters the signal width repair circuit 1500, the input signal IN is negated; after the signal width repair circuit 1500 processes the signal, its output signal OUT can be negated to obtain a high-level signal.

[0108] Reference Fig.16 , which shows a flow chart of a signal width repair method according to an exemplary embodiment of the present disclosure. Fig.16 The signal width repair method is used for a signal width repair circuit, the signal width repair circuit includes a delay unit, a signal reconstruction unit and a signal selection unit; the signal width repair method includes the following steps:

[0109] Step S1610, controlling the delay unit to access the input signal, and delaying the input signal by a preset time through the delay unit to obtain a delayed signal, wherein the input signal is a low level signal;

[0110] Step S1620, controlling the signal reconstruction unit to access the input signal and the delayed signal, and performing repair processing on the input signal and the delayed signal through the signal reconstruction unit to obtain a repaired signal;

[0111] Step S1630, the control signal selection unit accesses the input signal and the repair signal, and selects and outputs the input signal and the repair signal through the signal selection unit to obtain a target signal whose width meets a preset width; wherein the preset time is equal to or greater than the duration of the preset width.

[0112] The specific details of the delay unit, signal reconstruction unit and signal selection unit for performing steps S1610 to S1630 in the above-mentioned signal width repair method have been described in detail in the corresponding signal width repair circuit, so they will not be repeated here.

[0113] This exemplary embodiment also provides an electronic device, which includes the above-mentioned signal width repair circuit. After the signal in the electronic device is processed by the signal width repair circuit, the width can meet the use requirements of the next level circuit, and the signal strength can also be enhanced.

[0114] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present disclosure is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more media integrated therein. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state disk (SSD)), etc. In the embodiment of the present disclosure, the computer may include the device described above.

[0115] Although the present disclosure is described herein in conjunction with various embodiments, in the process of implementing the claimed disclosure, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in a claim. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0116] Although the present disclosure has been described in conjunction with specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present disclosure. Accordingly, this specification and the drawings are merely exemplary illustrations of the present disclosure as defined by the appended claims, and are deemed to have covered any and all modifications, variations, combinations or equivalents within the scope of the present disclosure. Obviously, those skilled in the art may make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A signal width repair circuit, characterized in that: include: A delay unit, used for receiving an input signal and delaying the input signal for a preset time to obtain a delayed signal, wherein the input signal is a low level signal; A signal reconstruction unit, configured to access the input signal and the delayed signal, and perform repair processing on the input signal and the delayed signal to obtain a repair signal; the repair processing comprises: at the start time when the input signal is flipped to a low level signal, flipping the repair signal to a low level signal, and at the start time when the delayed signal is flipped to a low level signal, flipping the repair signal to a high level signal, and the width of the repair signal is equal to the preset time; A signal selection unit is used to access the input signal and the repair signal, and select and output the input signal and the repair signal to obtain a target signal whose width meets a preset width; wherein the preset time is equal to or greater than the duration of the preset width.

2. The signal width repair circuit according to claim 1, characterized in that: The signal reconstruction unit includes a first NAND gate, a second NAND gate and a first NOT gate; wherein, The input terminals of the first NAND gate are respectively connected to the input signal and the output signal of the second NAND gate; The input ends of the second NAND gate are respectively connected to the system reset signal, the delay signal and the output signal of the first NAND gate; The input end of the first NOT gate is connected to the output end of the first NAND gate, the output end of the first NOT gate outputs the repair signal, and the width of the repair signal satisfies the preset width.

3. The signal width repair circuit according to claim 1, characterized in that: The signal selection unit is a first multiplexer; The input end of the first multiplexer is connected to the input signal and the repair signal respectively, the control end of the first multiplexer is connected to the repair signal, and the output end of the first multiplexer is used to output the target signal; The first multiplexer is used for selecting to output the repair signal when the repair signal is a 0 signal, and for selecting to output the input signal when the repair signal is a 1 signal.

4. The signal width repair circuit according to claim 3, characterized in that: The input signal is connected to the 1 input terminal of the first multiplexer, and the repair signal is connected to the 0 input terminal of the first multiplexer.

5. The signal width repair circuit according to claim 3 or 4, characterized in that: Also includes: The first buffer; wherein The first buffer is arranged on an input line of the first multiplexer for receiving the input signal.

6. The signal width repair circuit according to claim 1, characterized in that: The signal selection unit includes a second multiplexer and a signal width detection unit; wherein, The input end of the signal width detection unit is connected to the input signal and the delayed signal respectively, and the output end of the signal width detection unit is connected to the control end of the second multiplexer; The input end of the second multiplexer is respectively connected to the input signal and the repair signal, and the output end of the second multiplexer is used to output the target signal; The signal selection unit is used to select and output the input signal when the output signal of the signal width detection unit is a 0 signal, and to select and output the repair signal when the output signal of the signal width detection unit is a 1 signal.

7. The signal width repair circuit according to claim 6, characterized in that: The input signal is connected to the 0 input terminal of the second multiplexer, and the repair signal is connected to the 1 input terminal of the second multiplexer.

8. The signal width repair circuit according to claim 6 or 7, characterized in that: The signal width detection unit is an AND gate.

9. The signal width repair circuit according to claim 6, characterized in that: Also includes: The second buffer; wherein The second buffer is arranged on an input line of the second multiplexer for receiving the input signal.

10. The signal width repair circuit according to claim 1, characterized in that: The delay unit includes at least one inverter string, and the inverter string includes a plurality of inverters connected in series.

11. The signal width repair circuit according to claim 10, characterized in that: The delay unit further includes a plurality of switches. The plurality of inverter strings in the delay unit are connected in series, and each of the switches is connected in parallel with one of the inverter strings.

12. The signal width repair circuit according to claim 11, characterized in that: The delay unit includes four inverter strings connected in series, and the delay times of the four inverter strings are 0.1ns, 0.2ns, 0.2ns, and 0.5ns respectively.

13. The signal width repair circuit according to claim 1 or 10, characterized in that: The preset time is 0.1ns-1.0ns.

14. The signal width repair circuit according to any one of claims 10 to 12, characterized in that: The inverter has a width-to-length ratio of 1-2.

15. A signal width repair method, characterized in that: Used in a signal width repair circuit, the signal width repair circuit includes a delay unit, a signal reconstruction unit and a signal selection unit; the signal width repair method includes: Control the delay unit to access an input signal, and delay the input signal by a preset time through the delay unit to obtain a delayed signal, wherein the input signal is a low level signal; Control the signal reconstruction unit to access the input signal and the delayed signal, and perform repair processing on the input signal and the delayed signal through the signal reconstruction unit to obtain a repair signal; the repair processing includes: at the starting moment when the input signal flips to a low-level signal, flipping the repair signal to a low-level signal, and at the starting moment when the delayed signal flips to a low-level signal, flipping the repair signal to a high-level signal, and the width of the repair signal is equal to the preset time; Control the signal selection unit to access the input signal and the repair signal, and select and output the input signal and the repair signal through the signal selection unit to obtain a target signal whose width meets a preset width; wherein the preset time is equal to or greater than the duration of the preset width.

16. An electronic device, characterized in that: include: A signal width repair circuit as described in any one of claims 1 to 14.

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