High-density fan-out package structure and method of manufacturing the same

Abstract

The application provides a high-density fan-out packaging structure and a preparation method thereof. The method comprises the following steps: providing a silicon substrate, pasting a passive surface of a chip to be packaged on the silicon substrate; plastic packaging the chip to be packaged to obtain a plastic packaging layer, wherein a top surface of the plastic packaging layer is at the same horizontal plane as a top end of an interconnection column on an active surface of the chip to be packaged; preparing a multilayer wiring layer on the top surface of the plastic packaging layer, so that the multilayer wiring layer and the interconnection column are interconnected; preparing a welding member on the multilayer wiring layer, which is in conductive connection with a packaging interconnection body; and thinning the silicon substrate to obtain a high-density fan-out packaging structure. The application solves the problem of chip warping in the preparation of the high-density fan-out packaging structure in the prior art.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip packaging, in particular to a high-density fan-out packaging structure and a preparation method thereof. BACKGROUND

[0002] In the prior art, the preparation process of the fan-out packaging structure is usually to fix the active surface of the chip towards the carrier board, to perform bottom filling on the chip, to perform plastic encapsulation filling through epoxy resin material, to paste the carrier board on the passive surface of the chip corresponding to the plastic encapsulation filling layer, and to remove the carrier board corresponding to the active surface of the chip, and to prepare a redistribution layer of the fan-out packaging structure on the active surface of the chip. However, this packaging process has a warping problem that cannot be solved at present, and the reason is that the carrier board is usually made of stainless steel or glass material, and the CTE (Coefficient of Thermal Expansion) of these two materials is quite different from that of the silicon material of the chip, so that the chip warping phenomenon occurs in the subsequent multiple high-temperature reflow processes.

[0003] It can be seen that the high-density fan-out packaging structure in the prior art has the problem of chip warping in the manufacturing process, which affects the stability and reliability of the packaging structure. SUMMARY

[0004] In view of the deficiencies in the prior art, the high-density fan-out packaging structure and the preparation method thereof provided by the present application solve the problem of chip warping in the manufacturing process of the high-density fan-out packaging structure in the prior art.

[0005] In a first aspect, the present application provides a preparation method of a high-density fan-out packaging structure, which comprises: providing a silicon substrate, pasting a passive surface of a chip to be packaged on the silicon substrate; performing plastic encapsulation on the chip to be packaged to obtain a plastic encapsulation layer, wherein the top surface of the plastic encapsulation layer is at the same horizontal plane as the top end of an interconnection column on the active surface of the chip to be packaged; preparing a multilayer wiring layer on the top surface of the plastic encapsulation layer, so that the multilayer wiring layer and the interconnection column are connected to each other; preparing a soldering member for conductive interconnection with a packaging interconnection body on the multilayer wiring layer; and performing thinning treatment on the silicon substrate to obtain a high-density fan-out packaging structure.

[0006] Optionally, pasting the passive surface of the chip to be packaged on the silicon substrate comprises: providing a glue connecting structure, pasting one surface of the glue connecting structure on the silicon substrate; and pasting the passive surface of the chip to be packaged on the other surface of the glue connecting structure.

[0007] Optionally, the passive surface of the chip to be packaged is attached to the silicon substrate, comprising: grinding the passive surface of the chip to be packaged and one surface of the silicon substrate respectively to obtain a chip mirror surface silicon base and a substrate mirror surface silicon base respectively; providing a metal sheet, grinding two surfaces of the metal sheet respectively to obtain a first mirror surface metal surface and a second mirror surface metal surface; bonding the chip mirror surface silicon base to the first mirror surface metal surface, and bonding the second mirror surface metal surface to the substrate mirror surface silicon base.

[0008] Optionally, the bonding of the chip mirror surface silicon base to the first mirror surface metal surface and the bonding of the second mirror surface metal surface to the substrate mirror surface silicon base comprises: providing a support carrier, and thermally pressing the first mirror surface metal surface on the support carrier through a temporary bonding glue layer; bonding the second mirror surface metal surface to the substrate mirror surface silicon base; after removing the support carrier by debonding, bonding the first mirror surface metal surface to the chip mirror surface silicon base.

[0009] Optionally, a silicon-aluminum alloy layer is formed between the chip mirror surface silicon base and the first mirror surface metal surface, and the bonding temperature between the chip mirror surface silicon base and the first mirror surface metal surface is 550-600°C; a silicon-aluminum alloy layer is formed between the second mirror surface metal surface and the substrate mirror surface silicon base, and the bonding temperature between the second mirror surface metal surface and the substrate mirror surface silicon base is 550-600°C.

[0010] Optionally, a multilayer wiring layer is prepared on the top surface of the plastic package layer, comprising: step S1, after spin coating photoresist on the top surface of the plastic package layer and performing baking, exposure and development, a first dielectric layer with a first opening array is prepared; wherein the first opening array corresponds to the interconnection column on the active surface of the chip to be packaged; step S2, a copper nucleus layer is prepared on the first opening array and copper is electroplated to prepare a first copper wiring layer; step S3, after spin coating photoresist on the first copper wiring layer and performing baking, exposure and development, a second dielectric layer with a second opening array is prepared; wherein the second opening array corresponds to the copper column in the first copper wiring layer; step S4, a copper nucleus layer is prepared on the second opening array and copper is electroplated to prepare a second copper wiring layer; step S4, steps S3-S4 are repeated, and a (n+1)th dielectric layer and a (n+1)th copper wiring layer are prepared in turn on the nth copper wiring layer until the preparation of the multilayer wiring layer is completed; wherein n is a positive integer greater than 1.

[0011] Optionally, the silicon substrate is thinned to obtain a high-density fan-out packaging structure, including: providing a protective film and covering the welding member with the protective film; providing a temporary carrier and attaching the temporary carrier to the protective film to obtain a chip package; flipping the chip package, thinning the silicon substrate, and removing the temporary carrier and the protective film to obtain the high-density fan-out packaging structure.

[0012] Optionally, the chip to be packaged is encapsulated to obtain a molding layer, wherein the top surface of the molding layer is at the same level as the top of the interconnect pillars on the active surface of the chip to be packaged, comprising: encapsulating the chip to be packaged to obtain a pre-molding layer, wherein the top surface of the pre-molding layer is at the same level as the conductive pads in the chip to be packaged that are flush with the active surface; preparing interconnect pillars on the top surface of the pre-molding layer, such that the interconnect pillars are connected to the conductive pads; and encapsulating the interconnect pillars to obtain a molding layer, wherein the top surface of the molding layer is at the same level as the top of the interconnect pillars on the active surface of the chip to be packaged.

[0013] Secondly, the present invention provides a high-density fan-out packaging structure, the packaging structure comprising: a silicon substrate, a chip to be packaged, a molding compound, a multilayer wiring layer, and a welding component; one side of the silicon substrate is bonded to the passive side of the chip to be packaged; the chip to be packaged includes a conductive pad flush with the active side of the chip and an interconnect pillar connected to the conductive pad, and the chip to be packaged and the interconnect pillar are disposed on the molding compound, wherein the top surface of the molding compound and the top end of the interconnect pillar on the active side of the chip to be packaged are at the same horizontal plane; the multilayer wiring layer is disposed on the top surface of the molding compound, such that the multilayer wiring layer and the interconnect pillar are interconnected; the welding component is disposed on the multilayer wiring layer for conductive interconnection with the package interconnect.

[0014] Optionally, the packaging structure further includes a metal sheet disposed between the silicon substrate and the passive surface of the chip to be packaged.

[0015] Optionally, the metal sheet may include an aluminum sheet.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] In the packaging structure fabrication method of this embodiment, a silicon substrate is used to provide mechanical support for the chip to be packaged. After the packaging process is completed, the silicon substrate is not removed, but only thinned to reduce the complexity and workload of the dicing process in the board-level packaging plant. Compared with the packaging structure in the prior art, the packaging structure of the present invention increases the volume ratio of silicon material to molding layer, and the difference in thermal expansion coefficients between the silicon substrate, molding layer and chip substrate material is small, which can reduce the chip warpage problem in subsequent heat treatment processes. In addition, the silicon substrate is still retained after chip packaging. During its long-distance transportation, the silicon substrate is used to provide the chip package with anti-mechanical vibration caused by transportation, thereby improving the mechanical reliability of the chip package. Attached Figure Description

[0018] Figure 1 The diagram shown is a flowchart illustrating a method for fabricating a high-density fan-out packaging structure according to an embodiment of the present invention.

[0019] Figure 2 The diagram shown is a schematic diagram of a molding compound preparation method provided by an embodiment of the present invention;

[0020] Figure 3 The diagram shown is a schematic diagram of a thinning treatment of the molding compound layer according to an embodiment of the present invention;

[0021] Figure 4 The diagram shown is a schematic diagram of a method for fabricating a first dielectric layer according to an embodiment of the present invention;

[0022] Figure 5 The diagram shown is a schematic diagram of a method for preparing a first metal layer according to an embodiment of the present invention;

[0023] Figure 6 The diagram shown is a schematic diagram of a method for fabricating a multilayer wiring layer according to an embodiment of the present invention;

[0024] Figure 7 The diagram shown is a schematic representation of a method for preparing a welded component according to an embodiment of the present invention.

[0025] Figure 8 The diagram shown is a schematic diagram of a chip package fabrication method provided by an embodiment of the present invention;

[0026] Figure 9 The diagram shown is a schematic diagram of a silicon substrate after thinning according to an embodiment of the present invention;

[0027] Figure 10 The diagram shown is a schematic representation of cutting a chip package according to an embodiment of the present invention;

[0028] Figure 11 The diagram shown is a structural schematic of a high-density fan-out packaging structure provided in an embodiment of the present invention.

[0029] Figure 12 The diagram shown is a schematic representation of grinding a chip, a metal sheet, and a silicon substrate according to an embodiment of the present invention.

[0030] Figure 13 The diagram shown is a schematic representation of the bonding of a chip, a metal sheet, and a silicon substrate according to an embodiment of the present invention.

[0031] Figure 14 The diagram shown is a schematic diagram of a method for preparing interconnect pillars according to an embodiment of the present invention;

[0032] Figure 15 The diagram shown is a schematic diagram of another method for preparing a molding compound according to an embodiment of the present invention;

[0033] Figure 16 The diagram shown is a schematic diagram of another high-density fan-out packaging structure provided in an embodiment of the present invention. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0035] In a first aspect, the present invention provides a method for fabricating a high-density fan-out packaging structure, specifically including the following embodiments:

[0036] Example 1

[0037] Figure 1 The diagram shown is a flowchart illustrating a method for fabricating a high-density fan-out packaging structure according to an embodiment of the present invention; as shown... Figure 1 As shown, the fabrication method of the high-density fan-out packaging structure specifically includes the following steps:

[0038] Step S101: Provide a silicon substrate and attach the passive side of the chip to be packaged onto the silicon substrate.

[0039] In this embodiment, attaching the passive side of the chip to be packaged onto the silicon substrate includes: providing an adhesive structure, attaching one side of the adhesive structure to the silicon substrate, and attaching the passive side of the chip to be packaged to the other side of the adhesive structure.

[0040] It should be noted that, as Figure 2As shown, an adhesive bonding structure 11 is attached to the silicon substrate 10, and the passive surfaces of the chip to be packaged 100 and the chip to be packaged 200 are attached to the silicon substrate 10 through the adhesive bonding structure 11.

[0041] Step S102: The chip to be packaged is encapsulated to obtain a molding layer, wherein the top surface of the molding layer is at the same level as the top of the interconnect pillars on the active surface of the chip to be packaged.

[0042] like Figure 2 As shown, the chip to be packaged and the interconnect pillars on the chip are encapsulated with plastic, and chip 100 and chip 200 are encapsulated by plastic layer 12.

[0043] like Figure 3 As shown, the molding compound 12 is thinned until the interconnect post 21 is exposed, so that the top surface of the molding compound 12 and the top of the interconnect post 21 are on the same horizontal plane.

[0044] Step S103: Prepare a multilayer wiring layer on the top surface of the molding compound, and connect the multilayer wiring layer to the interconnect pillars.

[0045] In this embodiment, a multilayer wiring layer is fabricated on the top surface of the molding compound, including:

[0046] Step S1: After spin coating photoresist on the top surface of the molding layer and drying, exposing and developing it, a first dielectric layer with a first opening array is prepared; wherein, the first opening array corresponds to the interconnect pillars on the active surface of the chip to be packaged.

[0047] like Figure 4 As shown, a first dielectric layer 31 with a first opening array 30 is prepared by spin-coating photoresist on the surface of the thinned molding layer 12, followed by drying, exposure, and development; wherein the first opening array 30 corresponds to the interconnect pillar 21.

[0048] Step S2: Prepare a copper nucleus layer on the first opening array and electroplate copper to obtain the first copper wiring layer.

[0049] In this embodiment, a metal nucleus layer and / or a metal stack of a metal barrier layer and a metal nucleus layer are magnetron sputtered on the first opening array, and copper is electroplated on the metal nucleus layer to prepare a first copper wiring layer.

[0050] Other deposition methods can also be used to prepare the metal nucleus layer and the metal barrier layer, including physical vapor deposition, chemical vapor deposition, and magnetron sputtering of metal targets.

[0051] The metal barrier layer can be made of one or any combination of Ni, Ti, Cu, Pd, Pt or Ti-W.

[0052] Copper is preferred as the metal nucleus layer.

[0053] like Figure 5 As shown, a nickel barrier layer and a copper seed layer are magnetron sputtered on a first dielectric layer 31 having a first opening array 30; then, electroplating of metallic copper fills the first opening array 30 to prepare a first metal layer 32.

[0054] Step S3: After spin-coating photoresist onto the first copper wiring layer and performing drying, exposure and development, a second dielectric layer with a second opening array is prepared; wherein, the second opening array corresponds to the copper pillars in the first copper wiring layer;

[0055] Step S4: Electroplating copper on the second opening array to prepare a second copper wiring layer;

[0056] Step S4: Repeat steps S3-S4 to sequentially prepare the (n+1)th dielectric layer and the (n+1)th copper wiring layer until the fabrication of the multilayer wiring layer is completed.

[0057] Where n is a positive integer greater than 1.

[0058] like Figure 6 As shown, when n=4, the above steps are repeated to prepare 4 wiring layers. The first wiring layer includes a first dielectric layer 31 and a first copper wiring layer 32; the second wiring layer includes a second dielectric layer 41 and a second copper wiring layer 42; the third wiring layer includes a third dielectric layer 51 and a third copper wiring layer 52; and the fourth wiring layer includes a fourth dielectric layer 61 and a fourth copper wiring layer 62.

[0059] Step S104: Prepare a solder component on the multilayer wiring layer that is electrically interconnected with the package interconnect.

[0060] like Figure 7 As shown, a welding component 22 is prepared on a copper pad on a fourth metal layer 62, wherein the welding component 22 includes a connecting post and a C4 solder ball.

[0061] In this embodiment, the preparation of C4 solder balls requires a high-temperature reflow process.

[0062] The package interconnect may include: a PCB board, a chip package with electrical connection structure, a silicon substrate with conductive vias, a bridging chip with conductive vias, and a metal routing layer (RDL).

[0063] Step S105: The silicon substrate is thinned to obtain a high-density fan-out packaging structure.

[0064] In this embodiment, the silicon substrate is thinned to obtain a high-density fan-out packaging structure, including: providing a protective film and covering the welding member with the protective film; providing a temporary carrier and attaching the temporary carrier to the protective film to obtain a chip package; flipping the chip package, thinning the silicon substrate, and removing the temporary carrier and the protective film to obtain the high-density fan-out packaging structure.

[0065] like Figure 8 As shown, a protective film 13 and a temporary carrier plate 14 are provided. The protective film 13 is covered on the welding component 22 to protect the welding component 22. The temporary carrier plate 14 is attached to the protective film 13 to obtain a chip package. The chip package is then flipped over to perform a thinning process on the silicon substrate 10. The thickness of the silicon substrate 10 after the thinning process is 5-100 μm. Figure 9 As shown.

[0066] like Figure 10 As shown, after removing the protective film 13 and the temporary carrier 14, the chip package is cut along the cutting line 15 to obtain the following... Figure 10 The high-density fan-out package structure M10 is shown.

[0067] Alternatively, a temporary carrier plate can be attached using temporary bonding adhesive, and then removed using laser debonding.

[0068] Compared with the prior art, this embodiment has the following beneficial effects:

[0069] 1. In the packaging structure preparation method of this embodiment, a silicon substrate is used to provide mechanical support for the chip to be packaged. After the packaging process is completed, the silicon substrate is not removed, but only thinned to reduce the complexity and workload of the dicing process in the board-level packaging plant. Compared with the packaging structure in the prior art, the packaging structure of the present invention increases the volume ratio of silicon material to molding layer, and the difference in thermal expansion coefficients between the silicon substrate, molding layer and chip substrate material is small, which can reduce the chip warpage problem in subsequent heat treatment processes. In addition, the silicon substrate is still retained after chip packaging. During its long-distance transportation, the silicon substrate is used to provide the chip package with anti-mechanical vibration caused by transportation, thereby improving the mechanical reliability of the chip package.

[0070] 2. In the packaging structure preparation method of this embodiment, by electroplating a metal layer in the multilayer wiring layer on the chip interconnect pillar, the conductive connection between the interconnect pillar and the metal layer can be achieved without undergoing a heat treatment process. In contrast, the prior art generally achieves the conductive connection between the chip interconnect pillar and the multilayer wiring layer by depositing tin-based alloy solder and then performing a high-temperature reflow process. Compared with the prior art, this embodiment can reduce the warpage problem caused by the added high-temperature reflow heat treatment process in the chip package.

[0071] 3. In the packaging structure preparation method of this embodiment, a silicon substrate is used as the chip-level packaging substrate. When the chip is packaged at the board level, the high thermal conductivity of the silicon substrate can improve the heat dissipation capacity of the chip.

[0072] Example 2

[0073] In this embodiment, attaching the passive side of the chip to be packaged onto the silicon substrate includes: grinding the passive side of the chip to be packaged and one side of the silicon substrate to obtain a mirror silicon substrate surface of the chip and a mirror silicon substrate surface of the substrate, respectively; providing a metal sheet and grinding both sides of the metal sheet to obtain a first mirror metal surface and a second mirror metal surface, respectively; and bonding the mirror silicon substrate surface of the chip to the first mirror metal surface.

[0074] In this embodiment, bonding the chip's mirror silicon substrate to the first mirror metal surface and bonding the second mirror metal surface to the substrate's mirror silicon substrate includes: providing a support carrier; hot-pressing the first mirror metal surface onto the support carrier using a temporary bonding adhesive layer; bonding the second mirror metal surface to the substrate's mirror silicon substrate; and after debonding and removing the support carrier, bonding the first mirror metal surface to the chip's mirror silicon substrate.

[0075] A silicon-aluminum alloy layer is formed between the silicon substrate of the chip mirror and the first mirror metal surface, and the bonding temperature between the silicon substrate of the chip mirror and the first mirror metal surface is 550℃-600℃; a silicon-aluminum alloy layer is formed between the second mirror metal surface and the silicon substrate of the substrate mirror, and the bonding temperature between the second mirror metal surface and the silicon substrate of the substrate mirror is 550℃-600℃.

[0076] It should be noted that, as Figure 12 As shown, the passive surface F2 of chips 100, 200, and 300 is refined through grinding to obtain a mirror-like silicon substrate surface; the first mirror metal surface F3 and the second mirror metal surface F4 of metal sheet 16 are refined through grinding to obtain a mirror-like first metal surface and a mirror-like second metal surface; the first surface F5 of silicon substrate 10 is refined through grinding to obtain a mirror-like substrate surface.

[0077] like Figure 13As shown, the hot pressing device provides an aluminum-silicon alloy temperature of 550℃-600℃, a pressing pressure, and a vacuum atmosphere. 577℃ is the melting point temperature of the aluminum-silicon alloy. The heating module in the hot pressing device can achieve bonding between the chip mirror silicon substrate F2 and the first mirror metal surface F3 of the metal sheet 16, the substrate mirror silicon substrate F5 of the silicon substrate 10 and the second mirror metal surface F4 of the metal sheet 16, so that aluminum atoms diffuse into the silicon lattice under high temperature and high pressure to obtain a silicon-aluminum alloy layer. The chip and the silicon substrate 10 are bonded together by the metal sheet 16.

[0078] In this embodiment, the metal sheet includes an aluminum sheet.

[0079] In this embodiment, the chip to be packaged is encapsulated to obtain an encapsulation layer, wherein the top surface of the encapsulation layer is at the same horizontal level as the top of the interconnect pillars on the active surface of the chip to be packaged. This includes: encapsulating the chip to be packaged to obtain a pre-encapsulation layer, wherein the top surface of the pre-encapsulation layer is at the same horizontal level as the conductive pads flush with the active surface of the chip to be packaged; preparing interconnect pillars on the top surface of the pre-encapsulation layer, connecting the interconnect pillars to the conductive pads; and encapsulating the interconnect pillars to obtain the encapsulation layer, wherein the top surface of the encapsulation layer is at the same horizontal level as the top of the interconnect pillars on the active surface of the chip to be packaged.

[0080] like Figure 14 As shown, the chip is encapsulated to obtain a pre-encapsulation layer 17; the pre-encapsulation layer 17 is thinned until the conductive pads on the active surface of the chip are exposed, so that the top surface of the pre-encapsulation layer is at the same level as the conductive pads that are flush with the active surface in the chip to be encapsulated; interconnect pillars 21 are prepared on the surface of the pre-encapsulation layer 17.

[0081] like Figure 15 As shown, the interconnect pillar 21 is encapsulated to obtain an encapsulation layer 18. The encapsulation layer 18 is then thinned until the interconnect pillar 21 is exposed, so that the top surface of the encapsulation layer 18 is at the same level as the top of the interconnect pillar 21 on the active surface of the chip to be encapsulated.

[0082] In this embodiment, the processes of fabricating a multilayer wiring layer on the top surface of the molding compound, fabricating a welding component on the multilayer wiring layer that is electrically interconnected with the package interconnect, and thinning the silicon substrate are the same as in Embodiment 1 above, thereby obtaining the desired product. Figure 16 The high-density fan-out packaging structure shown.

[0083] Compared with the prior art, this embodiment has the following beneficial effects:

[0084] 1. In the packaging structure preparation method of this embodiment, a silicon substrate is used to provide mechanical support for the chip to be packaged. After the packaging process is completed, the silicon substrate is not removed, but only thinned to reduce the complexity and workload of the dicing process in the board-level packaging plant. Compared with the packaging structure in the prior art, the packaging structure of the present invention increases the volume ratio of silicon material to molding layer, and the difference in thermal expansion coefficients between the silicon substrate, molding layer and chip substrate material is small, which can reduce the chip warpage problem in subsequent heat treatment processes. In addition, the silicon substrate is still retained after chip packaging. During its long-distance transportation, the silicon substrate is used to provide the chip package with anti-mechanical vibration caused by transportation, thereby improving the mechanical reliability of the chip package.

[0085] 2. In the packaging structure preparation method of this embodiment, the passive surface of the silicon substrate of the chip and the aluminum sheet, and the surface of the aluminum sheet and the silicon substrate are pressed together by hot pressing aluminum sheet. The aluminum atoms diffuse into the silicon lattice by silicon-aluminum bonding, which not only realizes the bonding between the silicon substrate and the passive surface of the chip, but also provides a fast heat dissipation channel for the packaging structure.

[0086] Secondly, the present invention provides a high-density fan-out packaging structure, specifically including the following embodiments:

[0087] Example 3

[0088] like Figure 11 As shown, the high-density fan-out packaging structure includes:

[0089] Silicon substrate, chip to be packaged, molding layer, multilayer wiring layer and soldering components;

[0090] One side of the silicon substrate is bonded to the passive side of the chip to be packaged;

[0091] The chip to be packaged includes a conductive pad flush with the active surface of the chip and an interconnect post connected to the conductive pad. The chip to be packaged and the interconnect post are disposed in the plastic package, wherein the top surface of the plastic package layer and the top of the interconnect post on the active surface of the chip to be packaged are at the same level.

[0092] The multi-layer wiring layer is disposed on the top surface of the molding layer, and the multi-layer wiring layer is interconnected with the interconnect post;

[0093] The welding component is disposed on the multilayer wiring layer and is used for conductive interconnection with the package interconnect.

[0094] In this embodiment, the packaging structure further includes an adhesive bonding structure disposed between the silicon substrate and the passive surface of the chip to be packaged.

[0095] It should be noted that, in this embodiment, the active surface F1 of chip 100 corresponds to the circuit structure of the chip. The conductive pad 20 built into chip 100 is flush with the active surface F1 of chip 100, and the interconnect pillar 21 is connected to the conductive pad 20. Chip 100 and the interconnect pillar 21 on it are encapsulated in the molding compound 12. The surface of the molding compound 12 corresponding to the active surface F1 of chip 100 is a multi-layer high-density fan-out wiring layer. The wiring layer includes: a first wiring layer, a second wiring layer, a third wiring layer and a fourth wiring layer. The first wiring layer includes a first dielectric layer 31 and a first copper wiring layer 32. The second wiring layer includes a second dielectric layer 41 and a second copper wiring layer 42. The third wiring layer includes a third dielectric layer 51 and a third copper wiring layer 52. The fourth wiring layer includes a fourth dielectric layer 61 and a fourth copper wiring layer 62. C4 solder balls are on the fourth copper wiring layer 62 for interconnection with the package interconnect. The passive surface F2 of the chip 100 is bonded to the first surface of the adhesive structure 11, and the second surface of the adhesive structure 11 is correspondingly bonded to the silicon substrate 10a.

[0096] This embodiment uses a silicon substrate to provide mechanical support for the chip to be packaged, and retains the silicon substrate after the fabrication process is completed. Only the silicon substrate is thinned to reduce the complexity and workload of the dicing process in the board-level packaging plant. Compared with the packaging structure in the prior art, the packaging structure of the present invention improves the volume ratio of silicon material to molding layer, and the difference in thermal expansion coefficients between the silicon substrate, molding layer and chip base material is small, which can reduce the problem of chip warpage in subsequent heat treatment processes.

[0097] Example 4

[0098] like Figure 16 As shown, the high-density fan-out packaging structure provided in this embodiment includes: a silicon substrate, a chip to be packaged, a molding layer, a multilayer wiring layer, and welding components;

[0099] One side of the silicon substrate is bonded to the passive side of the chip to be packaged;

[0100] The chip to be packaged includes a conductive pad flush with the active surface of the chip and an interconnect post connected to the conductive pad. The chip to be packaged and the interconnect post are disposed in the molding compound, wherein the top surface of the molding compound and the top of the interconnect post on the active surface of the chip to be packaged are at the same level.

[0101] The multi-layer wiring layer is disposed on the top surface of the molding layer, and the multi-layer wiring layer is interconnected with the interconnect post;

[0102] The welding component is disposed on the multilayer wiring layer and is used for conductive interconnection with the package interconnect.

[0103] In this embodiment, the packaging structure further includes a metal sheet disposed between the silicon substrate and the passive surface of the chip to be packaged.

[0104] In this embodiment, the metal sheet includes an aluminum sheet.

[0105] It should be noted that the aluminum sheet 16 connects the passive surface F2 of the chip 100 and the silicon substrate 10a. The aluminum sheet has a higher thermal conductivity than the adhesive structure 11 in Embodiment 1, which can quickly conduct the heat generated by the chip 100 to the silicon material with high thermal conductivity, thereby quickly dissipating the heat of the chip.

[0106] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A method for fabricating a high-density fan-out packaging structure, characterized in that, The method includes: A silicon substrate is provided, and the passive side of the chip to be packaged is attached to the silicon substrate; The chip to be packaged is encapsulated to prepare an encapsulation layer, wherein the top surface of the encapsulation layer is at the same level as the top of the interconnect pillars on the active surface of the chip to be packaged; A multi-layer wiring layer is prepared on the top surface of the molding compound, and the multi-layer wiring layer is interconnected with the interconnect pillars; A soldered component is fabricated on the multilayer wiring layer to be electrically interconnected with the package interconnect; The silicon substrate is thinned to obtain a high-density fan-out packaging structure; The passive side of the chip to be packaged is attached to the silicon substrate, including: The passive side of the chip to be packaged and one side of the silicon substrate are respectively ground to obtain a mirror silicon substrate surface of the chip and a mirror silicon substrate surface of the substrate. A metal sheet is provided, and both sides of the metal sheet are ground to obtain a first mirror metal surface and a second mirror metal surface, respectively. The chip's mirror silicon substrate is bonded to the first mirror metal surface, and the second mirror metal surface is bonded to the substrate's mirror silicon substrate.

2. The method for preparing the high-density fan-out packaging structure as described in claim 1, characterized in that, The passive side of the chip to be packaged is attached to the silicon substrate, including: An adhesive bonding structure is provided, wherein one side of the adhesive bonding structure is attached to the silicon substrate; The passive side of the chip to be packaged is attached to the other side of the adhesive structure.

3. The method for preparing the high-density fan-out packaging structure as described in claim 1, characterized in that, Bonding the chip's mirror silicon substrate to the first mirror metal surface, and bonding the second mirror metal surface to the substrate's mirror silicon substrate, includes: A support substrate is provided, and the first mirror metal surface is hot-pressed onto the support substrate through a temporary bonding adhesive layer; The second mirror metal surface is bonded to the mirror silicon substrate surface of the substrate; After debonding and removing the support substrate, the first mirror metal surface is bonded to the chip mirror silicon substrate surface.

4. The method for preparing the high-density fan-out packaging structure as described in claim 3, characterized in that, A silicon-aluminum alloy layer is formed between the silicon substrate of the chip mirror and the first metal surface of the mirror, and the bonding temperature between the silicon substrate of the chip mirror and the first metal surface of the mirror is 550℃-600℃. A silicon-aluminum alloy layer is formed between the second mirror metal surface and the substrate mirror silicon base surface, and the bonding temperature between the second mirror metal surface and the substrate mirror silicon base surface is 550℃-600℃.

5. The method for preparing the high-density fan-out packaging structure as described in claim 2, characterized in that, A multilayer wiring layer is fabricated on the top surface of the molding compound, including: Step S1: After spin coating photoresist on the top surface of the molding layer and drying, exposing and developing it, a first dielectric layer with a first opening array is prepared; wherein, the first opening array corresponds to the interconnect pillars on the active surface of the chip to be packaged. Step S2: Prepare a copper nucleus layer on the first opening array and electroplate copper to obtain the first copper wiring layer; Step S3: After spin-coating photoresist onto the first copper wiring layer and performing drying, exposure and development, a second dielectric layer with a second opening array is prepared; wherein, the second opening array corresponds to the copper pillars in the first copper wiring layer; Step S4: Prepare a copper nucleus layer on the second opening array and electroplate copper to obtain a second copper wiring layer; Step S5: Repeat steps S3-S4 to sequentially prepare the (n+1)th dielectric layer and the (n+1)th copper wiring layer on the nth copper wiring layer until the fabrication of the multilayer wiring layer is completed. Where n is a positive integer greater than 1.

6. The method for preparing the high-density fan-out packaging structure as described in claim 1, characterized in that, The silicon substrate is thinned to obtain a high-density fan-out package structure, comprising: A protective film is provided to cover the welded component; A temporary carrier board is provided, and the temporary carrier board is attached to the protective film to obtain a chip package. The chip package is flipped over, the silicon substrate is thinned, and the temporary carrier and protective film are removed to obtain a high-density fan-out package structure.

7. The method for preparing the high-density fan-out packaging structure as described in claim 1, characterized in that, The chip to be packaged is encapsulated to obtain a molding layer, wherein the top surface of the molding layer is at the same level as the top of the interconnect pillars on the active surface of the chip to be packaged, including: The chip to be packaged is encapsulated to obtain a pre-encapsulation layer, wherein the top surface of the pre-encapsulation layer is on the same horizontal plane as the conductive pad in the chip to be packaged that is flush with the active surface. Interconnect pillars are fabricated on the top surface of the pre-molded layer, and the interconnect pillars are connected to the conductive pad; The interconnect pillars are encapsulated to obtain an encapsulation layer, wherein the top surface of the encapsulation layer is at the same level as the top of the interconnect pillars on the active surface of the chip to be encapsulated.

8. A high-density fan-out packaging structure, characterized in that, The method for preparing the high-density fan-out packaging structure using any one of claims 1 to 7, wherein the packaging structure comprises: Silicon substrate, chip to be packaged, molding layer, multilayer wiring layer and soldering components; One side of the silicon substrate is bonded to the passive side of the chip to be packaged; The chip to be packaged includes a conductive pad flush with the active surface of the chip and an interconnect post connected to the conductive pad. The chip to be packaged and the interconnect post are disposed on the molding compound, wherein the top surface of the molding compound and the top of the interconnect post on the active surface of the chip to be packaged are at the same level. The multi-layer wiring layer is disposed on the top surface of the molding layer, and the multi-layer wiring layer is interconnected with the interconnect post; The welding component is disposed on the multilayer wiring layer and is used for conductive interconnection with the package interconnect.

9. The high-density fan-out packaging structure as described in claim 8, characterized in that, The packaging structure further includes: A metal sheet is disposed between the silicon substrate and the passive surface of the chip to be packaged.

10. The high-density fan-out packaging structure as described in claim 9, characterized in that, The metal sheet includes an aluminum sheet.

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