An adaptive background calibration method for all-digital phase-locked loop bandwidth

Abstract

The present invention discloses an adaptive background calibration method for the bandwidth of a fully digital phase-locked loop. The method uses a two-tap LMS algorithm, and adopts two LMS algorithm calibration loops to replace a single LMS algorithm calibration loop to estimate the loop bandwidth factor. After both calibration loops generate corresponding loop gain estimation values, the two are added to obtain the final loop gain estimation value, and the loop is connected through a negation operation, thereby avoiding the problem that the bandwidth estimation result is inaccurate due to the influence of non-ideal factors such as loop divider delay. In order to avoid the influence of an externally input training sequence on the noise performance and power consumption of the loop, the present invention uses a pseudo-random sequence output by a △-∑ modulator in the loop to replace the externally input training sequence.

Description

Technical Field

[0001] The invention relates to integrated circuit design, and in particular to an adaptive background calibration method for a full digital phase-locked loop bandwidth. Background Art

[0002] Fully digital phase-locked loops have been widely used in many fields, such as analog and digital communications and radio electronics. In particular, various phase-locked loops are often used in modulation, demodulation and phase synchronization in digital communications. Fully digital phase-locked loops have shown advantages that are particularly important for wireless communication devices, such as small area, low power consumption and good system integration. The bandwidth background calibration technology using the LMS algorithm estimates the variable factor of the full digital phase-locked loop bandwidth, which greatly reduces the sensitivity of the phase-locked loop bandwidth to the analog parameters in the loop, thereby preventing the loop bandwidth changes caused by non-ideal factors such as process, voltage, and temperature, and improving the loop performance.

[0003] In the prior art, some technicians have proposed a digital bandwidth background calibration technology for compensating for the gain variation of a digital controlled oscillator in a phase domain digital phase-locked loop. This technology relies on a mathematical approximation of the gain of the digital controlled oscillator extracted from the control word of the digital controlled oscillator and the frequency control word of the phase-locked loop, and requires the use of a lookup table to mitigate the approximation error. This technology relies on a lookup table, and the estimation result is not accurate enough and is not convenient to use. In addition, this technology can only estimate the gain of the digital controlled oscillator, but not the gain of the time-to-digital converter, and therefore cannot be directly applied to a phase-locked loop based on a time-to-digital converter.

[0004] In the prior art, some technicians have proposed a method of associating a Bang-Bang PLL loop with a random signal injected from outside the loop to estimate the bandwidth of the loop and adjust the loop filter coefficient to make the loop bandwidth constant. The random signal used in this method is injected into the loop from outside the loop. The injection of random signals in the loop will introduce additional noise into the loop, deteriorate the noise performance of the loop, and increase the total output noise power of the loop. In addition, the analog delay in the loop will lead to inaccurate estimation of the loop gain.

[0005] Patent "Chinese Patent CN113037280A, 2021.04.08": A bandwidth calibration method is proposed. First, the phase-locked loop is placed in a closed-loop state. After the phase-locked loop is locked, the first frequency output by the voltage-controlled oscillator and the corresponding input control voltage are obtained. Then, the phase-locked loop is placed in the first mode, and the output current of the charge pump is controlled so that the input voltage of the voltage-controlled oscillator is the preset first input voltage, and the first period is obtained according to the second frequency output by the voltage-controlled oscillator within the preset time and the frequency division value of the first frequency divider. Then, the phase-locked loop is adjusted to the second mode, and the charge pump is controlled so that the input voltage of the voltage-controlled oscillator is the preset second input voltage, and the second period is obtained according to the third frequency output by the voltage-controlled oscillator within the preset time and the frequency division value of the first frequency divider. Finally, the control bit value is obtained according to the first period, the second period and the target gain bandwidth, and the charge pump is configured according to the value so that the gain bandwidth of the phase-locked loop remains constant. However, the steps of this method are too complicated and inconvenient to implement. Summary of the invention

[0006] In view of this, the purpose of the present invention is to provide an adaptive background calibration method for the bandwidth of a fully digital phase-locked loop. The method calibrates the loop bandwidth of the fully digital phase-locked loop. Compared with a traditional phase-locked loop that does not perform loop bandwidth calibration, the sensitivity of the loop to analog parameters is greatly reduced, thereby preventing the loop bandwidth from changing due to non-ideal factors such as process, voltage, temperature, etc., and greatly improving the loop performance.

[0007] In order to achieve the above object, the present invention adopts the following technical solution:

[0008] An adaptive background calibration method for the bandwidth of a fully digital phase-locked loop, the fully digital phase-locked loop comprising: a variable phase accumulator VPA, a reference phase accumulator RPA, an automatic frequency calibration module AFC, a digitally controlled oscillator DCO, a digital loop filter DLF, a time-to-digital converter TDC, a delta-sigma modulator DSM and a subtractor;

[0009] The calibration method comprises the following steps:

[0010] First, for the fully digital phase-locked loop, determine its loop gain, the expression is:

[0011]

[0012] In this formula, N is the phase-locked loop frequency division ratio, which means that the frequency divider accumulates N DCO output signal cycles in one reference clock cycle, and K T and K TDC are the gains of the digitally controlled oscillator DCO and the time-to-digital converter TDC, respectively, and α and β are the loop filter parameters;

[0013] The loop bandwidth is then approximated using its normalized gain frequency, and the loop bandwidth is expressed as:

[0014]

[0015] In this formula, f ref is the reference frequency of the phase-locked loop, and the loop gain factor G = NK T K TDC ;

[0016] Finally, two calibration loops based on the LMS algorithm are introduced to estimate the loop gain factor, and then the loop gain factor g obtained by estimation is connected to the loop through an inversion operation, so that the loop bandwidth becomes:

[0017]

[0018] At this time, the loop bandwidth depends only on the filter parameter β and the phase-locked loop reference clock frequency f ref Related;

[0019] Among them, two calibration loops based on the LMS algorithm are used, the input of one loop is a training sequence that has not been delayed, and the input of the other loop is a training sequence that has been delayed by a reference clock cycle. After the two calibration loops generate corresponding loop gain factor estimation values, the two are added to obtain the final loop gain factor estimation value, and the loop is connected through an inversion operation, and finally a bandwidth calibration loop is obtained whose bandwidth estimation result is not affected by non-ideal factors.

[0020] Furthermore, two calibration loops based on the LMS algorithm are used, and the training sequence used is a pseudo-random sequence, and the pseudo-random sequence is a pseudo-random sequence output by the delta-sigma modulator DSM between the digital loop filter DLF and the digitally controlled oscillator DCO.

[0021] Furthermore, the gain of the digitally controlled oscillator DCO is specifically expressed as:

[0022]

[0023] △C is the minimum variable capacitance value of the digital controlled oscillator switch capacitor array, C tot is the capacitance of the resonant cavity of the numerically controlled oscillator, T out is the period of the DCO output signal.

[0024] Furthermore, the gain of the time-to-digital converter TDC is specifically expressed as:

[0025]

[0026] In this formula, △t TDC is the resolution of the time-to-digital converter.

[0027] Furthermore, the non-ideal factors specifically include: process P, voltage V, and temperature T.

[0028] Furthermore, the variable phase accumulator VPA and the reference phase accumulator RPA are used to convert the frequency information into phase information;

[0029] The automatic frequency calibration module AFC is used to compare the output values ​​of the variable phase accumulator VPA and the reference clock cycle counter counter, determine the magnitude relationship between the two, and then change the coarse adjustment and medium adjustment control words of the digital control oscillator DCO;

[0030] The digitally controlled oscillator DCO outputs a signal of corresponding frequency according to an input multi-bit control word.

[0031] Furthermore, when the all-digital phase-locked loop starts working, it specifically includes the following working process:

[0032] First, the output signal frequency of the digital controlled oscillator DCO is locked to the sub-band of the target frequency through the automatic frequency calibration module AFC, and the calibration of the coarse adjustment and intermediate adjustment control words of the digital controlled oscillator DCO is completed; after the calibration is completed, the coarse adjustment and intermediate adjustment loops of the full digital phase-locked loop are locked again; after the locking is completed, the phase detection loop adjusts the fine adjustment part of the DCO control word to make it locked to the target frequency, wherein the phase detection loop includes: a reference phase accumulator RPA, a variable phase accumulator VPA, a time-to-digital converter TDC, a digital loop filter DLF, a delta-sigma modulator DSM and a subtractor;

[0033] Then, the fine tuning loop of the all-digital phase-locked loop starts to work, which includes: the output signal CKV of the digitally controlled oscillator DCO after being divided by the frequency divider N enters the time-to-digital converter TDC and the variable phase accumulator VPA respectively; the variable phase accumulator VPA counts the integer part of the cycle of CKV of the DCO after being divided by the frequency divider N, and the time-to-digital converter TDC quantizes the decimal part of CKV; and then integrates the output of the variable phase accumulator VPA and the time-to-digital converter TDC, wherein the output obtained after the integration is the phase value of the output frequency CKV;

[0034] Finally, the subtractor subtracts the reference phase from the output phase to obtain the phase error, which is sent to the digital loop filter DLF. The digital loop filter DLF calculates a new digital controlled oscillator DCO control word based on the phase error, wherein the new digital controlled oscillator DCO control word is sent to the input end of the digital controlled oscillator DCO after passing through the Δ-Σ modulator DSM; after the fine-tuning part of the digital controlled oscillator DCO control word is calibrated, the fully digital phase-locked loop is locked.

[0035] The beneficial effects of the present invention are:

[0036] The present invention uses a two-tap LMS algorithm, and adopts two LMS algorithm calibration loops to replace a single LMS algorithm calibration loop to estimate the loop bandwidth factor. After the two calibration loops generate corresponding loop gain estimation values, the two are added to obtain a final loop gain estimation value, and the loop is connected through an inversion operation, thereby avoiding the problem that the bandwidth estimation result is inaccurate due to the influence of non-ideal factors such as loop divider delay.

[0037] The present invention uses a pseudo-random sequence output by a delta-sigma modulator in a loop to replace an externally input random training sequence, thereby avoiding the influence of the externally input training sequence on the noise performance and power consumption of the loop.

[0038] The LMS algorithm of the present invention adopts floating-point number calculation. Compared with the traditional fixed-point number algorithm, the floating-point number calculation has higher precision and a much larger range of expression, and can track the change of loop bandwidth more accurately. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 Schematic diagram of the structure of the ADPLL loop used in Example 1;

[0040] Figure 2 This is a schematic diagram of the loop bandwidth factor estimation in Example 1;

[0041] Figure 3 For the target mentioned in Example 1 Figure 1 The loop shown adopts the structural schematic diagram of the traditional single-tap LMS calibration loop;

[0042] Figure 4 For the one mentioned in Example 1 Figure 1 Schematic diagram of the non-ideal factors caused by the delay of the mid-loop divider;

[0043] Figure 5 For the target mentioned in Example 1 Figure 1 The loop shown is a schematic diagram of the structure of a two-tap LMS calibration loop. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] Example 1

[0046] See also Figure 1-Figure 5 This embodiment provides an adaptive background calibration method for the bandwidth of an all-digital phase-locked loop. The method is directed to a specific structure of an all-digital phase-locked loop ADPLL (All-Digital Phase Lock Loop). Figure 1 As shown, it includes:

[0047] Variable phase accumulator VPA (Variable Phase Accumulator), reference phase accumulator RPA (Reference Phase Accumulator), automatic frequency calibration module AFC (Auto Frequency Calibrator), digitally controlled oscillator DCO, digital loop filter DLF (Digital Loop Filter), time-to-digital converter TDC (TimeDigital Convertor), Δ-Σ modulator DSM (Delta-Sigma Modulator) and subtractor.

[0048] The variable phase accumulator VPA and the reference phase accumulator RPA are used to convert frequency information into phase information;

[0049] The automatic frequency calibration module AFC is used to compare the output values ​​of the variable phase accumulator VPA and the reference clock cycle counter counter, determine the magnitude relationship between the two, and then change the coarse adjustment and medium adjustment control words of the digital controlled oscillator DCO;

[0050] The digitally controlled oscillator DCO outputs a signal of a corresponding frequency according to an input multi-bit control word.

[0051] Specifically, when the all-digital phase-locked loop starts working, it specifically includes the following working process:

[0052] First, the output signal frequency of the digital controlled oscillator DCO is quickly locked to the sub-band of the target frequency through the above-mentioned automatic frequency calibration module AFC, and the calibration of the coarse adjustment and medium adjustment control words of the digital controlled oscillator DCO is completed. After the coarse adjustment and medium adjustment parts of the digital controlled oscillator DCO control word are calibrated, the coarse adjustment and medium adjustment loops of the full digital phase-locked loop are locked. After the locking is completed, the phase detection loop adjusts the fine adjustment part of the DCO control word to lock it to the target frequency, wherein the phase detection loop includes: a reference phase accumulator RPA, a variable phase accumulator VPA, a time-to-digital converter TDC, a digital loop filter DLF, a delta-sigma modulator DSM and a subtractor.

[0053] Then, the fine tuning loop of the all-digital phase-locked loop starts to work, which includes: the output signal CKV of the digitally controlled oscillator DCO after being divided by the frequency divider N enters the time-to-digital converter TDC and the variable phase accumulator VPA respectively. The variable phase accumulator VPA counts the integer part of the cycle of CKV after the DCO is divided by the frequency divider N, and the time-to-digital converter TDC quantizes the decimal part of CKV; and then integrates the output of the variable phase accumulator VPA and the time-to-digital converter TDC, wherein the output obtained after integration is the phase value of the output frequency CKV.

[0054] Finally, the subtractor subtracts the reference phase from the output phase, and the obtained phase error is sent to the digital loop filter DLF, which calculates a new digital controlled oscillator DCO control word based on the phase error, wherein the new digital controlled oscillator DCO control word is sent to the input end of the digital controlled oscillator DCO after passing through the Δ-Σ modulator DSM. After the fine adjustment part of the digital controlled oscillator DCO control word is calibrated, the fully digital phase-locked loop is locked.

[0055] Specifically, in this embodiment, if Figure 1 As shown, the output signal of the digital controlled oscillator DCO is CKV with N times the frequency. The output frequency accuracy of the DCO is improved by using a Δ-Σ modulator DSM in the digital controlled oscillator DCO. At the same time, the quantization noise of the DCO can be shaped and moved from low frequency to high frequency.

[0056] The method specifically comprises the following steps:

[0057] Step S1, calculating the bandwidth of the all-digital phase-locked loop;

[0058] Specifically, in this embodiment, step S1 includes the following steps:

[0059] Step S101, determine its loop gain, the expression is:

[0060]

[0061] In this formula, N is the phase-locked loop frequency division ratio, which means that the frequency divider accumulates N DCO output signal cycles in one reference clock cycle, and K T and K TDC are the gains of the digital controlled oscillator DCO (s / bit) and the time-to-digital converter TDC (bit / s), respectively, and α and β are the loop filter parameters;

[0062] Step S102: In order to obtain a simplified formula of the loop bandwidth, the normalized gain frequency of the loop bandwidth may be used to approximate the loop bandwidth. Therefore, the loop bandwidth is obtained by the following formula:

[0063]

[0064] In this formula, f ref is the reference frequency of the phase-locked loop, and the loop gain factor G = NK T K TDC , this gain factor is proportional to the DCO and TDC gains.

[0065] The above DCO gain (s / bit) is specifically expressed as:

[0066]

[0067] In this formula, △C is the minimum variable capacitance value of the digital controlled oscillator switched capacitor array, C tot is the capacitance of the resonant cavity of the numerically controlled oscillator, T out It is the period of the DCO output signal, which is determined by the resistance and capacitance of the DCO and is greatly affected by the process.

[0068] The above TDC gain (bit / s) is specifically expressed as:

[0069]

[0070] In this formula, △t TDC is the resolution of the time-to-digital converter, which is proportional to the propagation delay of the digital logic gate and is greatly affected by process, voltage, and temperature. Therefore, the loop bandwidth factor G is easily affected by non-ideal factors such as process, voltage, and temperature.

[0071] Step S103: The loop gain factor is estimated through an adaptive calibration loop, and the loop gain factor g obtained through the estimation is then connected to the loop through an inversion operation, so that the loop bandwidth becomes:

[0072]

[0073] At this time, the loop bandwidth is only related to the filter parameter β and the phase-locked loop reference clock frequency, and will not change due to the influence of loop non-ideal factors such as process, voltage, temperature, etc.

[0074] Step S2: estimating the loop bandwidth factor of the all-digital phase-locked loop;

[0075] Specifically, in this embodiment, step S2 specifically includes:

[0076] Depend on Figure 1 It can be seen that the ADPLL fine-tuning loop consists of an analog part and a digital part, wherein the analog part includes a signal transmission chain of DCO, divider, and TDC, and the rest is the digital part.

[0077] The open-loop transfer function of the analog part of the loop can be expressed as Therefore the loop gain factor G can be estimated by injecting a training signal at the DCO input and calibrated at the TDC output.

[0078] The schematic diagram of loop bandwidth factor estimation is as follows: Figure 2 As shown, specifically including:

[0079] x[n] is a training sequence, which is a pseudo-random sequence that is injected into both the ADPLL loop and the calibration loop to link the two.

[0080] In the calibration loop, the integration operation in the ADPLL open-loop transfer function is replaced by a digital integrator. The result of x[n] after passing through the integrator is multiplied by the estimated loop gain factor g[n] and compared with the TDC output d[n]. The difference between the two, e[n], is fed back to the adaptive algorithm module, and then the latest estimated loop gain factor g[n] is output, and this cycle continues until e[n] is zero.

[0081] Step S3, selecting a training sequence;

[0082] Specifically, in this embodiment, step S3 specifically includes:

[0083] For the training sequence x[n], a pseudo-random sequence input from the outside can be used instead, but this will introduce additional noise into the loop and deteriorate the noise performance of the loop.

[0084] In order to avoid the impact of the external input training sequence on the noise performance and power consumption of the loop, it is best to use the signal that already exists in the loop instead.

[0085] The ADPLL loop in this embodiment uses DSM in the DCO to improve the output frequency accuracy of the DCO and shape the DCO quantization noise. The output of the DSM is just a random sequence. This embodiment uses the pseudo-random sequence output by the DSM in the loop to replace the external input training sequence, thereby ensuring the noise performance of the loop.

[0086] Step S4: Execute the adaptive LMS algorithm in the calibration loop:

[0087] Specifically, the adaptive LMS algorithm in the calibration loop is divided into a single-tap LMS algorithm and a two-tap LMS algorithm proposed in this embodiment.

[0088] Single-tap adaptive LMS algorithm:

[0089] ADPLL using a traditional single-tap calibration loop such as Figure 3 The pseudo-random sequence output by the DSM in the loop is used as the input training sequence of the calibration loop. The estimated value of the loop gain factor obtained by the calibration loop is connected to the loop through an inversion operation, so that the loop bandwidth is not affected by non-ideal factors.

[0090] The two-tap adaptive LMS algorithm used in this embodiment is:

[0091] Non-ideal factors such as the loop divider will cause the loop gain factor estimated by the single-tap adaptive LMS algorithm to be inaccurate. Non-ideal factors such as the delay of the loop divider Figure 4 As shown, assuming that the training signal x[n] injected into the DCO is a unit pulse, the period increment of the DCO output signal is the duration T ref , amplitude K T Rectangular pulse.

[0092] In the next reference cycle, x[n] becomes zero, so the phase jump variable is maintained to its final peak value NK T .like Figure 4 As shown in (a), assuming that the loop divider has no delay, the output signal of the DCO is sub-sampled by the divider and multiplied by the TDC gain K. TDC The obtained sequence d[n] is a training signal x[n] that is delayed by one reference clock cycle and has an amplitude increased by a gain factor of G. At this time, the single-tap LMS algorithm can accurately predict the loop gain factor G.

[0093] like Figure 4As shown in (b), in actual situations, there is a delay in the loop divider. Since the loop divider subsamples the output signal of the DCO once in each reference clock cycle, due to the existence of the loop divider delay, the phase jump variable has not reached the peak value when it is subsampled by the divider one reference clock cycle after the value of the training sequence x[n] changes. Therefore, the sequence d[n] is less than the loop gain factor G one reference clock cycle after the value of the training sequence x[n] changes. At this time, the loop gain factor G predicted by the single-tap LMS algorithm has a large error. Due to the existence of the loop divider delay, the output signal of the DCO is subsampled again by the divider and multiplied by the TDC gain K two reference clock cycles after the change of x[n]. TDC After that, the d[n] value obtained at this moment is not zero. T is constant, and the sum of the instantaneous d[n] values ​​obtained from these two reference clock cycles is exactly equal to the loop gain factor G.

[0094] This embodiment uses two LMS algorithm calibration loops to replace a single LMS algorithm calibration loop to estimate the loop bandwidth, such as Figure 5 As shown in the figure, the input of one loop is the original training sequence x[n] without delay processing, and the input of the other loop is the training sequence after a reference clock cycle delay processing. After the two calibration loops generate corresponding loop gain factor estimation values ​​g[k], they are added to obtain an accurate loop gain factor estimation value G, and then connected to the loop through an inversion operation, and finally a bandwidth calibration loop is obtained whose bandwidth estimation result is not affected by non-ideal factors such as loop divider delay.

[0095] In summary, the present invention provides an adaptive background calibration method for the bandwidth of a fully digital phase-locked loop, which reduces the sensitivity of the loop bandwidth to the analog parameters in the loop by using a fully digital automatic control loop, so that the bandwidth remains constant. The calibration algorithm in the present invention adopts a two-tap LMS algorithm, which can eliminate the problem of inaccurate estimation results due to non-ideal factors such as loop divider delay compared to a single-tap LMS algorithm. At the same time, the algorithm uses floating-point operations, which have higher precision and a much larger range of representation than fixed-point operations, and can track changes in the loop bandwidth more accurately.

[0096] The matters not described in detail in the present invention are all known technologies to those skilled in the art.

[0097] The preferred specific embodiments of the present invention are described in detail above. It should be understood that a person skilled in the art can make many modifications and changes based on the concept of the present invention without creative work. Therefore, any technical solution that can be obtained by a person skilled in the art through logical analysis, reasoning or limited experiments based on the concept of the present invention on the basis of the prior art should be within the scope of protection determined by the claims.

Claims

1. An adaptive background calibration method for a full digital phase-locked loop bandwidth, characterized in that: The all-digital phase-locked loop comprises: a variable phase accumulator VPA, a reference phase accumulator RPA, an automatic frequency calibration module AFC, a digitally controlled oscillator DCO, a digital loop filter DLF, a time-to-digital converter TDC, a delta-sigma modulator DSM and a subtractor; The calibration method comprises the following steps: First, for the fully digital phase-locked loop, determine its loop gain, the expression is: In this expression, N is the phase-locked loop frequency division ratio, which means that the frequency divider accumulates N cycles of the DCO output signal in one reference clock cycle, and K T and K TDC are the gains of the digitally controlled oscillator DCO and the time-to-digital converter TDC, respectively, and α and β are the loop filter parameters; The loop bandwidth is then approximated using its normalized gain frequency, and the loop bandwidth is expressed as: In this expression, f ref is the reference frequency of the phase-locked loop, and the loop gain factor G = NK T K TDC ; Finally, two calibration loops based on the LMS algorithm are introduced to estimate the loop gain factor, and then the loop gain factor g obtained by estimation is connected to the loop through an inversion operation, so that the loop bandwidth becomes: At this time, the loop bandwidth depends only on the filter parameter β and the phase-locked loop reference clock frequency f ref Related; Among them, two calibration loops based on the LMS algorithm are used, the input of one loop is a training sequence that has not been delayed, and the input of the other loop is a training sequence that has been delayed by a reference clock cycle. After the two calibration loops generate corresponding loop gain factor estimates, the two are added to obtain the final loop gain factor estimate, and the loop is connected through an inversion operation, and finally a fully digital phase-locked loop loop whose bandwidth is not affected by non-ideal factors is obtained.

2. The adaptive background calibration method for the bandwidth of a fully digital phase-locked loop according to claim 1, characterized in that: The two calibration loops based on the LMS algorithm are used, and the input training sequence used is a pseudo-random sequence, and the pseudo-random sequence is a pseudo-random sequence output by the delta-sigma modulator DSM between the digital loop filter DLF and the digitally controlled oscillator DCO.

3. The adaptive background calibration method for full digital phase-locked loop bandwidth according to claim 1, characterized in that: The gain of the digital controlled oscillator DCO is specifically expressed as: △C is the minimum variable capacitance value of the digital controlled oscillator switch capacitor array, C tot is the capacitance of the resonant cavity of the numerically controlled oscillator, T out is the period of the DCO output signal.

4. The adaptive background calibration method for full digital phase-locked loop bandwidth according to claim 1, characterized in that: The gain of the time-to-digital converter TDC is specifically expressed as: In this expression, △t TDC is the resolution of the time-to-digital converter.

5. The adaptive background calibration method for full digital phase-locked loop bandwidth according to claim 1, characterized in that: The non-ideal factors specifically include: process P, voltage V, and temperature T.

6. The adaptive background calibration method for full digital phase-locked loop bandwidth according to claim 1, characterized in that: The variable phase accumulator VPA and the reference phase accumulator RPA are used to convert frequency information into phase information; The automatic frequency calibration module AFC is used to compare the output values ​​of the variable phase accumulator VPA and the reference clock cycle counter counter, determine the magnitude relationship between the two, and then change the coarse adjustment and medium adjustment control words of the digital control oscillator DCO; The digitally controlled oscillator DCO outputs a signal of corresponding frequency according to an input multi-bit control word.

7. The adaptive background calibration method for full digital phase-locked loop bandwidth according to claim 6, characterized in that: When the all-digital phase-locked loop starts working, it specifically includes the following working process: First, the output signal frequency of the digital controlled oscillator DCO is locked to the sub-band of the target frequency through the automatic frequency calibration module AFC, and the calibration of the coarse adjustment and medium adjustment control words of the digital controlled oscillator DCO is completed; After the calibration is completed, the coarse adjustment and medium adjustment loops of the all-digital phase-locked loop are locked again; After the locking is completed, the phase detection loop adjusts the fine adjustment part of the DCO control word to lock it to the target frequency, wherein the phase detection loop includes: a reference phase accumulator RPA, a variable phase accumulator VPA, a time-to-digital converter TDC, a digital loop filter DLF, a delta-sigma modulator DSM and a subtractor; Then, the fine tuning loop of the all-digital phase-locked loop starts to work, which includes: the output signal CKV of the digitally controlled oscillator DCO after being divided by the frequency divider N enters the time-to-digital converter TDC and the variable phase accumulator VPA respectively; the variable phase accumulator VPA counts the integer part of the cycle of CKV of the DCO after being divided by the frequency divider N, and the time-to-digital converter TDC quantizes the decimal part of CKV; and then integrates the output of the variable phase accumulator VPA and the time-to-digital converter TDC, wherein the output obtained after the integration is the phase value of the output frequency CKV; Finally, the subtractor subtracts the reference phase from the output phase to obtain the phase error, which is sent to the digital loop filter DLF. The digital loop filter DLF calculates a new digital controlled oscillator DCO control word based on the phase error, wherein the new digital controlled oscillator DCO control word is sent to the input end of the digital controlled oscillator DCO after passing through the Δ-Σ modulator DSM; after the fine-tuning part of the digital controlled oscillator DCO control word is calibrated, the fully digital phase-locked loop is locked.

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