Operational amplifier input circuit and method for dynamically adjusting substrate voltage of operational amplifier input circuit

Abstract

The present invention discloses an operational amplifier input circuit and a method for dynamically adjusting the substrate voltage of the operational amplifier input circuit. The operational amplifier input circuit includes an input stage unit, a substrate bias unit, and a substrate voltage adjustment unit. The input stage unit includes a first differential transistor pair; the substrate bias unit includes a second differential transistor pair and a resistor unit, the resistor unit being configured to output a substrate voltage provided to the first differential transistor pair; and the substrate voltage adjustment unit adjusts the substrate voltage based on changes in the input common-mode voltage. According to the operational amplifier input circuit of the present invention, the substrate voltage of the first differential transistor pair of the input stage unit is set by the substrate bias unit, and the substrate voltage adjustment unit adjusts the substrate voltage when the input common-mode voltage varies over a wide range, thereby providing the input stage unit with a better operating point and improving the circuit's performance indicators, such as the common-mode rejection ratio, at low and high common-mode voltages.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, in particular to an operational amplifier input circuit and a method for dynamically adjusting a substrate voltage of the operational amplifier input circuit. Background Art

[0002] The op amp's high-voltage input common-mode voltage generally ranges from 0V to Vdd-1.5V or Vdd, which is a relatively large range. In commonly used op amp structures, there is a margin trade-off between the differential transistor pair and the tail current tube of the input stage unit. In extreme cases, the margins of both may only be relatively small. Existing solutions utilize the channel modulation effect to increase the turn-on voltage Vth by giving the substrate of the differential transistor pair a voltage level between the power supply voltage Vdd and the source terminal voltage, thereby optimizing the performance at 0V common mode. However, due to the large input common-mode voltage range and the changes in full temperature and full process angle, the working state of the input stage unit is still not ideal.

[0003] The information disclosed in this background technology section is only intended to enhance understanding of the overall background of the invention and should not be regarded as an admission or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the Invention

[0004] The object of the present invention is to provide an operational amplifier input circuit and a method for dynamically adjusting the substrate voltage of the operational amplifier input circuit, which can provide a better operating point for the input stage unit when the input common mode voltage has a large variation range.

[0005] To achieve the above objectives, an embodiment of the present invention provides an operational amplifier input circuit, comprising: an input stage unit, a substrate bias unit, and a substrate voltage adjustment unit.

[0006] The input stage unit includes a first differential transistor pair for receiving a differential input signal.

[0007] The substrate bias unit includes a second differential transistor pair and a resistor unit, wherein a first end of the resistor unit is used to output a substrate voltage provided to the first differential transistor pair of the input stage unit, and a second end of the resistor unit is connected to the second differential transistor pair, and the second differential transistor pair is used to receive a differential input signal.

[0008] The substrate voltage adjustment unit is used to adaptively adjust the voltage difference between the first end and the second end of the resistance unit according to the input common mode voltage, so as to adjust the substrate voltage.

[0009] In one or more embodiments of the present invention, the substrate voltage adjustment unit is configured to dynamically adjust the current flowing through the resistance unit and / or adjust the resistance value of the resistance unit according to the magnitude of the input common mode voltage to change the substrate voltage.

[0010] In one or more embodiments of the present invention, the substrate voltage regulating unit includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a current mirror unit;

[0011] The first ends of the fourth transistor and the fifth transistor are connected to the power supply voltage, the control ends of the fourth transistor and the fifth transistor are connected to the first control voltage, the second end of the fifth transistor is connected to the second end of the first transistor, the first ends of the sixth transistor, the seventh transistor and the eighth transistor are connected to the second end of the fourth transistor, the control ends of the sixth transistor and the seventh transistor are used to receive the differential input signal, the second ends of the sixth transistor and the seventh transistor are grounded, the control end of the eighth transistor is connected to the reference voltage, the current mirror unit is connected to the second end of the eighth transistor and the first end of the resistance unit, and the substrates of the sixth transistor, the seventh transistor and the eighth transistor are connected to the first end of the resistance unit.

[0012] In one or more embodiments of the present invention, the substrate bias unit includes:

[0013] a first transistor, wherein a first terminal of the first transistor is connected to a power supply voltage, a second terminal of the first transistor is connected to a substrate voltage adjustment unit, and a control terminal of the first transistor is connected to a first control voltage;

[0014] The first end of the resistor unit is connected to the second end of the first transistor and the substrate voltage adjustment unit to form an intermediate node for providing a substrate voltage to the differential transistor pair of the input stage unit, and the resistance of the resistor unit is a fixed resistance or an adjustable resistance; and

[0015] A second transistor and a third transistor, the second transistor and the third transistor constitute a second differential transistor pair, the control ends of the second transistor and the third transistor are used to receive the differential input signal, the first ends of the second transistor and the third transistor are connected to the second end of the resistance unit, the second ends of the second transistor and the third transistor are grounded, and the substrates of the second transistor and the third transistor are connected to the first end of the resistance unit.

[0016] In one or more embodiments of the present invention, the input stage unit includes an eleventh transistor, a twelfth transistor and a thirteenth transistor, the first end of the eleventh transistor is connected to the power supply voltage, the control end of the eleventh transistor is connected to the first control voltage, the twelfth transistor and the thirteenth transistor constitute a first differential transistor pair, the control ends of the twelfth transistor and the thirteenth transistor are used to receive the differential input signal, the first ends of the twelfth transistor and the thirteenth transistor are connected to the second end of the eleventh transistor, the second ends of the twelfth transistor and the thirteenth transistor are used to output a differential current signal, and the substrates of the twelfth transistor and the thirteenth transistor are connected to the first end of the resistance unit.

[0017] In one or more embodiments of the present invention, the input stage unit includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor;

[0018] The first terminal of the eleventh transistor is connected to a power supply voltage, the control terminal of the eleventh transistor is connected to a first control voltage, the twelfth transistor and the thirteenth transistor constitute a first differential transistor pair, the control terminals of the twelfth transistor and the thirteenth transistor are used to receive the differential input signal, the first terminals of the twelfth transistor and the thirteenth transistor are connected to the second terminal of the eleventh transistor, the second terminals of the twelfth transistor and the thirteenth transistor are used to output a differential current signal, and substrates of the twelfth transistor and the thirteenth transistor are connected to the first terminal of the resistance unit;

[0019] The substrate bias unit includes:

[0020] a first transistor, wherein a first terminal of the first transistor is connected to a power supply voltage, a second terminal of the first transistor is connected to a substrate voltage adjustment unit, and a control terminal of the first transistor is connected to a first control voltage;

[0021] The first end of the resistor unit is connected to the second end of the first transistor and the substrate voltage adjustment unit to form an intermediate node for providing a substrate voltage to the differential transistor pair of the input stage unit, and the resistance of the resistor unit is a fixed resistance or an adjustable resistance; and

[0022] a second transistor and a third transistor, wherein the second transistor and the third transistor constitute a second differential transistor pair, control terminals of the second transistor and the third transistor are used to receive the differential input signal, first terminals of the second transistor and the third transistor are connected to the second terminal of the resistance unit, second terminals of the second transistor and the third transistor are grounded, and substrates of the second transistor and the third transistor are connected to the first terminal of the resistance unit;

[0023] The substrate bias unit further includes a level shift circuit, and the input stage unit further includes a seventeenth transistor and an eighteenth transistor;

[0024] The level shifting circuit is connected to the first ends of the second and third transistors, the second end of the resistance unit, and the control ends of the seventeenth and eighteenth transistors. The level shifting circuit controls the voltage of the control ends of the seventeenth and eighteenth transistors to follow the voltage change of the first ends of the second and third transistors, thereby clamping the voltage between the first and second ends of the twelfth transistor and the voltage between the first and second ends of the thirteenth transistor. The first end of the seventeenth transistor is connected to the second end of the twelfth transistor, the first end of the eighteenth transistor is connected to the second end of the thirteenth transistor, and the second ends of the seventeenth and eighteenth transistors are used to output differential current signals.

[0025] In one or more embodiments of the present invention, the level shifting circuit includes a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor;

[0026] The first end of the fourteenth transistor is connected to the second end of the resistance unit, the control end of the fourteenth transistor is short-circuited to the second end, the first end of the fifteenth transistor is connected to the second end of the fourteenth transistor, the second end of the fifteenth transistor is short-circuited to the control end, the second end of the sixteenth transistor is connected to the second end of the fifteenth transistor, the control end of the sixteenth transistor is connected to the second control voltage, the first end of the sixteenth transistor is grounded, and the second end of the fifteenth transistor is connected to the control ends of the seventeenth transistor and the eighteenth transistor.

[0027] In one or more embodiments of the present invention, the substrate bias unit further includes a twentieth transistor; a first terminal of the twentieth transistor is connected to the second terminals of the second transistor and the third transistor, and a control terminal of the twentieth transistor is connected to the second terminal of the fifteenth transistor.

[0028] In one or more embodiments of the present invention, the substrate voltage regulating unit includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a current mirror unit;

[0029] The first terminals of the fourth transistor and the fifth transistor are connected to a power supply voltage, the control terminals of the fourth transistor and the fifth transistor are connected to a first control voltage, the second terminal of the fifth transistor is connected to the second terminal of the first transistor, the first terminals of the sixth transistor, the seventh transistor, and the eighth transistor are connected to the second terminal of the fourth transistor, the control terminals of the sixth transistor and the seventh transistor are used to receive the differential input signal, the second terminals of the sixth transistor and the seventh transistor are grounded, the control terminal of the eighth transistor is connected to a reference voltage, the current mirror unit is connected to the second terminal of the eighth transistor and the first terminal of the resistance unit, and the substrates of the sixth transistor, the seventh transistor, and the eighth transistor are connected to the first terminal of the resistance unit;

[0030] The substrate voltage adjustment unit further includes a twenty-fifth transistor and a twenty-sixth transistor;

[0031] A first terminal of the twenty-fifth transistor is connected to the second terminals of the sixth transistor and the seventh transistor, and a control terminal of the twenty-fifth transistor is connected to the second terminal of the fifteenth transistor;

[0032] The first end of the twenty-sixth transistor is connected to the second end of the eighth transistor, the second end of the twenty-sixth transistor is connected to the current mirror unit, and the control end of the twenty-sixth transistor is connected to the second end of the fifteenth transistor.

[0033] In one or more embodiments of the present invention, the operational amplifier input circuit further includes a protection circuit, wherein the protection circuit includes a twenty-ninth transistor, a thirtieth transistor, and a first clamping circuit;

[0034] The second end of the 29th transistor is coupled to the first input end, the second end of the 30th transistor is coupled to the second input end, the control ends of the 29th transistor and the 30th transistor are connected to the first end of the resistance unit, and the first ends of the 29th transistor and the 30th transistor are connected to the first clamping circuit and are simultaneously used to output differential input signals.

[0035] The present invention also discloses a method for dynamically adjusting the substrate voltage of an operational amplifier input circuit. The operational amplifier input circuit includes a resistor unit, and a first differential transistor pair and a second differential transistor pair that receive differential input signals. The first end of the resistor unit is used to output the substrate voltage provided to the first differential transistor pair of the input stage unit, and the second end of the resistor unit is connected to the second differential transistor pair. The method includes:

[0036] Setting a substrate voltage of the first differential transistor pair of the input stage unit through the second differential transistor pair and the resistor unit based on an input common mode voltage of the differential input signal;

[0037] The voltage difference between the first end and the second end of the resistance unit is adaptively adjusted according to the input common mode voltage to adjust the substrate voltage.

[0038] In one or more embodiments of the present invention, the method further includes dynamically adjusting the current flowing through the resistance unit and / or adjusting the resistance value of the resistance unit according to the magnitude of the input common mode voltage to change the substrate voltage.

[0039] Compared with the prior art, the operational amplifier input circuit and the method for dynamically adjusting the substrate voltage of the operational amplifier input circuit according to the embodiments of the present invention set the substrate voltage of the first differential transistor pair of the input stage unit based on the input common-mode voltage of the differential input signal through a substrate bias unit, and adjust the substrate voltage when the input common-mode voltage varies over a large range through a substrate voltage adjustment unit, thereby providing a better operating point for the input stage unit and improving the circuit's performance indicators at low common-mode voltage and high common-mode voltage, such as the common-mode rejection ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 FIG. 4 is a circuit schematic diagram of an operational amplifier input circuit according to an embodiment of the present invention.

[0041] Figure 2 FIG. 4 is a circuit diagram of an input stage unit according to an embodiment of the present invention.

[0042] Figure 3 FIG. 4 is a circuit diagram of a substrate bias unit according to an embodiment of the present invention.

[0043] Figure 4 FIG. 4 is a circuit diagram of a substrate voltage regulating unit according to an embodiment of the present invention.

[0044] Figure 5 FIG. 4 is a circuit schematic diagram of a protection circuit according to an embodiment of the present invention.

[0045] Figure 6 is a flow chart of a method for dynamically adjusting the substrate voltage of an operational amplifier input circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0046] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific embodiments.

[0047] Unless expressly stated otherwise, throughout the specification and claims, the term "comprise" or variations such as "include" or "comprising", etc., will be understood to include the stated elements or components but not to exclude other elements or other components.

[0048] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by a programmable circuit. When an element or circuit is said to be "connected to" another element, or "connected to" another element, or when an element / circuit is said to be "connected" between two nodes, it may be directly coupled or connected to the other element or there may be an intermediate element, and the connection between the elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between the two.

[0049] In the present application, the transistor may be a MOS transistor or a triode, and the transistor includes a first end, a second end, and a control end. The first end, the second end, and the control end of the P-type MOS transistor and the N-type MOS transistor are respectively the source, the drain, and the gate. When the P-type MOS transistor is in the on state, the current flows from the first end to the second end, and when the N-type MOS transistor is in the on state, the current flows from the second end to the first end. The first end, the second end, and the control end of the NPN-type triode and the PNP-type triode are respectively the emitter, the collector, and the base. When the NPN-type triode is in the on state, the current flows from the second end to the first end, and when the PNP-type triode is in the on state, the current flows from the first end to the second end.

[0050] The present invention will be further described below with reference to the accompanying drawings and examples.

[0051] like Figure 1 As shown, an operational amplifier input circuit includes: an input stage unit 10 , a substrate bias unit 20 and a substrate voltage adjustment unit 30 .

[0052] The input stage unit 10 includes a first differential transistor pair, which is configured to receive differential input signals INN_G and INP_G and output a differential current signal.

[0053] like Figure 1 and Figure 2 As shown, the input stage unit 10 specifically includes an eleventh transistor MP_BIAS1 , a twelfth transistor MP_IN1 , and a thirteenth transistor MP_IN2 .

[0054] In this embodiment, a first terminal of the eleventh transistor MP_BIAS1 is connected to the power supply voltage Vdd, and a control terminal of the eleventh transistor MP_BIAS1 is connected to the first control voltage Vpbias.

[0055] The twelfth transistor MP_IN1 and the thirteenth transistor MP_IN2 form a first differential transistor pair. The control ends of the twelfth transistor MP_IN1 and the thirteenth transistor MP_IN2 are used to receive differential input signals INN_G and INP_G. The first ends of the twelfth transistor MP_IN1 and the thirteenth transistor MP_IN2 are connected to the second end of the eleventh transistor MP_BIAS1. The second ends of the twelfth transistor MP_IN1 and the thirteenth transistor MP_IN2 are used to output a differential current signal.

[0056] In addition, the input stage unit 10 further includes a twenty-third transistor HV_PCAS1, which is a high-voltage isolation bias transistor for high-voltage protection. A first terminal of the twenty-third transistor HV_PCAS1 is connected to the second terminal of the eleventh transistor MP_BIAS1. A second terminal of the twenty-third transistor HV_PCAS1 is connected to the first terminals of the twelfth transistor MP_IN1 and the thirteenth transistor MP_IN2. A control terminal of the twenty-third transistor HV_PCAS1 is connected to a third control voltage Vp_cas_bias.

[0057] In other embodiments, the twenty-third transistor HV_PCAS1 may be removed.

[0058] like Figure 1 and Figure 3 As shown, the substrate bias unit 20 in this embodiment includes a second differential transistor pair and a resistor unit. The first end of the resistor unit is used to output a substrate voltage VNW provided to the first differential transistor pair of the input stage unit 10. The second end of the resistor unit is connected to the second differential transistor pair, which is used to receive differential input signals INN_G and INP_G. The substrate bias unit 20 is used to set the substrate voltage VNW of the first differential transistor pair of the input stage unit 10 based on the input common-mode voltage of the differential input signals INN_G and INP_G, via the second differential transistor pair and the resistor unit.

[0059] like Figure 1 As shown, the substrate bias unit 20 includes: a first transistor MP_BIAS2, a resistor unit, a second transistor MP_IN3, and a third transistor MP_IN4. The resistance of the resistor unit is fixed or adjustable.

[0060] Specifically, a first terminal of the first transistor MP_BIAS2 is connected to the power supply voltage Vdd, a second terminal of the first transistor MP_BIAS2 is connected to the substrate voltage adjustment unit 30, and a control terminal of the first transistor MP_BIAS2 is connected to the first control voltage Vpbias.

[0061] In this embodiment, the first resistor R1 constitutes a resistor unit. The first and second ends of the first resistor R1 form the first and second ends of the resistor unit. The first end of the first resistor R1 is connected to the second end of the transistor MP_BIAS2 and the substrate voltage adjustment unit 30, forming an intermediate node O for providing the substrate voltage VNW to the differential transistor pair of the input stage unit 10. In other embodiments, the resistor unit may be composed of multiple first resistors R1 and switches. The first resistors R1 are connected in series or parallel by opening and closing the switches, thereby changing the resistance of the resistor unit. Alternatively, the resistance of the first resistor R1 itself can be changed, thereby changing the substrate voltage VNW by adjusting the resistance value under fluctuations in the input common-mode voltage.

[0062] In this embodiment, substrates of the twelfth transistor MP_IN1 and the thirteenth transistor MP_IN2 are connected to the first end of the first resistor R1 to receive the substrate voltage VNW.

[0063] The second transistor MP_IN3 and the third transistor MP_IN4 form a second differential transistor pair. The control terminals of the second transistor MP_IN3 and the third transistor MP_IN4 are used to receive differential input signals INN_G and INP_G. The first terminals of the second transistor MP_IN3 and the third transistor MP_IN4 are connected to the second terminal of the first resistor R1. The second terminals of the second transistor MP_IN3 and the third transistor MP_IN4 are grounded. The substrate terminals of the second transistor MP_IN3 and the third transistor MP_IN4 are connected to the first terminal of the first resistor R1 to receive a substrate voltage VNW.

[0064] like Figure 1 As shown, the substrate bias unit 20 further includes a level shift circuit 21, and the input stage unit 10 further includes a seventeenth transistor HV_P1 and an eighteenth transistor HV_P2. The seventeenth transistor HV_P1 and the eighteenth transistor HV_P2 are high-voltage isolation bias transistors.

[0065] The level shifter circuit 21 is connected to the first terminals of the second and third transistors MP_IN3 and MP_IN4, the second terminal of the first resistor R1, and the control terminals of the seventeenth and eighteenth transistors HV_P1 and HV_P2. The level shifter circuit 21 controls the voltages of the control terminals of the seventeenth and eighteenth transistors HV_P1 and HV_P2 to follow the voltage changes of the first terminals of the second and third transistors MP_IN3 and MP_IN4, thereby clamping the voltage between the first and second terminals of the twelfth and thirteenth transistors MP_IN1 and MP_IN2, preventing the voltage between the first and second terminals of the twelfth and thirteenth transistors MP_IN1 and MP_IN2 from exceeding the withstand voltage, thus providing protection.

[0066] The level shift circuit 21 includes a fourteenth transistor MP_DIO1 , a fifteenth transistor MP_DIO2 , and a sixteenth transistor MN_BIAS1 .

[0067] Specifically, a first end of the fourteenth transistor MP_DIO1 is connected to the second end of the first resistor R1, the control end of the fourteenth transistor MP_DIO1 is short-circuited to the second end, a first end of the fifteenth transistor MP_DIO2 is connected to the second end of the fourteenth transistor MP_DIO1, and the second end of the fifteenth transistor MP_DIO2 is short-circuited to the control end. A second end of the sixteenth transistor MN_BIAS1 is connected to the second end of the fifteenth transistor MP_DIO2, the control end of the sixteenth transistor MN_BIAS1 is connected to the second control voltage, and the first end of the sixteenth transistor MN_BIAS1 is grounded. A first end of the seventeenth transistor HV_P1 is connected to the second end of the twelfth transistor MP_IN1, and the control end of the seventeenth transistor HV_P1 is connected to the second end of the fifteenth transistor MP_DIO2. A first end of the eighteenth transistor HV_P2 is connected to the second end of the thirteenth transistor MP_IN2, and the control end of the eighteenth transistor HV_P2 is connected to the second end of the fifteenth transistor MP_DIO2.

[0068] In other embodiments, if the input voltages of the second transistor MP_IN3, the third transistor MP_IN4, the twelfth transistor MP_IN1, and the thirteenth transistor MP_IN2 are low voltages, the transistor level shifter circuit 21, the seventeenth transistor HV_P1, and the eighteenth transistor HV_P2 can be removed. In other embodiments, in low voltage environments, the seventeenth transistor HV_P1 and the eighteenth transistor HV_P2 can be ordinary transistors.

[0069] In addition, the substrate bias unit 20 further includes a nineteenth transistor HV_PCAS2, a twentieth transistor HV_P3, and a twenty-first transistor MN_DIO1. The nineteenth transistor HV_PCAS2 and the twenty-first transistor HV_P3 are high-voltage isolation bias transistors.

[0070] Specifically, the first end of the nineteenth transistor HV_PCAS2 is connected to the second end of the first transistor MP_BIAS2 to form a Q connection point. Since the nineteenth transistor HV_PCAS2 is added, the second end of the nineteenth transistor HV_PCAS2 is connected to the first end of the first resistor R1 to re-form the intermediate node O, and the control end of the nineteenth transistor HV_PCAS2 is connected to the third control voltage Vp_cas_bias.

[0071] A first end of the twentieth transistor HV_P3 is connected to the second ends of the second transistor MP_IN3 and the third transistor MP_IN4. The control end of the twentieth transistor HV_P3 is connected to the second end of the fifteenth transistor MP_DIO2 to form a P connection point. A second end and the control end of the twenty-first transistor MN_DIO1 are short-circuited and connected to the second end of the twentieth transistor HV_P3. A first end of the twenty-first transistor MN_DIO1 is grounded.

[0072] The level shift circuit 21 further includes a twenty-second transistor HV_NCAS1, which is a high-voltage isolation bias transistor. A second terminal of the twenty-second transistor HV_NCAS1 is connected to the second terminal of the fifteenth transistor MP_DIO2, a first terminal of the twenty-second transistor HV_NCAS1 is connected to the second terminal of the sixteenth transistor MN_BIAS1, and a control terminal of the twenty-second transistor HV_NCAS1 is connected to a fourth control voltage Vn_cas_bias.

[0073] In other embodiments, when high voltage protection is not required, the nineteenth transistor HV_PCAS2 , the twentieth transistor HV_P3 , the twenty-first transistor MN_DIO1 , and the twenty-second transistor HV_NCAS1 may be removed.

[0074] In this embodiment, substrate voltage adjustment unit 30 is configured to adaptively adjust the voltage difference between the first and second terminals of the resistor unit based on the input common-mode voltage to adjust substrate voltage VNW. This adaptive adjustment means that the voltage difference between the first and second terminals of the resistor unit dynamically changes in real time based on the input common-mode voltage, achieving autonomous regulation.

[0075] Furthermore, the substrate voltage adjustment unit 30 is configured to dynamically adjust the current flowing through the resistor unit according to the magnitude of the input common-mode voltage to change the substrate voltage VNW. In other embodiments, the substrate voltage adjustment unit 30 may also dynamically adjust the resistance of the resistor unit according to the magnitude of the input common-mode voltage, or may adjust both the current flowing through the resistor unit and the resistance of the resistor unit.

[0076] like Figure 1 and Figure 4 As shown, the substrate voltage adjustment unit 30 includes a fourth transistor MP_BIAS4 , a fifth transistor MP_BIAS3 , a sixth transistor MP3 , a seventh transistor MP2 , an eighth transistor MP1 and a current mirror unit.

[0077] The first terminals of the fourth transistor MP_BIAS4 and the fifth transistor MP_BIAS3 are connected to the power supply voltage Vdd. The control terminals of the fourth transistor MP_BIAS4 and the fifth transistor MP_BIAS3 are connected to the first control voltage Vpbias. The second terminal of the fifth transistor MP_BIAS3 is connected to the second terminal of the first transistor MP_BIAS2 and the Q connection point. The second terminal of the fifth transistor MP_BIAS3 is indirectly connected to the first terminal of the resistor unit. If the nineteenth transistor HV_PCAS2 is not provided, the second terminal of the fifth transistor MP_BIAS3 is directly connected to the first terminal of the resistor unit. The first terminals of the sixth transistor MP3, the seventh transistor MP2, and the eighth transistor MP1 are connected to the second terminal of the fourth transistor MP_BIAS4. The control terminals of the sixth transistor MP3 and the seventh transistor MP2 are used to receive the differential input signals INN_G and INP_G. The second terminals of the sixth transistor MP3 and the seventh transistor MP2 are grounded. The control terminal of the eighth transistor MP1 is connected to a reference voltage Vref, which is generated by a constant voltage source. The current mirror unit is connected to the second terminal of the eighth transistor MP1, the first terminal of the first resistor R1, and the intermediate node O. Substrates of the sixth transistor MP3 , the seventh transistor MP2 , and the eighth transistor MP1 are connected to the first end of the first resistor R1 to receive a substrate voltage VNW.

[0078] The current mirror unit in this embodiment includes a ninth transistor MN_BIAS3 and a tenth transistor MN_BIAS2. A second end of the ninth transistor MN_BIAS3 is shorted to the control end and connected to the second end of the eighth transistor MP1 and the control end of the tenth transistor MN_BIAS2. A second end of the tenth transistor MN_BIAS2 is connected to the first end of the first resistor R1 and the intermediate node O. The first ends of the ninth transistor MN_BIAS3 and the tenth transistor MN_BIAS2 are grounded.

[0079] In addition, the substrate voltage adjustment unit 30 further includes a 24th transistor HV_PCAS3, a 25th transistor HV_P5, a 26th transistor HV_P4, a 27th transistor MN_DIO3, and a 28th transistor HV_NCAS2. The 24th transistor HV_PCAS3, the 25th transistor HV_P5, and the 26th transistor HV_P4 are high-voltage isolation bias transistors.

[0080] Specifically, the first end of the twenty-fourth transistor HV_PCAS3 is connected to the second end of the fourth transistor MP_BIAS4, the second end of the twenty-fourth transistor HV_PCAS3 is connected to the first ends of the sixth transistor MP3, the seventh transistor MP2 and the eighth transistor MP1, and the control end of the twenty-fourth transistor HV_PCAS3 is connected to the third control voltage.

[0081] A first end of the twenty-fifth transistor HV_P5 is connected to the second ends of the sixth transistor MP3 and the seventh transistor MP2. Control ends of the twenty-fifth transistor HV_P5 and the twenty-sixth transistor HV_P4 are connected to the second end of the fifteenth transistor MP_DIO2 and the P connection point. A first end of the twenty-sixth transistor HV_P4 is connected to the second end of the eighth transistor MP1, and a second end of the twenty-sixth transistor HV_P4 is connected to the second end of the ninth transistor MN_BIAS3.

[0082] A second end of the twenty-seventh transistor MN_DIO3 is connected to the second end of the twenty-fifth transistor HV_P5, a first end of the twenty-seventh transistor MN_DIO3 is grounded, and a second end of the twenty-seventh transistor MN_DIO3 is short-circuited to the control end. A second end of the twenty-eighth transistor HV_NCAS2 is connected to the first end of the first resistor R1 and the intermediate node O, a first end of the twenty-eighth transistor HV_NCAS2 is connected to the second end of the tenth transistor MN_BIAS2, and a control end of the twenty-eighth transistor HV_NCAS2 is connected to the fourth control voltage Vn_cas_bias.

[0083] In other embodiments, when high voltage protection is not required, the twenty-fourth transistor HV_PCAS3 , the twenty-fifth transistor HV_P5 , the twenty-sixth transistor HV_P4 , and the twenty-eighth transistor HV_NCAS2 may be removed, and the twenty-seventh transistor MN_DIO3 may also be removed.

[0084] like Figure 1 and Figure 5 As shown, in this embodiment, the op amp input circuit further includes a protection circuit 40. The protection circuit 40 includes a second resistor R2, a third resistor R3, a 29th transistor HV_SP1, a 30th transistor HV_SP2, and a first clamping circuit. The 29th transistor HV_SP1 and the 30th transistor HV_SP2 are high-voltage isolation bias transistors.

[0085] A first end of the second resistor R2 is connected to the first input terminal INP, and a second end of the second resistor R2 is connected to the second end of the twenty-ninth transistor HV_SP1. A first end of the third resistor R3 is connected to the second input terminal INN, and a second end of the third resistor R3 is connected to the second end of the thirtieth transistor HV_SP2. Control terminals of the twenty-ninth transistor HV_SP1 and the thirtieth transistor HV_SP2 are connected to the first end of the first resistor R1 to receive the substrate voltage VNW. The first ends of the twenty-ninth transistor HV_SP1 and the thirtieth transistor HV_SP2 are connected to the first clamp circuit and are simultaneously configured to output differential input signals INP_G and INN_G.

[0086] In this embodiment, the first transistor MP_BIAS2, the second transistor MP_IN3, the third transistor MP_IN4, the fourth transistor MP_BIAS4, the fifth transistor MP_BIAS3, the sixth transistor MP3, the seventh transistor MP2, the eighth transistor MP1, the eleventh transistor MP_BIAS1, the twelfth transistor MP_IN1, the thirteenth transistor MP_IN2, the fourteenth transistor MP_DIO1, the fifteenth transistor MP_DIO2, the seventeenth transistor HV_P1, the eighteenth transistor HV_P2, the nineteenth transistor HV_PCAS2, the twentieth transistor HV_P3, the twenty-third transistor HV_PCAS1, the twenty-fourth transistor HV_PCAS3, the twenty-fifth transistor HV_P5, the twenty-sixth transistor HV_P4, the twenty-ninth transistor HV_SP1, and the thirtieth transistor HV_SP2 are P-type MOS transistors.

[0087] The ninth transistor MN_BIAS3 , the tenth transistor MN_BIAS2 , the sixteenth transistor MN_BIAS1 , the twenty-first transistor MN_DIO1 , the twenty-second transistor HV_NCAS1 , the twenty-seventh transistor MN_DIO3 and the twenty-eighth transistor HV_NCAS2 are N-type MOS transistors.

[0088] In other embodiments, the N-type MOS transistor and the P-type MOS transistor can be interchanged.

[0089] Next, combine Figures 1 to 5 The working principle of this embodiment is described in detail.

[0090] The substrate bias unit 20 sets the substrate voltage VNW of the twelfth transistor MP_IN1 and the thirteenth transistor MP_IN2 in the input stage unit 10 according to the input common mode voltage of the differential input signals INN_G and INP_P, wherein the substrate voltage VNW is:

[0091] VNW=VGS+I1*R1

[0092] Wherein, VGS is the gate-source voltage of the second transistor MP_IN3 and the third transistor MP_IN4 , I1 is the current flowing through the resistor R1 , and R1 is the resistance value of the first resistor R1 .

[0093] When the input common-mode voltage is a low common-mode voltage, typically 0V, the current output by the fourth transistor MP_BIAS4 flows into both the sixth transistor MP3 and the seventh transistor MP2. Due to the setting of the reference voltage Vref, which is typically approximately 500mV, the eighth transistor MP1 is turned off. No current flows through the current mirror unit. At this time, the current I1 flowing through the first resistor R1 is the sum of the currents flowing through the first transistor MP_BIAS2 and the fifth transistor MP_BIAS3. The substrate voltage VNW provided by the intermediate node O increases, thereby increasing the threshold voltage VTH of the twelfth transistor MP_IN1 and the thirteenth transistor MP_IN2. This causes the twelfth transistor MP_IN1 and the thirteenth transistor MP_IN2 to operate in the saturation region, ensuring normal operation of the operational amplifier.

[0094] When the input common-mode voltage is a high common-mode voltage, typically Vdd to Vdd-1.5V, the eighth transistor MP1 is turned on, the sixth transistor MP3 and the seventh transistor MP2 are turned off, and the current output by the fourth transistor MP_BIAS4 flows into the eighth transistor MP1. A current is also generated in the current mirror unit. At this time, the current I1 flowing through the first resistor R1 is the sum of the currents flowing through the first transistor MP_BIAS2 and the fifth transistor MP_BIAS3 minus the current flowing into the tenth transistor MN_BIAS2. The substrate voltage VNW provided by the intermediate node O decreases, thereby providing a larger margin for the source-drain voltage of the eleventh transistor MP_BIAS1.

[0095] like Figure 6 and Figure 1 As shown, this embodiment also discloses a method for dynamically adjusting the substrate voltage of an operational amplifier input circuit. Based on the above operational amplifier input circuit, the method includes:

[0096] S1 . The substrate voltage VNW of the first differential transistor pair of the input stage unit 10 is set through the second differential transistor pair and the resistor unit based on the input common mode voltage of the differential input signals INN_G and INP_G.

[0097] S2. Adaptively adjust the voltage difference between the first end and the second end of the resistor unit according to the input common mode voltage to adjust the substrate voltage VNW.

[0098] In addition, the above method further includes: dynamically adjusting the current flowing through the resistance unit and / or adjusting the resistance value of the resistance unit according to the magnitude of the input common mode voltage, so as to change the substrate voltage VNW.

[0099] In summary, the dynamic substrate voltage VNW can provide the input stage unit 10 with a better operating point, thereby improving the circuit's performance indicators at low common mode voltage and high common mode voltage, such as the common mode rejection ratio.

[0100] The foregoing descriptions of specific exemplary embodiments of the present invention are for purposes of illustration and description. These descriptions are not intended to limit the invention to the precise forms disclosed, and it is apparent that many variations and modifications are possible in light of the foregoing teachings. The exemplary embodiments have been selected and described for the purpose of explaining the specific principles of the invention and their practical application, thereby enabling those skilled in the art to realize and utilize a variety of exemplary embodiments of the invention and various options and modifications. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. An operational amplifier input circuit, characterized in that: include: An input stage unit, comprising a first differential transistor pair, wherein the first differential transistor pair is configured to receive a differential input signal; a substrate bias unit, comprising a second differential transistor pair and a resistor unit, wherein a first end of the resistor unit is used to output a substrate voltage provided to the first differential transistor pair of the input stage unit, and a second end of the resistor unit is connected to the second differential transistor pair, and the second differential transistor pair is used to receive a differential input signal; as well as a substrate voltage regulating unit, configured to adaptively regulate a voltage difference between a first terminal and a second terminal of the resistor unit according to an input common-mode voltage, so as to regulate the substrate voltage; The substrate voltage regulating unit includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a current mirror unit; The first ends of the fourth transistor and the fifth transistor are connected to the power supply voltage, the control ends of the fourth transistor and the fifth transistor are connected to the first control voltage, the second end of the fifth transistor is connected to the first end of the resistance unit, the first ends of the sixth transistor, the seventh transistor and the eighth transistor are connected to the second end of the fourth transistor, the control ends of the sixth transistor and the seventh transistor are used to receive the differential input signal, the second ends of the sixth transistor and the seventh transistor are grounded, the control end of the eighth transistor is connected to the reference voltage, the current mirror unit is connected to the second end of the eighth transistor and the first end of the resistance unit, and the substrates of the sixth transistor, the seventh transistor and the eighth transistor are connected to the first end of the resistance unit.

2. The operational amplifier input circuit according to claim 1, wherein: The substrate voltage adjustment unit is used to dynamically adjust the current flowing through the resistance unit and / or adjust the resistance value of the resistance unit according to the magnitude of the input common mode voltage, so as to change the substrate voltage.

3. The operational amplifier input circuit according to claim 1, wherein: The substrate bias unit includes: a first transistor, wherein a first terminal of the first transistor is connected to a power supply voltage, a second terminal of the first transistor is connected to a substrate voltage adjustment unit, and a control terminal of the first transistor is connected to a first control voltage; The first end of the resistor unit is connected to the second end of the first transistor and the substrate voltage adjustment unit to form an intermediate node for providing a substrate voltage to the differential transistor pair of the input stage unit, and the resistance of the resistor unit is a fixed resistance or an adjustable resistance; and A second transistor and a third transistor, the second transistor and the third transistor constitute a second differential transistor pair, the control ends of the second transistor and the third transistor are used to receive the differential input signal, the first ends of the second transistor and the third transistor are connected to the second end of the resistance unit, the second ends of the second transistor and the third transistor are grounded, and the substrates of the second transistor and the third transistor are connected to the first end of the resistance unit.

4. The operational amplifier input circuit according to claim 1, wherein: The input stage unit includes an eleventh transistor, a twelfth transistor and a thirteenth transistor, the first end of the eleventh transistor is connected to the power supply voltage, the control end of the eleventh transistor is connected to the first control voltage, the twelfth transistor and the thirteenth transistor constitute a first differential transistor pair, the control ends of the twelfth transistor and the thirteenth transistor are used to receive the differential input signal, the first ends of the twelfth transistor and the thirteenth transistor are connected to the second end of the eleventh transistor, the second ends of the twelfth transistor and the thirteenth transistor are used to output a differential current signal, and the substrates of the twelfth transistor and the thirteenth transistor are connected to the first end of the resistance unit.

5. The operational amplifier input circuit according to claim 1 or 2, wherein: The input stage unit includes an eleventh transistor, a twelfth transistor and a thirteenth transistor; The first terminal of the eleventh transistor is connected to a power supply voltage, the control terminal of the eleventh transistor is connected to a first control voltage, the twelfth transistor and the thirteenth transistor constitute a first differential transistor pair, the control terminals of the twelfth transistor and the thirteenth transistor are used to receive the differential input signal, the first terminals of the twelfth transistor and the thirteenth transistor are connected to the second terminal of the eleventh transistor, the second terminals of the twelfth transistor and the thirteenth transistor are used to output a differential current signal, and substrates of the twelfth transistor and the thirteenth transistor are connected to the first terminal of the resistance unit; The substrate bias unit includes: a first transistor, wherein a first terminal of the first transistor is connected to a power supply voltage, a second terminal of the first transistor is connected to a substrate voltage adjustment unit, and a control terminal of the first transistor is connected to a first control voltage; The first end of the resistor unit is connected to the second end of the first transistor and the substrate voltage adjustment unit to form an intermediate node for providing a substrate voltage to the differential transistor pair of the input stage unit, and the resistance of the resistor unit is a fixed resistance or an adjustable resistance; and a second transistor and a third transistor, wherein the second transistor and the third transistor constitute a second differential transistor pair, control terminals of the second transistor and the third transistor are used to receive the differential input signal, first terminals of the second transistor and the third transistor are connected to the second terminal of the resistance unit, second terminals of the second transistor and the third transistor are grounded, and substrates of the second transistor and the third transistor are connected to the first terminal of the resistance unit; The substrate bias unit further includes a level shift circuit, and the input stage unit further includes a seventeenth transistor and an eighteenth transistor; The level shifting circuit is connected to the first ends of the second and third transistors, the second end of the resistance unit, and the control ends of the seventeenth and eighteenth transistors. The level shifting circuit controls the voltage of the control ends of the seventeenth and eighteenth transistors to follow the voltage change of the first ends of the second and third transistors, thereby clamping the voltage between the first and second ends of the twelfth transistor and the voltage between the first and second ends of the thirteenth transistor. The first end of the seventeenth transistor is connected to the second end of the twelfth transistor, the first end of the eighteenth transistor is connected to the second end of the thirteenth transistor, and the second ends of the seventeenth and eighteenth transistors are used to output differential current signals.

6. The operational amplifier input circuit according to claim 5, wherein: The level shift circuit includes a fourteenth transistor, a fifteenth transistor and a sixteenth transistor; The first end of the fourteenth transistor is connected to the second end of the resistance unit, the control end of the fourteenth transistor is short-circuited to the second end, the first end of the fifteenth transistor is connected to the second end of the fourteenth transistor, the second end of the fifteenth transistor is short-circuited to the control end, the second end of the sixteenth transistor is connected to the second end of the fifteenth transistor, the control end of the sixteenth transistor is connected to the second control voltage, the first end of the sixteenth transistor is grounded, and the second end of the fifteenth transistor is connected to the control ends of the seventeenth transistor and the eighteenth transistor.

7. The operational amplifier input circuit according to claim 6, wherein: The substrate bias unit further includes a twentieth transistor; a first terminal of the twentieth transistor is connected to the second terminals of the second transistor and the third transistor, a control terminal of the twentieth transistor is connected to the second terminal of the fifteenth transistor, and a second terminal of the twentieth transistor is grounded; or The substrate bias unit further includes a twentieth transistor and a twenty-first transistor, wherein a first terminal of the twentieth transistor is connected to the second terminals of the second transistor and the third transistor, a control terminal of the twentieth transistor is connected to the second terminal of the fifteenth transistor, a second terminal of the twentieth transistor is connected to the second terminal of the twenty-first transistor and the control terminal of the twenty-first transistor, and a first terminal of the twenty-first transistor is grounded.

8. The operational amplifier input circuit according to claim 6, wherein: The substrate voltage adjustment unit further includes a twenty-fifth transistor and a twenty-sixth transistor; A first terminal of the twenty-fifth transistor is connected to the second terminals of the sixth transistor and the seventh transistor, and a control terminal of the twenty-fifth transistor is connected to the second terminal of the fifteenth transistor; The first end of the twenty-sixth transistor is connected to the second end of the eighth transistor, the second end of the twenty-sixth transistor is connected to the current mirror unit, and the control end of the twenty-sixth transistor is connected to the second end of the fifteenth transistor.

9. The operational amplifier input circuit according to claim 1, wherein: The operational amplifier input circuit further includes a protection circuit, wherein the protection circuit includes a twenty-ninth transistor, a thirtieth transistor, and a first clamping circuit; The second end of the 29th transistor is coupled to the first input end, the second end of the 30th transistor is coupled to the second input end, the control ends of the 29th transistor and the 30th transistor are connected to the first end of the resistance unit, and the first ends of the 29th transistor and the 30th transistor are connected to the first clamping circuit and are simultaneously used to output differential input signals.

10. A method for dynamically adjusting the substrate voltage of an operational amplifier input circuit, characterized in that: Based on the operational amplifier input circuit according to any one of claims 1 to 9, the operational amplifier input circuit includes a resistor unit, and a first differential transistor pair and a second differential transistor pair receiving a differential input signal, a first end of the resistor unit being used to output a substrate voltage provided to the first differential transistor pair of the input stage unit, and a second end of the resistor unit being connected to the second differential transistor pair, the method comprising: Setting a substrate voltage of the first differential transistor pair of the input stage unit through the second differential transistor pair and the resistor unit based on an input common mode voltage of the differential input signal; The voltage difference between the first end and the second end of the resistance unit is adaptively adjusted according to the input common mode voltage to adjust the substrate voltage.

11. The method for dynamically adjusting the substrate voltage of an operational amplifier input circuit according to claim 10, wherein: The method further includes dynamically adjusting the current flowing through the resistance unit and / or adjusting the resistance value of the resistance unit according to the magnitude of the input common mode voltage to change the substrate voltage.

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