Pulse generating circuit and interleaved pulse generating circuit

Abstract

The embodiments of the present application provide a pulse generating circuit and an interlaced pulse generating circuit, wherein the pulse generating circuit comprises: an oscillation module, which receives a control signal and generates a first oscillation signal according to the control signal; a period adjustment module, which receives the first oscillation signal and a multiplier selection signal and outputs a second oscillation signal, wherein the period of the second oscillation signal is the period of the first oscillation signal adjusted based on the multiplier selection signal; a pulse conversion module, which receives the second oscillation signal and outputs a pulse signal, wherein the pulse of the pulse signal is generated based on the rising edge or the falling edge of the second oscillation signal, and the pulse period of the pulse signal is the same as the oscillation period of the second oscillation signal; the embodiments of the present application generate a pulse signal with an adjustable period, and the area of ​​the circuit layout is small, and the power consumption of the circuit is low.

Description

Technical Field

[0001] The present application relates to the field of semiconductor circuit design, and in particular to a pulse generating circuit and an interleaved pulse generating circuit. Background Art

[0002] In semiconductor circuit design, staggered signals are often used. Staggered signals refer to signals generated with a fixed delay at each interval.

[0003] For synchronous signals, clock signals are usually used to generate equally spaced interleaved signals; for asynchronous signals, delay cells are inserted to generate the required equally spaced interleaved signals, and the delay between signals can be achieved by inserting corresponding delay cells as required. Among them, when synchronous signals are used to generate equally spaced interleaved signals, the delay between equally spaced interleaved signals is an integer multiple of the clock cycle, and the controllability of the delay between equally spaced interleaved signals is poor; when asynchronous signals are used to generate equally spaced interleaved signals, although the delay between signals is well controllable, it will significantly increase the area of ​​the formed circuit layout and the power consumption of the circuit.

[0004] However, the applicant discovered that adjusting the signal delay of the equally spaced interlaced signal by the period of the pulse signal can reduce the area of ​​the circuit layout and the power consumption of the circuit, and the delay between signals does not need to be an integer multiple of the clock period. How to generate a pulse signal with a variable period is a prerequisite for optimizing the method of generating equally spaced interlaced signals. Summary of the invention

[0005] The embodiments of the present application provide a pulse generating circuit and an interleaved pulse generating circuit to generate a pulse signal with an adjustable period, and the circuit layout area is small and the power consumption of the circuit is low.

[0006] To solve the above technical problems, an embodiment of the present application provides a pulse generating circuit, including: an oscillation module, which receives a control signal and generates a first oscillation signal according to the control signal; a period adjustment module, which receives the first oscillation signal and a multiplier selection signal, and outputs a second oscillation signal, wherein the period of the second oscillation signal is the period of the first oscillation signal adjusted based on the multiplier selection signal; a pulse conversion module, which receives the second oscillation signal and outputs a pulse signal, wherein the pulses of the pulse signal are generated based on the rising edge or falling edge of the second oscillation signal, and the pulse period of the pulse signal is the same as the oscillation period of the second oscillation signal.

[0007] Compared with the related art, a first oscillation signal is generated according to a control signal, that is, when the control signal is at an effective level, a first oscillation signal with a certain period is generated; a second oscillation signal is generated based on the first oscillation signal according to a multiplier selection signal, that is, based on the multiplier selection signal, the period of the first oscillation signal is changed to generate a corresponding second oscillation signal; then the second oscillation signal is used as a signal source to generate a pulse signal, and the pulse period of the generated pulse signal is the same as the oscillation period of the second oscillation signal; in the process of generating the pulse signal, if the multiplier selection signal changes, the amplitude of the period of the first oscillation signal is adjusted to change, so that the period of the generated second oscillation signal changes, thereby generating a pulse signal with an adjustable period.

[0008] In addition, the period adjustment module includes: a delay unit, which receives the first oscillation signal and generates an oscillation adjustment signal based on the first oscillation signal, and the period of the oscillation adjustment signal is different from the period of the first oscillation signal; a selection unit, which receives a multiplier selection signal and selects the first oscillation signal or the oscillation adjustment signal as the second oscillation signal based on the multiplier selection signal.

[0009] In addition, the delay unit includes: a D trigger, the D trigger includes an input end, a clock end, a reset end and an output end, the clock end is used to receive a first oscillation signal, the reset end is used to receive a reset signal, the output end is used to trigger the inverter in series and connected to the input end, and is used to output an oscillation adjustment signal.

[0010] In addition, the selection unit includes: a multiplier selector, the multiplier selector includes a first selection input terminal, a second selection input terminal, a selection signal terminal and a selection output terminal, the first selection input terminal is used to receive a first oscillation signal, the second selection input terminal is used to receive an oscillation adjustment signal, the selection signal terminal is used to receive a multiplier selection signal, and the selection output terminal is used to output a second oscillation signal.

[0011] In addition, the delay unit includes E delay subunits connected in series, the oscillation adjustment signal includes E delay signals, E is a positive integer; the first-stage delay subunit is used to generate a first delay signal according to the first oscillation signal, and input the first delay signal into the second-stage delay subunit; the F-stage delay subunit is used to generate an F-th delay signal according to the F-1-th delay signal, and F is a positive integer less than or equal to E and greater than or equal to 2. The delay unit includes multiple delay sub-signals, and the period of the oscillation adjustment signal generated by the multiple delay sub-signals is greatly different from that of the first oscillation signal, that is, the period of the first oscillation signal is greatly changed by the multiple delay sub-signals.

[0012] In addition, the selection unit selects the first oscillation signal or the oscillation adjustment signal as the second oscillation signal based on the magnification selection signal, including: selecting the E-1th delayed signal or the Eth delayed signal as the second oscillation signal based on the magnification selection signal.

[0013] In addition, the F-th level delay sub-unit includes: a D flip-flop, the D flip-flop includes an input terminal, a clock terminal, a reset terminal and an output terminal, the clock terminal is used to receive the F-1th delay signal, the reset terminal is used to receive the reset signal, the output terminal is used to trigger the inverter in series and connected to the input terminal, and is used to output the F-th level delay signal.

[0014] In addition, the selection unit includes E selection subunits connected in series, and the multiplier selection signal includes a submultiplier selection signal corresponding to each selection subunit; the first-level selection subunit is used to select the first oscillation signal or the first delay signal according to the corresponding submultiplier selection signal and input it into the second-level selection subunit; the F-th-level selection subunit is used to select the output signal of the F-1-th-level selection subunit or the F-th delay signal according to the corresponding submultiplier selection signal and input it into the F+1-th-level selection subunit; the E-th-level selection subunit is used to select the output signal or the oscillation adjustment signal of the E-1-th-level selection subunit as the second oscillation signal according to the corresponding submultiplier selection signal, and F is a positive integer less than E and greater than or equal to 2. Through the multiple selection subunits corresponding to the multiple delay subunits, in addition to selecting the first oscillation signal or the oscillation adjustment signal as the second oscillation signal, the F-th-level delay signal can also be selected as the second oscillation signal, which provides more options for the selection of the second oscillation signal.

[0015] In addition, the F-th level selection subunit includes: a multiplier selector, the multiplier selector includes a first selection input terminal, a second selection input terminal, a selection signal terminal and a selection output terminal, the first selection input terminal is used to receive the output signal of the F-1-th level selection subunit, the second selection input terminal is used to receive the F-th delay signal, the selection signal terminal is used to receive the corresponding sub-multiplier selection signal, and the selection output terminal is used to output the output signal of the F-1-th level selection subunit or the F-th delay signal.

[0016] In addition, the oscillation module includes: an oscillation unit and a trigger unit connected to the oscillation unit; the trigger unit is used to receive a reset signal and a control signal, and trigger the oscillation unit based on the reset signal and the control signal; after the oscillation unit is triggered, a first oscillation signal is generated according to the control signal.

[0017] In addition, the oscillation unit includes: a ring oscillator formed by A inverters connected in series, where A is a positive odd number.

[0018] In addition, the trigger unit includes: a first NAND gate and a second NAND gate, the output end of the first NAND gate is connected to an input end of the second NAND gate; an input end of the first NAND gate and an output end of the second NAND gate are used to access a ring oscillator; one of the first NAND gate and the second NAND gate is used to receive a control signal, and the other is used to receive a reset signal.

[0019] In addition, the oscillation module also includes: a first inverter group, including B inverters connected in series, where B is a positive even number; a first selection unit, used to receive a first selection signal and, based on the first selection signal, connect the first inverter group in series between adjacent inverters in the ring oscillator.

[0020] In addition, the oscillation module also includes: a second inverter group, including C inverters connected in series, where C is a positive even number; a second selection unit, used to receive a second selection signal and, based on the second selection signal, connect the second inverter group in series between adjacent inverters in the ring oscillator.

[0021] In addition, the pulse conversion module includes: a pulse converter, which is used to receive the second oscillation signal and generate a pulse signal based on the second oscillation signal.

[0022] An embodiment of the present application also provides an interlaced pulse generating circuit, comprising: a signal generating module, used to generate a first control signal and a second control signal according to an activation signal, the first control signal and the second control signal are inverted signals; a first pulse generating unit, including the above-mentioned pulse generating circuit, the first pulse generating unit is used to generate a first pulse signal according to the first control signal; a second pulse generating unit, including the above-mentioned pulse generating circuit, the second pulse generating unit is used to generate a second pulse signal according to the second control signal; the first pulse signal and the second pulse signal are interlaced pulse signals.

[0023] In addition, the signal generating module includes: a reset unit, receiving a first reset signal and an activation signal, and generating a first control signal based on the first reset signal and the activation signal; and a reverse unit, receiving a first control signal, and generating a second control signal based on the first control signal.

[0024] In addition, the reset unit includes: a reset NAND gate and a reset inverter, the reset inverter is connected to the output end of the reset NAND gate, and the reset NAND gate is used to receive the first reset signal and the activation signal.

[0025] In addition, the signal generating module also includes: a reset signal generating unit, which is used to generate a second reset signal based on the first reset signal and the first control signal, so that when the first reset signal is in a reset state, the second reset signal is also in a reset state, and when the first reset signal is in a non-reset state, the second reset signal generates a reset narrow pulse based on the changing edge of the first control signal.

[0026] In addition, the signal generating module further includes: a selection signal generating unit for receiving a selection signal and generating a selection signal group based on the selection signal; the selection signal group includes a selection signal and an inverted selection signal, and the selection signal and the inverted selection signal are inverted signals.

[0027] Compared with the related art, the present invention is used to generate a first control signal and a second control signal according to an activation signal, and the first control signal and the second control signal are inverted signals to each other; the first pulse signal and the second pulse signal generated according to the inverted control signal are staggered pulse signals, that is, when the first pulse signal is in a pulse period, the second pulse signal is at an invalid level; when the second pulse signal is in a pulse period, the first pulse signal is at an invalid level, and the periods of the generated first pulse signal and the second pulse signal are adjustable, that is, a pulse signal with an adjustable period is generated, and the circuit involves fewer devices, the area of ​​the circuit board diagram is small, and the power consumption of the circuit board is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 and Figure 2 A schematic diagram of the structure of a pulse generating circuit provided in one embodiment of the present application;

[0029] Figure 3 A specific circuit diagram of an oscillation module provided in one embodiment of the present application;

[0030] Figure 4 A schematic diagram of the structure of a delay unit provided in one embodiment of the present application;

[0031] Figure 5 A schematic diagram of the structure of a selection unit provided in an embodiment of the present application;

[0032] Figure 6 and Figure 7 A circuit diagram of a period adjustment module provided in an embodiment of the present application;

[0033] Figure 8 A schematic diagram of the timing of signals in a pulse generating circuit provided in an embodiment of the present application;

[0034] Fig. 9 and Fig.10 A schematic diagram of the structure of an interleaved pulse generating circuit provided in another embodiment of the present application;

[0035] Fig.11 A specific circuit diagram of a signal generating module provided in another embodiment of the present application;

[0036] Fig.12 A schematic diagram of the timing of signals in an interleaved pulse generating circuit provided in another embodiment of the present application. DETAILED DESCRIPTION

[0037] When using synchronous signals to generate equally spaced interleaved signals, the delay between equally spaced interleaved signals must be an integer multiple of the clock period, and the controllability of the delay between equally spaced interleaved signals is poor; when using asynchronous signals to generate equally spaced interleaved signals, although the delay between signals is well controllable, it will significantly increase the area of ​​the circuit layout and the power consumption of the circuit.

[0038] To solve the above problems, an embodiment of the present application provides a pulse generating circuit, including: an oscillation module, which receives a control signal and generates a first oscillation signal according to the control signal; a period adjustment module, which receives the first oscillation signal and a multiplier selection signal, and outputs a second oscillation signal, wherein the period of the second oscillation signal is the period of the first oscillation signal adjusted based on the multiplier selection signal; a pulse conversion module, which receives the second oscillation signal and outputs a pulse signal, wherein the pulses of the pulse signal are generated based on the rising edge or falling edge of the second oscillation signal, and the pulse period of the pulse signal is the same as the oscillation period of the second oscillation signal.

[0039] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. However, it will be appreciated by those skilled in the art that in the embodiments of the present application, many technical details are proposed in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can also be implemented. The division of the following embodiments is for the convenience of description, and the specific implementation of the present application should not be construed as any limitation, and the various embodiments can be combined with each other and quoted from each other without contradiction.

[0040] Figure 1 and Figure 2 A schematic diagram of the structure of the pulse generating circuit provided in this embodiment, Figure 3 A specific circuit diagram of the oscillation module provided in this embodiment, Figure 4 A schematic diagram of the structure of the delay unit provided in this embodiment, Figure 5 A schematic diagram of the structure of the selection unit provided in this embodiment, Figure 6 and Figure 7 A circuit diagram of the cycle adjustment module provided in this embodiment, Figure 8 This is a schematic diagram of the timing of signals in the pulse generating circuit provided in this embodiment; the pulse generating circuit provided in this embodiment is further described in detail below in conjunction with the accompanying drawings.

[0041] refer to Figure 1 The pulse generating circuit 100 includes: an oscillating module 101, which receives a control signal RasEn and generates a first oscillating signal Osc1 according to the control signal RasEn.

[0042] The control signal RasEn is an externally input instruction, and the oscillation module 101 is used to generate the first oscillation signal Osc1 according to the external instruction; specifically, when the control signal RasEn is at a valid level, the oscillation module 101 generates the first oscillation signal Osc1; in this embodiment, it is assumed that the period of the first oscillation signal Osc1 is T.

[0043] In one example, when the control signal RasEn is received and the control signal RasEn is at an effective level, the oscillation module 101 starts to oscillate to generate the first oscillation signal Osc1 .

[0044] Further, refer to Figure 2 The oscillation module 101 includes an oscillation unit 111 and a trigger unit 121 connected to the oscillation unit 111; the trigger unit 121 is used to receive a reset signal fnRasEn and a control signal RasEn, and trigger the oscillation unit 111 based on the reset signal fnRasEn and the control signal RasEn; after the oscillation unit 111 is triggered, a first oscillation signal Osc1 is generated according to the control signal RasEn.

[0045] It should be noted that in the description of “triggering the oscillation unit 111 based on the reset signal fnRasEn and the control signal RasEn”, the meaning of “based on” includes but is not limited to: when the reset signal fnRasEn is in a non-reset state and the control signal RasEn is at a valid level, the trigger unit 121 triggers the oscillation unit 111.

[0046] The reset signal fnRasEn is an externally input reset instruction for resetting the trigger unit 121; specifically, after the trigger unit 121 is reset, if the control signal RasEn received by the trigger unit 121 is at a valid level, the trigger unit 121 triggers the oscillation unit 111 to enable the oscillation unit 111 to generate the first oscillation signal Osc1.

[0047] In one example, refer to Figure 3 , the oscillation unit 111 includes a ring oscillator formed by A inverters connected in series, where A is a positive odd number; A can be 5, 7, 9, 11, etc. In this embodiment, A=7, i.e., a ring oscillator formed by 7 inverters connected in series, is used as an example for illustration, which does not constitute a limitation of this embodiment. In specific applications, the number of inverters in the ring oscillator can be selected according to actual needs. The trigger unit 121 includes a first NAND gate 211 and a second NAND gate 212, wherein the output end of the first NAND gate 211 is connected to an input end of the second NAND gate 212, and an input end of the first NAND gate 211 and an output end of the second NAND gate 212 are used to access the ring oscillator; one of the first NAND gate 211 and the second NAND gate 212 is used to receive the control signal RasEn, and the other is used to receive the reset signal fnRasEn; it should be noted that, Figure 3 The first NAND gate 211 is used to receive the control signal RasEn, and the second NAND gate 212 is used to receive the reset signal fnRasEn. This does not constitute a limitation to this embodiment. In other embodiments, the second NAND gate may receive the control signal, and the first NAND gate may receive the reset signal.

[0048] In this embodiment, the oscillation module 101 further includes: a first inverter group 215, including B inverters connected in series, where B is a positive even number; B can be 2, 4, 6, etc. In this embodiment, B=2, i.e., the first inverter group 215 formed by two inverters connected in series is used as an example for illustration, which does not constitute a limitation of this embodiment. In specific applications, the number of inverters in the first inverter group 215 can be selected according to actual needs. A first selection unit (not shown) is used to receive a first selection signal fnAdjDly1, and based on the first selection signal fnAdjDly1, connect the first inverter group 215 in series between adjacent inverters in the ring oscillator.

[0049] Specifically, the purpose of having B inverters in the first inverter group 215 is to ensure that the total number of inverters in the ring oscillator is an odd number; specifically, the first selection unit (not shown) includes a first selector 214, which is used to select the first branch or the second branch according to the first selection signal fnAdjDly1 and the reverse first selection signal fnAdjDly1N; wherein the first branch serves as a connection circuit of adjacent inverters in the ring oscillator, and the second branch connects the first inverter group 215 in series to the connection circuit of the adjacent inverters of the ring oscillator; the first inverter group 2 The purpose of connecting the first inverter group 215 to the ring oscillator is to increase the number of inverters in the ring oscillator, thereby increasing the period of the first oscillation signal Osc1 generated by the oscillation unit 111. In this embodiment, it is assumed that after adding the inverters of the first inverter group 215, the generated first oscillation signal Osc1 is 1.2T. Since the connection of the first inverter group 215 to the ring oscillator is controlled by the first selection signal fnAdjDly1, the period of the first oscillation signal Osc1 generated by the oscillation unit 111 can be adjusted by the externally input first selection signal fnAdjDly1.

[0050] In this embodiment, the oscillation module 101 further includes: a second inverter group 217, including C inverters connected in series, where C is a positive even number; C can be 2, 4, 6, etc. In this embodiment, C=4, i.e., a second inverter group 217 formed by 4 inverters connected in series, is used as an example for illustration, which does not constitute a limitation of this embodiment. In specific applications, the number of inverters in the second inverter group 217 can be selected according to actual needs. A second selection unit (not shown) is used to receive a second selection signal fnAdjDly2, and based on the second selection signal fnAdjDly2, connect the second inverter group 217 in series between adjacent inverters in the ring oscillator.

[0051] Specifically, the purpose of having C inverters in the second inverter group 217 is to ensure that the total number of inverters in the ring oscillator is an odd number; specifically, the second selection unit (not shown) includes a second selector 216, which is used to select the third branch or the fourth branch according to the second selection signal fnAdjDly2 and the reverse second selection signal fnAdjDly2N; wherein the third branch serves as a connection circuit of adjacent inverters in the ring oscillator, and the fourth branch connects the second inverter group 217 in series to the connection circuit of the adjacent inverters of the ring oscillator; the second inverter group 2 The purpose of connecting 17 to the ring oscillator is to increase the number of inverters in the ring oscillator, thereby increasing the period of the first oscillation signal Osc1 generated by the oscillation unit 111. In this embodiment, it is assumed that after adding the inverter of the second inverter group 217, the generated first oscillation signal Osc1 is 1.4T; since the connection of the second inverter group 217 to the ring oscillator is controlled by the second selection signal fnAdjDly2, the period of the first oscillation signal Osc1 generated by the oscillation unit 111 can be adjusted by the externally input second selection signal fnAdjDly2.

[0052] In this embodiment, B and C can be set to any positive even number. In specific applications, the values ​​of B and C can be reasonably set according to the required changes in the first oscillation signal Osc1 generated by the oscillation unit 111. In addition, this embodiment describes the implementation method of two inverter groups. On the basis of this embodiment, the implementation scheme of continuing to add a third inverter group and a fourth inverter group should all fall within the protection scope of this application.

[0053] In addition, by simultaneously connecting the first inverter group 215 and the second inverter group 217 to the ring oscillator, the period of the first oscillation signal Osc1 can be changed by different amplitudes; at this time, the periodic table 1 of the first oscillation signal Osc1 generated according to the difference between the first selection signal fnAdjDly1 and the second selection signal fnAdjDly2 is shown in:

[0054] Table 1 Osc1 periodic table

[0055] fnAdjDly1 fnAdjDly2 Osc1 cycle 0 0 T 1 0 1.2T 0 1 1.4T 1 1 1.6T

[0056] Continue to refer Figure 1The pulse generating circuit 100 includes: a period adjustment module 102, which receives the first oscillation signal Osc1 and the multiplication factor selection signal fnAdjDlyx, and outputs a second oscillation signal Osc2. The period of the second oscillation signal Osc2 is the period of the first oscillation signal Osc1 adjusted based on the multiplication factor selection signal fnAdjDlyx. The multiplication factor selection signal fnAdjDlyx is an externally input selection instruction for adjusting the period of the second oscillation signal Osc2. That is, the pulse generating circuit can adjust the period of the second oscillation signal Osc2 generated by the period adjustment module 102 through the externally input multiplication factor selection signal fnAdjDlyx.

[0057] In one example, the first oscillation signal Osc1 can be used to generate the oscillation adjustment signal OscT, and then the first oscillation signal Osc1 is selected as the second oscillation signal Osc2 for output according to the magnification selection signal fnAdjDlyx, or the oscillation adjustment signal OscT is selected as the second oscillation signal Osc2 for output. It is also possible to determine whether the oscillation adjustment signal OscT needs to be generated according to the magnification selection signal fnAdjDlyx, that is, the second oscillation signal Osc2 is output by first determining and then generating.

[0058] refer to Figure 2 The period adjustment module 102 includes: a delay unit 112, which receives the first oscillation signal Osc1 and generates an oscillation adjustment signal OscT based on the first oscillation signal Osc1, and the period of the oscillation adjustment signal OscT is different from the period of the first oscillation signal Osc1; a selection unit 122, which receives the multiplication selection signal fnAdjDlyx and selects the first oscillation signal Osc1 or the oscillation adjustment signal OscT as the second oscillation signal Osc2 based on the multiplication selection signal fnAdjDlyx.

[0059] In one example, refer to Figure 4 The delay unit 112 includes: a D flip-flop 201, the D flip-flop includes an input terminal D, clock terminals Clk and ClkN, a reset terminal RN and an output terminal Q, the clock terminals Clk and ClkN are used to receive the first oscillation signal Osc1 and the reverse first oscillation signal Osc1N, the reset terminal RN is used to receive the reset signal fnRasEn, the output terminal Q is used to trigger the inverter 202 in series and is connected to the input terminal D, and is used to output the oscillation adjustment signal OscT. Those skilled in the art will know that the period of the oscillation adjustment signal OscT output at this time is twice the period of the first oscillation signal Osc1.

[0060] refer to Figure 5The selection unit 122 includes a multiplier selector 203, which includes a first selection input terminal, a second selection input terminal, a selection signal terminal and a selection output terminal. The first selection input terminal is used to receive the first oscillation signal Osc1, the second selection input terminal is used to receive the oscillation adjustment signal OscT, the selection signal terminal is used to receive the multiplier selection signal fnAdjDlyx and the reverse multiplier selection signal fnAdjDlyxN, and the selection output terminal is used to output the second oscillation signal Osc2. The period of the oscillation signal can be greatly changed by the multiplier selection signal fnAdjDlyx.

[0061] At this time, the period of the second oscillation signal Osc2 generated according to the first selection signal fnAdjDly1, the second selection signal fnAdjDly2 and the magnification selection signal fnAdjDlyx is shown in Table 2:

[0062] Table 2 Periodic table of Osc2

[0063] fnAdjDlyx fnAdjDly1 fnAdjDly2 Osc2 cycle 0 0 0 T 0 1 0 1.2T 0 0 1 1.4T 0 1 1 1.6T 1 0 0 2T 1 1 0 2.4T 1 0 1 2.8T 1 1 1 3.2T

[0064] In this embodiment, the delay unit 112 includes E delay sub-units connected in series, the oscillation adjustment signal OscT includes E delay signals, E is a positive integer; the first-stage delay sub-unit is used to generate a first delay signal Osc11 according to the first oscillation signal Osc1, and input the first delay signal Osc11 into the second-stage delay sub-unit; the F-th-stage delay sub-unit is used to generate an F-th delay signal Osc1F according to the F-1-th-stage delay signal Osc1F-1, where F is a positive integer less than or equal to E and greater than or equal to 2.

[0065] Specifically, the F-th level delay subunit includes: a D flip-flop, the D flip-flop includes an input terminal, a clock terminal, a reset terminal and an output terminal, the clock terminal and the clock terminal are used to receive the F-1st delay signal Osc1F-1 and the inverted F-1st delay signal Osc1F-1N, the reset terminal is used to receive the reset signal, the output terminal is used to trigger the inverter in series and is connected to the input terminal, and is used to output the F-th delay signal Osc1F. Those skilled in the art will know that the period of the F-th delay signal Osc1F output at this time is twice the period of the F-1st delay signal Osc1F-1.

[0066] refer to Figure 6The delay unit 112 includes three delay sub-units connected in series, namely a first-stage delay sub-unit 221, a second-stage delay sub-unit 223 and a third-stage delay sub-unit 225; wherein the first-stage delay sub-unit 221 is used to generate a first delay signal Osc11 according to the first oscillation signal Osc1, and the period of the first delay signal Osc11 is twice the period of the first oscillation signal Osc1; the second-stage delay sub-unit 223 is used to generate a second delay signal Osc12 according to the first delay signal Osc11, and the period of the second delay signal Osc12 is twice the period of the first delay signal Osc11; the third-stage delay sub-unit 225 is used to generate a third delay signal Osc13 according to the second delay signal Osc12, and the period of the third delay signal Osc13 is twice the period of the second delay signal Osc12.

[0067] In an example, the selection unit 122 selects the first oscillation signal Osc1 or the oscillation adjustment signal OscT as the second oscillation signal Osc2 based on the magnification selection signal fnAdjDlyx, including: selecting the E-1th delayed signal Osc1E-1 or the Eth delayed signal Osc1E as the second oscillation signal Osc2 based on the magnification selection signal fnAdjDlyx.

[0068] In this embodiment, the selection unit 122 selects the first oscillation signal Osc1 or the oscillation adjustment signal OscT as the second oscillation signal Osc2 based on the magnification selection signal fnAdjDlyx, including: selecting the second delay signal Osc12 or the third delay signal Osc13 as the second oscillation signal Osc2 based on the magnification selection signal fnAdjDlyx. The first-stage delay unit 221 and the second-stage delay sub-unit 223 are used to expand the period of the output second oscillation signal Osc2.

[0069] At this time, the period of the second oscillation signal Osc2 generated according to the first selection signal fnAdjDly1, the second selection signal fnAdjDly2 and the magnification selection signal fnAdjDlyx is shown in Table 3:

[0070] Table 3 Periodic table of Osc2

[0071] fnAdjDlyx fnAdjDly1 fnAdjDly2 Osc2 cycle 0 0 0 4T 0 1 0 4.8T 0 0 1 5.6T 0 1 1 6.4T 1 0 0 8T 1 1 0 9.6T 1 0 1 11.2T 1 1 1 12.8T

[0072] In another example, the selection unit 122 includes E selection sub-units connected in series, and the rate selection signal fnAdjDlyx includes a sub-rate selection signal corresponding to each selection sub-unit; the first-level selection sub-unit is used to select the first oscillation signal Osc1 or the first delay signal Osc11 according to the corresponding sub-rate selection signal, and input it into the second-level selection sub-unit; the F-th-level selection sub-unit is used to select the output signal of the F-1-th-level selection sub-unit or the F-th delay signal Osc1F according to the corresponding sub-rate selection signal, and input it into the F+1-th-level selection sub-unit; the E-th-level selection sub-unit is used to select the output signal of the E-1-th-level selection sub-unit or the oscillation adjustment signal OscT as the second oscillation signal Osc2 according to the corresponding sub-rate selection signal, where F is a positive integer less than E and greater than or equal to 2.

[0073] Specifically, the F-th level selection subunit includes: a multiplier selector, the multiplier selector includes a first selection input terminal, a second selection input terminal, a selection signal terminal and a selection output terminal, the first selection terminal is used to receive the output signal of the F-1-th level selection subunit, the second selection input terminal is used to receive the F-th delay signal Osc1F, the selection signal terminal is used to receive the corresponding sub-multiplier selection signal, and the selection output terminal is used to output the output signal of the F-1-th level selection subunit or the F-th delay signal Osc1F.

[0074] refer to Figure 7 , the selection unit 122 includes three selection subunits connected in series, namely, a first-stage selection subunit 227, a second-stage selection subunit 228, and a third-stage selection subunit 229; wherein, the first-stage selection subunit 227 is used to select the first oscillation signal Osc1 or the first delay signal Osc11 to be input to the second-stage selection subunit 228, the second-stage selection subunit 228 is used to select the output signal of the first-stage selection subunit 227 or the second delay signal Osc12 to be input to the third-stage selection subunit 229, and the third-stage selection subunit 229 is used to select the output signal of the second-stage selection subunit 228 or the third delay signal Osc13 as the oscillation adjustment signal OscT. By connecting multiple selection subunits in series, more variation selections of the second oscillation signal Osc2 period are achieved.

[0075] It should be noted that, in the specific application process, the rate selection signal fnAdjDlyx, the first selection signal fnAdjDly1 and the second selection signal fnAdjDly2 can be realized by a multi-bit binary number, that is, the selection signal is a multi-bit binary number, one bit is used as the rate selection signal fnAdjDlyx, one bit is used as the first selection signal fnAdjDly1, and one bit is used as the second selection signal fnAdjDly2.

[0076] Continue to refer Figure 1The pulse generating circuit 100 includes: a pulse conversion module 103, which receives the second oscillation signal Osc2 and outputs a pulse signal OscClk, wherein the pulse of the pulse signal OscClk is generated based on the rising edge or the falling edge of the second oscillation signal, and the pulse period of the pulse signal OscClk is the same as the oscillation period of the second oscillation signal.

[0077] Specifically, refer to Figure 2 The pulse conversion module 103 includes: a pulse converter 113, which is used to receive the second oscillation signal Osc2 and generate a pulse signal OscClk based on the second oscillation signal Osc2.

[0078] In one example, when the pulse converter 113 detects the rising edge of the second oscillation signal Osc2, it outputs a narrow upward pulse. The output end of the pulse converter 113 can also pass through a series inverter to output a narrow downward pulse. In another example, when the pulse converter 113 detects the rising edge of the second oscillation signal Osc2, it outputs a narrow downward pulse. The output end of the pulse converter 113 can also pass through a series inverter to output a narrow upward pulse. In addition, in this embodiment, the pulse converter 113 works based on the rising edge of the second oscillation signal Osc2. In other embodiments, the pulse converter can also work based on the falling edge of the second oscillation signal.

[0079] It should be noted that in the description of “generating the pulse signal OscClk based on the second oscillation signal Osc2”, the meaning of “based on” includes but is not limited to: detecting the rising edge of the second oscillation signal Osc2, or detecting that the second oscillation signal Osc2 changes from a low level to a high level (high level to a low level) and then generating a narrow pulse of the pulse signal OscClk.

[0080] It should be noted that, in the present embodiment, the pulse signal OscClk is generated based on the rising edge of the second oscillation signal Osc2 , and in other embodiments, the pulse signal may also be generated based on the falling edge of the second oscillation signal.

[0081] refer to Figure 8 When the control signal RasEn is at the effective level, the oscillation module 101 generates the first oscillation signal Osc1 with a period of T, and the period adjustment module 102 adjusts the period of the second oscillation signal Osc2 (Osc2′) according to the magnification selection signal fnAdjDlyx.

[0082] Specifically, if the multiplier selection signal fnAdjDlyx is changed during the period when the control signal RasEn is at the effective level, the second oscillation signal Osc2 generated at this time has a period change. Assuming that the period changes from T to 2T, the pulse period in the pulse signal OscClk generated at this time also changes from T to 2T; if the multiplier selection signal fnAdjDlyx is changed before the control signal RasEn is at the effective level, the second oscillation signal Osc2′ generated at this time does not have a period change, and the pulse period in the generated pulse signal OscClk′ also does not have a change in the pulse period.

[0083] Compared with the related art, a first oscillation signal is generated according to a control signal, that is, when the control signal is at an effective level, a first oscillation signal with a certain period is generated; a second oscillation signal is generated based on the first oscillation signal according to a multiplier selection signal, that is, based on the multiplier selection signal, the period of the first oscillation signal is changed to generate a corresponding second oscillation signal; then the second oscillation signal is used as a signal source to generate a pulse signal, and the pulse period of the generated pulse signal is the same as the oscillation period of the second oscillation signal; in the process of generating the pulse signal, if the multiplier selection signal changes, the amplitude of the period of the first oscillation signal is adjusted to change, so that the period of the generated second oscillation signal changes, thereby generating a pulse signal with an adjustable period.

[0084] It is worth mentioning that all units involved in this embodiment are logical units. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, in order to highlight the innovative part of this application, this embodiment does not introduce units that are not closely related to solving the technical problems proposed by this application, but this does not mean that there are no other units in this embodiment.

[0085] Another embodiment of the present application relates to an interlaced pulse generating circuit, comprising: a signal generating module, used to generate a first control signal and a second control signal according to an activation signal, the first control signal and the second control signal are inverted signals; a first pulse generating unit, including the above-mentioned pulse generating circuit, the first pulse generating unit is used to generate a first pulse signal according to the first control signal; a second pulse generating unit, including the above-mentioned pulse generating circuit, the second pulse generating unit is used to generate a second pulse signal according to the second control signal; the first pulse signal and the second pulse signal are interlaced pulse signals.

[0086] Fig. 9 and Fig.10 A schematic diagram of the structure of the staggered pulse generating circuit provided in this embodiment; Fig.11 A specific circuit diagram of the signal generating module provided in this embodiment; Fig.12A timing diagram of signals in the interleaved pulse generating circuit provided in the present embodiment; the interleaved pulse generating circuit provided in the present embodiment will be described in detail below in conjunction with the accompanying drawings, and the parts that are the same as or corresponding to the above-mentioned embodiments will not be described in detail below.

[0087] refer to Fig. 9 The interleaved pulse generating circuit 300 includes: a signal generating module 303, which is used to generate a first control signal ActEn and a second control signal PreEn according to an activation signal Active, wherein the first control signal ActEn and the second control signal PreEn are inverted signals. The activation signal Active is an activation instruction input from the outside, and the signal generating module 303 is used to generate the first control signal ActEn and the second control signal PreEn, which are inverted signals to each other, according to the external activation instruction.

[0088] Specifically, refer to Fig.10 , the signal generating module 303 comprises:

[0089] The reset unit 313 receives the first reset signal fnActEn and the activation signal Active, and generates a first control signal ActEn based on the first reset signal fnActEn and the activation signal Active.

[0090] The first reset signal fnActEn is an externally input reset instruction, which is used to reset the reset unit 313; specifically, after the reset unit 313 is reset, if the activation signal Active received by the reset unit 313 is at a valid level, the reset unit 313 generates the first control signal ActEn.

[0091] The inverting unit 323 receives the first control signal ActEn and generates a second control signal PreEn based on the first control signal ActEn.

[0092] In this embodiment, the signal generating module 303 also includes: a reset signal generating unit 333, which is used to generate a second reset signal fnPreEn based on the first reset signal fnActEn and the first control signal ActEn, so that when the first reset signal fnActEn is in a reset state, the second reset signal fnPreEn is also in a reset state, and when the first reset signal fnActEn is in a non-reset state, the second reset signal fnPreEn generates a reset narrow pulse based on the changing edge of the first control signal ActEn.

[0093] In this embodiment, the signal generating module 303 further includes: a selection signal generating unit 343, which is used to receive the selection signal fnAdjDly and generate a selection signal group based on the selection signal fnAdjDly, the selection signal group including the selection signal fnAdjDly and the inverted selection signal fnAdjDlyN, and the selection signal fnAdjDly and the inverted selection signal fnAdjDlyN are inverted signals.

[0094] It should be noted that, in this embodiment, the selection signal fnAdjDly includes a rate selection signal fnAdjDlyx, a first selection signal fnAdjDly1 and a second selection signal fnAdjDly2 for adjusting the pulse generating circuit 100 .

[0095] In one example, refer to Fig.11 The reset unit 313 includes a reset NAND gate 403 and a reset inverter 404. The reset inverter 404 is connected to the output end of the reset NAND gate 403. The reset NAND gate 403 is used to receive the first reset signal fnActEn and the activation signal Active.

[0096] The inverting unit 323 includes an output inverter 405 connected to the reset unit 313 and configured to generate the second control signal PreEn according to the first control signal ActEn.

[0097] The reset signal generating unit 333 includes a pulse conversion device 406, which is used to detect the changing edge (such as the rising edge) of the first control signal ActEn and generate a pulse control signal; an output NAND gate 407 and an output inverter 408. The output NAND gate 407 is also used to receive the first reset signal fnActEn, at which time the output inverter 408 outputs the second reset signal fnPreEn.

[0098] The selection signal generating unit 343 includes: a first selection inverter 401 and a second selection inverter 402 connected in series, wherein the output end of the first selection inverter 401 is connected to the input end of the second selection inverter 402, and is used to generate a selection signal group according to the selection signal fnAdjDly.

[0099] Continue to refer Fig. 9, the interleaved pulse generating circuit 300 also includes: a first pulse generating unit 301 and a second pulse generating unit 302; the first pulse generating unit 301 includes the above-mentioned pulse generating circuit 100, and the first pulse generating unit 301 is used to generate a first pulse signal ActClk according to the first control signal ActEn; the second pulse generating unit 302 includes the above-mentioned pulse generating circuit 100, and the second pulse generating unit 302 is used to generate a second pulse signal PreClk according to the second control signal PreEn; the first pulse signal ActClk and the second pulse signal PreClk are interleaved pulse signals, and the interleaved pulse signal is a pulse signal (the first pulse signal ActClk and the second pulse signal PreClk) generated according to the inverted signal (the first control signal ActEn and the second control signal PreEn).

[0100] refer to Fig.10 The staggered pulse generating circuit 300 is used to receive an external activation signal Active, and the signal generating module 303 is used to generate a first control signal ActEn and a second control signal PreEn according to the external activation signal Active, and the first control signal ActEn and the second control signal PreEn are inverted signals.

[0101] Specifically, refer to Fig.12 , when the activation signal Active is at an effective level, the generated first control signal ActEn is at an effective level; the first pulse generating unit 301 is used to generate a first oscillation signal Osc1 with a period of T and a second oscillation signal Osc2 with a period of 2T according to the first control signal ActEn; in the present embodiment, the second oscillation signal Osc2 has the same period as the first oscillation signal Osc1, and the first pulse signal ActClk is generated based on the rising edge of the second oscillation signal Osc2. The second pulse generating unit 302 is used to generate a first oscillation signal Osc1″ with a period of T and a second oscillation signal Osc2″ with a period of 2T according to the second control signal PreEn; in the present embodiment, the second oscillation signal Osc2″ has the same period as the first oscillation signal Osc1″, and the second pulse signal PreClk is generated based on the rising edge of the second oscillation signal Osc2″. The first pulse signal ActClk and the second pulse signal PreClk generated at this time are staggered pulse signals.

[0102] Compared with the related art, the present invention is used to generate a first control signal and a second control signal according to an activation signal, wherein the first control signal and the second control signal are inverted signals to each other; the first pulse signal and the second pulse signal generated according to the inverted control signal are staggered pulse signals, i.e., when the first pulse signal is in a pulse period, the second pulse signal is at an invalid level; when the second pulse signal is in a pulse period, the first pulse signal is at an invalid level, and the periods of the generated first pulse signal and the second pulse signal are adjustable, i.e., a pulse signal with an adjustable period is generated, and the circuit involves fewer devices, the area of ​​the circuit board diagram is small, and the power consumption of the circuit board is low.

[0103] It is worth mentioning that all units involved in this embodiment are logical units. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, in order to highlight the innovative part of this application, this embodiment does not introduce units that are not closely related to solving the technical problems proposed by this application, but this does not mean that there are no other units in this embodiment.

[0104] Since the above embodiments correspond to this embodiment, this embodiment can be implemented in conjunction with the above embodiments. The relevant technical details mentioned in the above embodiments are still valid in this embodiment, and the technical effects that can be achieved in the above embodiments can also be achieved in this embodiment. In order to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied in the above embodiments.

[0105] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present application, and in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present application.

Claims

1. A pulse generating circuit, characterized in that: include: An oscillation module receives a control signal and generates a first oscillation signal according to the control signal; a period adjustment module, receiving the first oscillation signal and a magnification selection signal, and outputting a second oscillation signal, wherein the period of the second oscillation signal is the period of the first oscillation signal adjusted based on the magnification selection signal; a pulse conversion module, receiving the second oscillation signal, and outputting a pulse signal, wherein the pulse of the pulse signal is generated based on a rising edge or a falling edge of the second oscillation signal, and the pulse period of the pulse signal is the same as the oscillation period of the second oscillation signal; The cycle adjustment module includes: a delay unit, receiving the first oscillation signal, and generating an oscillation adjustment signal based on the first oscillation signal, wherein a period of the oscillation adjustment signal is different from a period of the first oscillation signal; The selection unit receives the magnification selection signal and selects the first oscillation signal or the oscillation adjustment signal as the second oscillation signal based on the magnification selection signal.

2. The pulse generating circuit according to claim 1, characterized in that: The delay unit includes: a D trigger, the D trigger includes an input end, a clock end, a reset end and an output end, the clock end is used to receive the first oscillation signal, the reset end is used to receive a reset signal, the output end is used to trigger an inverter in series and is connected to the input end, and is used to output the oscillation adjustment signal.

3. The pulse generating circuit according to claim 1, characterized in that: The selection unit includes: a multiplier selector, which includes a first selection input terminal, a second selection input terminal, a selection signal terminal and a selection output terminal, wherein the first selection input terminal is used to receive the first oscillation signal, the second selection input terminal is used to receive the oscillation adjustment signal, the selection signal terminal is used to receive the multiplier selection signal, and the selection output terminal is used to output the second oscillation signal.

4. The pulse generating circuit according to claim 1, characterized in that: The delay unit includes E delay sub-units connected in series, the oscillation adjustment signal includes E delay signals, and E is a positive integer; A first-stage delay subunit, configured to generate a first delay signal according to the first oscillation signal, and input the first delay signal into a second-stage delay subunit; The Fth delay subunit is used to generate an Fth delay signal according to the F-1th delay signal, where F is a positive integer less than or equal to E and greater than or equal to 2.

5. The pulse generating circuit according to claim 4, characterized in that: The selection unit selects the first oscillation signal or the oscillation adjustment signal as the second oscillation signal based on the magnification selection signal, including: selecting the E-1th delayed signal or the Eth delayed signal as the second oscillation signal based on the magnification selection signal.

6. The pulse generating circuit according to claim 4, characterized in that: The F-th level delay sub-unit includes: a D trigger, the D trigger includes an input terminal, a clock terminal, a reset terminal and an output terminal, the clock terminal is used to receive the F-1th delay signal, the reset terminal is used to receive the reset signal, the output terminal is used to trigger the inverter in series and is connected to the input terminal, and is used to output the F-th level delay signal.

7. The pulse generating circuit according to claim 4, characterized in that: The selection unit includes E selection sub-units connected in series, and the multiplication rate selection signal includes a sub-multiplication rate selection signal corresponding to each of the selection sub-units; The first-stage selection subunit is used to select the first oscillation signal or the first delay signal according to the corresponding sub-multiplication rate selection signal and input it into the second-stage selection subunit; The Fth level selection subunit is used to select the output signal of the F-1th level selection subunit or the Fth delay signal to be input into the F+1th level selection subunit according to the corresponding sub-multiplication rate selection signal; The E-th level selection subunit is used to select the output signal of the E-1-th level selection subunit or the oscillation adjustment signal as the second oscillation signal according to the corresponding sub-multiplier selection signal, and the F is a positive integer less than the E and greater than or equal to 2.

8. The pulse generating circuit according to claim 7, characterized in that: The F-th level selection subunit includes: a multiplier selector, the multiplier selector includes a first selection input terminal, a second selection input terminal, a selection signal terminal and a selection output terminal, the first selection input terminal is used to receive the output signal of the F-1-th level selection subunit, the second selection input terminal is used to receive the F-th delay signal, the selection signal terminal is used to receive the corresponding sub-multiplier selection signal, and the selection output terminal is used to output the output signal of the F-1-th level selection subunit or the F-th delay signal.

9. The pulse generating circuit according to claim 1, characterized in that: The oscillation module comprises: An oscillating unit and a triggering unit connected to the oscillating unit; The trigger unit is used to receive a reset signal and the control signal, and trigger the oscillation unit based on the reset signal and the control signal; After the oscillation unit is triggered, the first oscillation signal is generated according to the control signal.

10. The pulse generating circuit according to claim 9, characterized in that: The oscillation unit comprises: a ring oscillator formed by A inverters connected in series, wherein A is a positive odd number.

11. The pulse generating circuit according to claim 10, characterized in that: The trigger unit comprises: A first NAND gate and a second NAND gate, wherein an output terminal of the first NAND gate is connected to an input terminal of the second NAND gate; An input end of the first NAND gate and an output end of the second NAND gate are used to access the ring oscillator; One of the first NAND gate and the second NAND gate is used to receive the control signal, and the other is used to receive a reset signal.

12. The pulse generating circuit according to claim 11, characterized in that: The oscillation module further comprises: A first inverter group includes B inverters connected in series, where B is a positive even number; The first selection unit is used to receive a first selection signal and, based on the first selection signal, connect the first inverter group in series between adjacent inverters in the ring oscillator.

13. The pulse generating circuit according to claim 12, characterized in that: The oscillation module further comprises: A second inverter group includes C inverters connected in series, where C is a positive even number; The second selection unit is used to receive a second selection signal and connect the second inverter group in series between adjacent inverters in the ring oscillator based on the second selection signal.

14. The pulse generating circuit according to claim 1, characterized in that: The pulse conversion module includes: a pulse converter, configured to receive the second oscillation signal and generate the pulse signal based on the second oscillation signal.

15. A staggered pulse generating circuit, characterized in that: include: A signal generating module, configured to generate a first control signal and a second control signal according to an activation signal, wherein the first control signal and the second control signal are anti-phase signals; A first pulse generating unit, comprising the pulse generating circuit according to any one of claims 1 to 14, wherein the first pulse generating unit is used to generate a first pulse signal according to the first control signal; A second pulse generating unit, comprising the pulse generating circuit according to any one of claims 1 to 14, wherein the second pulse generating unit is used to generate a second pulse signal according to the second control signal; The first pulse signal and the second pulse signal are interlaced pulse signals.

16. The staggered pulse generating circuit according to claim 15, characterized in that: The signal generating module comprises: a reset unit, receiving a first reset signal and the activation signal, and generating the first control signal based on the first reset signal and the activation signal; The inverting unit receives the first control signal and generates the second control signal based on the first control signal.

17. The staggered pulse generating circuit according to claim 16, characterized in that: The reset unit includes: a reset NAND gate and a reset inverter, the reset inverter is connected to the output end of the reset NAND gate, and the reset NAND gate is used to receive the first reset signal and the activation signal.

18. The staggered pulse generating circuit according to claim 16, characterized in that: The signal generating module also includes: a reset signal generating unit, which is used to generate a second reset signal according to the first reset signal and the first control signal, so that when the first reset signal is in a reset state, the second reset signal is also in a reset state, and when the first reset signal is in a non-reset state, the second reset signal generates a reset narrow pulse based on the changing edge of the first control signal.

19. The staggered pulse generating circuit according to claim 15, characterized in that: The signal generating module further includes: a selection signal generating unit, configured to receive a selection signal and generate a selection signal group based on the selection signal; The selection signal group includes the selection signal and an inverted selection signal, and the selection signal and the inverted selection signal are inverted signals.

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