Composite terminal structure for power devices
By setting a cut-off trench in the terminal structure of the power semiconductor device and filling it with low dielectric insulating material, combined with the use of the polysilicon layer, the problem of insufficient voltage withstandness of the terminal structure under the influence of external charge is solved, and the reliability of the device is improved. Breakdown voltage.
Patent Information
- Application Number
- CN202210860597.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-07-21
- Publication Date
- 2024-12-31
- Estimated Expiration
- 2042-07-21
AI Technical Summary
The terminal structure of existing power semiconductor devices is insufficient under the influence of external charges, and is greatly affected by the charge introduced into the process line, resulting in poor reliability.
Design a composite terminal structure, including setting up several cutoff trenches in the JTE lateral terminal expansion structure, filling the trenches with low dielectric insulating filler, adding a polysilicon layer as a diffusion barrier layer, reducing the charge introduced by the process line Influence.
Through passivation treatment and the introduction of polysilicon layer, the breakdown voltage and reliability of the terminal are improved, process costs are reduced, and the voltage withstand performance of the terminal is enhanced.
Smart Images
Figure CN115084233B_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a terminal structure, in particular to a composite terminal structure for a power device. Background Art
[0002] Power semiconductor devices are one of the core devices in power electronic circuits and are widely used in automobiles, power supplies, motor drivers, etc. At present, the terminals of power semiconductor devices have a JTE lateral junction terminal extension structure, but the surface injection dose of the existing JTE (junction terminal extension) lateral junction terminal extension structure is low, basically at 1e12~1e13 / cm 2 Order of magnitude, without field plate protection, is greatly affected by the charge introduced by the process line.
[0003] For the terminals of power devices, the surface implantation dose of the main ring is relatively high, and the specific implantation dose is 1e13~1e15 / cm 2 The order of magnitude makes the terminal structure breakdown position at the bend of the main junction ring, that is, the electric field strength at the bend of the main junction ring is the largest. However, in the actual process, the deviation of the injection dose of the production line machine will affect the JTE lateral junction terminal extension structure, and the concentration is low, so the breakdown occurs at the JTE lateral junction terminal extension structure, resulting in poor terminal reliability and insufficient withstand voltage in the actual wafer. Summary of the invention
[0004] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a composite terminal structure for a power device, which effectively improves the influence of external charges on the terminal and improves the reliability of the terminal withstand voltage.
[0005] According to the technical solution provided by the present invention, the composite terminal structure for power devices includes a first conductive type substrate and a JTE lateral terminal extension structure located in the first conductive type substrate, wherein the JTE lateral terminal extension structure includes a second conductive type JTE region;
[0006] In the cross-sectional view of the terminal structure, a plurality of truncated trenches are provided in the second conductive type JTE region, the truncated trenches are arranged in sequence from the center of the first conductive type substrate to the outer edge of the first conductive type substrate, and the depth of the truncated trenches in the first conductive type substrate is greater than the junction depth of the second conductive type JTE region;
[0007] A low-dielectric insulating filling body is arranged in any truncated trench, and the low-dielectric insulating filling body fills up the truncated trench.
[0008] At least three truncated trenches are arranged in the second conductive type JTE region, and the spacing between adjacent truncated trenches is equal, or the spacing between adjacent truncated trenches gradually decreases in the direction from the center of the first conductive type substrate to the outer edge of the first conductive type substrate.
[0009] In a direction from the center of the first conductive type substrate to the outer edge of the first conductive type substrate, the width of the truncated trench gradually decreases, and the depth of the truncated trench in the first conductive type substrate gradually decreases.
[0010] The second conductive type JTE region contacts the second conductive type base region forming the main junction loop bend, and a junction depth of the second conductive type JTE region in the first conductive type substrate is smaller than a junction depth of the second conductive type base region in the first conductive type substrate.
[0011] It also includes a front metal in ohmic contact with the second conductive type base region. A back metal is arranged on the back side of the first conductive type substrate, and the back metal is in ohmic contact with the first conductive type substrate.
[0012] The material of the low dielectric insulating filler includes benzocyclobutene resin.
[0013] It also includes an insulating dielectric layer covering the front surface of the first conductive type substrate, and a polysilicon layer is also arranged in the insulating dielectric layer;
[0014] In the cross-sectional view of the terminal structure, the polysilicon layer corresponds to the JTE lateral terminal extension structure, and the lateral length of the polysilicon layer is greater than the lateral length of the JTE lateral terminal extension structure.
[0015] A first conductive type cutoff ring is arranged on the outer edge of the first conductive type substrate, and the first conductive type cutoff ring is in ohmic contact with the cutoff ring metal.
[0016] The polysilicon layer is undoped polysilicon, and the thickness of the polysilicon layer is
[0017] A truncated trench adjacent to the center of the first conductive type substrate, the truncated trench spans the second conductive type base region and the second conductive type JTE region at the bend of the main junction ring, and the depth of the truncated trench adjacent to the center of the first conductive type substrate is not less than the junction depth of the second conductive type base region in the main junction.
[0018] The advantages of the present invention are as follows: n truncated grooves are arranged in the JTE lateral terminal extension structure, where n≥3, and low-dielectric insulating fillers are filled in the truncated grooves as a passivation treatment, thereby eliminating the electric field concentration at the periphery of the main junction and at the periphery of other injection junctions due to the deviation of the injection dose of the production line machine, thereby increasing the breakdown voltage. The low-dielectric insulating filler filled in the truncated groove is mainly a low-dielectric constant insulating material, and the low-dielectric constant material can withstand a larger peak electric field than silicon, thereby having a higher breakdown voltage.
[0019] The present invention sets an insulating dielectric layer and a polysilicon layer just above the second conductive type JTE region. According to the process of preparing the polysilicon layer, it can be known that the B impurities in the polysilicon layer will not be lost to the insulating dielectric layer due to the thermal oxidation process. At the same time, due to the introduction of the polysilicon layer, as a diffusion barrier layer, it will also prevent the process line from introducing charges that affect the terminal, thereby improving the reliability of the terminal area; it is compatible with existing processes and reduces process costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 A schematic diagram of the invention.
[0021] Explanation of the reference numerals: 1-front metal, 2-polysilicon layer, 3-insulating dielectric layer, 4-stop ring metal, 5-P-type base region, 6-truncated trench group, 61-truncated trench, 7-P-type JTE region, 71-inter-groove JTE region, 8-N+ stop ring, 9-N-type drift region, 10-N+ substrate, 11-back metal and 12-low dielectric insulating filler. DETAILED DESCRIPTION
[0022] The present invention will be further described below in conjunction with specific drawings and embodiments.
[0023] like Figure 1 As shown: In order to effectively improve the influence of external charges on the terminal and improve the reliability of the terminal withstand voltage, taking the first conductivity type as N type and the second conductivity type as P type as an example, the composite terminal structure for the power device of the present invention specifically includes: an N type substrate and a JTE lateral terminal extension structure located in the N type substrate, wherein the JTE lateral terminal extension structure includes a P type JTE region 7;
[0024] In the cross-sectional view of the terminal structure, a plurality of truncated trenches 61 are provided in the P-type JTE region 7, and the truncated trenches 61 are arranged in sequence from the center of the first conductive type substrate to the outer edge of the first conductive type substrate, and the depth of the truncated trenches 61 in the N-type substrate is greater than the junction depth of the P-type JTE region 7;
[0025] A low-dielectric insulating filler 12 is disposed in any truncated trench 61 , and the low-dielectric insulating filler 12 fills the truncated trench 61 .
[0026] Specifically, the material of the N-type substrate may be selected from existing commonly used materials, such as silicon, etc. The specific material type may be selected as required to meet actual application requirements. Figure 1 In the figure, the N-type substrate includes an N+ substrate 10 and an N-type drift region 9 arranged on the N+ substrate 10. The doping concentration of the N-type drift region 9 is less than the doping concentration of the N+ substrate 10. The surface of the N-type drift region 9 is used to form the front side of the N-type substrate, and the surface of the N+ substrate 10 is used to form the back side of the N-type substrate. The back side is a surface corresponding to the front side. The details of the back side and the front side of the N-type substrate are consistent with the existing ones and are not repeated here.
[0027] For power devices, the central area of the N-type substrate is generally set as an active area, and a terminal area is set in the outer circle of the active area. The terminal area surrounds the active area. The specific positional relationship between the active area and the terminal area and the specific coordination work are consistent with the existing ones, which are well known to those in the technical field and will not be repeated here. A JTE lateral terminal extension structure is set in the terminal area of the N-type substrate. The JTE lateral terminal extension structure can be consistent with the existing ones, that is, the JTE lateral terminal extension structure includes a P-type JTE area 7, and the P-type JTE area 7 is distributed laterally in the terminal area of the N-type substrate. The lateral distribution specifically refers to the distribution in the direction from the active area to the terminal area, and the lateral length of the P-type JTE area is less than the width of the terminal area.
[0028] In order to improve the withstand voltage of the terminal area, a plurality of truncated grooves 61 are arranged in the P-type JTE area 7, wherein the plurality of truncated grooves 61 are arranged along the lateral length direction of the P-type JTE area 7, that is, the truncated grooves 61 are arranged in sequence from the center of the first conductive type substrate to the outer edge of the first conductive type substrate, and the plurality of truncated grooves 61 form a truncated groove group 6. For any truncated groove 61, the truncated groove 61 penetrates the P-type JTE area 7 in the area where it is located, that is, the depth of the truncated groove 61 in the N-type substrate is greater than the junction depth of the P-type JTE area 7. Figure 1 In the embodiment, after a plurality of truncated trenches 6 are provided in the P-type JTE region 7 , an inter-groove JTE region 71 is formed between adjacent truncated trenches 6 .
[0029] Furthermore, at least three truncated trenches 61 are provided in the P-type JTE region 7, and the spacing between adjacent truncated trenches 61 is equal, or the spacing between adjacent truncated trenches 61 gradually decreases in the direction from the center of the N-type substrate to the outer edge of the N-type substrate.
[0030] In a specific implementation, n truncated trenches 61 are arranged in the P-type JTE region 7, where n≥3, and the number of n is related to the terminal withstand voltage. The larger n is, the higher the withstand voltage of the terminal region is. Figure 1The case where n is 4 is shown in FIG. 1 , and the direction from the center of the N-type substrate to the outer edge of the N-type substrate is Figure 1 In the X direction, the spacing between adjacent truncated grooves 61 can be equal or smaller. The spacing between the truncated grooves 61 can be selected as needed to meet the actual application requirements.
[0031] In a specific implementation, a low-dielectric insulating filling body 12 is disposed in any truncated trench 61 , and the low-dielectric insulating filling body 12 fills up the truncated trench 61 .
[0032] In an embodiment of the present invention, the material of the low dielectric insulating filler 12 includes benzocyclobutene resin. The low dielectric insulating filler 12 is filled in the truncated groove 61 to perform passivation treatment to eliminate the electric field concentration around the main junction and other injection junctions due to the deviation of the injection dose of the production line machine, thereby increasing the breakdown voltage. The medium filled in the truncated groove 61 is mainly a low dielectric constant insulating material, such as benzocyclobutene resin (BCB). The low dielectric constant material can withstand a larger peak electric field than silicon, so it can have a higher breakdown voltage.
[0033] Furthermore, in a direction from the center of the N-type substrate to the outer edge of the N-type substrate, the width of the truncated trench 61 gradually decreases, and the depth of the truncated trench 61 in the N-type substrate gradually decreases.
[0034] In the embodiment of the present invention, along Figure 1 In the X direction, the width of the truncated groove 61 gradually decreases, and the depth of the truncated groove 61 also gradually decreases. Figure 1 In the four truncated grooves 61, the width and corresponding depth of the truncated grooves 61 along the X direction gradually decrease.
[0035] Furthermore, the P-type JTE region 7 contacts the P-type base region 5 forming the turning point of the main junction ring, and the junction depth of the P-type JTE region 7 in the N-type substrate is smaller than the junction depth of the P-type base region 5 in the N-type substrate.
[0036] In specific implementation, the edge of the P-type JTE region 7 away from the center of the N-type substrate is arc-shaped, and the edge of the main junction adjacent to the P-type JTE region 7 is also arc-shaped, that is, a main junction bend is formed, and the main junction area is partially straight.
[0037] In the embodiment of the present invention, the P-type JTE region 7 contacts the P-type base region 5 forming the main junction ring bend, and the junction depth of the P-type JTE region 7 in the N-type substrate is less than the junction depth of the P-type base region 5 in the N-type substrate. The P-type base region 5 generally traverses the active region of the N-type substrate, and the specific situation of using the P-type base region 5 and the N-type drift region 9 to form the main junction is consistent with the prior art.
[0038] Furthermore, the truncated trench 61 adjacent to the center of the N-type substrate spans the P-type base region 5 and the P-type JTE region 71 at the bend of the main junction ring, and the depth of the truncated trench 61 adjacent to the center of the N-type substrate is not less than the junction depth of the P-type base region 5 in the main junction.
[0039] Specifically, the truncated trench 61 adjacent to the center of the N-type substrate is Figure 1 The leftmost truncated trench 61 in the figure crosses the P-type base region 5 and the P-type JTE region 71 at the bend of the main junction ring, that is, a part of the truncated trench 61 is located in the P-type base region 6, and a part of the truncated trench 61 is located in the P-type JTE region 71. The depth of the truncated trench 61 near the center of the N-type substrate is not less than the junction depth of the P-type base region 5 in the main junction, that is, the depth of the truncated trench 61 near the center of the N-type substrate is not less than the junction depth of the P-type base region 5.
[0040] Furthermore, it also includes a front metal 1 in ohmic contact with the P-type base region 5, and a back metal 11 is arranged on the back side of the N-type substrate, and the back metal 11 is in ohmic contact with the N-type substrate.
[0041] During specific implementation, both the front metal 1 and the back metal 11 can be selected from corresponding commonly used metal materials, and the specific material type can be selected as needed to meet the actual application requirements. The front metal 1 is in ohmic contact with the P-type base region 5. When the power device is a MOSFET type device or an IGBT type device, the front metal 1 can be used to form the source electrode of the power device. When the power device is a power fast recovery diode, the front metal 1 can be used to form the positive electrode. The back metal 11 is in ohmic contact with the N-type substrate, specifically refers to ohmic contact with the N+ substrate 10 in the N-type substrate. When the power device is a MOSFET device, the back metal 11 is used to form the drain electrode. When the power device is a power fast recovery diode, the back metal 11 can be used to form the cathode. The other conditions of the front metal 1 and the back metal 11 are consistent with the existing ones, and will not be listed one by one here.
[0042] When the power device is a fast recovery diode, when a forward bias is applied to the back metal 11 and the front metal 1 is grounded, the PN junction formed between the P-type JTE region 7 and the N-type drift region 9 in the JTE lateral terminal extension structure exhibits a reverse bias state, and the P-type JTE region 7 is fully depleted due to the light doping. The P-type JTE region 7 is adjacent to the truncated trench 61, thereby increasing the peak electric field at the bottom of the P-type JTE region 7 and achieving an increase in the breakdown voltage.
[0043] Furthermore, it also includes an insulating dielectric layer 3 covering the front side of the N-type substrate, and a polysilicon layer 2 is also arranged in the insulating dielectric layer 3;
[0044] In the cross-sectional view of the terminal structure, the polysilicon layer 2 corresponds to the JTE lateral terminal extension structure, and the lateral length of the polysilicon layer 2 is greater than the lateral length of the JTE lateral terminal extension structure.
[0045] In the embodiment of the present invention, the insulating dielectric layer 3 can be a commonly used material, such as a silicon dioxide layer. The insulating dielectric layer 3 covers the front surface of the N-type substrate, that is, covers the top of the N-type drift region, and the insulating dielectric layer 3 covers the notch of the truncated groove 61. The polysilicon layer 2 is arranged in the insulating dielectric layer 3, that is, the polysilicon layer 2 is completely surrounded by the insulating dielectric layer 3. The polysilicon layer 2 corresponds to the P-type JTE region 7, and the lateral length of the polysilicon layer 2 is greater than the lateral length of the JTE region 7. The lateral length is the length along the Figure 1 The length in the X direction.
[0046] In a specific implementation, the polysilicon layer 2 is undoped polysilicon, and the thickness of the polysilicon layer 2 is
[0047] In the specific process, in order to prepare the polysilicon layer 2 in the insulating dielectric layer 3, a thin insulating dielectric layer 3 can be prepared on the front of the N-type substrate 1. After the thin insulating dielectric layer 3 is prepared, a P-type JTE region 7 is prepared in the N-type substrate by a doping implantation process to form a JTE lateral terminal extension structure. Then, a polysilicon base layer is prepared on the thin insulating dielectric layer 3, and then the final insulating oxide layer 3 and the polysilicon layer 2 are prepared by oxidation, and the polysilicon layer 2 is located in the insulating dielectric layer 3.
[0048] From the above process description, it can be seen that during oxidation, only the surface part of the polysilicon base layer is oxidized, while the silicon under the polysilicon base layer is not oxidized. Therefore, the B impurities in the polysilicon base layer will not be lost to the insulating dielectric layer 3 due to the thermal oxidation process. At the same time, due to the introduction of the polysilicon layer 2, as a diffusion barrier layer, it will also prevent the influence of the charge introduced by the process line on the terminal, thereby improving the reliability of the terminal.
[0049] Furthermore, an N+ cut-off ring 8 is provided at the outer edge of the N-type substrate, and the N+ cut-off ring 8 is in ohmic contact with the cut-off ring metal 4 .
[0050] In the embodiment of the present invention, the doping concentration of the N+ cut-off ring 8 is greater than the doping concentration of the N-type drift region 9, and the cut-off ring metal 4 is in ohmic contact with the N+ cut-off ring 8. Generally, the cut-off ring metal 4 and the front metal can be the same process step layer. The cut-off ring metal 4 is supported on the insulating dielectric layer 3 and is in ohmic contact with the N+ cut-off ring 8 through the contact hole. The role of the N+ cut-off ring 8 prepared in the terminal area is consistent with the existing ones, and will not be repeated here.
[0051] In summary, n truncated trenches 61 are set in the JTE lateral terminal extension structure, where n≥3, and a low dielectric insulating filler 12 is filled in the truncated trenches 61 as a passivation treatment to eliminate the electric field concentration at the periphery of the main junction and at the periphery of other injection junctions due to the deviation of the injection dose of the production line machine, thereby increasing the breakdown voltage. The low dielectric insulating filler 12 filled in the truncated trenches 61 is mainly a low dielectric constant insulating material. The low dielectric constant material can withstand a larger peak electric field than silicon, and thus can have a higher breakdown voltage.
[0052] The present invention sets an insulating dielectric layer 3 and a polysilicon layer 2 just above the P-type JTE region 7. According to the process of preparing the polysilicon layer 2, the B impurities in the polysilicon layer 2 will not be lost to the insulating dielectric layer 3 due to the thermal oxidation process. At the same time, due to the introduction of the polysilicon layer 2, as a diffusion barrier layer, it will also prevent the influence of the charge introduced by the process line on the terminal, thereby improving the reliability of the terminal area.
Claims
1. A composite terminal structure for a power device, comprising a first conductive type substrate and a JTE lateral terminal extension structure located in the first conductive type substrate, wherein the JTE lateral terminal extension structure comprises a second conductive type JTE region; wherein: In the cross-sectional view of the terminal structure, a plurality of truncated trenches are provided in the second conductive type JTE region, the truncated trenches are arranged in sequence from the center of the first conductive type substrate to the outer edge of the first conductive type substrate, and the depth of the truncated trenches in the first conductive type substrate is greater than the junction depth of the second conductive type JTE region; A low dielectric insulating filler is arranged in any truncated trench, and the low dielectric insulating filler fills the truncated trench; The second conductive type JTE region is in contact with the second conductive type base region forming a bend of the main junction loop, and the junction depth of the second conductive type JTE region in the first conductive type substrate is smaller than the junction depth of the second conductive type base region in the first conductive type substrate; A truncated trench adjacent to the center of the first conductive type substrate, the truncated trench spans the second conductive type base region and the second conductive type JTE region at the bend of the main junction ring, and the depth of the truncated trench adjacent to the center of the first conductive type substrate is not less than the junction depth of the second conductive type base region in the main junction.
2. The composite terminal structure for a power device according to claim 1, characterized in that: At least three truncated trenches are arranged in the second conductive type JTE region, and the spacing between adjacent truncated trenches is equal, or the spacing between adjacent truncated trenches gradually decreases in the direction from the center of the first conductive type substrate to the outer edge of the first conductive type substrate.
3. The composite terminal structure for a power device according to claim 1, characterized in that: In a direction from the center of the first conductive type substrate to the outer edge of the first conductive type substrate, the width of the truncated trench gradually decreases, and the depth of the truncated trench in the first conductive type substrate gradually decreases.
4. The composite terminal structure for a power device according to claim 1, characterized in that: It also includes a front metal in ohmic contact with the second conductive type base region. A back metal is arranged on the back side of the first conductive type substrate, and the back metal is in ohmic contact with the first conductive type substrate.
5. The composite terminal structure for a power device according to any one of claims 1 to 4, characterized in that: The material of the low dielectric insulating filler includes benzocyclobutene resin.
6. The composite terminal structure for a power device according to any one of claims 1 to 4, characterized in that: It also includes an insulating dielectric layer covering the front surface of the first conductive type substrate, and a polysilicon layer is also arranged in the insulating dielectric layer; In the cross-sectional view of the terminal structure, the polysilicon layer corresponds to the JTE lateral terminal extension structure, and the lateral length of the polysilicon layer is greater than the lateral length of the JTE lateral terminal extension structure.
7. The composite terminal structure for a power device according to any one of claims 1 to 3, characterized in that: A first conductive type cutoff ring is disposed on the outer edge of the first conductive type substrate, and the first conductive type cutoff ring is in ohmic contact with the cutoff ring metal.
8. The composite terminal structure for a power device according to claim 6, characterized in that: The polysilicon layer is undoped polysilicon, and the thickness of the polysilicon layer is 2000Å~3000Å.