Circuit and method for detecting clock glitch, clock circuit, chip and radar

Abstract

The present application relates to a circuit and method for detecting clock glitches, a clock circuit, a chip and a radar. The circuit for detecting clock glitches includes: a first sampling unit, configured to sample a first test signal based on a clock signal to obtain a first sampling result; a second sampling unit, configured to sample a second test signal based on a clock signal to obtain a second sampling result; a detection unit, coupled to the first sampling unit and the second sampling unit, respectively, configured to compare the first sampling result and the second sampling result to obtain a detection result; wherein the delay duration of the first test signal for the third test signal and the delay duration of the second test signal for the third test signal are different. The present application can detect clock glitches, thereby improving the personal safety and property safety of users.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a circuit and method for detecting clock glitches, a clock circuit, a chip and a radar. Background Art

[0002] With the rapid development of computer technology and information technology, circuits play an increasingly important role in users' daily lives and work. Clock signals can play the role of timers in circuits, ensuring that related electronic components can operate synchronously, thereby realizing the preset functions of the circuits.

[0003] Taking autonomous driving technology as an example, radar can collect environmental information so that the autonomous driving decision-making system can adopt a driving strategy that is compatible with the environmental information, such as obstacle avoidance. The clock generation unit of the radar's main control chip is responsible for providing the main control chip and at least part of the functional circuit with the clock signal required for work. Therefore, the clock signal is an important signal that multiple digital circuit functions rely on. The applicant found that the clock generation unit may physically generate clock glitches due to interference or device aging factors, resulting in abnormal radar function and failure to ensure the personal safety and property safety of users. Summary of the invention

[0004] In order to solve or partially solve the problems existing in the related art, the present application provides a circuit and method for detecting clock glitches, a clock circuit, a chip and a radar, which can detect clock glitches, improve the reliability of clock signals, and thereby improve the personal safety and property safety of users.

[0005] The first aspect of the present application provides a circuit for detecting clock glitches, including: a first sampling unit, a second sampling unit, and a detection unit. Specifically, the first sampling unit is configured to sample a first test signal based on a clock signal to obtain a first sampling result; the second sampling unit is configured to sample a second test signal based on a clock signal to obtain a second sampling result; the detection unit is coupled to the first sampling unit and the second sampling unit, respectively, and is configured to compare the first sampling result and the second sampling result to obtain a detection result; wherein the delay duration of the first test signal with respect to the third test signal is different from the delay duration of the second test signal with respect to the third test signal.

[0006] The second aspect of the present application provides a clock circuit, comprising a first clock generating unit and a circuit for detecting clock glitches as shown above. The first clock generating unit is configured to output a first clock signal. The circuit for detecting clock glitches is connected to the first clock generating unit and is configured to detect the clock signal.

[0007] The third aspect of the present application provides a chip, comprising a functional circuit and at least one of the following: a clock circuit or a circuit for detecting clock glitches as described above, wherein the functional circuit is configured to implement a specific function based on a clock signal or a backup clock signal.

[0008] A fourth aspect of the present application provides a board, comprising a circuit, a clock circuit or a chip for detecting clock glitches as described above.

[0009] A fifth aspect of the present application provides a radar, comprising at least one of the circuits, clock circuits, chips or boards for detecting clock glitches as described above.

[0010] In a sixth aspect, the present application provides a method for detecting clock glitches, including: sampling a first test signal based on a clock signal to obtain a first sampling result; sampling a second test signal based on the clock signal to obtain a second sampling result; comparing the first sampling result and the second sampling result to obtain a detection result; wherein the first test signal and the second test signal are generated based on a third test signal, and a delay duration of the first test signal with respect to the third test signal is different from a delay duration of the second test signal with respect to the third test signal.

[0011] A seventh aspect of the present application provides an electronic device, comprising: a processor; and a memory, on which executable code is stored, and when the executable code is executed by the processor, the processor executes the method as described above.

[0012] An eighth aspect of the present application provides a computer-readable storage medium having executable code stored thereon. When the executable code is executed by a processor of an electronic device, the processor executes the above method.

[0013] A ninth aspect of the present application provides a computer program product, comprising an executable code, which implements the above method when the executable code is executed.

[0014] The technical solution provided by this application may have the following beneficial effects:

[0015] In some embodiments of the present application, the first sampling unit and the second sampling unit respectively sample test signals with different delay durations based on the clock signal to be detected to obtain a first sampling result and a second sampling result. This may result in the test signal being unable to be correctly sampled during the burr period of the clock signal, causing the first sampling result and the second sampling result to be different. The clock signal is detected by comparing the first sampling result and the second sampling result. In these embodiments, it is possible to detect whether there are glitches in the clock signal, so as to perform abnormal detection on the clock circuit, improve the reliability of the clock signal, and help improve the personal safety and property safety of users.

[0016] In some embodiments of the present application, the delay duration of the first test signal and / or the second test signal relative to the third test signal can be adjusted, so as to facilitate the detection of glitch signals at different positions in a clock cycle.

[0017] In certain embodiments of the present application, the delay duration may be configured by a delay selection unit to facilitate adjustment of the delay duration of the first test signal and / or the second test signal relative to the third test signal.

[0018] In some embodiments of the present application, the position range of the glitch in the clock cycle can be determined according to the delay duration of the test signal to facilitate diagnosis.

[0019] In some embodiments of the present application, when a glitch is detected in a clock signal, a backup clock signal may be replaced to improve system reliability.

[0020] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and other objects, features and advantages of the present application will become more apparent by describing in more detail exemplary embodiments of the present application in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments of the present application.

[0022] Figure 1 It is a schematic diagram of an application scenario of a circuit and method for detecting clock glitches, a clock circuit, a chip, and a radar shown in an embodiment of the present application;

[0023] Figure 2 It is a schematic diagram of another application scenario of a circuit and method for detecting clock glitches, a clock circuit, a chip, and a radar shown in an embodiment of the present application;

[0024] Figure 3 It is a schematic diagram showing that a clock glitch causes abnormal sampling results for test signals with different delays according to an embodiment of the present application;

[0025] Figure 4 is a block diagram of a circuit for detecting clock glitches according to an embodiment of the present application;

[0026] Figure 5 is a block diagram of a test signal generating circuit shown in an embodiment of the present application;

[0027] Figure 6 is a schematic diagram of setup time and hold time shown in an embodiment of the present application;

[0028] Figure 7is a schematic diagram of line clock delay shown in an embodiment of the present application;

[0029] Figure 8 is a block diagram of a circuit for detecting clock glitches according to another embodiment of the present application;

[0030] Fig. 9 is a schematic diagram of a delay selection unit shown in an embodiment of the present application;

[0031] Fig.10 is a block diagram of a circuit for detecting clock glitches according to another embodiment of the present application;

[0032] Fig.11 is a signal timing diagram shown in an embodiment of the present application;

[0033] Fig.12 is a circuit diagram of a detection unit shown in an embodiment of the present application;

[0034] Fig.13 is a circuit diagram of a detection unit shown in another embodiment of the present application;

[0035] Fig.14 is a block diagram of a circuit for detecting clock glitches according to an embodiment of the present application;

[0036] Fig.15 is a circuit diagram of a unit data comparison logic circuit shown in an embodiment of the present application;

[0037] Fig.16 is a circuit diagram of an eight-bit data comparison logic circuit shown in an embodiment of the present application;

[0038] Fig.17 is a flow chart of a method for detecting clock glitches according to an embodiment of the present application;

[0039] Fig.18 is a schematic structural diagram of a device for detecting clock glitches according to an embodiment of the present application;

[0040] Fig.19 is a schematic diagram of the structure of a radar shown in an embodiment of the present application;

[0041] Fig. 20 It is a schematic diagram of the structure of an electronic device shown in an embodiment of the present application. DETAILED DESCRIPTION

[0042] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to make the present application more thorough and complete, and to fully convey the scope of the present application to those skilled in the art.

[0043] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "an" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0044] It should be understood that although the terms "first", "second", "third", etc. may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0045] In order to facilitate the understanding of the present application, some concepts involved in the present application are first explained.

[0046] Crystal oscillator is a mechanical vibration with the characteristics of mechanical vibration, which is related to shape, geometric dimensions, mass, etc. These parameters determine the vibration frequency. Taking quartz crystal oscillator as an example, the vibration frequency of the crystal is related to the area, thickness, cutting orientation, etc. of the quartz crystal.

[0047] Vehicle-mounted laser radar: By emitting outgoing light (such as a laser beam) with a wavelength of about 900nm, the outgoing light will be reflected by the obstacle after encountering it. The processing unit calculates the distance between the obstacle and the vehicle-mounted laser radar based on the time difference between the reflected light and the outgoing light. In addition, the processing unit can also estimate the reflectivity of the target based on the cross-section of the reflected light signal obtained after receiving the reflected light. Vehicle-mounted laser radar has a small size and a high degree of integration.

[0048] In the autonomous driving scenario, the system architecture suitable for the autonomous driving scenario may include mobile devices, networks, and the cloud. The cloud may include a server cluster or a distributed system consisting of multiple physical servers. Electronic devices such as sensors may be provided on the mobile device to obtain information about obstacles in the surrounding environment of the mobile device. Electronic devices may include: radars (including lidars), image sensors, etc. A variety of electronic devices require clock signals during operation or communication.

[0049] The embodiments of the present application provide a circuit and method for detecting clock glitches, a clock circuit, a chip, and a radar. At least two test paths use the same test pattern (test signal), and each test path has a different delay duration. When there are glitches in the clock, it will cause at least two test paths to have different sampling results for the same test pattern with different delay durations. This embodiment can detect whether there are glitches in the clock to ensure the reliability of the clock signal. This can improve the reliability of the circuit, thereby ensuring the personal safety and property safety of users in scenarios such as using assisted / automatic driving.

[0050] The technical solution of the embodiments of the present application is described in detail below with reference to the accompanying drawings.

[0051] Figure 1 It is a schematic diagram of an application scenario of a circuit and method for detecting clock glitches, a clock circuit, a chip, and a radar shown in an embodiment of the present application.

[0052] Figure 1 The hardware structure of the vehicle 10 supporting assisted driving or automatic driving functions is shown. For example, at least one laser radar (Light Detection and Ranging, referred to as LIDAR) 11 is mounted on the roof and / or the side of the vehicle body of the vehicle 10. The detection area of ​​the LIDAR 11 can be fixed, such as a certain LIDAR 11 can be used only for detection of a preset area. The detection area of ​​the LIDAR 11 can be adjustable, such as the laser radar on the vehicle body can scan multiple detection areas by adjusting the posture, etc., or by adjusting the field of view angle range of the laser radar itself. In addition, the vehicle 10 can also be equipped with multiple millimeter wave radars in a manner surrounding the vehicle 10. For example, the vehicle 10 is equipped with 4 millimeter wave radars, with the left side in front of the vehicle, the right side in front of the vehicle, the left side behind the vehicle, and the right side behind the vehicle as the detection range. Through the millimeter wave radar, the distance of the object existing in each detection area can be detected, and the relative speed of the object and the vehicle 10 can be detected.

[0053] Furthermore, the vehicle 10 may also be equipped with a positioning device 12 , such as a Beidou positioning device, a Global Positioning System (GPS), etc. The current position of the vehicle 10 can be determined by the positioning device 12 .

[0054] In addition, the vehicle 10 may also be equipped with an electronic control unit (ECU). The detection signal of at least one of the above-mentioned LIDAR 11, millimeter wave radar and positioning device 12 is sent to the ECU. The ECU can detect and identify obstacles (such as roadblocks, moving objects, trees, adjacent vehicles, etc. around the vehicle 10) based on these signals. In addition, the ECU can be physically divided into multiple units according to their functions, and this application will collectively refer to them as ECUs.

[0055] It should be noted that although the movable device is described as a car, such description is not restrictive and is applicable to a variety of movable devices, such as land robots, water robots, etc.

[0056] Figure 2 It is a schematic diagram of another application scenario of a circuit and method for detecting clock glitches, a clock circuit, a chip, and a radar shown in an embodiment of the present application.

[0057] Figure 2 The aircraft 20 shown may be an aircraft with an assisted driving function and an automatic driving function. The aircraft 20 may include a sensor system 21 and a power mechanism 22 .

[0058] The sensing system 21 may include one or more sensors to sense at least one of the surrounding obstacles, spatial orientation, speed or acceleration of the aircraft 20. The types of sensors include, but are not limited to, ranging sensors, position sensors, motion sensors, inertial sensors or image sensors. The sensing data provided by the sensing system 21 can be used to control the spatial orientation, speed and / or acceleration of the aircraft 20. The sensing system 21 is used to collect relevant information of the aircraft 20. Different types of sensors can sense different types of signals or sense signals from different sources. For example, the sensor includes a radar, an inertial sensor, a GPS sensor, or a visual / image sensor (such as a camera).

[0059] The circuit and method for detecting clock glitches and the clock circuit of the embodiment of the present application can be applied to Figure 1 or Figure 2 Any one or more electronic devices such as the LIDAR 11, millimeter wave radar, positioning device 12, ECU, sensor system 21 or communication system shown need to use a clock.

[0060] In the above-mentioned application scenarios such as assisted driving, autonomous driving, and smart transportation, quickly and accurately perceiving the surrounding environment of movable equipment is a key point.

[0061] Here, the vehicle's autonomous driving scenario is used as an example for illustrative explanation. According to the vehicle position information, obstacle information, and road information perceived by the sensor system, road signal control is coordinated to improve the quality and efficiency of road management. Specifically, the corresponding autonomous driving vehicle decision can be determined based on the information perceived by the sensor system, and the safe distance between autonomous driving vehicles can be adjusted, so that the vehicle can drive safely and reliably on the road.

[0062] As one of the most important sensors for autonomous driving, LiDAR can provide the decision-making system with important information such as the location, size, and movement of traffic participants in the fields of smart transportation, assisted driving, and autonomous driving. LiDAR is like a person's eyes to autonomous vehicles. How to protect the security of LiDAR data collection and transmission is particularly important, as it is directly related to the personal safety, property safety, and even life safety of the drivers and passengers of the vehicle.

[0063] The main control chip of the laser radar is the core component of the laser radar. The main control chip is responsible for collecting, processing and transmitting at least part of the laser radar information. The crystal oscillator device is responsible for providing the clock source for the main control chip. It is the source of all clocks and is very important for system stability. The clock of the main control chip is responsible for providing the clock source required for the relevant functional circuits to work. It is the basis for realizing the functions of the relevant digital circuits. The stability of the clock signal is very important for laser radars and devices that need to use laser radar data.

[0064] However, the applicant found that the crystal oscillator device may fail physically due to interference or device aging, generating unqualified clocks, such as clock glitch signals. In addition, the crystal oscillator is a device located outside the chip. Hackers can control the crystal oscillator outside the chip or replace the crystal oscillator with a signal generator to provide a clock signal to the lidar chip, causing glitches on the clock. If the glitches occur when the main control chip jumps or runs key commands, the chip security system will crash.

[0065] In the field of LiDAR technology, the related technologies lack hardware monitoring solutions or defense strategies for clock generation modules (such as crystal oscillator circuits), or can only rely on more complex analog circuits to implement. The related technologies lack solutions for monitoring the underlying hardware of the chip, resulting in the need for improvement of the monitoring strategy.

[0066] Based on the above reasons, the present application aims to provide a technical solution that can conveniently implement functions such as monitoring and exception handling of a clock generation unit at a relatively low cost.

[0067] Figure 3 It is a schematic diagram showing that a clock glitch causes abnormal sampling results for test signals with different delays according to an embodiment of the present application.

[0068] See also Figure 3 , using the clock signal output by the clock generating unit, the test signal d1 and the test signal d2 which have been processed with different delays are sampled respectively. Figure 3 There is a Figure 3 The delay shown. There is no glitch in the clock clk1, but there is a glitch in the clock clk2. The sampling results obtained by sampling the test signal d1 and the test signal d2 based on the clock clk1 are the same, and the sampling results obtained by sampling the test signal d1 and the test signal d2 based on the clock clk2 are different. In this way, it can be judged whether the clock signal has a glitch by the sampling results.

[0069] In addition, the same test signal with different delay durations can be sampled separately. The position of the burr in the clock can be determined based on the delay duration of the test signal with the burr detected. This makes it easier to analyze the cause of the burr, eliminate the anomaly, and improve the reliability of the clock signal output by the clock generation unit, so as to better achieve the safe operation of the laser radar and improve the personal safety and property safety of users.

[0070] In addition, in some embodiments, after a glitch is detected in the clock, an interrupt signal or a reset signal may be issued so that the system can protect and handle the clock generation unit.

[0071] Figure 4 It is a block diagram of a circuit for detecting clock glitches according to an embodiment of the present application.

[0072] See also Figure 4 The circuit 400 for detecting clock glitches may include: a first sampling unit 410 , a second sampling unit 420 and a detection unit 430 .

[0073] The first sampling unit 410 is configured to sample the first test signal based on the clock signal to obtain a first sampling result. Specifically, the test signal can be sampled using a register. When the test signal is a test pattern (TestPattern), the test pattern can be sampled using a register group.

[0074] The second sampling unit 420 is configured to sample the second test signal based on the clock signal to obtain a second sampling result. Specifically, the test signal can be sampled using a register. When the test signal is a test pattern, the test pattern can be sampled using a register group.

[0075] The delay duration of the first test signal relative to the third test signal is different from the delay duration of the second test signal relative to the third test signal. For example, the circuits of the first sampling unit 410 and / or the second sampling unit 420 can be designed so that after the third test signal is processed by the first sampling unit 410 and / or the second sampling unit 420, the first test signal and the second test signal as well as the sampling results for each are obtained. The first test signal and the second test signal have different delay durations relative to the third test signal.

[0076] It should be noted that when the test signal is processed by the circuit, such as when it is transmitted in the wire, there is inevitably a time delay. For example, the longer the signal transmission distance, the longer the time delay. For low-frequency signals, the above time delay can be ignored, but for high-frequency signals, the above time delay cannot be ignored. Therefore, the duration of the time delay of the first test signal relative to the third test signal can be the duration of the unavoidable time delay caused by reasons such as the circuit layout in the first sampling unit. Alternatively, the duration of the time delay of the second test signal relative to the third test signal can be the duration of the unavoidable time delay caused by reasons such as the circuit layout in the second sampling unit.

[0077] In addition, the duration of the unavoidable delay may be inappropriate, which is not conducive to the detection of glitches in the clock. In order to solve the above problem, the first sampling circuit and / or the second sampling circuit can be specially designed so that there is a preset delay duration between the first test signal and the second test signal. For example, a delay circuit (such as a delay line, etc.) can be set in at least one sampling circuit to delay the third test signal and obtain a first test signal or a second test signal with a specific delay duration relative to the third test signal.

[0078] In some embodiments, in order to further increase the convenience of testing, such as facilitating sampling of multiple test signals with required delay durations based on a clock, the delay duration may be adjustable. Specifically, the delay duration of the first test signal relative to the third test signal may be adjusted, and / or the delay duration of the second test signal relative to the third test signal may be adjusted.

[0079] In some embodiments, the first sampling unit includes a first signal delay circuit, which is configured to delay and output the first test signal according to a first set of delay values ​​to sample the delayed first test signal. The first signal delay circuit may include at least one signal delay unit.

[0080] The signal delay unit can be composed of a variety of components, such as a delay line, a series inverter, etc. For example, a charge coupled device (CCD) delay line is a MOS integrated circuit. MOS devices can be equivalent to capacitors, and a large number of capacitors are closely arranged to form a capacitive coupling device. Capacitors can store charge packets representing information, which are directed and transferred between adjacent capacitors under the control of clock pulses to achieve time delay. In addition, digital technology can also be used to achieve signal time delay. For example, the pulse signal is converted into a discrete digital signal through analog-to-digital conversion, and then a multi-stage shift register is used as a delay circuit. The signal is shifted step by step under the drive of the clock signal, and the signal is delayed.

[0081] In some embodiments, the second sampling unit includes a second signal delay circuit configured to delay and output the second test signal to sample the delayed second test signal. The structure of the second signal delay circuit may refer to the first signal delay circuit.

[0082] In some embodiments, the first sampling unit includes a first signal delay circuit configured to delay and output the first test signal according to a first set of delay values ​​to sample the delayed first test signal. The second sampling unit includes a second signal delay circuit configured to delay and output the second test signal to sample the delayed second test signal.

[0083] The detection unit 430 is coupled to the first sampling unit and the second sampling unit respectively, and is configured to compare the first sampling result and the second sampling result to obtain a detection result.

[0084] Specifically, the detection unit 430 may include a numerical comparator, such as comparing whether the sampling results are consistent. In addition, the detection unit 430 may include a logic operation unit, performing a logic operation on the first sampling result and the second sampling result, and counting the results of the logic operation, such as comparing the values ​​of the same bit to determine whether the first sampling result and the second sampling result are the same.

[0085] Please also see Figure 3 , there is a glitch in the clock clk2. When the test data d1 and the test data d2 are sampled based on the clock clk2, different sampling results may be obtained. In this way, it can be determined that there is a glitch in the clock clk2 based on the different sampling results.

[0086] Figure 5 is a block diagram of a test signal generating circuit shown in an embodiment of the present application.

[0087] In this embodiment, a test signal / test pattern can be generated based on a built-in self-test (BIST) technology to detect the clock. BIST is a technology that implants relevant functional circuits in a circuit during design to provide a self-test function, thereby reducing the degree of dependence of device testing on automatic test equipment (ATE). BIST can be applied to almost all circuits, and is therefore widely used in the semiconductor industry. For example, at least one of a test pattern generation circuit, a timing circuit, a mode selection circuit, and a debugging test circuit can be implanted in the circuit.

[0088] See also Figure 5 The BIST circuit may include: a test pattern generator (TPG), an output response analyzer (ORA), and a built-in self-test controller (BISTcontroller).

[0089] The test vector generator is used to automatically generate test vectors and inject them into the input pins of the circuit under test (CUT). The output response analyzer is used to compress and compare the output of the circuit under test to determine whether the circuit has errors. The built-in self-test controller is used to control when and what test pattern is input to the circuit under test, control the clock of the circuit under test and determine when to read the expected response. The built-in self-test can implement at least some operations such as loading, reading and comparing the test pattern.

[0090] The first sampling unit and the second sampling unit are respectively described exemplarily below.

[0091] In some embodiments, the first sampling unit includes a first register group, a first signal delay circuit, and a second register group connected in series.

[0092] Among them, the register group is composed of multiple registers. Registers are small storage areas used to store data, such as temporarily storing data involved in operations and operation results. Registers are essentially a sequential logic circuit, but this sequential logic circuit only contains storage circuits. The storage circuit of the register is composed of latches or flip-flops (Flip-Flop, abbreviated as FF). A latch or flip-flop can store 1 binary number, and N latches or flip-flops can form an N-bit register group. The register group can be designed according to the number of bits of a byte in the computer, for example, an 8-bit register group, a 16-bit register group, etc.

[0093] Latches and flip-flops are both logic circuits with storage functions and are the basic logic units that constitute sequential circuits. Latches are circuits that are sensitive to pulse levels and change their states under a certain level. Flip-flops are circuits that are sensitive to the edge of clock pulses and change their states under the rising or falling edge of clock pulses. Flip-flops are classified by logic function into D flip-flops, JK flip-flops, T flip-flops, and SR flip-flops.

[0094] A D flip-flop is taken as an example for illustration.

[0095] The flip-flop is sensitive to pulse edges, and its state changes only at the rising or falling edge of the clock pulse. A flip-flop, also called a bistable gate or a bistable flip-flop, is a digital logic circuit that can operate in two states. The flip-flops maintain their state until they receive an input pulse, also called a trigger. When an input pulse is received, the flip-flop output changes state according to the rules, and then maintains this state until another trigger is received. The flip-flop has the following characteristics: the clock is valid later than the data, which means that the data signal is established first, the clock signal is established later, and is stored in the flip-flop at the valid edge (such as the rising edge or the falling edge).

[0096] For ease of understanding, the signal timing of the D flip-flop and the like are exemplarily described.

[0097] Figure 6 It is a schematic diagram of setup time and hold time shown in an embodiment of the present application.

[0098] See also Figure 6 , setup time (tsu for short) and hold time (th for short) are the time requirements between the input signal and the clock of the sequential logic circuit. Setup time refers to the time that the input data signal remains unchanged before the rising edge of the trigger clock signal arrives. If the setup time is not enough, the data will not be entered (stored in) the trigger at this clock rising edge. Hold time refers to the time that the input data signal remains unchanged after the rising edge of the trigger clock arrives. If the hold time is not enough, the data cannot be entered into the trigger. If these two time requirements are not met, the output of the circuit may be an indefinite value, that is, the circuit is in a metastable state.

[0099] Specifically, the setup time refers to the time required for the data to go from unstable to stable before the clock edge arrives. If the setup time does not meet the requirements, the data will not be stably entered into the trigger at this clock rising edge. The hold time refers to the time the data is held after it is stable. If the hold time does not meet the requirements, the data will also not be stably entered into the trigger. For example, if Figure 6 The data arrives at the flip-flop after the start time tsu, or, Figure 6If the data stops entering the trigger before the end time of th, there is no guarantee that the data will be successfully stored in the trigger.

[0100] Figure 7 It is a schematic diagram of line clock delay shown in an embodiment of the present application.

[0101] See also Figure 7 , shows the data transmission between two flip-flops. The register includes a data input terminal D, a clock terminal clk, and a data output terminal Q. The data of register A (RA) is driven by clock clk and output to register B (RB). RB collects data on the rising edge of clk, and the clock source is the same clock clk output by the system clock. Figure 7 There are several time periods as shown below.

[0102] TclkA: Line clock delay from the clock on the pad to the RA.

[0103] Tco: The delay from the clock input D to the clock output Q in RA.

[0104] Tdelay: The clock delay on the line from the Q end of RA to the D end of RB.

[0105] The time it takes for data to arrive at the RB can be obtained through the above parameters.

[0106] TclkB: Line clock delay from pad clock to RB.

[0107] Assume that the clock cycle is T_cycle and the setup time threshold is tsu: it indicates the shortest time that the data remains stable before the clock sampling edge comes.

[0108] The required data time required by the sampling clock can be obtained through tsu.

[0109] The setup time margin (setupslack) required for stable data acquisition can be obtained from the required data time, and the calculation formula shown in formula (1) can be obtained.

[0110] setup slack=T_cycle+TclkB-Tco-Tdelay-tsu–TclkA Formula (1)

[0111] Among them, when setup slack is 0, T_cycle is the minimum, and the data arrival time is equal to the required data time. If the frequency is further increased, the setup time margin is negative. That is, before the clock sampling edge arrives, the data stabilization time is less than tsu, resulting in received data errors. Therefore, when the clock frequency is higher than a certain value, the chip cannot work normally. In this embodiment, the clock can be detected by adjusting the delay duration of Tdelay, and judging whether there is a burr in the clock based on the sampling result.

[0112] In some embodiments, the second sampling unit includes a third register group, a second signal delay circuit, and a fourth register group connected in series in sequence. The structure of the third register group can refer to the first register group, the structure of the second signal delay circuit can refer to the first signal delay circuit, and the structure of the fourth register group can refer to the second register group.

[0113] Figure 8 It is a block diagram of a circuit for detecting clock glitches according to another embodiment of the present application.

[0114] See also Figure 8 The third register group (register group 3) is configured to receive the third test signal at the input end and output the second sub-sampling result to the second signal delay circuit at the output end.

[0115] The second signal delay circuit (eg, a high-frequency timing constraint path) is configured to delay the second sub-sampling result and output it to the fourth register group according to a preset delay value.

[0116] The fourth register group (register group 4) is configured to receive the second sub-sampling result at an input end and output the second sub-sampling result to the detection unit at an output end.

[0117] The third register group and the fourth register group receive clock signals at clock ends respectively.

[0118] In some embodiments, the first sampling unit includes a first register group (register group 1), a first signal delay circuit, and a second register group (register group 2) connected in series. The second sampling unit includes a third register group, a second signal delay circuit, and a fourth register group connected in series.

[0119] Specifically, the first register group is configured to receive the third test signal at an input terminal and output the first sub-sampling result to the first signal delay circuit at an output terminal. For example, the third test signal is a BIST pattern.

[0120] The first signal delay circuit is configured to delay the first sub-sampling result and output it to the second register group according to a selected delay value in the first group of delay values.

[0121] The second register group is configured to receive the first sub-sampling result at an input end and output the first sub-sampling result to the detection unit at an output end.

[0122] The first register group and the second register group receive clock signals at clock ends respectively.

[0123] See also Figure 8 The first signal delay circuit includes at least two parallel clock delay sub-circuits, and each of the at least two parallel clock delay sub-circuits has a different delay duration for the first sub-sampling result.

[0124] Accordingly, the above circuit may further include: a first delay selection unit. The first delay selection unit is coupled to the first signal delay circuit, and is used to receive configuration data, generate a configuration signal, and determine a target clock delay subcircuit from at least two parallel clock delay subcircuits based on the configuration signal, so as to use the test signal output by the target clock delay subcircuit as the delayed first test signal.

[0125] See also Figure 8 , four register groups are shown, each register group includes multiple flip-flops (FF). Each flip-flop (FF) has a data input terminal D, a clock input terminal CK, and a data output terminal Q. The input data at the D terminal is latched at the rising edge of the clock, and then the latched data is output to the Q terminal.

[0126] Figure 8 The first sampling unit includes a first signal delay circuit, which includes a plurality of parallel clock delay subcircuits, and each clock delay subcircuit can realize a specific delay duration for the third test information. For example, each clock delay subcircuit can be a delay line. The delay line can be implemented by a continuous inverter or other standard unit, and the goal is to increase the delay on the timing path. Among them, the delay duration of each of the different clock delay subcircuits can be a preset duration, such as the delay duration of the first delay line (Delay line1) is 50MHz, the delay duration of the second delay line (Delay line2) is 100MHz, the delay duration of the third delay line (Delay line3) is 150MHz, the delay duration of the fourth delay line (Delay line4) is 200MHz, the delay duration of the fifth delay line (Delay line5) is 300MHz, ... the delay duration of the Nth delay line (Delay line N) is 500MHz, etc.

[0127] Figure 8The second sampling unit includes a second signal delay circuit, which can be a connecting line between register group 3 and register group 4. When the circuit is laid out, register group 3 and register group 4 need to be connected by wires. The circuit between register group 3 and register group 4 will inevitably cause the test signal transmitted from the data output terminal Q of register group 3 to the data input terminal D of register group 4 to be delayed relative to the test signal received by the data input terminal D of register group 3. It should be noted that the second signal delay circuit can also be composed of an inverter, etc., but the delay duration of the second signal delay circuit for the third test signal needs to be different from the delay duration of the first signal delay circuit for the third test signal.

[0128] The first delay selection unit can select a target clock delay subcircuit from a plurality of parallel clock delay subcircuits and output an output test signal of the target clock delay subcircuit. For example, if the user wishes to delay the third test signal by 100 MHz, the second clock delay subcircuit can be selected. Specifically, the first delay selection unit can be a multiplexer (MUX for short). The multiplexer is respectively connected to a plurality of clock delay subcircuits and is configured to select a target clock delay subcircuit from a plurality of clock delay subcircuits.

[0129] Fig. 9 It is a schematic diagram of a delay selection unit shown in an embodiment of the present application.

[0130] See also Fig. 9 The multiplexer may be a multiple-choice selector. It should be noted that, in order to switch the path of the clock delay sub-circuit, at least one of a wiring switch, a look-up table (LUT) circuit, etc. may also be used.

[0131] For example, the implementation logic of the two-choice MUX can be shown as formula (2).

[0132]

[0133] Among them, Y is the signal output by MUX, S is the control signal, NOT S, A and B are the two signals input to the MUX. In addition, a buffer (such as a single NOT gate) can be connected to the output of the multiplexer to provide a positive logic output (logic "1", high) at one terminal and a complementary negative logic output (logic "0", low) at the buffer output.

[0134] In some embodiments, in order to reduce the chip area occupied by the first signal delay circuit and the first delay selection unit and improve the signal processing speed, it can be achieved by sharing the delay components in different clock delay sub-circuits. For example, in the previous embodiment, each clock delay sub-circuit has its own exclusive delay component, but only one of the clock delay sub-circuits will be used at the same time, and the remaining clock delay sub-circuits will be idle. By improving the circuits of the first signal delay circuit and the first delay selection unit and sharing at least some components of multiple clock delay sub-circuits, the chip area occupied by the first signal delay circuit and the first delay selection unit can be effectively reduced.

[0135] For example, the circuit for detecting clock glitches may further include: a second delay selection unit. The second delay selection unit is coupled to the first signal delay circuit and is used to receive configuration data and generate a configuration signal.

[0136] Accordingly, the first signal delay circuit includes: a plurality of delay groups, configured to output a delayed first test signal in response to a configuration signal, any of the plurality of delay groups including a first multiplexer and a delay device, the delay device being coupled to the first multiplexer of the corresponding delay group. In this way, a desired number of delay groups can be selected from the plurality of delay groups to form a signal delay circuit having a desired delay duration, effectively reducing the number of components (such as inverters) in an idle state. The delay device includes, but is not limited to, at least one of a delay line and a delay element. For example, the delay element includes an inverter or at least two inverters connected in series.

[0137] In some embodiments, multiple delay groups are cascaded, the delay device of each of the multiple delay groups is configured to receive a first input signal and output a delayed first input signal, and the first multiplexer of each of the multiple delay groups is configured to receive the delayed first input signal and the undelayed first input signal output by the delay device in the delay group.

[0138] Fig.10 It is a block diagram of a circuit for detecting clock glitches according to another embodiment of the present application.

[0139] See also Fig.10, the first signal delay circuit may include a configuration register, an encoder and a plurality of delay groups. Wherein, each delay group includes a paired inverter and a multiplexer. The input of the current-stage inverter is connected to the output of the multiplexer of the previous-stage delay group, and the input of the current-stage inverter is connected to the input of the multiplexer of the current-stage delay group. The control end of the multiplexer in each delay group is connected to a specific bit of the encoder, and the input of the encoder is connected to the output of the configuration register. For example, the second delay selection unit may include a configuration register and an encoder. Alternatively, the second delay selection unit may include a configuration register, an encoder and a plurality of multiplexers.

[0140] For example, the inverters in the eight delay groups can all achieve a delay effect of 50MHz. If the configuration information stored in the configuration register represents 50MHz, the data output by the encoder can be 10000000, 10000000, 01000000, 00100000, 00010000, etc. The multiplexer of the delay group corresponding to the bit of the encoder with a value of 1 selects the channel with the inverter to be turned on. The multiplexers of the delay groups corresponding to the remaining bits of the encoder select the channel without the inverter to be turned on. In this way, a signal delay circuit consisting of a single inverter is constructed, so that the delay duration of the first signal delay circuit is 50MHz.

[0141] For example, the inverters in the eight delay groups can each achieve a delay effect of 50MHz, 50MHz, 100MHz, 100MHz, 200MHz, 200MHz, 500MHz, and 500MHz. If the configuration information stored in the configuration register represents 1000MHz, the data output by the encoder can include multiple schemes, such as 00000011, 11001110, 00101110, 00011110, etc. The multiplexer of the delay group corresponding to the bit position of the encoder with the bit position of 1 selects the channel with the inverter to be turned on. The multiplexers of the delay groups corresponding to the remaining bits of the encoder respectively select the channel without the inverter to be turned on. In this way, a signal delay circuit composed of multiple inverters is constructed, so that the delay duration of the first signal delay circuit is 1000MHz.

[0142] For example, the inverters in the eight delay groups can each achieve a delay effect of 10MHz, 20MHz, 30MHz, 50MHz, 100MHz, 200MHz, 300MHz, and 500MHz. If the configuration information stored in the configuration register represents 280MHz, the data output by the encoder can include multiple schemes, such as 0011010, 11010100, etc. The multiplexer of the delay group corresponding to the bit position of the encoder with a bit position of 1 selects the channel with an inverter to be turned on. The multiplexers of the delay groups corresponding to the remaining bits of the encoder respectively select the channel without an inverter to be turned on. In this way, a signal delay circuit composed of multiple inverters is constructed, so that the delay duration of the first signal delay circuit is 280MHz.

[0143] For example, the inverters in the eight delay groups can each achieve a delay effect of 10MHz, 20MHz, 40MHz, 80MHz, 160MHz, 320MHz, 640MHz, and 1280MHz. If the configuration information stored in the configuration register represents 500MHz, the data output by the encoder can include multiple schemes, such as 01001100, etc. The multiplexer of the delay group corresponding to the bit position of the encoder with a bit position of 1 selects the channel with the inverter to be turned on. The multiplexers of the delay groups corresponding to the remaining bits of the encoder respectively select the channel without the inverter to be turned on. In this way, a signal delay circuit composed of multiple inverters is constructed, so that the delay duration of the first signal delay circuit is 500MHz.

[0144] In order to facilitate understanding that whether a clock includes glitches can be detected by adjusting the delay duration of the signal delay circuit, a timing diagram of a circuit for detecting clock glitches is exemplarily described below.

[0145] Fig.11 This is a signal timing diagram shown in an embodiment of the present application. Please also refer to Figure 7 and 11 , the clock CLK includes glitches. The first signal delay circuit is a path with a delay line (delay_line). The second signal delay circuit is a path without a delay line (delay_line). The test signal may be a BIST pattern (Pattern), which may include test patterns D0 to D5, etc., wherein each test pattern, such as test pattern D0, may include multiple bits of test data, for example, an 8-bit test signal 00000000, 11111111 or 11001100...etc.

[0146] Fig.11 The delay of the path with delay_line can be referred to Figure 7For details about Tdelay, refer to the following. Figure 7 The delay component of the path with delay_line includes the delay introduced by the first signal delay circuit, which is greater than the delay of the path without delay_line. The delay of the path without delay_line can be an unavoidable delay introduced by factors such as circuit layout, which can be small and even negligible in some cases.

[0147] Please also see Fig.10 and Fig.11 , Fig.11 Due to the presence of glitches in the clock, the presence of glitches causes the setup time (Set_up) of the test pattern D3 transmitted in the path with delay_line to be shorter than the setup time required by register group 2 to store the test pattern, and it is impossible to ensure that the test pattern D3 can be correctly stored in register group 2. This may cause the test pattern stored in register group 2 to be different from the actual test pattern D3.

[0148] In contrast, the glitch in the clock may not cause the setup time (Set_up) of the test pattern D3 transmitted in the path without delay_line to be less than the setup time required for register group 4 to store the test pattern. That is, the setup time requirement of register group 4 is met. Therefore, the test pattern D3 can be correctly stored in register group 4.

[0149] The above situation will cause the first sampling result based on the path with delay_line and the second sampling result based on the path without delay_line to be different. Therefore, by comparing whether the first sampling result and the second sampling result are the same, it can be detected whether the clock has a glitch.

[0150] It should be noted that the above only shows the situation of considering the setup time, and the sampling result may also be affected by, for example, the hold time. For example, although the setup time requirements of register group 2 and / or register group 4 are met, the hold time requirements of register group 2 and / or register group 4 are not met. This may also cause abnormal sampling results, and further lead to inconsistent comparison results.

[0151] In a specific embodiment, the circuit for detecting clock glitches includes two data paths (register group 1 (FF1) -> register group 2 (FF2) and register group 3 (FF3) -> register group 4 (FF4)), wherein the highest frequency on the FF1->FF2 path is delayed by delay_line, so that the frequency that meets the setup_time becomes lower (can be controlled to 50MHz, 100MHz to 500MHz, etc.), and the other path only adjusts the hold_time so that its setup_time can run higher (for example, 3GHz). Then, the test pattern (sampling data) is multi-bit (for example, 8 bits or 16 bits), from 8 bits 01010101->8 bits b10101010->8 bits 01010101, so that each bit performs a 0 to 1 cycle.

[0152] When the clock generated based on the crystal oscillator is correct (such as 24MHz or 26MHz), both data paths are captured correctly and the comparator will compare through.

[0153] When a glitch occurs, the glitch frequency is greater than 50M, and a sampling error may occur in the register group 3 capture in the data path FF1->FF2.

[0154] Because the capture of FF3->FF4 can support higher frequency, if it is correct. Therefore, as long as FF1->FF2 has a sampling error of 1 bit, and FF3->FF4 is sampled correctly, the comparator will fail. Or if FF1->FF2 has a sampling error of 1 bit, and FF3->FF4 also has a probabilistic sampling error, it will also be judged as a comparison failure, and the comparator will also fail.

[0155] Even if the glitch frequency is higher than 3G, the comparator will fail if both FF1->FF2 and FF3->FF4 fail. This makes it possible to detect that the clock includes glitches when the comparator fails.

[0156] The automatic detection design method provided in this embodiment can automatically detect whether abnormal glitches appear on the crystal oscillator clock signal.

[0157] In some embodiments, the detection unit includes a numerical comparator, which is coupled to the first sampling unit and the second sampling unit respectively and is configured to compare the first sampling result and the second sampling result to obtain the detection result.

[0158] Fig.12 is a circuit diagram of a detection unit according to an embodiment of the present application.

[0159] See also Fig.12, the first sampling result of the first sampling unit can be 01011101, and the second sampling result of the second sampling unit can be 00100110. By comparing the first sampling result and the second sampling result, it can be known that the first sampling result and the second sampling result are different. For example, an XOR logic operation can be performed on the first sampling result and the second sampling result. If the logic operation result is not 0, it can be determined that the first sampling result and the second sampling result are different.

[0160] In some embodiments, the detection unit includes an XOR logic operation unit and a counter, the XOR logic operation unit is coupled to the first sampling unit, the second sampling unit and the counter, respectively, and the detection unit is configured to perform statistics on bits with different values ​​in the first sampling result and the second sampling result to obtain a detection result.

[0161] Fig.13 is a circuit diagram of a detection unit shown in another embodiment of the present application.

[0162] See also Fig.13 After performing an XOR logic operation on the first sampling result and the second sampling result, the XOR logic operation result can be processed based on a counter or the like to obtain bits with different values ​​in the first sampling result and the second sampling result. Fig.12 If the first bit (bit1) to the fourth bit (bit4) are not 1, and the sixth bit (bit6) and the seventh bit (bit6) are not 1, it indicates that the first bit (bit1) to the fourth bit (bit4), the sixth bit (bit6), and the seventh bit (bit7) in the first sampling result and the second sampling result have different values. It can be further determined that the clock includes glitches.

[0163] Taking the adder counter as an example, a binary adder counter can be constructed using flip-flops. Specifically, a 3-bit binary asynchronous adder is composed of 3 falling edge triggered flip-flops T, the output signal of which is controlled by a pulse signal, and the counter starts counting from the state of Q2 Q1 Q0 = 000.

[0164] Under the trigger of the falling edge of the counting input pulse CP, the output Q0 of the trigger FFa will flip. 0 becomes 1 or 1 becomes 0. Since CP1 is taken from Q0, the output Q1 of the trigger FFb will flip under the trigger of the falling edge of Q0. Similarly, since CP2=Q1, the output Q2 of the trigger FFc will flip under the trigger of the falling edge of Q1. If the trigger T′ is triggered by the rising edge, an asynchronous binary addition counter can also be formed, but the carry pulse of each level of the trigger should be changed to the Qˉ terminal output. This is because when the output terminal Q of the low-order trigger changes from 1 to 0, the rising edge of the Qˉ terminal can just be used as a trigger pulse for the high-order.

[0165] Taking the subtraction counter as an example, if the triggers T′ are connected according to the binary subtraction rule, a binary subtraction counter can be obtained. According to the binary subtraction counting rule, if the low-order trigger is already 0, it should flip to 1 after inputting a subtraction counting pulse, and at the same time send a borrow signal to the high-order bit to flip the high-order bit.

[0166] Taking counting by software as an example, the operation: n&(n–1) can be repeatedly performed until n becomes 0. The operation: n&(n–1) is used to remove the last 1 of n, that is, the last 1 of n becomes 0. For example, let n = 11111, the calculation process is as follows: n = 11110, the count is 1; n = 11100, the count is 2; n = 11000, the count is 3; n = 10000, the count is 4; n = 00000, the count is 5.

[0167] It should be noted that Fig.12 and Fig.13 The logic operation circuits and combinations thereof shown in are only illustrative examples and are not limited here. It should be noted that logic operations include but are not limited to: "OR", "AND", "NOT", "NOR", "NAND", "XOR", etc. Logic operation circuits include but are not limited to: "OR operation circuit", "AND operation circuit", "NOT operation circuit", "NOR operation circuit", "NAND operation circuit", "XOR operation circuit", etc. These logic operation circuits may also be referred to as logic operation units. In order to compare whether two values ​​are the same, a combination of multiple logic operation circuits may be used to implement it. Accordingly, a combination of multiple logic operation circuits may be used to implement it, which is not limited here.

[0168] In some embodiments, the circuit for detecting clock glitches may also determine the position of the glitches in the clock based on the delay duration of the signal delay circuit.

[0169] Specifically, the circuit for detecting clock glitches may further include: a diagnosis module. The diagnosis module is connected to the detection unit and is configured to output a diagnosis signal corresponding to the configuration data in response to the detection result being abnormal.

[0170] refer to Fig.11It can be learned from the relevant content that the comparison will fail only when the clock glitch causes the sampling circuit with a larger delay duration to have a sampling abnormality. The clock glitch may not cause the sampling circuit with a smaller delay duration to have a sampling abnormality. Therefore, the location of the glitch in the clock can be judged based on the delay duration of the sampling circuit with abnormal sampling results. For example, when the glitch is closer to the previous falling edge of the clock, the sampling circuit with a larger delay duration may have a sampling abnormality. For example, when the glitch is closer to the next falling edge of the clock, the sampling circuit with a smaller delay duration may have a sampling abnormality.

[0171] Specifically, the approximate position of the burr on the clock can be determined by comparison.

[0172] For example, refer to Figure 8 , the sampling results of the channels where the delay line with 500MHz and the delay line with 400MHz are located are inconsistent, but the sampling results of the channels where the delay line with 400MHz and the delay line with 300MHz are located are consistent. It can be preliminarily determined that the glitch occurs near the falling edge of the clock.

[0173] For another example, a mapping relationship between the delay duration and the position of the glitch in the clock can be pre-built, so that when the sampling results between the two paths are different, the approximate position of the glitch in the clock can be obtained by looking up a table or the like.

[0174] In some embodiments, the circuit for detecting clock glitches may further perform exception processing when a clock glitch exists, so as to improve clock reliability.

[0175] Fig.14 It is a block diagram of a circuit for detecting clock glitches according to an embodiment of the present application.

[0176] See also Fig.14 The circuit for detecting clock glitches may include: an exception handling unit. The exception handling unit may include at least one of an interrupt signal generating module and a reset signal generating module.

[0177] The interrupt signal generating module is connected to the detection unit and is configured to output a clock signal interrupt signal when the detection result is abnormal.

[0178] The reset signal generating module is connected to the detection unit and is configured to output a clock signal reset signal when the detection result is abnormal.

[0179] For example, a reset signal is a signal output when a glitch is included for a short period of time (such as one or several clock cycles), and is used to improve the quality of the clock by resetting and restarting. If the clock generation circuit is affected by external interference and other factors, resulting in the output of glitches in a short period of time, in order to improve the quality of the clock signal, the reset signal generation module can output a reset signal to a functional circuit such as a central processing unit (CPU).

[0180] For example, an interrupt signal is a signal output when glitches continue to appear for a long time (such as clock cycles exceeding a specific number of counts). For example, after a reset process is performed based on a reset signal, the clock signal still has glitches or the number of glitches is large and does not meet the requirements. In order to improve the personal safety and property safety of users, the interrupt signal generation module can output an interrupt signal to a control unit such as a central processing unit (CPU) to control the clock generation unit to stop outputting the clock signal, or switch to a backup clock signal, etc.

[0181] In some embodiments, the detection unit includes a first count value comparator, which is configured to compare a count value (such as a count of a clock cycle with a glitch, etc.) with a first preset count threshold, and / or compare the count value with a second preset count threshold, so as to detect an abnormality of the clock signal, wherein the count value is a difference between the first count value and the second count value, and the first preset count threshold and the second preset count threshold are different. For example, the first preset count threshold and the second preset count threshold can be set according to expert experience, usage effect, etc.

[0182] The following is an exemplary description of a comparator having a numerical value comparison function.

[0183] For ease of understanding, a 1-bit parallel value comparator is first described as an example. Assume that two 1-bit binary numbers are A and i , B i , then the comparison result L A>B , L A<B , L A＝B The single-digit value ratio truth table is shown in Table 1.

[0184] Table 1

[0185]

[0186] The three output functions of the 1-bit parallel comparator can be shown as equations (3) to (5).

[0187]

[0188]

[0189]

[0190] Based on the above three output functions, a comparator circuit can be designed.

[0191] Reference Fig.15 As shown, Ci represents the comparator circuit, which can include a combination of multiple logic operation circuits. For example, Fig.15 in 1 can be represented by a high level. & represents bitwise AND, and the bitwise operation process includes: converting the character into binary representation and then performing bitwise operations.

[0192] For a comparator of multi-bit values, the principle of comparing the higher bits first can be adopted. For example, for two four-bit value comparators A and B, A = A4A3A2A1, B = B4B3B2B1. If A4 > B4, then A > B. If A4 < B4, then A < B. When the higher bits are equal, the next higher bits are compared according to the same principle, and so on until the comparison of the lowest bit is completed.

[0193] In addition, in addition to comparing these four bits, when these four bits are equal, the comparison result input of the lower bits can also be compared to enable the comparison of more bits. To achieve the above functions, this embodiment also provides a truth table for comparing four-bit values, as shown in Table 2.

[0194] Table 2

[0195]

[0196] Based on Table 2, output functions as shown in Equations (6) to (8) can be obtained. In Table 2, × indicates that no calculation is required. G4 represents that the value of the fourth bit of value A is greater than the value of the fourth bit of value B, and the meanings of G3, G2, and G1 are similar. L4 represents that the value of the fourth bit of value A is less than the value of the fourth bit of value B, and the meanings of L3, L2, and L1 are similar. E4 represents that the value of the fourth bit of value A is equal to the value of the fourth bit of value B, and the meanings of E3, E2, and E1 are similar.

[0197] L A>B = G4 + E4G3 + E4E3E2 + E4E3E2G1 + E4E3E2E1l A>B Equation (6)

[0198] L A<B = L4 + E4L3 + E4E3L2 + E4E3E2L1 + E4E3E2E1l A<B Equation (7)

[0199] L A＝B = E4E3E2E1l A＝B Equation (8)

[0200] where, l A>B represents that the lower four-bit value of data A is greater than the lower four-bit value of data B, lA<B Indicates that the lower four digits of data A are less than the lower four digits of data B. A＝B Indicates that the lower four digits of data A are equal to the lower four digits of data B.

[0201] The circuit diagram of the multi-bit comparator is shown in Fig.16 Wherein, C1 to C4 each represent a combination of multiple logic operation circuits, such as Fig.15 Middle C i The logic operation circuit shown.

[0202] It should be noted that Fig.15 and Fig.16 The combination of logic operation circuits shown in is only an illustrative example and is not limited here. It should be noted that logical operations include but are not limited to: "OR", "AND", "NOT", "NOR", "NAND", "XOR", etc. Logic operation circuits include but are not limited to: "OR operation circuit", "AND operation circuit", "NOT operation circuit", "NOR operation circuit", "NAND operation circuit", "XOR operation circuit", etc. These logic operation circuits may also be referred to as logic operation units. In order to compare the size relationship between two numerical values, a combination of multiple logic operation circuits may be used to achieve this, and accordingly, a combination of multiple logic operation circuits may be used to achieve this, which is not limited here.

[0203] Taking the comparison of values ​​by software as an example, the comparison functions of the database include but are not limited to the functions shown below. BETWEEN AND: Determine whether it is between two values ​​(including the boundary), and the output results include not between the two values ​​(NOT) and between the two values ​​(BETWEEN). IN(x1, x2, x3, ...): Determine whether the input value is equal to one in the value list, and the output results can be not in the list (NOT) or in the list (IN). CASE WHEN: Output a certain result under certain conditions.

[0204] It should be noted that the first preset counting threshold and the second preset counting threshold may each include multiple levels: a low-quality threshold level and an abnormal threshold level, etc. Among them, when the clock frequency of the first clock is greater than the abnormal threshold level and less than the low-quality threshold level, a reset signal can be output. The quality of the clock is improved by the reset signal. It should be noted that the above conditions for outputting the reset signal are only exemplary and cannot be understood as limitations on the present application. Specifically, the reset signal will reset the main circuit and clear the key information. When the clock frequency of the first clock is greater than the abnormal threshold level and greater than the low-quality threshold level, an interrupt signal can be output.

[0205] It should be noted that the above conditions for outputting an interrupt signal are only exemplary and cannot be understood as a limitation of the present application. The potential risks brought to users by abnormal clocks are reduced by interrupt signals. Specifically, an interrupt signal can be sent to a central processing unit (CPU) so that the CPU can respond to the interrupt signal and perform corresponding processing according to the interrupt type, such as destroying important information, restarting, shutting down the first clock generating unit, etc. In addition, in addition to reset, interrupt processing, etc., other processing methods can also be introduced: such as changing the clock generating unit channel, alarming, etc., which are not limited here.

[0206] In some embodiments, a backup clock generating unit for generating a backup clock signal may be further provided in the circuit for detecting clock glitches.

[0207] The frequency of the reference clock signal (hereinafter referred to as the second clock signal) generated by the standby clock generating unit may be the same as or different from the frequency of the clock signal. For example, a crystal oscillator with the same oscillation frequency as that in the first clock generating unit may be set in the second clock generating unit, such as the second clock generating unit may include a crystal oscillator, a crystal oscillator control chip and a capacitor. For example, an oscillation circuit may be set in the second clock generating unit to reduce the cost of generating the second clock signal.

[0208] The circuit for detecting clock glitches provided in the present application can be applied to multiple fields such as precise three-dimensional (3D) modeling, detection, home improvement, unmanned driving, and drones.

[0209] The circuit for detecting clock glitches provided in the present application can automatically detect whether glitches (such as high-frequency glitches) appear in the clock signal output by the clock generating unit, and after detection, send out interrupt and reset signals to notify the system to protect and dispose of the main control chip.

[0210] Another aspect of the present application also provides a clock circuit.

[0211] The clock circuit may include a first clock generating unit and a circuit for detecting clock glitches.

[0212] The first clock generating unit is configured to output a first clock signal. The circuit for detecting clock glitches is shown in the above related content, which is connected to the first clock generating unit and is configured to detect the first clock signal. For example, the first clock generating unit may include a quartz crystal oscillator and other devices.

[0213] In some embodiments, the circuit for detecting clock glitch may further include a second clock generating unit and a second multiplexer.

[0214] The second clock generating unit is configured to output a backup clock signal.

[0215] The second multiplexer is connected to the circuit for detecting clock glitches, and is configured to output the clock signal when the clock of the clock signal is normal, or to output the backup clock signal when the clock of the clock signal has glitches.

[0216] The second multiplexer may be a two-to-one selector. It should be noted that, in order to achieve the change of the path of the clock signal, at least one of a wiring switch, a look-up table (LUT) circuit, etc. may also be used.

[0217] The second multiplexer provided in this embodiment is configured to switch the functional circuit clock to the reference clock when it is determined that the current clock signal has glitches, so as to prevent the functional circuit from operating on the clock with glitches. When the clock signal is normal, the path corresponding to the first clock generating unit is used. This ensures that the function based on the clock signal can be realized, thereby improving the personal safety and property safety of users.

[0218] Another aspect of the present application also provides a chip. The chip may include a clock circuit as described above, and a functional circuit that implements a specific function based on a clock signal output by the clock circuit. The functional circuit includes but is not limited to: a processor, a transmitter, a receiver, etc.

[0219] In a possible implementation, another aspect of the present application further provides a board, which includes a storage device, an interface device, a control device and the above-mentioned chip. The chip is connected to the storage device, the control device and the interface device respectively. The storage device is configured to store data. The interface device is configured to realize data transmission between the artificial intelligence chip and the external device. The control device is configured to monitor the status of the artificial intelligence chip.

[0220] Another aspect of the present application also provides a method for detecting clock glitches.

[0221] Fig.17 It is a flowchart of a method for detecting clock glitches according to an embodiment of the present application.

[0222] See also Fig.17 , the method for detecting clock glitches may include operations S1710 to S1730.

[0223] In operation S1710 , a first test signal is sampled based on a clock signal to obtain a first sampling result. Specifically, reference may be made to the related operations performed by the first sampling unit 410 .

[0224] In operation S1720 , the second test signal is sampled based on the clock signal to obtain a second sampling result. Specifically, reference may be made to the related operations performed by the second sampling unit 420 .

[0225] In operation S1730 , the first sampling result and the second sampling result are compared to obtain a detection result. Specifically, reference may be made to the related operations performed by the detection unit 430 .

[0226] The first test signal and the second test signal are generated based on the third test signal, and a delay duration of the first test signal with respect to the third test signal is different from a delay duration of the second test signal with respect to the third test signal.

[0227] In some embodiments, the delay duration of the first test signal relative to the third test signal can be adjusted, and / or the delay duration of the second test signal relative to the third test signal can be adjusted.

[0228] In some embodiments, the test pattern may be sampled on a clock basis through a register set.

[0229] In some embodiments, the test signal may be delayed by a signal delay circuit.

[0230] In some embodiments, in response to the detection result being abnormal, a diagnosis signal corresponding to the configuration data is output.

[0231] In some embodiments, the delay duration of the test signal generated by the signal delay circuit can be adjusted by configuring data.

[0232] Another aspect of the present application also provides a device for detecting clock glitches.

[0233] Fig.18 It is a schematic diagram of the structure of a device for detecting clock glitches according to an embodiment of the present application.

[0234] See also Fig.18 The device 1800 for detecting clock glitches may include a first sampling module 1810 , a second sampling module 1820 and a result comparison module 1830 .

[0235] The first sampling module 1810 is used to sample the first test signal based on the clock signal to obtain a first sampling result.

[0236] The second sampling module 1820 is used to sample the second test signal based on the clock signal to obtain a second sampling result.

[0237] The result comparison module 1830 is used to compare the first sampling result and the second sampling result to obtain a detection result.

[0238] The first test signal and the second test signal are generated based on the third test signal, and a delay duration of the first test signal with respect to the third test signal is different from a delay duration of the second test signal with respect to the third test signal.

[0239] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated again here.

[0240] Another aspect of the present application further provides a radar. The radar may include the chip or board as described above.

[0241] Fig.19 It is a schematic diagram of the structure of a radar shown in an embodiment of the present application.

[0242] See also Fig.19 , the radar 1900 may include a chip or board as shown above, and the chip and / or board may include a clock circuit as described above. Specifically, the clock circuit may include a circuit for detecting clock glitches as shown above. The clock circuit may be provided on a board 1910, and a plurality of chips, such as a central control chip, may be provided on the board 1910. The board 1910 may be provided in a housing 1920.

[0243] The radar may be a laser radar, a millimeter wave radar, an ultrasonic radar, etc. The radar may be a scanning radar or a non-scanning radar.

[0244] Fig. 20 It is a schematic diagram of the structure of an electronic device shown in an embodiment of the present application.

[0245] See also Fig. 20 The electronic device 2000 may include a memory 2010 and a processor 2020. In addition, the electronic device 2000 may be provided with at least one of a clock generating circuit, a clock glitch detecting circuit, or a radar.

[0246] The processor 2020 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

[0247] The memory 2010 may include various types of storage units, such as system memory, read-only memory (ROM) and permanent storage. Among them, ROM can store static data or instructions required by the processor 2020 or other modules of the computer. The permanent storage device may be a readable and writable storage device. The permanent storage device may be a non-volatile storage device that does not lose the stored instructions and data even after the computer is powered off. In some embodiments, the permanent storage device uses a large-capacity storage device (such as a magnetic or optical disk, flash memory) as a permanent storage device. In some other embodiments, the permanent storage device may be a removable storage device (such as a floppy disk, an optical drive). The system memory may be a readable and writable storage device or a volatile readable and writable storage device, such as a dynamic random access memory. The system memory may store some or all instructions and data required by the processor at run time. In addition, the memory 2010 may include any combination of computer-readable storage media, including various types of semiconductor memory chips (such as DRAM, SRAM, SDRAM, flash memory, programmable read-only memory), and disks and / or optical disks may also be used. In some embodiments, the memory 2010 may include a readable and / or writable removable storage device, such as a laser disc (CD), a read-only digital versatile disc (such as a DVD-ROM, a double-layer DVD-ROM), a read-only Blu-ray disc, an ultra-density optical disc, a flash memory card (such as an SD card, a mini SD card, a Micro-SD card, etc.), a magnetic floppy disk, etc. The computer-readable storage medium does not include carrier waves and transient electronic signals transmitted wirelessly or wired.

[0248] The memory 2010 stores executable codes, and when the executable codes are processed by the processor 2020 , the processor 2020 can execute part or all of the methods described above.

[0249] In addition, the method according to the present application may also be implemented as a computer program or a computer program product, which includes computer program code instructions for executing some or all of the steps in the above method of the present application.

[0250] Alternatively, the present application can also be implemented as a computer-readable storage medium (or non-transitory machine-readable storage medium or machine-readable storage medium) on which executable code (or computer program or computer instruction code) is stored. When the executable code (or computer program or computer instruction code) is executed by a processor of an electronic device (or server, etc.), the processor executes part or all of the steps of the above-mentioned method according to the present application.

[0251] The embodiments of the present application have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A circuit for detecting clock glitches, characterized in that: include: A first sampling unit is configured to sample the first test signal based on the clock signal to obtain a first sampling result; A second sampling unit is configured to sample a second test signal based on the clock signal to obtain a second sampling result; a detection unit, coupled to the first sampling unit and the second sampling unit respectively, and configured to compare the first sampling result and the second sampling result to obtain a detection result; The delay duration of the first test signal relative to the third test signal is different from the delay duration of the second test signal relative to the third test signal; The first sampling unit includes a first signal delay circuit, the first signal delay circuit includes at least two parallel clock delay sub-circuits, and the at least two parallel clock delay sub-circuits are respectively used to delay the third test signal to obtain the first test signal with a specific delay duration relative to the third test signal; The second sampling unit comprises a second signal delay circuit, and the second signal delay circuit is used to delay the third test signal to obtain the second test signal having a delay duration relative to the third test signal; The circuit further comprises: a first delay selection unit, coupled to the first signal delay circuit, configured to receive configuration data, generate a configuration signal, and determine a target clock delay subcircuit from the at least two parallel clock delay subcircuits based on the configuration signal, so as to use a test signal output by the target clock delay subcircuit as the first test signal; The delay duration of the first test signal relative to the third test signal is the delay duration introduced by the target clock delay subcircuit, and the delay duration of the second test signal relative to the third test signal is the delay duration introduced by the circuit layout of the second sampling unit.

2. The circuit according to claim 1, characterized in that The delay duration of the first test signal relative to the third test signal can be adjusted, and / or the delay duration of the second test signal relative to the third test signal can be adjusted.

3. The circuit according to claim 2, characterized in that The first signal delay circuit is configured to delay and output the first test signal according to a first set of delay values ​​to sample the delayed first test signal; and / or The second signal delay circuit is configured to delay and output the second test signal to sample the delayed second test signal.

4. The circuit according to claim 3, characterized in that: The first sampling unit comprises a first register group, a first signal delay circuit and a second register group connected in series in sequence; and / or The second sampling unit includes a third register group, a second signal delay circuit and a fourth register group which are sequentially connected in series.

5. The circuit according to claim 4, characterized in that: The first register group is configured to receive the third test signal at an input terminal and output a first sub-sampling result to the first signal delay circuit at an output terminal; The first signal delay circuit is configured to delay and output the first sub-sampling result to the second register group according to a selected delay value in a first group of delay values; The second register group is configured to receive the first sub-sampling result at an input end and output the first sampling result to the detection unit at an output end; The first register group and the second register group receive the clock signal at the clock end respectively; and / or The third register group is configured to receive the third test signal at an input terminal and output the second sub-sampling result to the second signal delay circuit at an output terminal; The second signal delay circuit is configured to delay the second sub-sampling result and output it to the fourth register group according to a preset delay value; The fourth register group is configured to receive the second sub-sampling result at an input end and output the second sub-sampling result to the detection unit at an output end; The third register group and the fourth register group receive the clock signal at clock ends respectively.

6. The circuit according to claim 5, characterized in that The at least two parallel clock delay sub-circuits each delay the first sub-sampling result for a different duration.

7. The circuit according to claim 5, characterized in that Also includes: A second delay selection unit, coupled to the first signal delay circuit, configured to receive configuration data and generate a configuration signal; The first signal delay circuit comprises: A plurality of delay groups are configured to output delayed first test signals in response to the configuration signal, wherein any delay group of the plurality of delay groups comprises a first multiplexer and a delay device, wherein the delay device is coupled to the first multiplexer of the corresponding delay group.

8. The circuit according to claim 7, characterized in that The multiple delay groups are cascaded, the delay device of each of the multiple delay groups is configured to receive a first input signal and output a delayed first input signal, and the first multiplexer of each of the multiple delay groups is configured to receive the delayed first input signal output by the delay device in the delay group and the first input signal.

9. The circuit according to claim 6 or 7, characterized in that Also includes: The diagnosis module is connected to the detection unit and is configured to output a diagnosis signal corresponding to the configuration data in response to the detection result being abnormal.

10. The circuit according to any one of claims 1 to 8, characterized in that: The detection unit includes a numerical comparator, which is coupled to the first sampling unit and the second sampling unit respectively and is configured to compare the first sampling result and the second sampling result to obtain the detection result; or The detection unit includes an exclusive OR logic operation unit and a counter, wherein the exclusive OR logic operation unit is coupled to the first sampling unit, the second sampling unit and the counter respectively, and the detection unit is configured to perform statistics on bits with different values ​​in the first sampling result and the second sampling result to obtain the detection result.

11. The circuit according to any one of claims 1 to 8, characterized in that: Also includes: The exception handling unit includes at least one of the following: an interrupt signal generating module, configured to output a clock signal interrupt signal when the detection result is abnormal; The reset signal generating module is configured to output a clock signal reset signal when the detection result is abnormal.

12. A clock circuit, characterized in that: include: A first clock generating unit, configured to output the clock signal; The circuit for detecting clock glitches according to any one of claims 1 to 11 is connected to the first clock generating unit and is configured to detect the clock signal.

13. The clock circuit according to claim 12, characterized in that: Also includes: A second clock generating unit is configured to output a backup clock signal; The second multiplexer is connected to the circuit for detecting clock glitches and is configured to output the clock signal when the clock of the clock signal is normal, or to output the backup clock signal when the clock of the clock signal is abnormal.

14. A chip, characterized in that: include: A circuit for detecting clock glitches according to any one of claims 1 to 11, or a clock circuit according to claim 12 or 13; The functional circuit is configured to implement a specific function based on the clock signal or the backup clock signal. 15 . A radar, comprising the circuit for detecting clock glitches according to claim 1 , or the clock circuit according to claim 12 or 13 , or the chip according to claim 14 .

16. A method for detecting clock glitches, characterized in that: include: Sampling the first test signal based on the clock signal to obtain a first sampling result; Sampling a second test signal based on the clock signal to obtain a second sampling result; Comparing the first sampling result and the second sampling result to obtain a detection result; The first test signal and the second test signal are generated based on a third test signal, and a delay duration of the first test signal with respect to the third test signal is different from a delay duration of the second test signal with respect to the third test signal; The first sampling result is obtained by sampling by a first sampling unit, the first sampling unit includes a first signal delay circuit, the first signal delay circuit includes at least two parallel clock delay sub-circuits, the at least two parallel clock delay sub-circuits are respectively used to delay the third test signal to obtain the first test signal with a specific delay duration relative to the third test signal; The second sampling result is obtained by sampling by a second sampling unit, and the second sampling unit includes a second signal delay circuit, and the second signal delay circuit is used to delay the third test signal to obtain the second test signal with a delay duration relative to the third test signal; The method further comprises: receiving configuration data, generating a configuration signal, and determining a target clock delay subcircuit from the at least two parallel clock delay subcircuits based on the configuration signal, so as to use a test signal output by the target clock delay subcircuit as the first test signal; The delay duration of the first test signal relative to the third test signal is the delay duration introduced by the target clock delay subcircuit, and the delay duration of the second test signal relative to the third test signal is the delay duration introduced by the circuit layout of the second sampling unit.

17. An electronic device, characterized in that: include: processor; as well as A memory having executable codes stored thereon, which, when executed by the processor, causes the processor to perform the method according to claim 16.

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