Long press switch circuit

Abstract

The present application relates to a long-press switch circuit, which controls the long-press and short-press level control of the off state and the on state respectively through two on-off modules composed of a NAND gate and a plurality of TG gates, so that long-press power-on when powering on and long-press power-on when powering off can be realized. The on-off states of the two on-off modules are opposite, so there is no interference between the power-on and power-off processes, thereby improving the stability of the switch. On the other hand, the charging time of the first capacitor and the second capacitor can also be used to set the long-press power-on or power-off time.

Description

Technical Field

[0001] The present application relates to the field of power electronics technology, and in particular to a long-press switch circuit. Background Art

[0002] At present, the power switches of electrical equipment on the market are usually traditional mechanical self-locking switches, which have the advantages of simple design, reliable operation, and zero standby power consumption. However, since they are generally connected in series on the power bus and the current is large, the size is generally large. Moreover, when a short circuit occurs in the load, this type of switch usually cannot automatically cut off the power supply and cannot effectively protect the circuit. In addition, there are fewer styles of such switches. Common styles such as rocker switches, toggle switches, and button switches are difficult to meet the appearance requirements of portable electronic devices. Therefore, many portable electronic devices use electronic switch solutions inside. It has the advantages of novel appearance and compact size.

[0003] Solutions using discrete components. Such solutions usually work unstably. When users make irregular key operations, it is easy to cause logical confusion and fail to work properly. Moreover, such solutions usually cannot realize long press to power on and long press to power off at the same time. In addition, if the user keeps pressing the button, such solutions usually turn on and off repeatedly. Summary of the invention

[0004] Based on this, it is necessary to provide a long-press switch circuit that solves the problem of repeated startup in order to solve the above technical problems.

[0005] A long-press switch circuit, the circuit comprising:

[0006] A first on-off module, a second on-off module, a switch input module and an output module;

[0007] The first on-off module, the second on-off module, the switch input module and the output module;

[0008] The input ends of the first on-off module and the second on-off module are connected to a power supply, the input ends of the first on-off module and the second on-off module are symmetrical, the first on-off module is used for switch control in the off state, and the second on-off module is used for switch control in the on state; the first on-off module and the second on-off module include a plurality of NAND gates and a plurality of TG gates;

[0009] The switch input module is connected to the power supply through a key switch; the key switch is turned on when in a pressed state; the output module includes: a switch signal output terminal;

[0010] When the key switch is short-pressed in the shutdown state, the first capacitor in the switch input module is charged, and the positive electrode of the charged first capacitor outputs a low level, and the low level is input into the first on-off module and the output module, so that the switch signal output end is in a high impedance state; when the switch signal output end is in a high impedance state, it corresponds to the shutdown state;

[0011] When the key switch is long pressed in the shutdown state, the first capacitor in the switch input module is charged, and the positive electrode of the charged first capacitor outputs a high level, which is input into the first on-off module and the output module, so that the power-on / off signal output terminal is at a low level; when the power-on / off signal output terminal is at a low level, it corresponds to the power-on state;

[0012] When the key switch is short-pressed in the power-on state, the second capacitor in the switch input module is charged, and the positive electrode of the second capacitor outputs a low level, and the low level is input into the second on-off module and the output module, so that the power-on / off signal output terminal is at a low level; when the power-on / off signal output terminal is at a low level, it corresponds to the power-on state;

[0013] When the button switch is long pressed in the power-on state, the second capacitor in the switch input module is charged, and the positive electrode of the second capacitor outputs a high level, and the high level is input into the second on-off module and the output module to make the power-on / off signal output end in a high-impedance state; when the power-on / off signal output end is in a high-impedance state, it corresponds to the power-off state.

[0014] In one embodiment, the input ends of the first on-off module and the second on-off module both include: a first input end, a second input end and a third input end; the output ends of the first on-off module and the second on-off module both include: a first output end and a second output end; the level states of the first input end of the first on-off module and the first input end of the second on-off module are opposite, and the second input end of the first on-off module is connected to the second input end of the second on-off module; the third input end of the first on-off module is connected to the positive electrode of the first capacitor; and the third input end of the second on-off module is connected to a power supply.

[0015] In one embodiment, the first on-off module includes: a third capacitor, a first inverter, a first TG gate, a first NAND gate, a second TG gate, a second NAND gate, a third TG gate, a third NAND gate, a fourth NAND gate, a fourth TG gate and a second inverter; one end of the third capacitor is the first input end of the first on-off module, and the other end is grounded; the input end of the first inverter is connected to the ground end of the third capacitor, and the output end is respectively connected to the first input end of the first NAND gate and the first input end of the fourth NAND gate; the input end of the first TG gate is the second input end of the first on-off module, and the output end is connected to the second input end of the first NAND gate and the input end of the second TG gate. The output end of the first NAND gate is connected to the first input end of the second NAND gate and the input end of the third TG gate respectively, the output end of the second NAND gate is connected to the output end of the second TG gate, the output end of the third TG gate is connected to the first input end of the third NAND gate, the output end of the third NAND gate is connected to the second input end of the fourth NAND gate, the output end of the fourth NAND gate is connected to the output end of the fourth TG gate, the input end of the second inverter is the third input end, the output ends are respectively connected to the second input end of the second NAND gate and the second input end of the fourth NAND gate, and the input end of the fourth TG gate is connected to the output end of the third TG gate.

[0016] In one embodiment, the second on-off module includes: a fourth capacitor, a third inverter, a fifth TG gate, a fifth NAND gate, a sixth TG gate, a sixth NAND gate, a seventh TG gate, a seventh NAND gate, an eighth NAND gate and an eighth TG gate; one end of the fourth capacitor is the first input end of the second on-off module, and the other end is grounded; the input end of the third inverter is connected to the ground end of the fourth capacitor, and the output end is respectively connected to the first input end of the sixth NAND gate and the first input end of the seventh NAND gate; the input end of the fifth TG gate is the second input end of the second on-off module, and the output end is connected to the second input end of the fifth NAND gate and the input end of the sixth TG gate; the first input end of the fifth NAND gate is the first input end of the second on-off module, and the output end is respectively connected to the first input end of the sixth NAND gate and the input end of the seventh TG gate; the output end of the sixth NAND gate is connected to the output end of the sixth TG gate; the output end of the seventh TG gate is connected to the first input end of the seventh NAND gate; the output end of the seventh NAND gate is connected to the second input end of the eighth NAND gate; and the output end of the eighth NAND gate is connected to the output end of the eighth TG gate.

[0017] In one embodiment, the output end of the third TG gate is the first output end of the first on-off module, and the output end of the third NAND gate is the second output end of the first on-off module.

[0018] In one embodiment, the output end of the seventh TG gate is the first output end of the second on-off module, and the output end of the seventh NAND gate is the second output end of the second on-off module.

[0019] In one embodiment, the switch input module includes: a first resistor, a second resistor, a third resistor, a first diode, a second diode, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor, a third diode, a fourth diode, a fourth inverter, a fifth inverter, a first transistor, a ninth TG gate, a sixth resistor, a sixth inverter, a ninth NAND gate, a seventh inverter, and an eighth inverter; the first resistor, the second resistor and the third resistor are connected in series, and the fourth resistor and the fifth resistor are connected in series, and are all connected in parallel to the ground, and the other ends are all connected to the input end of the switch input module, the first diode is connected in series with the first capacitor, and the positive electrode of the first diode is connected to the second resistor and the third resistor, the second diode is connected in series with the second capacitor, and the positive electrode of the second diode is connected to the fourth resistor and the fifth resistor, the positive electrode of the first diode is also connected to the positive electrode of the fourth diode, the negative electrode of the fourth diode is connected to the drain of the first transistor, the source of the first transistor is grounded, the gate of the first transistor is connected to one end of the sixth resistor, and the other end of the sixth resistor is connected to the input end of the switch input module. The negative complementary signal port of the ninth TG gate and the output end of the sixth inverter are connected, the input end of the six inverters is connected to the positive complementary signal port of the ninth TG gate, the input end of the six inverters is also connected to the output end of the ninth NAND gate, the input end of the ninth NAND gate is respectively connected to the first on-off module and the output module, the input end of the ninth TG gate is connected to the cathode of the fourth diode, and the output end is connected to the second on-off module, the fourth inverter and the fifth inverter are connected in series, the output signal of the fourth inverter is used as the positive complementary signal of the TG gate in the first on-off module, the signal output by the fifth inverter is the negative complementary signal of the TG gate in the first on-off module, the anode of the third diode is connected to the anode of the third diode, the cathode of the third diode is connected to the second on-off module, the cathode of the second diode is also connected to the input end of the seventh inverter, the seventh inverter and the eighth inverter are connected in series, the output signal of the seventh inverter is used as the positive complementary signal of the TG gate in the second on-off module, and the signal output by the eighth inverter is the negative complementary signal of the TG gate in the second on-off module.

[0020] In one embodiment, the output module includes: a tenth NAND gate, an OR gate, a second transistor, a third transistor, a fourth transistor, a ninth inverter, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor and an eleventh resistor; the first input end of the tenth NAND gate is connected to the second on-off module, the second input end of the tenth NAND gate is connected to the cathode of the second diode, the output end of the tenth NAND gate is connected to one end of the seventh resistor, the other end connected to the seventh resistor is connected to the gate of the second transistor, the source of the second transistor is grounded, the first input end of the OR gate is connected to the first on-off module, the second input end of the OR gate is connected to the output end of the ninth inverter, the input end of the ninth inverter is respectively connected to one end of the eighth resistor and the drain of the third transistor, the other end of the eighth resistor is connected to the power supply, the source of the third transistor is grounded, the gate is connected to one end of the ninth resistor, the ninth resistor and the tenth resistor are connected in series to ground, the output end of the OR gate is connected to one end of the eleventh resistor, the other end of the eleventh resistor is connected to the gate of the fourth transistor, and the source of the fourth transistor is grounded.

[0021] In one of the embodiments, the output module further includes: an open-drain output terminal, and the open-drain output terminal outputs the level of the drain of the second transistor.

[0022] In one embodiment, the output module further includes: a shutdown signal output terminal, and the shutdown signal output terminal outputs the level of the other end of the ninth resistor.

[0023] The above-mentioned long-press switch circuit is based on the basic logic gate circuit design, with a small number of discrete components. It has the advantages of low price, reliable operation, extremely low power consumption, small size, simple use, and wide operating voltage range. The circuit only outputs the control level, not the system current, so it is flexible to use and has a wide range of applications. The circuit has a short-circuit protection function. When the load is abnormally short-circuited, the circuit can quickly turn off the power until the short circuit is removed. The circuit can simply and flexibly adjust the long-press time for power on and off. The circuit has an INT output pin, which can synchronously output the state of the button to the microprocessor for detection when the power is on. The circuit has a Kill input pin, which allows the microprocessor to save data before shutting down. The circuit has a button release detection mechanism. Only when the button is long pressed again after it is released, the switch state will be flipped to avoid the user pressing it all the time and repeatedly turning it on and off. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic diagram of a long-press switch circuit in an embodiment;

[0025] Figure 2 A power-on instant state diagram in an embodiment;

[0026] Figure 3 A diagram of a power-on stable state in one embodiment;

[0027] Figure 4 This is a diagram of a short-press button state in a shutdown state in an embodiment;

[0028] Figure 5 This is a diagram of a long press power-on state in an embodiment;

[0029] Figure 6 This is a state diagram after the power button is released in an embodiment;

[0030] Figure 7 A state diagram of a button being pressed at the moment of operation in one embodiment;

[0031] Figure 8 A circuit state diagram of a key being continuously pressed after operation in one embodiment;

[0032] Fig. 9 This is a diagram of a button release state after powering off in one embodiment. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0034] In one embodiment, if Figure 1As shown, a schematic diagram of a long-press switch circuit is provided, including: a first on-off module, a second on-off module, a switch input module and an output module; the input ends of the first on-off module and the second on-off module are connected to the power supply, the input ends of the first on-off module and the second on-off module are symmetrical, the first on-off module is used for switch control in the off state, and the second on-off module is used for switch control in the on state; the first on-off module and the second on-off module include a plurality of NAND gates and a plurality of TG gates; the switch input module is connected to the power supply through a key switch; the key switch is turned on when in a pressed state; the output module includes: a switch signal output end; when the key switch is short-pressed in the off state, the first capacitor in the switch input module is charged, and the positive electrode of the charged first capacitor outputs a low level, and the low level is input to the first on-off module and the output module, so that the switch signal output end is in a high impedance state; when the switch signal output end is in a high impedance state, the corresponding off state ; When the key switch is long pressed in the shutdown state, the first capacitor in the switch input module is charged, and the positive electrode of the charged first capacitor outputs a high level, which is input into the first on-off module and the output module, so that the power-on / off signal output end is at a low level; when the power-on / off signal output end is at a low level, it corresponds to the power-on state; when the key switch is short pressed in the power-on state, the second capacitor in the switch input module is charged, and the positive electrode of the second capacitor outputs a low level, which is input into the second on-off module and the output module, so that the power-on / off signal output end is at a low level; when the power-on / off signal output end is at a low level, it corresponds to the power-on state; when the key switch is long pressed in the power-on state, the second capacitor in the switch input module is charged, and the positive electrode of the second capacitor outputs a high level, which is input into the second on-off module and the output module, so that the power-on / off signal output end is in a high impedance state; when the power-on / off signal output end is in a high impedance state, it corresponds to the shutdown state.

[0035] The above-mentioned long-press switch circuit is based on the basic logic gate circuit design, with a small number of discrete components. It has the advantages of low price, reliable operation, extremely low power consumption, small size, simple use, and wide operating voltage range. The circuit only outputs the control level, not the system current, so it is flexible to use and has a wide range of applications. The circuit has a short-circuit protection function. When the load is abnormally short-circuited, the circuit can quickly turn off the power until the short circuit is removed. The circuit can simply and flexibly adjust the long-press time for power on and off. The circuit has an INT output pin, which can synchronously output the state of the button to the microprocessor for detection when the power is on. The circuit has a Kill input pin, which allows the microprocessor to save data before shutting down. The circuit has a button release detection mechanism. Only when the button is long pressed again after it is released, the switch state will be flipped to avoid the user pressing it all the time and repeatedly turning it on and off.

[0036] In one embodiment, the input ends of the first on-off module and the second on-off module both include: a first input end, a second input end and a third input end; the output ends of the first on-off module and the second on-off module both include: a first output end and a second output end; the level states of the first input end of the first on-off module and the first input end of the second on-off module are opposite, and the second input end of the first on-off module is connected to the second input end of the second on-off module; the third input end of the first on-off module is connected to the positive electrode of the first capacitor; and the third input end of the second on-off module is connected to the power supply.

[0037] In another embodiment, the first on-off module includes: a third capacitor, a first inverter, a first TG gate, a first NAND gate, a second TG gate, a second NAND gate, a third TG gate, a third NAND gate, a fourth NAND gate, a fourth TG gate and a second inverter; one end of the third capacitor is the first input end of the first on-off module, and the other end is grounded, the input end of the first inverter is connected to the ground end of the third capacitor, and the output end is respectively connected to the first input end of the first NAND gate and the first input end of the fourth NAND gate, the input end of the first TG gate is the second input end of the first on-off module, and the output end is connected to the second input end of the first NAND gate and the input end of the second TG gate. The output end of the first NAND gate is connected to the first input end of the second NAND gate and the input end of the third TG gate respectively, the output end of the second NAND gate is connected to the output end of the second TG gate, the output end of the third TG gate is connected to the first input end of the third NAND gate, the output end of the third NAND gate is connected to the second input end of the fourth NAND gate, the output end of the fourth NAND gate is connected to the output end of the fourth TG gate, the input end of the second inverter is the third input end, the output ends are respectively connected to the second input end of the second NAND gate and the second input end of the fourth NAND gate, and the input end of the fourth TG gate is connected to the output end of the third TG gate.

[0038] In one embodiment, the second on-off module includes: a fourth capacitor, a third inverter, a fifth TG gate, a fifth NAND gate, a sixth TG gate, a sixth NAND gate, a seventh TG gate, a seventh NAND gate, an eighth NAND gate and an eighth TG gate; one end of the fourth capacitor is the first input end of the second on-off module, and the other end is grounded; the input end of the third inverter is connected to the ground end of the fourth capacitor, and the output end is respectively connected to the first input end of the sixth NAND gate and the first input end of the seventh NAND gate; the input end of the fifth TG gate is the second input end of the second on-off module, and the output end is connected to the second input end of the fifth NAND gate and the input end of the sixth TG gate; the first input end of the fifth NAND gate is the first input end of the second on-off module, and the output end is respectively connected to the first input end of the sixth NAND gate and the input end of the seventh TG gate; the output end of the sixth NAND gate is connected to the output end of the sixth TG gate; the output end of the seventh TG gate is connected to the first input end of the seventh NAND gate; the output end of the seventh NAND gate is connected to the second input end of the eighth NAND gate; and the output end of the eighth NAND gate is connected to the output end of the eighth TG gate.

[0039] In one embodiment, the output end of the third TG gate is the first output end of the first on-off module, and the output end of the third NAND gate is the second output end of the first on-off module.

[0040] In one embodiment, the output end of the seventh TG gate is the first output end of the second on-off module, and the output end of the seventh NAND gate is the second output end of the second on-off module.

[0041] In one embodiment, the switch input module includes: a first resistor, a second resistor, a third resistor, a first diode, a second diode, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor, a third diode, a fourth diode, a fourth inverter, a fifth inverter, a first transistor, a ninth TG gate, a sixth resistor, a sixth inverter, a ninth NAND gate, a seventh inverter, and an eighth inverter; the first resistor, the second resistor and the third resistor are connected in series, and the fourth resistor and the fifth resistor are connected in series, and are all connected in parallel to the ground, and the other ends are all connected to the input end of the switch input module, the first diode is connected in series with the first capacitor, and the positive electrode of the first diode is connected to the second resistor and the third resistor, the second diode is connected in series with the second capacitor, and the positive electrode of the second diode is connected to the fourth resistor and the fifth resistor, the positive electrode of the first diode is also connected to the positive electrode of the fourth diode, the negative electrode of the fourth diode is connected to the drain of the first transistor, the source of the first transistor is grounded, the gate of the first transistor is connected to one end of the sixth resistor, and the other end of the sixth resistor is connected to the input end of the switch input module. The negative complementary signal port of the ninth TG gate and the output end of the sixth inverter are connected, the input end of the six inverters is connected to the positive complementary signal port of the ninth TG gate, the input end of the six inverters is also connected to the output end of the ninth NAND gate, the input end of the ninth NAND gate is respectively connected to the first on-off module and the output module, the input end of the ninth TG gate is connected to the cathode of the fourth diode, and the output end is connected to the second on-off module, the fourth inverter and the fifth inverter are connected in series, the output signal of the fourth inverter is used as the positive complementary signal of the TG gate in the first on-off module, the signal output by the fifth inverter is the negative complementary signal of the TG gate in the first on-off module, the anode of the third diode is connected to the anode of the third diode, the cathode of the third diode is connected to the second on-off module, the cathode of the second diode is also connected to the input end of the seventh inverter, the seventh inverter and the eighth inverter are connected in series, the output signal of the seventh inverter is used as the positive complementary signal of the TG gate in the second on-off module, and the signal output by the eighth inverter is the negative complementary signal of the TG gate in the second on-off module.

[0042] In one embodiment, the output module includes: a tenth NAND gate, an OR gate, a second transistor, a third transistor, a fourth transistor, a ninth inverter, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor and an eleventh resistor; the first input end of the tenth NAND gate is connected to the second on-off module, the second input end of the tenth NAND gate is connected to the cathode of the second diode, the output end of the tenth NAND gate is connected to one end of the seventh resistor, the other end connected to the seventh resistor is connected to the gate of the second transistor, the source of the second transistor is grounded, the first input end of the OR gate is connected to the first on-off module, the second input end of the OR gate is connected to the output end of the ninth inverter, the input end of the ninth inverter is respectively connected to one end of the eighth resistor and the drain of the third transistor, the other end of the eighth resistor is connected to the power supply, the source of the third transistor is grounded, the gate is connected to one end of the ninth resistor, the ninth resistor and the tenth resistor are connected in series to ground, the output end of the OR gate is connected to one end of the eleventh resistor, the other end of the eleventh resistor is connected to the gate of the fourth transistor, and the source of the fourth transistor is grounded.

[0043] In one of the embodiments, the open-drain output terminal outputs the level of the drain of the second transistor.

[0044] In one embodiment, the output module further includes: a shutdown signal output terminal, wherein the shutdown signal output terminal outputs the level of the other end of the ninth resistor.

[0045] The following is an explanation through specific switch control:

[0046] First, the switch circuit of the present invention can be packaged, corresponding to eight pins, namely:

[0047] PB (Pin 1): Push Button Input. Connect PB to VCC via a momentary switch.

[0048] ONT (pin 2): Power-on long press time adjustment. Place an external capacitor to ground to adjust the power-on long press time.

[0049] OFFT (Pin 3): Shutdown long press time adjustment. Place an external capacitor to ground to adjust the shutdown long press time.

[0050] GND (pin 4): ground of the module.

[0051] INT (pin 5): open drain output. When the device is powered on, it outputs the button status of the PB pin. When pressed, it is in high impedance state, and when released, it outputs low level. In other states, it outputs low level. You can connect an external pull-up resistor to the microprocessor to detect single clicks and long presses. When a long press is detected, the microprocessor needs to prepare for shutdown. If not used, connect a resistor to pull it up to the power output terminal.

[0052] KILL (pin 6): Input. The module has a pull-down resistor inside. It can be connected to a microprocessor. After the system is powered on, the microprocessor needs to keep this pin at a high level. When the microprocessor detects that the INT pin is pressed for a long time and completes the shutdown process, it outputs a low level to shut down the device. Leave it unconnected if not used.

[0053] EN (pin 7): On / off control signal, open drain output. Output high impedance in off state. Output low voltage 0V in on state.

[0054] VCC (pin 8): power input 3~20V.

[0055] 1. Initial state of power-on. At the moment of power-on, due to the charging of C1 and C4, a short high level will be generated at the input of U4B and U10B. At this time, the level state of each node of the circuit and the on-off state of the TG gate are as follows: Figure 2 Since the EN output is in high impedance state, the external PMOS remains off and the system has no power.

[0056] 2. The state after power-on and stability.

[0057] When C1 and C4 are fully charged, the input terminals of U4B and U10B remain at a low level. At this time, the level status of each node in the circuit and the on-off status of the TG gate are as follows: Figure 3 Since the EN output is in high impedance state, the external PMOS remains off and the system has no power.

[0058] 3. Short press the button in shutdown mode.

[0059] After the power is stable, if the user short presses S1, the power charged on C2 during the pressing process will be quickly released through D1 and R6 after releasing it. The level status of each node in the circuit and the on-off status of the TG gate at the moment the button is pressed are as follows: Figure 4 , short pressing the button in the shutdown state does not affect the circuit working state. After releasing the button, the circuit working state returns to Figure 3 .

[0060] 4. Long press the button in shutdown mode.

[0061] After the power-on is stable, if the user presses S1, C2 starts to charge slowly. After pressing it for a period of time, the input of U4A will become a high level. Since the cathode of D3 is at a low level, C3 will not be charged, causing the input of U4C to maintain a low level. If the user does not press the key for a long time, the key is released before the input of U4A becomes a high level, and the power on C2 will be quickly released through D1 and R6 to avoid accidental startup. The long press time can be modified by adjusting the capacitance of C2. After the input of U4A becomes a high level, the level status of each node in the circuit and the on-off status of the TG gate are changed by Figure 4 become Figure 5EN outputs L, the external PMOS is turned on, and the system starts to supply power.

[0062] If the system has a microprocessor and needs to store data when it is turned off, the microprocessor can turn the KILL pin to a high level after the system is turned on. At this time, Q2 is turned on, the input of U10D becomes L, the output becomes H, and EN remains L, which will not affect the power supply of the system. After the power is turned on, if the button is pressed and not released, the circuit will maintain Figure 5 state.

[0063] 5. The process of releasing buttons after powering on.

[0064] When the button is released, C2 will discharge quickly and the PB pin will become low level. At this time, the level status of each node in the circuit and the on-off status of the TG gate are as follows: Figure 6 After the button is released, the negative pole of D4 changes from H to L, further accelerating the discharge of C2. The EN pin still outputs a low level, and the system remains powered.

[0065] 6. Short press the button when working.

[0066] If the user short presses S1 during operation, the power charged on C3 during the pressing process will be quickly released through D2 and R6 after releasing it. The level status of each node in the circuit and the on-off status of the TG gate at the moment the button is pressed are as follows: Figure 7 When the button is pressed, the INT pin outputs high impedance. If a pull-up resistor is connected externally, a high level will be generated. After the button is released, the level state of each node in the circuit and the on-off state of the TG gate return to Figure 6 In this way, when the key is working, a short press will output a short pulse to the microprocessor at the INT pin. The short press during work does not affect the system power supply.

[0067] 7. Long press the button while working.

[0068] During operation, if the user presses S1, C3 starts to charge slowly. After being pressed for a period of time, the input of U4C will become a high level. Since the cathode of D4 is at a low level, C2 will not be charged, causing the input of U4A to maintain a low level. If the user does not press the key for a long time, the key is released before the input of U4C becomes a high level. The power on C3 will be quickly released through D2 and R6 to avoid accidental shutdown. The long press time can be modified by adjusting the capacitance of C3. After the input of U4C becomes a high level, the level status of each node in the circuit and the on-off status of the TG gate are changed by Figure 7 become Figure 8When the button is pressed continuously after operation, the INT pin will continue to maintain high impedance output. At this time, the microprocessor will detect a long press and can perform preparations before shutdown, such as data saving or shutdown animation. If the KILL pin is high level, the system will not be powered off immediately until the KILL pin becomes low level, thus ensuring data safety during shutdown. If the button is pressed continuously without being released, the circuit will maintain Figure 8 state.

[0069] 8. Long press again and then release the button.

[0070] When the key is released, C3 will discharge quickly and the PB pin will become low level. At this time, the level status of each node in the circuit and the on-off status of the TG gate are as follows: Fig. 9 As shown. After the button is released, the negative pole of D3 changes from H to L, further accelerating the discharge of C3. If the KILL pin is at a high level, the system will not be powered off immediately until the KILL pin becomes a low level, thus ensuring data security when shutting down. While the KILL pin is at a high level, the negative pole of D4 remains at L, preventing the user from long-pressing the power-on button again during this period, causing shutdown failure. After the KILL pin becomes a low level, the circuit's working state returns to Figure 3 , that is, the circuit state after power-on and stabilization.

[0071] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A long-press switch circuit, characterized in that: The circuit comprises: A first on-off module, a second on-off module, a switch input module and an output module; The input ends of the first on-off module and the second on-off module are connected to a power supply, the input ends of the first on-off module and the second on-off module are symmetrical, the first on-off module is used for switch control in the off state, and the second on-off module is used for switch control in the on state; the first on-off module and the second on-off module include a plurality of NAND gates and a plurality of TG gates; The switch input module is connected to the power supply through a key switch; the key switch is turned on when in a pressed state; the output module includes: a switch signal output terminal; When the key switch is short-pressed in the shutdown state, the first capacitor in the switch input module is charged, and the positive electrode of the charged first capacitor outputs a low level, and the low level is input into the first on-off module and the output module, so that the switch signal output end is in a high impedance state; when the switch signal output end is in a high impedance state, it corresponds to the shutdown state; When the key switch is long pressed in the shutdown state, the first capacitor in the switch input module is charged, and the positive electrode of the charged first capacitor outputs a high level, which is input into the first on-off module and the output module, so that the power-on / off signal output terminal is at a low level; when the power-on / off signal output terminal is at a low level, it corresponds to the power-on state; When the key switch is short-pressed in the power-on state, the second capacitor in the switch input module is charged, and the positive electrode of the second capacitor outputs a low level, and the low level is input into the second on-off module and the output module, so that the power-on / off signal output terminal is at a low level; when the power-on / off signal output terminal is at a low level, it corresponds to the power-on state; When the button switch is long pressed in the power-on state, the second capacitor in the switch input module is charged, and the positive electrode of the second capacitor outputs a high level, and the high level is input into the second on-off module and the output module to make the power-on / off signal output end in a high-impedance state; when the power-on / off signal output end is in a high-impedance state, it corresponds to the power-off state.

2. The switch circuit according to claim 1, characterized in that: The input ends of the first on-off module and the second on-off module both include: a first input end, a second input end and a third input end; the output ends of the first on-off module and the second on-off module both include: a first output end and a second output end; the level states of the first input end of the first on-off module and the first input end of the second on-off module are opposite, and the second input end of the first on-off module is connected to the second input end of the second on-off module; the third input end of the first on-off module is connected to the positive electrode of the first capacitor; the third input end of the second on-off module is connected to a power supply.

3. The switch circuit according to claim 2, characterized in that: The first on-off module includes: a third capacitor, a first inverter, a first TG gate, a first NAND gate, a second TG gate, a second NAND gate, a third TG gate, a third NAND gate, a fourth NAND gate, a fourth TG gate and a second inverter; One end of the third capacitor is the first input end of the first on-off module, and the other end is grounded. The input end of the first inverter is connected to the ground end of the third capacitor, and the output end is respectively connected to the first input end of the first NAND gate and the first input end of the fourth NAND gate. The input end of the first TG gate is the second input end of the first on-off module, and the output end is connected to the second input end of the first NAND gate and the input end of the second TG gate. The output end of the first NAND gate is respectively connected to the first input end of the second NAND gate and the input end of the third TG gate. The output end of the second NAND gate is connected to the output end of the second TG gate. The output end of the third TG gate is connected to the first input end of the third NAND gate. The output end of the third NAND gate is connected to the second input end of the fourth NAND gate. The output end of the fourth NAND gate is connected to the output end of the fourth TG gate. The input end of the second inverter is the third input end, and the output end is respectively connected to the second input end of the second NAND gate and the second input end of the fourth NAND gate. The input end of the fourth TG gate is connected to the output end of the third TG gate.

4. The switch circuit according to claim 2, characterized in that: The second on-off module includes: a fourth capacitor, a third inverter, a fifth TG gate, a fifth NAND gate, a sixth TG gate, a sixth NAND gate, a seventh TG gate, a seventh NAND gate, an eighth NAND gate and an eighth TG gate; One end of the fourth capacitor is the first input end of the second on-off module, and the other end is grounded. The input end of the third inverter is connected to the ground end of the fourth capacitor, and the output end is respectively connected to the first input end of the sixth NAND gate and the first input end of the seventh NAND gate. The input end of the fifth TG gate is the second input end of the second on-off module, and the output end is connected to the second input end of the fifth NAND gate and the input end of the sixth TG gate. The first input end of the fifth NAND gate is the first input end of the second on-off module, and the output end is respectively connected to the first input end of the sixth NAND gate and the input end of the seventh TG gate. The output end of the sixth NAND gate is connected to the output end of the sixth TG gate, the output end of the seventh TG gate is connected to the first input end of the seventh NAND gate, the output end of the seventh NAND gate is connected to the second input end of the eighth NAND gate, and the output end of the eighth NAND gate is connected to the output end of the eighth TG gate.

5. The switch circuit according to claim 3, characterized in that: The output end of the third TG gate is the first output end of the first on-off module, and the output end of the third NAND gate is the second output end of the first on-off module.

6. The switch circuit according to claim 4, characterized in that: The output end of the seventh TG gate is the first output end of the second on-off module, and the output end of the seventh NAND gate is the second output end of the second on-off module.

7. The switch circuit according to claim 1, characterized in that: The switch input module includes: a first resistor, a second resistor, a third resistor, a first diode, a second diode, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor, a third diode, a fourth diode, a fourth inverter, a fifth inverter, a first triode, a ninth TG gate, a sixth resistor, a sixth inverter, a ninth NAND gate, a seventh inverter, and an eighth inverter; The first resistor, the second resistor and the third resistor are connected in series, and the fourth resistor and the fifth resistor are connected in series and are all connected in parallel to the ground, and the other ends are all connected to the input end of the switch input module, the first diode is connected in series with the first capacitor, the positive electrode of the first diode is connected to the second resistor and the third resistor, the second diode is connected in series with the second capacitor, the positive electrode of the second diode is connected to the fourth resistor and the fifth resistor, the positive electrode of the first diode is also connected to the positive electrode of the fourth diode, the negative electrode of the fourth diode is connected to the drain of the first transistor, the source of the first transistor is grounded, the gate of the first transistor is connected to one end of the sixth resistor, the other end of the sixth resistor is connected to the negative complementary signal port of the ninth TG gate and the output end of the sixth inverter, the input end of the sixth inverter is connected to the positive complementary signal port of the ninth TG gate, and the input end of the sixth inverter is also connected The output end of the ninth NAND gate and the input end of the ninth NAND gate are respectively connected to the first on-off module and the output module, the input end of the ninth TG gate is connected to the cathode of the fourth diode, and the output end is connected to the second on-off module, the fourth inverter and the fifth inverter are connected in series, the output signal of the fourth inverter is used as the positive complementary signal of the TG gate in the first on-off module, the signal output by the fifth inverter is the negative complementary signal of the TG gate in the first on-off module, the anode of the third diode is connected to the anode of the third diode, the cathode of the third diode is connected to the second on-off module, the cathode of the second diode is also connected to the input end of the seventh inverter, the seventh inverter and the eighth inverter are connected in series, the output signal of the seventh inverter is used as the positive complementary signal of the TG gate in the second on-off module, and the signal output by the eighth inverter is the negative complementary signal of the TG gate in the second on-off module.

8. The switch circuit according to claim 7, characterized in that: The output module includes: a tenth NAND gate, an OR gate, a second transistor, a third transistor, a fourth transistor, a ninth inverter, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor and an eleventh resistor; The first input end of the tenth NAND gate is connected to the second on-off module, the second input end of the tenth NAND gate is connected to the cathode of the second diode, the output end of the tenth NAND gate is connected to one end of the seventh resistor, the other end connected to the seventh resistor is connected to the gate of the second transistor, the source of the second transistor is grounded, the first input end of the OR gate is connected to the first on-off module, the second input end of the OR gate is connected to the output end of the ninth inverter, the input end of the ninth inverter is respectively connected to one end of the eighth resistor and the drain of the third transistor, the other end of the eighth resistor is connected to the power supply, the source of the third transistor is grounded, the gate is connected to one end of the ninth resistor, the ninth resistor and the tenth resistor are connected in series to ground, the output end of the OR gate is connected to one end of the eleventh resistor, the other end of the eleventh resistor is connected to the gate of the fourth transistor, and the source of the fourth transistor is grounded.

9. The switch circuit according to claim 8, characterized in that: The output module also includes: An open-drain output terminal, wherein the open-drain output terminal outputs the electrical level of the drain of the second transistor.

10. The switch circuit according to claim 8, characterized in that: The output module also includes: A shutdown signal output terminal, wherein the shutdown signal output terminal outputs the electrical level of the other end of the ninth resistor.

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