A delay-locked loop and a memory

Abstract

Embodiments of the present disclosure provide a delay locked loop and a memory. The delay locked loop includes a coarse delay line, and the coarse delay line includes a first coarse adjustment module and a second coarse adjustment module. Among them, the first coarse adjustment module is configured to receive a preset control word and a first clock signal, perform delay processing on the first clock signal based on the preset control word, and output a first coarsely adjusted signal. The second coarse adjustment module is configured to receive the first coarsely adjusted signal, perform fixed delay processing on the first coarsely adjusted signal, and output a second coarsely adjusted signal. Among them, the phases of the first coarsely adjusted signal and the second coarsely adjusted signal are different, and the first coarsely adjusted signal and the second coarsely adjusted signal are used for fine delay processing. In this way, the coarse delay line only needs to set a main adjustment link to adjust the first clock signal, without setting odd and even links to adjust two clock signals respectively, simplifies the structure of the coarse delay line, and can reduce power consumption.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor memories, and particularly to a delay locked loop and a memory. Background Art

[0002] In a dynamic random access memory, a delay locked loop performs phase synchronization and locking on a four-phase clock signal through multiple delay lines respectively, so as to reduce timing variations caused by process, voltage, and temperature changes. Currently, each delay line includes at least a coarse delay line and a fine delay line. However, the structure and related control part of the coarse delay line are relatively complex, which not only increases the manufacturing cost of the circuit but also has high power consumption. Summary of the Invention

[0003] The present disclosure provides a delay locked loop and a memory, which can simplify the structure of the coarse delay line and reduce power consumption at the same time.

[0004] The technical solution of the present disclosure is implemented as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a delay locked loop, which includes a coarse delay line, and the coarse delay line includes a first coarse adjustment module and a second coarse adjustment module; wherein,

[0006] The first coarse adjustment module is configured to receive a preset control word and a first clock signal, perform delay processing on the first clock signal based on the preset control word, and output a first coarse adjustment signal;

[0007] The second coarse adjustment module is configured to receive the first coarse adjustment signal, perform fixed delay processing on the first coarse adjustment signal, and output a second coarse adjustment signal;

[0008] Wherein, the phases of the first coarse adjustment signal and the second coarse adjustment signal are different, and the first coarse adjustment signal and the second coarse adjustment signal are used for fine delay processing.

[0009] In some embodiments, the first coarse adjustment module is further configured to receive an enable signal, and perform delay processing on the first clock signal based on the preset control word to obtain a first coarse adjustment signal when the enable signal is in a first state; the second coarse adjustment module is further configured to receive the enable signal, and perform fixed delay processing on the first coarse adjustment signal to obtain a second coarse adjustment signal when the enable signal is in the first state.

[0010] In some embodiments, the first coarse tuning module includes M first delay units. The first first delay unit refers to the first delay unit close to the output end of the first coarse tuning module, and the Mth first delay unit refers to the first delay unit close to the input end of the first coarse tuning module. The preset control word includes M-bit parameters, and the Nth parameter of the preset control word is a first value, and the remaining parameters of the preset control word are second values. The first coarse tuning module is specifically configured to delay the first clock signal through the Nth to the first first delay units, and output the first coarse tuning signal through the first first delay unit. Wherein, N is a positive integer, and M is less than or equal to N.

[0011] In some embodiments, the first control end of the first first delay unit receives the first parameter of the preset control word, the second control end of the first first delay unit receives the ground signal, the first input end of the first first delay unit receives the first clock signal, the second input end of the first first delay unit receives the output signal of the second first delay unit, and the output end of the first first delay unit is used to output the first coarse tuning signal. The first control end of the ith first delay unit receives the ith parameter of the preset control word, the second control end of the ith first delay unit receives the (i - 1)th parameter of the preset control word, the first input end of the ith first delay unit receives the first clock signal, and the second input end of the ith first delay unit receives the output signal of the (i + 1)th first delay unit. The first control end of the Mth first delay unit receives the Mth parameter of the preset control word, the second control end of the Mth first delay unit receives the (M - 1)th parameter of the preset control word, the first input end of the Mth first delay unit receives the first clock signal, and the second input end of the Mth first delay unit receives the enable signal. Wherein, i is a positive integer, and i is less than or equal to M.

[0012] In some embodiments, the second coarse tuning module includes one second delay unit. The first control end of the second delay unit receives the power supply signal, the second control end of the second delay unit receives the ground signal, the first input end of the second delay unit receives the first coarse tuning signal, and the second input end of the second delay unit receives the enable signal.

[0013] In some embodiments, the first delay unit includes a first NOT gate, an OR gate, a first NAND gate, a second NAND gate, and a third NAND gate; wherein, a first input end of the OR gate is connected to a first input end of the first NAND gate, and a connection point is configured to form a first control end of the first delay unit; an input end of the first NOT gate is configured to form a second control end of the first delay unit; a second input end of the first NAND gate is configured to form a first input end of the first delay unit; a first input end of the second NAND gate is configured to form a second input end of the first delay unit; an output end of the third NAND gate is configured to form an output end of the first delay unit; an output end of the first NOT gate is connected to a second input end of the OR gate, an output end of the OR gate is connected to a second input end of the second NAND gate, an output end of the first NAND gate is connected to a first input end of the third NAND gate, and an output end of the second NAND gate is connected to a second input end of the third NAND gate; the second delay unit has the same structure as the first delay unit.

[0014] In some embodiments, the number of the first delay units is 2 to the power of a, where a is greater than or equal to 6.

[0015] In some embodiments, the delay locked loop further includes a coarse tuning control module, and the coarse tuning control module includes: a shift register module configured to generate a coarse tuning control signal; a thermal transcoding module configured to receive the coarse tuning control signal, convert the coarse tuning control signal, and output the preset control word.

[0016] In some embodiments, the coarse tuning control signal includes a first coding signal and a second coding signal, and both the first coding signal and the second coding signal each include (M + 1) sub-signals, and a level state of an i-th sub-signal of the first coding signal is opposite to a level state of an i-th sub-signal of the second coding signal; the thermal transcoding module includes M conversion units; wherein, the i-th conversion unit is configured to receive the i-th sub-signal of the first coding signal and the (i + 1)-th sub-signal of the second coding signal, perform an AND operation on the received signals, and output an i-th bit parameter of the preset control word.

[0017] In some embodiments, the conversion unit includes a fourth NAND gate and a second NOT gate; wherein, a first input end of the fourth NAND gate receives the i-th sub-signal of the first coding signal, a second input end of the fourth NAND gate receives the (i + 1)-th sub-signal of the second coding signal, an output end of the fourth NAND gate is connected to an input end of the second NOT gate, and an output end of the second NOT gate outputs the i-th bit parameter of the preset control word.

[0018] In some embodiments, the delay locked loop further includes: a fine tuning control module configured to receive a fine tuning control signal, convert the fine tuning control signal, and output a fine tuning control word; a fine tuning delay line configured to receive the fine tuning control word, the first coarse tuning signal, and the second coarse tuning signal, and perform phase interpolation on the first coarse tuning signal and the second coarse tuning signal based on the fine tuning control word to implement fine tuning delay processing.

[0019] In some embodiments, the delay locked loop includes a first tunable delay line, a second tunable delay line, a third tunable delay line, and a fourth tunable delay line, and each of the first tunable delay line, the second tunable delay line, the third tunable delay line, and the fourth tunable delay line includes at least the coarse tuning delay line and the fine tuning delay line; wherein, the first tunable delay line is configured to receive the first clock signal and output a first target clock signal; the second tunable delay line is configured to receive a second clock signal and output a second target clock signal; the third tunable delay line is configured to receive a third clock signal and output a third target clock signal; the fourth tunable delay line is configured to receive a fourth clock signal and output a fourth target clock signal; wherein, the phase differences between the first target clock signal, the second target clock signal, the third target clock signal, and the fourth target clock signal are 90 degrees in sequence, and the first target clock signal, the second target clock signal, the third target clock signal, and the fourth target clock signal are used for data sampling processing after passing through corresponding signal transmission paths.

[0020] In some embodiments, the delay locked loop further includes: a replica delay module configured to receive the first target clock signal and output a feedback clock signal; wherein, the feedback clock signal is used to simulate the waveform of the first target clock signal after passing through the signal transmission path; a detection module configured to receive the first clock signal and the feedback clock signal, detect the phase difference between the first clock signal and the feedback clock signal, and output a first indication signal and a second indication signal; a conversion control module configured to receive the first indication signal and the second indication signal, perform conversion processing on the first indication signal and the second indication signal, and output the fine tuning control signal.

[0021] In some embodiments, the conversion control module is further configured to perform conversion processing on the first indication signal and the second indication signal, and output the first coarse adjustment control signal; the time-to-digital conversion module is configured to be in a closed state when the delay locked loop is in the first operating mode; and output the second coarse adjustment control signal when the delay locked loop is in the second operating mode; correspondingly, the delay locked loop is further configured to determine the coarse adjustment control signal based on the first coarse adjustment control signal when in the first operating mode; or determine the coarse adjustment control signal based on the second coarse adjustment control signal when in the second operating mode.

[0022] In a second aspect, an embodiment of the present disclosure provides a memory, and the memory at least includes the delay locked loop as described in the first aspect.

[0023] An embodiment of the present disclosure provides a delay locked loop and a memory. The delay locked loop includes a coarse adjustment delay line, and the coarse adjustment delay line includes a first coarse adjustment module and a second coarse adjustment module; wherein, the first coarse adjustment module is configured to receive a preset control word and a first clock signal, perform delay processing on the first clock signal based on the preset control word, and output a first coarse adjustment signal; the second coarse adjustment module is configured to receive the first coarse adjustment signal, perform fixed delay processing on the first coarse adjustment signal, and output a second coarse adjustment signal; wherein, the phases of the first coarse adjustment signal and the second coarse adjustment signal are different, and the first coarse adjustment signal and the second coarse adjustment signal are used for performing fine adjustment delay processing. In this way, the coarse adjustment delay line only needs to set a main adjustment link to adjust the first clock signal, without setting odd and even links to adjust two clock signals respectively, simplifies the structure of the coarse adjustment delay line, and can reduce power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a schematic structural diagram of a delay locked loop;

[0025] Figure 2 It is a specific structural schematic diagram of a coarse adjustment delay line;

[0026] Figure 3A It is a specific structural schematic diagram of a delay unit;

[0027] Figure 3B It is a specific structural schematic diagram of a conversion unit;

[0028] Figure 4 It is a schematic structural diagram of a delay locked loop provided by an embodiment of the present disclosure;

[0029] Figure 5 It is a schematic structural diagram of another delay locked loop provided by an embodiment of the present disclosure;

[0030] Figure 6 Schematic structural diagram of a coarse delay line provided by an embodiment of the present disclosure;

[0031] Figure 7 Schematic structural diagram of a specific first delay unit provided by an embodiment of the present disclosure;

[0032] Figure 8 Schematic structural diagram of a specific conversion unit provided by an embodiment of the present disclosure;

[0033] Figure 9 Schematic diagram of signal timing provided by an embodiment of the present disclosure;

[0034] Figure 10 Schematic structural diagram of a specific delay locked loop provided by an embodiment of the present disclosure;

[0035] Figure 11 Schematic diagram of simulation effect provided by an embodiment of the present disclosure;

[0036] Figure 12 Another schematic diagram of simulation effect provided by an embodiment of the present disclosure;

[0037] Figure 13 Schematic structural diagram of a memory composition provided by an embodiment of the present disclosure. Specific implementation manners

[0038] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described herein are only for explaining the related application, rather than limiting the application. In addition, it should be noted that for the sake of description, only the parts related to the related application are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure. In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict. It should be pointed out that the terms "first / second / third" related to the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged with a specific order or sequence when allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0039] Dynamic Random Access Memory (DRAM)

[0040] Synchronous Dynamic Random Access Memory (SDRAM)

[0041] Double Data Rate SDRAM (DDR)

[0042] Low Power DDR (LPDDR)

[0043] nth Generation DDR Standard (DDRn Specification, DDRn), such as DDR3, DDR4, DDR5, DDR6

[0044] nth Generation LPDDR Standard (LPDDRn Specification, LPDDRn), such as LPDDR3, LPDDR4, LPDDR5, LPDDR6

[0045] Process, Voltage, Temperature (PVT)

[0046] For a memory, the Delay Locked Loop (DLL) therein can reduce the timing variations caused by PVT changes, thereby ensuring the synchronization of the clock signal and the data signal and achieving high-quality data communication. See Figure 1 , which shows a schematic structural diagram of a delay locked loop. As Figure 1 shown, the delay locked loop includes a first adjustable delay line to a fourth adjustable delay line, a replication delay module, a detection module, a conversion control module, a fine-tuning control module, a time-to-digital conversion module, a shift register module, a thermal transcoding module, and a top-level control module. Here, the top-level control module can generate control signals for other modules in the delay locked loop to work, and it can also be said to be the top-level signal module that controls the entire DLL. The first adjustable delay line to the fourth adjustable delay line are respectively used to adjust the four-phase clock signals (CLK_I, CLK_Q, CLK_IB, CLK_QB), and the adjusted clock signals are used for sampling the data signal after passing through the signal transmission path.

[0047] For convenience of explanation, the clock signal input to the first adjustable delay line is referred to as the first clock signal CLK_I, and the clock signal output from the first adjustable delay is referred to as the first target clock signal. Here, the replication delay module is used to replicate the delay generated by the signal transmission path, and the feedback clock signal CLKFB output therefrom is used to simulate the waveform of the first target clock signal after passing through the signal transmission path. The detection module detects the phase difference between the first clock signal CLK_I and the feedback clock signal CLKFB, and outputs the signal DlFast and the signal DlSlow. Specifically, with the first clock signal CLK_I as a reference, it is detected whether the phase of the feedback clock signal CLKFB is advanced or lagged. Therefore, the first clock signal CLK_I can also be regarded as the reference clock signal of the detection module, denoted as CLKREF. The conversion control module outputs the signal DlEdge Clk and the signal Fast / Slow Clk according to the signal DlFast and the signal DlSlow, and the fine-tuning control module outputs the control words of all the fine-tuning delay lines based on the signal DlEdge Clk.

[0048] For the control word of the coarse-tuning delay line, if the memory is in the Normal (or high-frequency) mode, the shift register module generates the signals Q<127:0> and Qn<127:0> based on the signal Fast / Slow Clk; if the memory is in the Fast (or low-frequency) mode, the shift register module generates the signals Q<127:0> and Qn<127:0> using the signal TDC Out<127:0> output by the time-to-digital conversion module. In addition, the thermal transcoding module includes a plurality of conversion units, and the structure of each conversion unit is as Figure 3B shown. That is to say, the thermal transcoding module uses 67 signals in the signal Q<127:0> and the corresponding 67 signals in the Qn<127:0> to obtain the control words of all the fine-tuning delay lines: InFEnE<63:0>, SelE<63:0>, InFEnO<63:0>, SelO<63:0>.

[0049] The specific structures of the coarse-tuning delay line and the fine-tuning delay line can have various possibilities. Exemplarily, the coarse-tuning delay line can be implemented by means of NAND gates, and the fine-tuning delay line can be implemented by means of phase difference values. In this case, refer to Figure 2 , which shows a schematic diagram of the specific structure of a coarse-tuning delay line. As Figure 2 shown, there are 64 delay units in the coarse-tuning delay line. The input clock signal is divided into two lines, odd (Even) and even (Odd). The increase and decrease of the delay units are controlled according to the control word obtained by the thermal transcoding module, so as to obtain a pair of clock signals (outE and outO), and then fine-tuning is performed through phase interpolation. Refer to Figure 3A, which shows a specific structural schematic diagram of a delay unit. As Figure 3A shown, each delay unit in the coarse delay line is composed of 8 NAND gates, and each delay unit can provide the delay of 2 NAND gates. The specific circuit connection relationship and signal input relationship can be combined with Figure 2 and Figure 3A for understanding, and the embodiments of the present disclosure will not be specifically described. On this basis, the thermal transcoding module is also composed of multiple conversion units, and each conversion unit is used to output InFEnE , SelE , InFEnO , SelO , where i is a positive integer. Refer to Figure 3B , which shows a schematic structural diagram of a conversion unit. As Figure 3B shown, each conversion unit is composed of multiple NAND gates and NOT gates, and there are 4 signal links to output corresponding signals. The specific circuit connection relationship and signal input relationship can be understood in combination with Figure 3B , and the embodiments of the present disclosure will not elaborate specifically.

[0050] As can be seen from the above, the core of the delay-locked loop is multiple adjustable delay lines. The adjustable delay lines are also the parts with the largest area and the highest power consumption in the delay-locked loop, which determine the performance of the delay-locked loop. However, the coarse delay line needs to divide the input clock signal into odd and even lines respectively for delay, so as to output the first coarse adjustment signal and the second coarse adjustment signal with different phases. At the same time, the structure and related control parts of the coarse delay line are relatively complex, which not only increases the manufacturing cost of the delay-locked loop, but also has a high power consumption.

[0051] Based on this, the embodiments of the present disclosure provide a delay-locked loop, which includes a coarse delay line, and the coarse delay line includes a first coarse adjustment module and a second coarse adjustment module; wherein, the first coarse adjustment module is configured to receive a preset control word and a first clock signal, and perform delay processing on the first clock signal based on the preset control word, and output a first coarse adjustment signal; the second coarse adjustment module is configured to receive the first coarse adjustment signal, perform fixed delay processing on the first coarse adjustment signal, and output a second coarse adjustment signal; wherein, the phases of the first coarse adjustment signal and the second coarse adjustment signal are different, and the first coarse adjustment signal and the second coarse adjustment signal are used for fine delay processing. In this way, the coarse delay line only needs to set a main adjustment link to adjust the first clock signal, and there is no need to set odd and even links to adjust two clock signals respectively, which simplifies the structure of the coarse delay line and can reduce the power consumption.

[0052] The following will describe each embodiment of the present disclosure in detail with reference to the accompanying drawings.

[0053] In an embodiment of the present disclosure, refer to Figure 4 , which shows a schematic structural diagram of a delay-locked loop 10 provided by an embodiment of the present disclosure. As Figure 4 shown, the delay-locked loop 10 includes a coarse delay line 11, and the coarse delay line 11 includes a first coarse adjustment module 111 and a second coarse adjustment module 112; wherein,

[0054] The first coarse adjustment module 111 is configured to receive a preset control word and a first clock signal, and perform delay processing on the first clock signal based on the preset control word, and output a first coarse adjustment signal;

[0055] The second coarse adjustment module 112 is configured to receive the first coarse adjustment signal, perform a fixed delay process on the first coarse adjustment signal, and output a second coarse adjustment signal.

[0056] Here, the phases of the first coarse adjustment signal and the second coarse adjustment signal are different, and the first coarse adjustment signal and the second coarse adjustment signal are used for fine delay processing. It should be understood that the phase difference between the first coarse adjustment signal and the second coarse adjustment signal can be determined according to the actual application scenario, and the embodiments of the present disclosure do not limit it.

[0057] It should be noted that the delay locked loop 10 in the embodiments of the present disclosure can be applied to but is not limited to memories, such as DRAM, SDRAM, DDR, LPDDR, etc.

[0058] In this way, in the delay locked loop 10, the coarse delay line 11 adjusts and outputs the first coarse adjustment signal through the first coarse adjustment module 111, and then, based on the first coarse adjustment signal, uses the second coarse adjustment module 112 to output the second coarse adjustment signal, so as to obtain a pair of signals with different phases. That is to say, the coarse delay line 11 only needs to set one main adjustment link to adjust the first clock signal, and there is no need to set odd and even links to adjust two clock signals respectively, which simplifies the structure of the coarse delay line 11 and reduces power consumption at the same time.

[0059] It should be noted that the preset control word includes M-bit parameters and can be expressed as S<M-1:0>, where M is a positive integer.

[0060] In some embodiments, refer to Figure 5 , which shows a schematic structural diagram of another delay locked loop 10 provided by the embodiments of the present disclosure. As Figure 5 shown:

[0061] The first coarse adjustment module 111 is further configured to receive an enable signal LD. When the enable signal LD is in the first state, it performs a delay process on the first clock signal CLK_I based on the preset control word S<M-1:0> to obtain a first coarse adjustment signal Out1;

[0062] The second coarse adjustment module 112 is further configured to receive the enable signal LD. When the enable signal LD is in the first state, it performs a fixed delay process on the first coarse adjustment signal Out1 to obtain a second coarse adjustment signal Out2.

[0063] Here, the first state can be a high level state or a low level state, as long as it meets the requirements of the actual circuit structure. In this way, the operation of the coarse delay line 11 can be controlled through the state of the enable signal LD.

[0064] In some embodiments, refer to Figure 6 , which shows a schematic structural diagram of a coarse delay line provided by an embodiment of the present disclosure. As Figure 6 shown, the first coarse adjustment module 111 includes M first delay units, which are respectively denoted as the 1st first delay unit (0), the 2nd first delay unit (1),..., the Mth first delay unit (M - 1). Here, the 1st first delay unit (0) refers to the first delay unit close to the output end of the first coarse adjustment module 111, and the Mth first delay unit (M - 1) refers to the first delay unit close to the input end of the first coarse adjustment module 111.

[0065] It should also be noted that for the preset control word S <m-1:0>For the Nth parameter S among them <n-1>is the first value, the preset control word S <m-1:0>The remaining parameters are the second value. It should be noted that the first value and the second value are different, and the specific values of the first value and the second value need to be determined according to the actual application scenario. Accordingly, the coarse delay line 11 is specifically configured to delay the first clock signal CLK_I through the Nth to the first first delay units, and output the first coarse adjustment signal Out1 through the first first delay unit (0); where N is a positive integer, and M is less than or equal to N.

[0066] That is to say, according to the preset control word S <m-1:0>The parameter positions presenting the first value are different. The first clock signal CLK_I will access the first coarse adjustment module 111 from the first delay units at different positions and finally be output via the 1st first delay unit to obtain the first coarse adjustment signal. In this way, by adjusting the preset control word S <m-1:0>The value can control the number of the first delay units that adjust the first clock signal CLK_I, thereby adjusting the delay between the first clock signal CLK_I and the first coarse adjustment signal Out1.

[0067] In some embodiments, as Figure 6 shown, the first control end of the first delay unit (0) receives the first bit parameter S<0> of the preset control word, the second control end of the first delay unit (0) receives the ground signal VSS, the first input end of the first delay unit (0) receives the first clock signal CLK_I, the second input end of the first delay unit (0) receives the output signal of the second delay unit (1), and the output end of the first delay unit (0) is used to output the first coarse adjustment signal Out1;

[0068] The first control end of the i-th first delay unit (i - 1) receives the i-th bit parameter S of the preset control word <i-1>, the second control terminal of the i-th first delay unit (i - 1) receives the (i - 1)-th bit parameter S of the preset control word <i-2>, the first input terminal of the i-th first delay unit receives the first clock signal CLK_I, and the second input terminal of the i-th first delay unit receives the output signal of the (i + 1)-th first delay unit (i);

[0069] The first control terminal of the M-th first delay unit (M - 1) receives the M-th bit parameter S of the preset control word <m-1>, the second control terminal of the Mth first delay unit (M-1) receives the (M-1)th bit parameter S of the preset control word <m-2>, the first input terminal of the Mth first delay unit (M-1) receives the first clock signal CLK_I, and the second input terminal of the Mth first delay unit (M-1) receives the enable signal LD;

[0070] where i is a positive integer and i is less than or equal to M.

[0071] In a specific embodiment, refer to Figure 7 , which shows a schematic structural diagram of the first delay unit provided by the embodiment of the present disclosure. As Figure 7 shown, the first delay unit includes a first NOT gate 204, an OR gate 205, a first NAND gate 201, a second NAND gate 202, and a third NAND gate 203; among them, the first input terminal of the OR gate 205 is connected to the first input terminal of the first NAND gate 201, and the connection point is used to form the first control terminal of the first delay unit; the input terminal of the first NOT gate 204 is used to form the second control terminal of the first delay unit; the second input terminal of the first NAND gate 201 is used to form the first input terminal of the first delay unit; the first input terminal of the second NAND gate 202 is used to form the second input terminal of the first delay unit; the output terminal of the third NAND gate 203 is used to form the output terminal of the first delay unit; the output terminal of the first NOT gate 204 is connected to the second input terminal of the OR gate 205, the output terminal of the OR gate 205 is connected to the second input terminal of the second NAND gate 202, the output terminal of the first NAND gate 201 is connected to the first input terminal of the third NAND gate 203, and the output terminal of the second NAND gate 202 is connected to the second input terminal of the third NAND gate 203.

[0072] Here, the essence of the first delay unit / second delay unit is similar to a two-to-one data selector Mux. In such a structure, the first state of the enable signal LD refers to the low level state; for the preset control word S <m-1:0>, the first value is 1 and the second value is 0, that is, the preset control word S <m-1:0>It can be "100000……00", "010000……00", ……, "000000……01".

[0073] Assume the preset control word S <m-1:0>There are 128 parameters, denoted as S<127:0>. Taking S<50> = 1, and S<49:0> and S<51:127> both being 0 as an example, the working principle of the first coarse adjustment module 111 will be described.

[0074] Please refer to Figure 6 and Figure 7 , for the last first delay unit (127), one input terminal of the second NAND gate 202 receives the enable signal LD = 0, so the second NAND gate 202 outputs signal 1; since one input terminal of the first NAND gate 201 receives S<127> = 0, the first NAND gate 201 outputs signal 1; since both input terminals of the third NAND gate 203 receive signal 1, the output terminal of the third NAND gate 203 outputs signal 0. Similarly, for the first delay unit (126) to the first delay unit (51), the processing process is similar, that is, the delay unit (50) also outputs signal 0.

[0075] For the first delay unit (50), the two input terminals of the first NAND gate 201 respectively receive S<50> = 1 and the first clock signal CLK_I, so the first NAND gate 201 outputs the inverted signal of the first clock signal CLK_I (with a certain delay), and one of the input terminals of the second NAND gate 202 receives signal 0 (the output of the 50th delay unit), so the second NAND gate 202 outputs signal 1; the two input terminals of the third NAND gate 203 respectively receive signal 1 and the inverted signal of the first clock signal CLK_I, so the third NAND gate 203 outputs the delayed clock signal, denoted as CLK_Delay1.

[0076] For the first delay unit (49), the two receiving terminals of the second NAND gate 202 respectively receive signal 1 and the output signal CLK_Delay1 of the first delay unit (50), and the second NAND gate 202 outputs the inverted signal of CLK_Delay1 (with a certain delay), one input terminal of the first NAND gate 201 receives S<49> = 0, so the first NAND gate 201 outputs signal 1, and the third NAND gate 203 receives signal 1 and the inverted signal of CLK_Delay1, and outputs the twice-delayed clock signal CLK_Delay2. The working process of the first delay unit (48) to the first delay unit (0) can refer to the first delay unit (49).

[0077] As can be seen from the above, the first coarse adjustment signal Out1 output by the first delay unit (0) is the first clock signal after being delayed by the first delay unit (50) to the first delay unit (0). Similarly, if S<88> = 1, then the first coarse adjustment signal Out1 output by the first delay unit (0) is the first clock signal after being delayed by the first delay unit (88) to the first delay unit (0), and the rest can be deduced by analogy.

[0078] In this way, for the first control unit, the previous stage control signal S <i-1>The inverting result and the local control signal S Perform an OR operation to remove interference from the previous stage, ensure that the signal only travels along one path, and at the same time, the delay effect is more accurate.

[0079] In some embodiments, the second coarse adjustment module 112 includes one second delay unit; the first control end of the second delay unit receives the power supply signal VCC, the second control end of the second delay unit receives the ground signal VSS, the first input end of the second delay unit receives the first coarse adjustment signal Out1, and the second input end of the second delay unit receives the enable signal LD.

[0080] It should be noted that the structures of the first delay unit and the second delay unit are the same. That is to say, Figure 7 It can also be regarded as the specific structural schematic diagram of the second delay unit. In the subsequent description, if the delay unit is not specified as the first delay unit or the second delay unit, it can refer to the first delay unit or the second delay unit.

[0081] Combined with Figure 6 and Figure 7 As shown, in the second delay unit, the first NAND gate 201 receives the signal 1 (power supply signal VCC) and the first coarse adjustment signal Out1 respectively, so the first NAND gate 201 outputs the inverted signal of the first coarse adjustment signal Out1. One of the input ends of the second NAND gate 202 receives the enable signal LD = 0, so the second NAND gate 202 outputs the signal 1. The third NAND gate 203 receives the signal 1 and the inverted signal of the first coarse adjustment signal Out1 respectively, and outputs the second coarse adjustment signal Out2. Here, the second coarse adjustment signal Out2 has a delay of two NAND gates compared to the first coarse adjustment signal Out1, and both are clock signals with the same clock period.

[0082] The delay unit provided by the embodiment of the present disclosure requires one NOT gate, one OR gate and three NAND gates. The delay unit provided in the related art requires eight NAND gates and there are two signal links at the same time. In contrast, each delay unit provided by the embodiment of the present disclosure can also provide a delay of two NAND gates, and has a simpler structure and more signal links, which not only reduces power consumption but also reduces the circuit area.

[0083] In some embodiments, as Figure 5 shown, the delay locked loop 10 further includes a coarse adjustment control module 13, and the coarse adjustment control module 13 includes:

[0084] A shift register module 131 configured to generate a coarse adjustment control signal;

[0085] A thermal transcoding module 132 configured to receive the coarse adjustment control signal, convert the coarse adjustment control signal, and output a preset control word S <m-1:0>。

[0086] Exemplarily, the thermal transcoding module 132 performs one-hot encoding conversion on the coarse adjustment control signal to obtain a preset control word S <m-1:0>. Here, the thermal transcoding module 132 can also be referred to as the Thermometer conversion code module.

[0087] It should be noted that, as Figure 5 shown, the coarse control signal includes a first coding signal and a second coding signal. Among them, the first coding signal includes (M + 1) sub-signals, denoted as Q <m:0>, the second encoded signal includes an (M + 1)-bit sub-signal, denoted as Qn <m:0>, and the i-th sub-signal Q of the first encoded signal <i-1>and the i-th sub-signal Qn of the second coding signal <i-1>has an opposite level state.

[0088] Accordingly, in some embodiments, the thermal transcoding module 132 includes M conversion units; among them,

[0089] the i-th conversion unit is configured to receive the i-th sub-signal Q of the first encoded signal <i-1>and the (i + 1)-th sub-signal Qn of the second encoded signal , and perform an AND operation on the received signal to output the i-th parameter S of the preset control word <i-1>。

[0090] It should be noted that, referring to Figure 8 , which shows a schematic structural diagram of the conversion unit provided in the embodiments of the present disclosure. As Figure 8 shown, the conversion unit includes a fourth NAND gate 206 and a second NOT gate 207; wherein, the first input terminal of the fourth NAND gate 206 receives the i-th sub-signal Q of the first encoded signal <i-1>, the second input terminal of the fourth NAND gate 206 receives the (i + 1)-th position sub-signal Qn of the second encoded signal , the output terminal of the fourth NAND gate 206 is connected to the input terminal of the second NOT gate 207, and the output terminal of the second NOT gate 207 outputs the i-th bit parameter S of the preset control word <i-1>。

[0091] Based on the above structure, a description of the conversion process of the coarse control signal and the preset control word is provided.

[0092] It should be understood that the first encoded signal Q <m:0>Generated by a shift register. Refer to Figure 9 , which shows a signal timing schematic diagram provided by an embodiment of the present disclosure. As Figure 9 shown in (a) of <m:0>Among them, each sub-signal (Q<0>, Q<1>... Q <m>) changes from the first state to the second state in sequence, and the level change edge of the (i + 1)-th sub-signal is delayed with respect to the level change edge of the i-th sub-signal. Meanwhile, the second encoded signal Qn <m:0>Each sub-signal therein and the first encoded signal Q <m:0>The states of the corresponding sub-signals are opposite. Figure 9 The second encoded signal Qn is not shown for the time being. <m:0>status.

[0093] According to the structure of the conversion unit, the first encoded signal Q <m:0>, the second encoded signal Qn <m:0>and the preset control word S <m-1:0>The relationship is as shown in Equation (1).

[0094] S ＝Q ·Qn<i+1>………………………………(1)

[0095] Therefore, as shown in (b) of Figure 9 , multiple conversion units sequentially output a pulse, and the pulse start time of the output signal of the (i + 1)-th conversion unit is delayed from the pulse end time of the output signal of the i-th conversion unit. Therefore, at each time point, the preset control word S <m-1:0>Only one of the parameters is at the first value, and the remaining parameters are at the second value. Thus, for the preset control word S <m-1:0>For example, the parameter position presenting the first value changes successively, and the number of first delay units that delay the first clock signal CLK_I increases or decreases until an appropriate number of first delay units is found, thereby locking the preset control word S <m-1:0>。

[0096] It should be noted that by comparing Figure 3B and Figure 8 it can be seen that in the related art, each conversion unit needs to be provided with 2 NAND gates and 6 NOT gates, and a total of 20 transistors are required, and there are 4 signal links at the same time; in the embodiments of the present disclosure, 1 NAND gate and 1 inverter are provided in each conversion unit, a total of 6 transistors, and there is only 1 signal link. In comparison, the structure of the conversion unit provided by the embodiments of the present disclosure is simpler, which not only reduces power consumption but also reduces the circuit area.

[0097] As can be seen from the above, the embodiments of the present disclosure reduce the power consumption of the coarse adjustment time line by using the delay unit composed of the data selector MUX and its unique internal structure, and at the same time improve the thermal transcoding part according to the requirements of the delay unit, reducing the number of transistors.

[0098] In some embodiments, the number of the first delay units is 2 to the power of a, where a is greater than or equal to 6.

[0099] It should be noted that in the related art, due to the complex circuit structure and large area of the delay unit and the conversion unit, the preset control word S <m-1:0>Generally set to 64 bits, there are 64 conversion units (a total of 1280 transistors), and there are also 64 delay units; in the embodiments of the present disclosure, the structure of the first delay unit is simpler, and the number of the first delay units can be set to 64 or more, so as to improve the resolution of delay adjustment. Exemplarily, the preset control word S <m-1:0>It may include 128-bit parameters, there are 128 conversion units (768 transistors), and the number of the first delay units can be set to 128. In this case, the adjustment resolution of the delay locked loop in the embodiments of the present disclosure is improved, the power consumption is lower, and the thermal transcoding module can still save 512 transistors.

[0100] In some embodiments, referring to Figure 10 , which shows a schematic structural diagram of a delay locked loop 10 provided by the embodiments of the present disclosure. As Figure 10 shown, the delay locked loop 10 further includes:

[0101] A fine-tuning control module 14, configured to receive a fine-tuning control signal DlEdge Clk, convert the fine-tuning control signal DlEdge Clk, and output a fine-tuning control word;

[0102] A fine-tuning delay line 12, configured to receive the fine-tuning control word, a first coarse-tuning signal Out1, and a second coarse-tuning signal Out2, and perform phase interpolation on the first coarse-tuning signal Out1 and the second coarse-tuning signal Out2 based on the fine-tuning control word to implement fine-tuning delay processing.

[0103] It should be noted that the fine-tuning control module 14 can also be composed of multiple shift registers. That is to say, the fine-tuning control signal DlEdge Clk is essentially a clock signal, and multiple shift registers sample using the fine-tuning control signal DlEdge Clk to generate a fine-tuning control word. As described above, the fine-tuning delay line 12 performs fine-tuning based on the principle of phase interpolation, and its specific structure can refer to the existing structure, which is not specifically described in the embodiments of the present disclosure.

[0104] In some embodiments, as Figure 10 shown, the delay locked loop 10 includes a first adjustable delay line 31, a second adjustable delay line 32, a third adjustable delay line 33, and a fourth adjustable delay line 34, and each of the first adjustable delay line 31, the second adjustable delay line 32, the third adjustable delay line 33, and the fourth adjustable delay line 34 includes the aforementioned coarse-tuning delay line 11 and the aforementioned fine-tuning delay line 12; wherein,

[0105] The first adjustable delay line 31 is configured to receive a first clock signal CLK_I and output a first target clock signal; the second adjustable delay line 32 is configured to receive a second clock signal CLK_Q and output a second target clock signal; the third adjustable delay line 33 is configured to receive a third clock signal CLK_IB and output a third target clock signal; the fourth adjustable delay line 34 is configured to receive a fourth clock signal CLK_QB and output a fourth target clock signal.

[0106] It should be noted that the phase differences of the first clock signal CLK_I, the second clock signal CLK_Q, the third clock signal CLK_IB, and the fourth clock signal CLK_QB are 90 degrees in sequence, and the phase differences of the first target clock signal, the second target clock signal, the third target clock signal, and the fourth target clock signal are 90 degrees in sequence. Moreover, the first target clock signal, the second target clock signal, the third target clock signal, and the fourth target clock signal are used for data sampling processing after passing through the corresponding signal transmission paths.

[0107] It should be noted that each adjustable delay line includes at least a coarse delay line and a fine delay line, and may also include other functional modules. It should be understood that the structures of the first adjustable delay line 31, the second adjustable delay line 32, the third adjustable delay line 33, and the fourth adjustable delay line 34 are always the same. In the following text, if only the adjustable delay line is mentioned, it may refer to any one of the first adjustable delay line 31, the second adjustable delay line 32, the third adjustable delay line 33, and the fourth adjustable delay line 34.

[0108] Taking the first adjustable delay line 31 as an example, if the first adjustable delay line 31 only includes a coarse delay line and a fine delay line, the output signal of the fine delay line is the first target clock signal; if the first adjustable delay line 31 is also provided with other functional modules on the output side of the fine delay line, the output signal of the fine delay line needs to be processed by other functional modules to obtain the first target clock signal.

[0109] In addition, the coarse delay lines in the first adjustable delay line 31, the second adjustable delay line 32, the third adjustable delay line 33, and the fourth adjustable delay line 34 receive the same preset control word, and the fine delay lines in the first adjustable delay line 31, the second adjustable delay line 32, the third adjustable delay line 33, and the fourth adjustable delay line 34 receive the same fine adjustment control word.

[0110] In some embodiments, as Figure 10 shown, the delay locked loop 10 further includes:

[0111] A replica delay module 15, configured to receive the first target clock signal and output a feedback clock signal CLKKFB; wherein, the feedback clock signal CLKKFB is used to simulate the waveform of the first target clock signal after passing through the signal transmission path;

[0112] A detection module 16, configured to receive the first clock signal CLK_I and the feedback clock signal CLKKFB, detect the phase difference between the first clock signal CLK_I and the feedback clock signal CLKKFB, and output a first indication signal DlFast and a second indication signal DSlow;

[0113] The conversion control module 17 is configured to receive a first indication signal DlFast and a second indication signal DSlow, perform conversion processing on the first indication signal DlFast and the second indication signal DSlow, and output a fine-tuning control signal DlEdge Clk.

[0114] As described above, for the detection module 16, with the first clock signal CLK_I as a reference, it detects whether the phase of the feedback clock signal CLKFB is advanced or lagged. Therefore, the first clock signal CLK_I can also be regarded as the reference clock signal (denoted by CLKREF) of the detection module 16.

[0115] It should be noted that the waveform of the first target clock signal after passing through the signal transmission path needs to be consistent with the waveform of the first clock signal CLK_I. Therefore, a feedback adjustment mechanism needs to be constructed. In other words, the replication delay module 15 is used to replicate the delay generated by the signal transmission path. Therefore, the feedback clock signal CLKKFB can simulate the waveform of the first target clock signal after passing through the signal transmission path, and then adjust and fine-tune the control signal DlEdge Clk according to the phase difference between the feedback clock signal CLKKFB and the first clock signal, so as to adjust the working parameters of the adjustable delay line.

[0116] In addition, the waveform of the feedback clock signal CLKKFB is not exactly the same as the waveform of the first target clock signal after passing through the signal transmission path. In an actual working scenario, after the memory enters a stable working state, the feedback clock signal CLKKFB can be frequency-divided to reduce the update frequency of the delay line adjustment signal, avoid signal jitter caused by signal glitches, and reduce power consumption at the same time.

[0117] In some embodiments, as Figure 10 shown, the conversion control module 17 is further configured to perform conversion processing on the first indication signal DlFast and the second indication signal DSlow, and output a first coarse-tuning control signal Fast / Slow Clk;

[0118] The time-to-digital conversion module 18 is configured to be in a closed state when the delay-locked loop 10 is in the first working mode; and output a second coarse-tuning control signal TDC Out when the delay-locked loop 10 is in the second working mode. <m:0>;

[0119] Accordingly, the delay locked loop 10 is further configured to determine the coarse adjustment control signal based on the first coarse adjustment control signal Fast / Slow Clk when in the first operating mode; or based on the second coarse adjustment control signal TDC Out when in the second operating mode <m:0>Determine the coarse adjustment control signal.

[0120] It should be noted that the first working mode can be the Normal mode (high-frequency case) of the memory. At this time, the time-to-digital conversion module 18 is turned off, and the conversion control module 17 generates the first coarse adjustment control signal Fast / Slow Clk. The first coarse adjustment control signal Fast / Slow Clk is essentially a clock signal. Multiple shift registers in the shift register module 131 use the first coarse adjustment control signal Fast / Slow Clk for sampling to generate the first encoded signal Q. <m:0>, thereby generating a coarse control signal. The second operating mode may be the Fast mode (low-frequency case) of the memory. At this time, the time-to-digital conversion module 18 is turned on to accelerate the lock-in time of the low frequency. The required delay is measured by the time-to-digital conversion module 18 to obtain a second coarse control signal TDC Out <m:0>, the second coarse control signal TDC Out is transferred through a plurality of shift registers in the shift register module 131 <m:0>Transmitted to generate a first encoded signal Q <m:0>, thereby generating a coarse adjustment control signal.

[0121] In addition, as Figure 10 shown, the delay locked loop 10 may further include a top control module 19; wherein, the top control module 19 is configured to receive the first clock signal CLK_I and control the operation of the delay locked loop 10 based on the first clock signal CLK_I. That is to say, the top control module 19 generates a control signal capable of making other modules of the delay locked loop 10 work, and can also be said to be a top signal module that controls the operation of the entire DLL.

[0122] In summary, the disclosed embodiment provides a brand-new structure of a delay locked loop. On the one hand, the coarse adjustment delay line 11 only needs to set a main adjustment link to adjust the first clock signal, without setting odd and even links to adjust two clock signals respectively, simplifying the structure of the coarse adjustment delay line 11 and reducing power consumption; on the other hand, the conversion unit in the thermal transcoding module 132 has a simple structure and also only needs to set a signal link, which can also reduce power consumption; on the other hand, the preset control word of the coarse adjustment delay line 11 can have 128-bit parameters. Although the number of delay units and conversion units increases correspondingly, it does not increase the circuit area (actually it will decrease), and can improve the resolution of delay adjustment.

[0123] Under the condition that the working voltage is 1.1 volts and the temperature is 25 degrees Celsius, simulation tests are carried out on the delay locked loops of two structures. Refer to Figure 11 , which shows a schematic diagram of a simulation effect provided by the disclosed embodiment. Refer to Figure 12 , which shows another schematic diagram of a simulation effect provided by the disclosed embodiment. In Figure 11 and Figure 12 , the experimental group refers to the delay locked loop provided by the disclosed embodiment, and the specific structure is shown in Figures 4 to 10 ; the control group is the delay locked loop of the related technology agent, and the specific structure is shown in Figure 1 ~Figure 3.

[0124] As Figure 11 shown, in the experimental group, the resolution of the delay unit is 65.8 picoseconds (p); in the control group, the resolution of the delay unit is 74.5 picoseconds. That is to say, the resolution of the delay unit proposed in the disclosed embodiment is higher than that of the original structure. As Figure 12 shown, in the experimental group, the average current passing through all delay units is 4.71 milliamperes (mA), and the average power consumption is 5.181 milliwatts (mw); in the control group, the average current passing through all delay units is 5.86 milliamperes, and the average power consumption is 6.446 milliwatts. That is to say, the power consumption of the delay unit proposed in the disclosed embodiment is lower.

[0125] An embodiment of the present disclosure provides a delay-locked loop, which includes a coarse delay line, and the coarse delay line includes a first coarse adjustment module and a second coarse adjustment module; wherein, the first coarse adjustment module is configured to receive a preset control word and a first clock signal, perform delay processing on the first clock signal based on the preset control word, and output a first coarse adjustment signal; the second coarse adjustment module is configured to receive the first coarse adjustment signal, perform fixed delay processing on the first coarse adjustment signal, and output a second coarse adjustment signal; wherein, the phases of the first coarse adjustment signal and the second coarse adjustment signal are different, and the first coarse adjustment signal and the second coarse adjustment signal are used for fine delay processing. In this way, the circuit structure of the coarse delay line is simpler, which can not only reduce power consumption, but also improve the resolution of delay adjustment.

[0126] In another embodiment of the present disclosure, refer to Figure 13 , which shows a schematic structural diagram of a composition of a memory 40 provided by an embodiment of the present disclosure. As Figure 13 shown, the memory 40 at least includes the aforementioned delay-locked loop 10.

[0127] It should be noted that since the memory 40 includes the aforementioned delay-locked loop 10, on the one hand, the coarse delay line 11 only needs to set a main adjustment link to adjust the first clock signal, and there is no need to set odd and even links to adjust two clock signals respectively, which simplifies the structure of the coarse delay line 11 and can reduce power consumption; on the other hand, the conversion unit in the thermal transcoding module 132 has a simple structure and also only needs to set a signal link, which can also reduce power consumption; on the other hand, the preset control word of the coarse delay line 11 can have 128-bit parameters. Although the number of delay units and conversion units increases correspondingly, it does not increase the circuit area (actually it will decrease), which can improve the resolution of delay adjustment.

[0128] In some embodiments, the memory complies with at least one of the following specifications: DDR3, DDR4, DDR5, DDR6, LPDDR3, LPDDR4, LPDDR5, LPDDR6.

[0129] The above are only the preferred embodiments of the present disclosure and are not intended to limit the protection scope of the present disclosure. It should be noted that in the present disclosure, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the presence of additional identical elements in the process, method, article or device comprising such element. The serial numbers of the embodiments of the present disclosure above are only for description and do not represent the superiority or inferiority of the embodiments. The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments. The above are only the specific implementation manners of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims. < / m>

Claims

1. A delay-locked loop, characterized in that, The delay locked loop includes a coarse delay line, and the coarse delay line includes a first coarse adjustment module and a second coarse adjustment module; wherein, The first coarse adjustment module is configured to receive a preset control word and a first clock signal, perform a delay process on the first clock signal based on the preset control word, and output a first coarse adjustment signal; The second coarse adjustment module is configured to receive the first coarse adjustment signal, perform a fixed delay process on the first coarse adjustment signal, and output a second coarse adjustment signal; Wherein, the phases of the first coarse adjustment signal and the second coarse adjustment signal are different, and the first coarse adjustment signal and the second coarse adjustment signal are used for a fine delay process; The first coarse adjustment module is further configured to receive an enable signal, and when the enable signal is in a first state, perform a delay process on the first clock signal based on the preset control word to obtain a first coarse adjustment signal; The second coarse adjustment module is further configured to receive the enable signal, and when the enable signal is in a first state, perform a fixed delay process on the first coarse adjustment signal to obtain a second coarse adjustment signal; The first coarse adjustment module includes M first delay units, and the first delay unit of the 1st is the first delay unit close to the output end of the first coarse adjustment module, and the first delay unit of the Mth is the first delay unit close to the input end of the first coarse adjustment module; The preset control word includes M-bit parameters, and the Nth bit parameter of the preset control word is a first value, and the remaining parameters of the preset control word are second values; The first coarse adjustment module is specifically configured to delay the first clock signal through the Nth to the 1st first delay units, and output the first coarse adjustment signal through the 1st first delay unit; Wherein, both N and M are positive integers, and N is less than or equal to M; The first control end of the 1st first delay unit receives the 1st bit parameter of the preset control word, the second control end of the 1st first delay unit receives a ground signal, the first input end of the 1st first delay unit receives the first clock signal, the second input end of the 1st first delay unit receives the output signal of the 2nd first delay unit, and the output end of the 1st first delay unit is used to output the first coarse adjustment signal; The first control end of the ith first delay unit receives the ith bit parameter of the preset control word, the second control end of the ith first delay unit receives the (i - 1)th bit parameter of the preset control word, the first input end of the ith first delay unit receives the first clock signal, and the second input end of the ith first delay unit receives the output signal of the (i + 1)th first delay unit; The first control end of the Mth first delay unit receives the Mth bit parameter of the preset control word, the second control end of the Mth first delay unit receives the (M - 1)th bit parameter of the preset control word, the first input end of the Mth first delay unit receives the first clock signal, and the second input end of the Mth first delay unit receives the enable signal; Wherein, i is a positive integer, and i is less than or equal to M.

2. The delay locked loop according to claim 1, wherein The second coarse tuning module includes one second delay unit; A first control end of the second delay unit receives a power signal, a second control end of the second delay unit receives a ground signal, a first input end of the second delay unit receives the first coarse tuning signal, and a second input end of the second delay unit receives the enable signal.

3. The delay-locked loop according to claim 2, wherein, The first delay unit includes a first NOT gate, an OR gate, a first NAND gate, a second NAND gate, and a third NAND gate; wherein, A first input end of the OR gate is connected to a first input end of the first NAND gate, and a connection point is used for forming a first control end of the first delay unit; an input end of the first NOT gate is used for forming a second control end of the first delay unit; a second input end of the first NAND gate is used for forming a first input end of the first delay unit; a first input end of the second NAND gate is used for forming a second input end of the first delay unit; an output end of the third NAND gate is used for forming an output end of the first delay unit; An output end of the first NOT gate is connected to a second input end of the OR gate, an output end of the OR gate is connected to a second input end of the second NAND gate, an output end of the first NAND gate is connected to a first input end of the third NAND gate, and an output end of the second NAND gate is connected to a second input end of the third NAND gate; The second delay unit has the same structure as the first delay unit.

4. The delay-locked loop according to claim 1, wherein The number of the first delay units is 2 to the power of a, where a is greater than or equal to 6.

5. The delay locked loop according to claim 1, wherein The delay locked loop further includes a coarse tuning control module, and the coarse tuning control module includes: A shift register module configured to generate a coarse tuning control signal; A thermal transcoding module configured to receive the coarse tuning control signal, convert the coarse tuning control signal, and output the preset control word.

6. The delay-locked loop according to claim 5, wherein The coarse tuning control signal includes a first coding signal and a second coding signal, and both the first coding signal and the second coding signal each include (M + 1) sub-signals, and a level state of the i-th sub-signal of the first coding signal is opposite to a level state of the i-th sub-signal of the second coding signal; The thermal transcoding module includes M conversion units; wherein, The i-th conversion unit is configured to receive the i-th sub-signal of the first coding signal and the (i + 1)-th sub-signal of the second coding signal, perform an AND operation on the received signals, and output the i-th bit parameter of the preset control word.

7. The delay-locked loop according to claim 6, wherein The conversion unit includes a fourth NAND gate and a second NOT gate; wherein, A first input end of the fourth NAND gate receives the i-th sub-signal of the first coding signal, a second input end of the fourth NAND gate receives the (i + 1)-th sub-signal of the second coding signal, an output end of the fourth NAND gate is connected to an input end of the second NOT gate, and an output end of the second NOT gate outputs the i-th bit parameter of the preset control word.

8. The delay-locked loop according to any one of claims 1-7, characterized in that, The delay locked loop further includes: A fine tuning control module configured to receive a fine tuning control signal, convert the fine tuning control signal, and output a fine tuning control word; The fine-tuning delay line is configured to receive the fine-tuning control word, the first coarse-tuning signal, and the second coarse-tuning signal, and perform phase interpolation on the first coarse-tuning signal and the second coarse-tuning signal based on the fine-tuning control word to achieve fine-tuning delay processing.

9. The delay locked loop according to claim 8, wherein The delay-locked loop includes a first adjustable delay line, a second adjustable delay line, a third adjustable delay line, and a fourth adjustable delay line, and each of the first adjustable delay line, the second adjustable delay line, the third adjustable delay line, and the fourth adjustable delay line includes at least the coarse-tuning delay line and the fine-tuning delay line; wherein, The first adjustable delay line is configured to receive the first clock signal and output a first target clock signal; The second adjustable delay line is configured to receive a second clock signal and output a second target clock signal; The third adjustable delay line is configured to receive a third clock signal and output a third target clock signal; The fourth adjustable delay line is configured to receive a fourth clock signal and output a fourth target clock signal; Wherein, the phase differences between the first target clock signal, the second target clock signal, the third target clock signal, and the fourth target clock signal are 90 degrees in sequence, and the first target clock signal, the second target clock signal, the third target clock signal, and the fourth target clock signal are used for data sampling processing after passing through the corresponding signal transmission paths.

10. The delay locked loop according to claim 9, wherein The delay-locked loop further includes: A replication delay module configured to receive the first target clock signal and output a feedback clock signal; wherein, the feedback clock signal is used to simulate the waveform of the first target clock signal after passing through the signal transmission path; A detection module configured to receive the first clock signal and the feedback clock signal, detect the phase difference between the first clock signal and the feedback clock signal, and output a first indication signal and a second indication signal; A conversion control module configured to receive the first indication signal and the second indication signal, perform conversion processing on the first indication signal and the second indication signal, and output the fine-tuning control signal.

11. The delay-locked loop according to claim 10, wherein The conversion control module is further configured to perform conversion processing on the first indication signal and the second indication signal and output the first coarse-tuning control signal; A time-to-digital conversion module is configured to be in a closed state when the delay-locked loop is in a first operating mode; and output the second coarse-tuning control signal when the delay-locked loop is in a second operating mode; Accordingly, the delay-locked loop is further configured to determine the coarse-tuning control signal based on the first coarse-tuning control signal when in the first operating mode; or determine the coarse-tuning control signal based on the second coarse-tuning control signal when in the second operating mode.

12. A memory, characterized in that, The memory includes the delay-locked loop according to any one of claims 1-11.

Images