Semiconductor device

Abstract

The semiconductor device of the present application includes: a semiconductor layer of a first conductivity type having a cell portion and a peripheral portion disposed around the cell portion, a gate trench being formed on a surface side of the cell portion; and a gate electrode embedded in the gate trench through a gate insulating film, a channel being formed on a side portion of the gate trench when turned on, the peripheral portion having a semiconductor surface disposed at a depth position above a depth of the gate trench, and further including a voltage-withstanding structure having a semiconductor region of a second conductivity type formed on the semiconductor surface of the peripheral portion.

Description

[0001] This application is a divisional application of the following invention patent application:

[0002] Invention title: Semiconductor device; Application date: March 4, 2014; Application number: 201810442488.1. Technical Field

[0003] This invention relates to semiconductor devices having a trench gate structure. Background Technology

[0004] Semiconductor power devices, primarily used in various power electronics fields such as motor control systems and power conversion systems, have always attracted much attention.

[0005] As such semiconductor power devices, SiC semiconductor devices with trench gate structures are proposed, for example.

[0006] For example, Patent Document 1 discloses a MIS transistor, including: n ＋ A SiC substrate of this type; n formed on this SiC substrate － The epitaxial layer (drift region) of the type; n formed in the active region of the epitaxial layer ＋ The system includes a source region of type p and a body region of type p; a lattice-shaped gate trench formed in a manner that penetrates the source region and the body region to reach the drift region; a gate insulating film formed on the inner surface of the gate trench; a gate electrode buried in the gate trench; and a p-type protective ring formed in the peripheral region of the transistor formed in the active region.

[0007] Existing technical documents

[0008] Patent documents

[0009] Patent document 1: Japanese Patent Application Publication No. 2012-178536. Summary of the Invention

[0010] The problem that the invention aims to solve

[0011] The purpose of this invention is to provide a semiconductor device that can form a stable electric field distribution in a semiconductor layer regardless of the depth of the gate trench.

[0012] Solution for solving the problem

[0013] The semiconductor device of the present invention includes: a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, wherein a gate trench is formed on the surface side of the cell portion; and a gate electrode buried in the gate trench through a gate insulating film, wherein a channel is formed on the side portion of the gate trench when the device is turned on, the outer peripheral portion having a semiconductor surface disposed at a depth above the depth of the gate trench, and further including a voltage-resistant structure having a semiconductor region of a second conductivity type formed on the semiconductor surface of the outer peripheral portion.

[0014] According to this structure, a breakdown voltage structure can be formed at a depth equal to or greater than the depth of the gate trench. This allows the thickness of the semiconductor layer from the bottom of the gate trench to the back side of the semiconductor layer to be greater than the thickness of the breakdown voltage structure from the semiconductor region to the back side. As a result, the breakdown voltage structure can stably distribute the electric field applied between the surface and back sides of the semiconductor layer. Therefore, a stable electric field distribution can be formed in the semiconductor layer regardless of the depth of the gate trench, thus effectively buffering the concentration of the electric field at the bottom of the gate trench.

[0015] The semiconductor device may further include a surface insulating film disposed across the unit portion and the outer peripheral portion, and formed to be thinner in the unit portion than in the outer peripheral portion.

[0016] Based on this structure, by selectively thinning the surface insulating film of the unit portion, for example when an opening (contact hole, etc.) is formed in the surface insulating film, the step difference (unevenness) between the surface of the surface insulating film and the surface of the unit portion (device surface) can be reduced. Therefore, when a surface metal layer is formed on the surface insulating film by embedding metal into the opening, the flatness of the surface metal layer can be improved. Thus, for example, when bonding leads to the surface metal layer, the adhesion between the surface metal layer and the leads can be improved. As a result, the leads can be bonded well, thereby improving the reliability of the lead bonding. Furthermore, the excellent flatness of the surface metal layer prevents damage to the device from ultrasonic vibrations and pressure during lead bonding, thereby preventing a decrease in assembly yield.

[0017] On the other hand, the thickness of the surface insulating film on the outer periphery can be designed separately from the thickness of the surface insulating film on the unit portion. Therefore, by designing a thickness that does not affect the electric field distribution on the outer periphery, the withstand voltage characteristics can be maintained. That is, according to this structure, while improving the flatness of the surface metal layer, it is possible to prevent changes in the withstand voltage characteristics or poor withstand voltage caused by such changes.

[0018] The semiconductor device may further include a gate finger for making contact with the gate electrode, and the gate trench includes a linear trench that cuts across the gate finger below the gate finger.

[0019] According to this structure, since the corners of the trenches (e.g., the corners of the intersections of lattice trenches) that are prone to concentrate electric field when the gate voltage is applied are not located below the gate finger, the reliability and withstand voltage of the gate insulating film can be improved.

[0020] The gate trench may also include: an inner trench in which the channel is formed on its side when the device is turned on; and an outer trench formed by an extension of the inner trench and disposed on the outside relative to the inner trench, the semiconductor device further including a layer of a second conductivity type formed on the side and bottom of the outer trench.

[0021] Based on this structure, a depletion layer can be generated at the junction (pn junction) between the second conductivity layer and the semiconductor layer by a layer of a second conductivity type different from that of the semiconductor layer. Furthermore, this depletion layer keeps the equipotential surface away from the outer trench, thus buffering the electric field applied to the bottom of the outer trench. Therefore, damage to the bottom of the outer trench can be prevented.

[0022] The semiconductor device may further include: a gate finger for making contact with the gate electrode, the gate trench being selectively formed in a region below the gate finger, and the semiconductor device further including a high-concentration layer of a first conductivity type, the high-concentration layer being formed on the semiconductor surface of the semiconductor layer in the region below where the gate trench is not formed, and containing an impurity concentration higher than that of the semiconductor layer.

[0023] Based on this structure, the oxidation rate of a high-concentration layer with a high impurity concentration can be faster than that of a semiconductor layer with a lower concentration. Therefore, when forming the gate insulating film using thermal oxidation, a thicker oxide film can be selectively formed on the upper part of the gate trench in the region below the gate finger. As a result, the electric field applied to the upper edge of the gate trench is reduced when a gate voltage is applied, thereby preventing insulation damage to the gate insulating film.

[0024] The unit portion may also include: a source region of a first conductivity type disposed in a manner exposed on the surface of the semiconductor layer; a channel region of a second conductivity type disposed in a manner connected to the source region and forming the channel when turned on; a drain region of the first conductivity type disposed in a manner connected to the channel region; a second trench selectively formed on the surface of the semiconductor layer in a source portion divided in a manner including the source region; and a channel contact region of the second conductivity type selectively disposed at the bottom of the second trench and electrically connected to the channel region.

[0025] The unit portion may also include: a source region of a first conductivity type disposed in a manner exposed on the surface of the semiconductor layer; a channel region of a second conductivity type disposed in a manner connected to the source region and forming the channel when turned on; a drain region of the first conductivity type disposed in a manner connected to the channel region; a second trench selectively formed on the surface of the semiconductor layer in a source portion divided in a manner including the source region; a trench embedding portion embedded in the second trench; and a channel contact region of the second conductivity type selectively disposed on the source portion at a position higher than the bottom of the second trench and electrically connected to the channel region.

[0026] According to this structure, the concentration of the equipotential surface near the bottom of the gate trench can be prevented by the second trench, and the potential gradient near the bottom can be mitigated. Therefore, the concentration of the electric field at the bottom of the gate trench can be buffered.

[0027] Furthermore, the presence of a trench embedding portion in the second trench reduces the step difference (unevenness) between the source portion and other portions on the surface of the semiconductor layer (device surface). This improves the flatness of the surface metal layer when forming it on the device surface. Consequently, the adhesion between the surface metal layer and the lead is improved, for example, when bonding leads to the surface metal layer. As a result, the leads can be bonded well, thus improving the reliability of the lead bonding. Moreover, due to the excellent flatness of the surface metal layer, damage to the device from ultrasonic vibrations and pressure can be prevented during lead bonding, thereby preventing a decrease in assembly yield.

[0028] Furthermore, the channel contact area is positioned higher than the bottom of the second trench, so even if a second trench is formed, reliable contact with the channel region can be achieved through this channel contact area. That is, while improving the flatness of the surface metal layer, it is possible to prevent degradation of device performance such as gate withstand voltage and channel region contact.

[0029] The trench embedment may also consist of an insulating film formed on the inner surface of the second trench and a polycrystalline silicon layer embedded inside the insulating film.

[0030] Based on this structure, for example, when a surface insulating film made of SiO2 is formed on the surface of the semiconductor layer, and the surface insulating film is selectively etched to expose the source portion from the contact hole, the polysilicon layer buried in the second trench can be used as an etch barrier layer. Therefore, the control of the contact etching process can be simplified.

[0031] The insulating film can also be composed of any one of SiO2, AlON, Al2O3, SiO2 / AlON, SiO2 / AlON / SiO2, SiO2 / SiN, and SiO2 / SiN / SiO2.

[0032] Based on this structure, for example, the gate insulating film and the insulating film in the second trench can be formed in the same process, thereby enabling the gate insulating film to be constructed using the materials illustrated above. In this case, if a high dielectric constant (High-k) film such as AlON or Al2O3 is used to construct the gate insulating film, the gate withstand voltage can be improved, and the reliability of the device can be enhanced.

[0033] The insulating film may also have a SiO2 film containing nitrogen (N).

[0034] Based on this structure, for example, by forming the gate insulating film and the insulating film in the second trench in the same process, the gate insulating film can be formed using a material having a SiO2 film containing nitrogen (N). This gate insulating film can improve channel mobility.

[0035] The insulating film may also be formed such that the bottom of the second trench is thicker than the portion of the side of the second trench.

[0036] Based on this structure, for example, by forming the gate insulating film and the insulating film in the second trench in the same process, the gate insulating film can be made thicker, for example, at the bottom of the gate trench than at the side of the gate trench. This improves the withstand voltage at the bottom of the gate trench.

[0037] The polycrystalline silicon layer can also be made of n ＋ It is composed of polycrystalline silicon.

[0038] Based on this structure, for example, by forming the gate electrode and the polysilicon layer in the second trench in the same process, it is possible to use n ＋ The gate electrode is made of polycrystalline silicon. ＋ Polycrystalline silicon has a relatively low chip resistance, which enables high-speed switching of transistors.

[0039] The trench embedment may also be composed of an insulating layer backfilled into the second trench.

[0040] According to this structure, since the second trench is filled with an insulating layer, leakage current flowing through the second trench can be prevented or reduced.

[0041] The insulating layer can also be composed of SiO2. In this case, the insulating layer can also be composed of SiO2 containing phosphorus (P) or boron (B).

[0042] Based on this structure, the melting point of SiO2 decreases due to the presence of phosphorus or boron, thus simplifying the embedding process of the insulating layer. For example, PSG (phosphosilicate glass) or PBSG (phosphosborosilicate glass) can be used as such SiO2.

[0043] The trench embedment can also be composed of a polycrystalline silicon layer backfilled in the second trench.

[0044] Based on this structure, for example, when a surface insulating film made of SiO2 is formed on the surface of the semiconductor layer, and the surface insulating film is selectively etched to expose the source portion from the contact hole, the polysilicon layer buried in the second trench can be used as an etch barrier layer. Therefore, the control of the contact etching process can be simplified.

[0045] The polycrystalline silicon layer can also be made of p ＋ It is composed of polycrystalline silicon.

[0046] Based on this structure, for example, when the channel region and the channel contact region are p-type, p can be utilized. ＋ A polysilicon layer of this type is used to electrically connect these regions. This shortens the current path length between the channel region and the channel contact region, thus reducing their base resistance. Consequently, latch-up is effectively prevented. Furthermore, when the channel contact region is in contact with the polysilicon layer, the contact resistance between them is reduced. This reduction in contact resistance also contributes to a reduction in the base resistance between the channel region and the channel contact region.

[0047] The semiconductor device of the present invention may further include a layer of a second conductivity type formed on the bottom and sides of the second trench in a manner continuous with the channel region and the channel contact region.

[0048] Based on this structure, a depletion layer can be generated by the junction (pn junction) between the second conductivity layer and the semiconductor layer through a layer of a second conductivity type different from that of the semiconductor layer. Moreover, this depletion layer moves the equipotential surface away from the gate trench, thus further buffering the electric field applied to the bottom of the gate trench.

[0049] The gate electrode may also include: a base film made of polysilicon formed on the inner surface of the gate trench; and an embedded metal comprising at least one of Mo, W, Al, Pt, Ni and Ti embedded inside the base film.

[0050] Based on this structure, the gate resistance can be reduced by embedding metal, thus enabling the transistor to switch at a higher speed.

[0051] The semiconductor device may further include a surface metal layer made of a metal containing copper (Cu) disposed on the surface side of the semiconductor layer. In this case, the surface metal layer may also contain an Al-Cu alloy.

[0052] Based on this structure, the sheet resistance of the surface metal layer can be reduced, thereby increasing the current density.

[0053] In the unit section, multiple unit cells can be divided by the gate trench in a grid pattern or by the gate trench in a stripe pattern.

[0054] The semiconductor layer can also be made of SiC, GaN or diamond. Attached Figure Description

[0055] Figure 1 This is a schematic plan view of a semiconductor device according to the first embodiment of the present invention.

[0056] Figure 2 yes Figure 1 An enlarged view of the main part, showing a portion in perspective.

[0057] Figure 3 Show Figure 2 The cross-sectional structure of the semiconductor device on section III-III.

[0058] Figure 4 Show Figure 2 The cross-sectional structure of the semiconductor device on the IV-IV section.

[0059] Figure 5 Show Figure 2 The cross-sectional structure of a semiconductor device on a V-V cross section.

[0060] Figure 6 It is shown Figure 2 The cross-sectional structure of the semiconductor device on the VI-VI section.

[0061] Figure 7 It is shown in magnification Figure 3 The diagram of the unit section.

[0062] Figure 8 This is a diagram showing a first modified example of the unit portion.

[0063] Figure 9 This is a diagram showing a second modified example of the unit portion.

[0064] Figure 10 This is a diagram showing a third modified example of the unit portion.

[0065] Figure 11This is a diagram showing the fourth modified example of the unit portion.

[0066] Figure 12 This is a diagram showing the fifth modified example of the unit portion.

[0067] Figure 13 This is a schematic cross-sectional view of a semiconductor device according to the second embodiment of the present invention.

[0068] Figure 14 This is a schematic cross-sectional view of a semiconductor device according to the second embodiment of the present invention.

[0069] Figure 15 This is a schematic cross-sectional view of the semiconductor device involved in the reference method.

[0070] Figure 16 This is a schematic cross-sectional view of the semiconductor device involved in the reference method.

[0071] Figure 17 This is a schematic cross-sectional view of a semiconductor device according to the third embodiment of the present invention.

[0072] Figure 18 This is a schematic cross-sectional view of a semiconductor device according to the third embodiment of the present invention.

[0073] Figure 19 This is a schematic cross-sectional view of a semiconductor device according to the fourth embodiment of the present invention.

[0074] Figure 20 This is a schematic cross-sectional view of a semiconductor device according to the fourth embodiment of the present invention.

[0075] Figure 21 This is a schematic cross-sectional view of a semiconductor device according to the fifth embodiment of the present invention. Detailed Implementation

[0076] <First Embodiment>

[0077] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0078] Figure 1 This is a schematic plan view of a semiconductor device according to the first embodiment of the present invention.

[0079] Semiconductor device 1 includes a SiC-based MISFET (Metal Insulator Field Effect Transistor). The external shape of semiconductor device 1 is as follows: Figure 1 The image shown is a top-view view of a square-shaped chip. Regarding the dimensions of the chip-shaped semiconductor device 1, Figure 1The lengths in the top, bottom, left, and right directions of the paper are approximately several millimeters. In the semiconductor device 1, a unit portion 2 and an outer peripheral portion 3 are disposed around the unit portion 2. In this embodiment, the outer peripheral portion 3 is provided in a ring shape to surround the unit portion 2; however, if it is located in a region outside the chip relative to the unit portion 2, it does not need to be specifically ring-shaped.

[0080] Semiconductor device 1 includes source pad 4, gate pad 5 and gate finger 6.

[0081] The source pad 4 is disposed in the upper region of the unit portion 2. In this embodiment, the source pad 4 is formed in a square shape when viewed from above, for example, so as to cover approximately the entire region of the unit portion 2. At the periphery of the source pad 4, a removed region 7 is formed along the outer periphery 3, surrounding the central region of the source pad 4. Figure 1 (The cross-hatching portion). A portion of region 7 is selectively recessed towards the central region of the source pad 4. The entire recess is configured in the upper region of the cell section 2, where the gate pad 5 is located.

[0082] The gate finger 6 extends from the gate pad 5 along the outer periphery 3 and throughout the entire removal region 7 in a position relative to the boundary between the cell portion 2 and the outer periphery 3 on the side of the outer periphery 3. In this embodiment, a pair of gate fingers 6 are formed in a symmetrical shape relative to the gate pad 5. Moreover, in this embodiment, for example, the boundary between the aforementioned cell portion 2 and the outer periphery 3 is set along the portion of the removal region 7 that is inward relative to the gate finger 6 (and...). Figure 2 (The boundary L is the same).

[0083] In unit 2, a gate trench 8 is further formed. In this embodiment, the gate trench 8 is selectively formed in the region below the source pad 4, avoiding the region below the gate pad 5. In this region, the gate trench 8 is formed in such a way that it divides into multiple unit cells 9. The pattern of the gate trench 8 is as follows: Figure 1 As shown, the pattern can be either grid-like or striped. Therefore, in unit section 2, multiple unit cells 9 are arranged regularly in a matrix (rows and columns) or striped (linear) pattern. Furthermore, although not shown, the pattern of the unit cells 9 can also be other shapes such as a honeycomb pattern.

[0084] Next, the internal structure of the unit section 2 and the peripheral section 3 of the semiconductor device 1 will be explained.

[0085] Figure 2 yes Figure 1 The main part is enlarged and a portion is shown in perspective. Specifically, the structure of the area below the source pad 4 and gate finger 6 is shown in solid lines, and the source pad 4 and gate finger 6 are shown in dashed lines. Figure 3 Show Figure 2The cross-sectional structure of the semiconductor device in section III-III. Figure 4 Show Figure 2 The cross-sectional structure of the semiconductor device in section IV-IV. Figure 5 Show Figure 2 The cross-sectional structure of a semiconductor device in a V-V section. Figure 6 Show Figure 2 The cross-sectional structure of the semiconductor device in the VI-VI section.

[0086] Semiconductor device 1 includes n ＋ Type SiC (e.g., concentration of 1×10⁻⁶) 18 ~1×10 21 cm －3 A substrate (not shown) composed of n; and a substrate formed on the substrate by n － Type SiC (e.g., concentration of 1×10⁻⁶) 15 ~1×10 17 cm －3 n constituted － Type epitaxial layer 10. n － The epitaxial layer 10 is a layer formed by epitaxial growth of SiC on the surface of a substrate. In this embodiment, the substrate and n － The epitaxial layer 10 is shown as an example of the semiconductor layer of the present invention. Furthermore, the thickness of the substrate is, for example, about 250 μm to 350 μm, n － The thickness of the epitaxial layer 10 is approximately 3 μm to 20 μm.

[0087] n － The epitaxial layer 10 has a semiconductor surface 11 with a height difference formed by selectively excavating a portion of it. In this embodiment, the height difference of the semiconductor surface 11 is formed by selectively forming gate trenches 8 and source trenches 33 (described later) in the cell portion 2 and the outer peripheral portion 3, and selectively forming low-level portions 12 in the outer peripheral portion 3. Hereinafter, the semiconductor surface 11 that maintains a height position after epitaxial growth without forming gate trenches 8, source trenches 33, and low-level portions 12 is called the base surface 11B, and the semiconductor surface 11 that is formed at a relatively low height position relative to the base surface 11B is called the low surface 11L.

[0088] In this embodiment, the gate trench 8 includes: an inner trench 13 serving as the gate of a MISFET; an outer trench 14 disposed on the outer side relative to the inner trench 13; and a contact trench 15 extending from the outer trench to the outer peripheral portion 3 and becoming a contact portion with the gate electrode 16 (described later). These trenches 13 to 15 are integrally formed in a manner that allows them to communicate with each other.

[0089] like Figure 2 As shown, the inner groove 13 is formed by dividing multiple unit units 9 into a grid-like structure where multiple linear grooves intersect each other. The ends of the lines in the inner groove 13 are connected to each other by the outer groove 14. That is, the outer groove 14 is formed to surround the inner groove 13 and spans across the ends of the adjacent lines in the inner groove 13.

[0090] The contact grooves 15 are formed by extensions of the lines of the inner grooves 13 and are arranged in a linear shape, with multiple grooves spaced apart from each other along the boundary L between the unit portion 2 and the outer peripheral portion 3. Furthermore, as... Figure 2 As shown, the contact trench 15 does not need to be provided on every line of the inner trench 13; for example, it can be provided on every other line of the inner trench 13. This linear contact trench 15 is formed in a manner that cuts across the gate finger 6 in the region below the gate finger 6. In this embodiment, the end portion of the contact trench 15 is positioned outwards from the gate finger 6. That is, the end portion of the contact trench 15 extends outwards from the gate finger 6.

[0091] Furthermore, a gate electrode 16, for example made of polysilicon, is buried in the gate trench 8, and a gate insulating film 17 is disposed between the gate electrode 16 and the n － Between the 10 epitaxial layers.

[0092] For example, Figure 3 and Figure 4 As shown, the gate electrode 16 is embedded in the base surface 11B within the inner trench 13 and outer trench 14 formed at a location separated from the region below the gate finger 6. Thus, the gate electrode 16 is also formed in a lattice pattern, with the upper surface of each unit cell 9 exposed and not covered by the gate electrode 16. On the other hand, the contact trench 15 formed in the region below the gate finger 6 has a covering portion 18 formed from the opening end of the contact trench 15 in a manner that selectively covers the base surface 11B. In this embodiment, the covering portion 18 is as follows... Figure 2 As shown, contact trenches 15 are formed along the gate fingers 6 in a tangential manner. Figure 5 and Figure 6 As shown, in the covering part 18 and n － The epitaxial layers 10 are also separated by a gate insulating film 17.

[0093] In unit 2, gate electrode 16 controls the formation of the inversion layer (channel) in unit cell 9. That is, the semiconductor device 1 has a so-called trench gate structure MISFET.

[0094] In this embodiment, the low-level portion 12 is formed covering the entire circumference of the outer peripheral portion 3, thereby surrounding the unit portion 2. The low-level portion 12 is formed at a depth greater than or equal to the depth of the gate trench 8. Therefore, in the outer peripheral portion 3, the bottom surface (low surface 11L) of the low-level portion 12 is positioned at a depth greater than or equal to the bottom surface (low surface 11L) of the gate trench 8. Its depth, for example, is 0.7 μm to 5 μm relative to the depth of the gate trench 8, based on the base surface 11B.

[0095] Moreover, n-type and p-type impurity regions are selectively formed on the semiconductor surface 11 with such a height difference.

[0096] Specifically, in n － The surface portion of the epitaxial layer 10 has a p-type well 19 formed across the unit portion 2 and the outer peripheral portion 3 (for example, with a concentration of 1×10⁻⁶). 16 ~1×10 19 cm －3 On the other hand, in n － The region below the p-type well 19 in the epitaxial layer 10 is n － Type-type drain region 20. In this embodiment, as... Figure 3 As shown, the p-type well 19 is formed continuously from the cell portion 2 through the region below the gate finger 6 to the low-order portion 12 of the outer peripheral portion 3, with its bottom mimicking the base surface 11B. Thus, the p-type well 19 is exposed on the side of the low-order portion 12.

[0097] In p-type trap 19, such as Figure 3 , Figure 5 and Figure 6 As shown, n is formed in the region below gate finger 6. ＋ Type region 21, and in n － The base surface 11B of the epitaxial layer 10 is exposed. ＋ Type 21 is based on n － The epitaxial layer 10 contains a high concentration region of n-type impurities (e.g., a concentration of 1 × 10⁻⁶). 18 ~1×10 21 cm －3 In this implementation, such as Figure 3 As shown, n ＋ The type region 21 is formed continuously from the cell portion 2 through the region below the gate finger 6 to the lower-order portion 12 of the outer peripheral portion 3, such that its bottom mimics the base surface 11B. Thus, n ＋ Type region 21 is exposed on the side of the lower part 12.

[0098] In n － In the epitaxial layer 10, such as Figure 4-6As shown, a p-type layer 22 (e.g., with a concentration of 1×10⁻⁶) is formed in the region below the gate finger 6 in a manner continuous with the p-type well 19. 16 ~1×10 19 cm －3 In this embodiment, the p-type layer 22 is formed across the bottom and sides (including the side of the end portion) of the contact groove 15, and its internal region is in contact with the contact groove 15 (exposed within the contact groove 15). In addition, the p-type layer 22 is formed to be thicker at the bottom of the contact groove 15 than at the sides of the contact groove 15.

[0099] Additionally, in n － In the epitaxial layer 10, such as Figure 3 and Figure 4 As shown, a p-type layer 23 (e.g., with a concentration of 1×10⁻⁶) is formed in the lower-order portion 12 in a manner continuous with the p-type well 19, serving as an example of the pressure-resistant structure of the present invention. 16 ~1×10 19 cm －3 In this embodiment, the p-type layer 23 is formed across the bottom and sides of the lower-level portion 12, and its internal region is in contact with the lower-level portion 12 (exposed within the lower-level portion 12). A p-type layer 23 is formed on its surface. ＋ Type-trap contact region 24 (e.g., concentration of 1×10⁻⁶) 18 ~1×10 21 cm －3 In this embodiment, p ＋ The trap contact region 24 is formed on the low surface 11L of the low-level portion 12 and is formed in a ring shape to surround the unit portion 2.

[0100] Furthermore, a p-type protective ring 25 (e.g., with a concentration of 1×10⁻⁶) is formed on the outer side of the p-type layer 23 in the lower-order portion 12, which is an example of the pressure-resistant structure of the present invention. 16 ~1×10 19 cm －3 In this embodiment, multiple p-type protective rings 25 are formed in the lower surface 11L of the lower-level portion 12, spaced apart from each other in a manner that surrounds the unit portion 2.

[0101] In n － A surface insulating film 26 is formed on the surface of the epitaxial layer 10, spanning the unit portion 2 and the outer peripheral portion 3. The surface insulating film 26 is made of an insulating material such as silicon oxide (SiO2). In this embodiment, the surface insulating film 26 forms the inner portion 27 of the unit portion 2 with the same thickness as the outer portion 28 on the outer peripheral portion 3, for example, about 5500 Å to 20000 Å. Although this surface insulating film 26 is not... Figure 2As shown in the figure, but when a multilayer wiring structure is configured on it, it can also be called an interlayer insulating film.

[0102] The surface insulating film 26 has a structure for n － The surface of the epitaxial layer 10 is uniformly integrated to form each unit cell 9, gate electrode 16 (masking portion 18) and p ＋ Contact holes 29 to 31 are selectively exposed in the trap contact area 24.

[0103] Active electrode pads 4 and gate fingers 6 are formed on the surface insulating film 26.

[0104] The source pad 4 connects to all unit cells 9 via contact holes 29 and 31. ＋ Type 34 contact area (described later) and n ＋ Type source pole region 32 (described later), and p ＋ The well contact regions 24 are connected in batches. That is, the source pad 4 becomes a common electrode for all unit cells 9. Furthermore, as the material of the source pad 4, a metal containing copper (Cu) can be used, and a metal containing an Al-Cu alloy is more preferred. This reduces the sheet resistance of the source pad 4, thereby increasing the current density. Additionally, the thickness (n) of the source pad 4... － The distance from the base surface 11B to the surface of the source pad 4 of the epitaxial layer 10 is, for example, 4 μm to 5 μm. Furthermore, the source pad 4 can also be located at the n... － The connecting portion of the epitaxial layer 10 has a contact metal, for example, composed of a stacked structure (Ti / TiN) of titanium (Ti) and titanium nitride (TiN).

[0105] The gate finger 6 is connected to the gate electrode 16 (cover portion 18) via the contact hole 30. Furthermore, the gate finger 6 and the gate pad 5, like the source pad 4, can be made of a metal containing copper (Cu), and more preferably a metal containing an Al-Cu alloy. By using the same material as the source pad 4, the source pad 4, the gate pad 5, and the gate finger 6 can be formed simultaneously.

[0106] Next, the construction of unit part 2 will be explained in more detail. Figure 7 It is shown in magnification Figure 3 Figure 2 of unit part.

[0107] In unit section 2, as described above, multiple unit cells 9, each performing transistor operation, are divided into a lattice structure by gate trenches 8 (inner trench 13 and outer trench 14). Each unit cell 9 contains annular n ＋ Type source region 32, n ＋The annular source trench 33 (second trench) surrounded by the source region 32, and the p-shaped islands formed inside the source trench 33. ＋ Contact area of ​​the channel type 34. ＋ The contact region 34 is surrounded by a source trench 33. Additionally, regarding the size of each unit cell 9, for example... Figure 7 The lengths of the paper in the top, bottom, left, and right directions are approximately 3 to 10 μm.

[0108] Specifically, in unit 2, n is formed on the surface of p-type well 19. ＋ Type source pole region 32, in n － The base surface 11B of the p-type epitaxial layer 10 is exposed. Additionally, a portion within the cell portion 2 of the p-type well 19 is aligned with the n-type epitaxial layer. ＋ The p-type source region 32 is configured to be connected in a way that forms a channel in the p-type channel region 35 when the transistor is operating.

[0109] Furthermore, the gate trench 8 and the source trench 33 are connected through n ＋ p-type source region 32 and p-type channel region 35 (p-type well 19), and to achieve n － The drain region 20 is formed in a manner similar to the gate trench 8. In this embodiment, the gate trench 8 and the source trench 33 are formed with the same width and the same depth, but they may also have different depths. For example, the source trench 33 may be either shallower or deeper than the gate trench 8.

[0110] Through the gate trench 8 and the source trench 33, each unit cell 9 is separated into a columnar portion 36 surrounded by the source trench 33 and an annular portion 37 disposed between the source trench 33 and the gate trench 8 and spaced apart from the columnar portion 36 by the source trench 33. In this embodiment, the width W1 (distance between the source trench 33 and the gate trench 8) of the annular portion 37 is, for example, 0.5 μm to 2.0 μm.

[0111] At the top of columnar section 36, to n － The base surface 11B of the epitaxial layer 10 is exposed to form a p-type epitaxial layer. ＋ Type 34 channel contact area (e.g., concentration of 1×10⁻⁶) 18 ~1×10 21 cm －3 Therefore, p ＋ The contact area 34 of the channel forms part of the side of the source trench 33. ＋ In this embodiment, the deepest part of the channel contact area 34 is located higher than the bottom of the source trench 33, but this location does not need to be specifically defined. As long as p ＋ The uppermost part of the groove contact area 34 (in this embodiment, at n) －The exposed portion of the base surface 11B of the epitaxial layer 10 is positioned higher than the bottom of the source trench 33 and is thus able to make contact. This deepest part can be at the same depth as the bottom of the source trench 33 or deeper.

[0112] n are sequentially formed in the annular portion 37 from the base surface 11B side. ＋ The n-type source region 32 and the p-type channel region 35. Therefore, n ＋ The p-type source region 32 and the p-type channel region 35 each form a portion of the side surface of the gate trench 8. ＋ In this embodiment, the source pole region 32 is in conjunction with n ＋ Type 21 (refer to) Figure 3-6 ) and p ＋ The contact area of ​​the type-shaped channel is formed at the same depth as 34.

[0113] Additionally, in n － The epitaxial layer 10 is connected to the p-type channel region 35 and p ＋ The contact area 34 of the channel and the aforementioned p-type layer 22 (refer to) Figure 4-6 p-type layers 38 are formed in a continuous manner (e.g., at a concentration of 1 × 10⁻⁶). 16 ~1×10 19 cm －3 The p-type layer 38 is formed across the columnar portion 36 and the annular portion 37 via the bottom of the source trench 33, and its internal region is in contact with the source trench 33 (exposed within the source trench 33). The p-type layer 38 connects to the p-type channel region 35 on the side of the source trench 33 in the annular portion 37, and connects to the p-type channel region 35 on the side of the source trench 33 in the columnar portion 36. ＋ The p-type channel contact area 34 is connected. Therefore, the p-type channel area 35 and p... ＋ The p-type channel contact area 34 is electrically connected via the p-type layer 38.

[0114] Additionally, the p-type layer 38 is also formed across the outer periphery of the outer trench 14 via the bottom of the outer trench 14, and in this outer periphery, it connects to the p-type well 19 extending towards the outer periphery 3. Furthermore, as... Figure 2 and Figure 4 As shown, the p-type layer 38 can also be formed only at the intersections of the lines constituting the inner trench 13. Furthermore, the intersections of the inner trench 13 do not form channels at each corner of each unit cell 9 during conduction, or even if a channel is formed, the current flowing through it is negligible. Therefore, forming the p-type layer 38 in a manner that connects it to the p-type channel region 35 at the intersection has almost no impact on the device performance.

[0115] Furthermore, like p-type layer 22, p-type layer 38 is formed to be thicker at the bottom of gate trench 8 and source trench 33 than at the sides of source trench 33. However, in pillar portion 36, the sides of source trench 33 are surrounded by source trench 33, and ions are implanted from its surroundings. Therefore, to fill p... ＋ The lower part of the channel contact area 34 is formed thicker than the bottom part of the source trench 33.

[0116] Furthermore, in this embodiment, the p-type layer 38 is formed such that it does not connect with the gate trench 8 at the intersection of the inner trench 13 and the portion other than the outer trench 14 (it is spaced apart from the gate trench 8), and it covers the entire circumference of the annular portion 37 surrounded by the gate trench 8. Thus, in each unit cell 9, n － The drain region 20 is configured on a portion of the side of the gate trench 8, thus ensuring the current path during channel formation.

[0117] In this embodiment, the gate trench 8 is formed in a cross-sectional shape that is approximately U-shaped, having a side surface and a bottom surface. A gate insulating film 17 is formed on the inner surface (side surface and bottom surface) of the gate trench 8 such that one surface and the other surface are aligned with the inner surface of the gate trench 8.

[0118] The gate insulating film 17 is formed to be thicker at the bottom of the gate trench 8 than at the sides. As in this embodiment, in a gate trench 8 that is approximately U-shaped in cross-section, the relatively thicker portion of the gate insulating film 17 is the portion that contacts the bottom surface of the gate trench 8, while the relatively thinner portion is the portion that contacts the sides of the gate trench 8. By thickening the insulating film at the bottom of the gate trench 8, where electric field concentration is easily caused, the withstand voltage at the bottom of the gate trench 8 can be improved. Furthermore, there are cases where the sides and bottom surfaces cannot be clearly distinguished depending on the shape of the gate trench 8; however, in such cases, it is sufficient to make the gate insulating film 17 relatively thicker at the surface that contacts the surface of the gate trench 8 in the direction intersecting the depth direction.

[0119] Furthermore, the inner side of the gate insulating film 17 is backfilled by the gate electrode 16. In this embodiment, the gate electrode 16 is positioned such that its upper surface is flush with n － The base surface 11B of the p-type epitaxial layer 10 is buried in a substantially coplanar manner in the gate trench 8. The gate electrode 16 is positioned opposite the p-type channel region 35 via the gate insulating film 17. In each unit cell 9, by controlling the voltage applied to the gate electrode 16, an annular channel is formed in the p-type channel region 35 along the periphery of the unit cell 9. Furthermore, it is possible to extend the channel along the side of the gate trench 8 towards the n-type channel region 35. － The drain current flowing through the base surface 11B of the epitaxial layer 10 flows through the channel n ＋ Type source region 32. Thus, the transistor operation of semiconductor device 1 can be performed.

[0120] Similarly, in this embodiment, the source trench 33 is formed in a roughly U-shaped cross-section having a side surface and a bottom surface. On the inner surface (side surface and bottom surface) of the source trench 33, a source trench insulating film 39 is formed such that one surface and the other surface are along the inner surface of the source trench 33.

[0121] The source trench insulating film 39 is formed such that it is thicker at the bottom of the source trench 33 than at the sides. Furthermore, due to the shape of the source trench 33, there are cases where the sides and bottom cannot be clearly distinguished; however, in such cases, the source trench insulating film 39 only needs to be relatively thick at the surface that intersects the depth direction of the source trench 33. Moreover, the inner side of the source trench insulating film 39 is backfilled by the trench embedding layer 40. In this embodiment, the trench embedding layer 40 is configured such that its upper surface is flush with n － The base surface 11B of the epitaxial layer 10 is buried in the source trench 33 in a manner that is approximately coplanar.

[0122] In this embodiment, the gate insulating film 17 and the source trench insulating film 39 are made of the same material, and the gate electrode 16 and the trench buried layer 40 are made of the same material.

[0123] For example, any of the following films can be used as materials for the gate insulating film 17 and the source trench insulating film 39: SiO2, AlON, Al2O3, SiO2 / AlON, SiO2 / AlON / SiO2, SiO2 / SiN, and SiO2 / SiN / SiO2. A film having a nitrogen (N)-containing SiO2 film is more preferred. Furthermore, SiO2 / AlON refers to a laminated film of SiO2 (bottom side) and AlON (top side). If the gate insulating film 17 is constructed using a high-k dielectric constant (High-k) film such as AlON or Al2O3, the gate withstand voltage can be improved, and the reliability of the device can be enhanced. Moreover, if the gate insulating film 17 is constructed using a material having a nitrogen (N)-containing SiO2 film, the channel mobility can also be improved.

[0124] Polysilicon can be used as the material for the gate electrode 16 and the trench buried layer 40, and n-silicon is more preferably used. ＋ Type n polycrystalline silicon. Due to n ＋ Polycrystalline silicon has a relatively low chip resistance, which enables transistors to switch at high speeds.

[0125] Furthermore, the gate insulating film 17 and the source trench insulating film 39 can also be made of different materials. Similarly, the gate electrode 16 and the trench buried layer 40 can also be made of different materials.

[0126] Contact holes 29 formed on the surface insulating film 26, relative to n －The surface of the epitaxial layer 10 is integral, making the source trench 33 and n ＋ The source region 32 is selectively exposed. In this embodiment, the source portion 41 is divided in each unit cell 9 by contact holes 29.

[0127] Next, explain the use of Figure 1-7 The manufacturing method of the semiconductor device 1 is described.

[0128] In the manufacture of semiconductor device 1, SiC crystals are grown on the surface of a SiC substrate (not shown) by epitaxial growth methods such as CVD, LPE, and MBE, while simultaneously doping with n-type impurities. This forms an n-type impurity on the SiC substrate. － Type epitaxial layer 10. At this time, n － The growth surface of the n-type epitaxial layer 10 is the base surface 11B. In addition, as n-type impurities, such as N (nitrogen), P (phosphorus), As (arsenic) and the like can be used.

[0129] Next, from n － The base surface 11B of the epitaxial layer 10 is selectively ion-implanted with p-type impurities. This forms a p-type well 19 (p-type channel region 35). Furthermore, p-type impurities such as Al (aluminum) and B (boron) can be used as p-type impurities. Additionally, simultaneously with the formation of the p-type well 19, n-type impurities are also selectively ion-implanted. － Type 20 drain region forms n － The remaining portion of the epitaxial layer 10.

[0130] Next, from n － The base surface 11B of the epitaxial layer 10 is selectively ion-implanted with n-type impurities. This simultaneously forms n-type impurities. ＋ Type region 21 and n ＋ Type source pole region 32.

[0131] Next, n is selectively etched using a mask with openings in the areas where the gate trench 8, source trench 33, and low-order portion 12 should be formed. － Type epitaxial layer 10. Therefore, n － The epitaxial layer 10 is selectively dry etched to form a gate trench 8, a source trench 33, and a low-level portion 12, while simultaneously forming a low surface 11L. Meanwhile, through the gate trench 8, n － The epitaxial layer 10 is divided into multiple unit cells 9. Each unit cell 9 has a columnar portion 36 and an annular portion 37. As the etching gas, a mixed gas containing SF6 (sulfur hexafluoride) and O2 (oxygen) (SF6 / O2 gas) or a mixed gas containing SF6, O2 and HBr (hydrogen bromide) (SF6 / O2 / HBr gas) can be used.

[0132] Furthermore, after performing the above etching, the lower-level portion 12 can be selectively etched further, with the lower surface 11L of the outer peripheral portion 3 located at a depth greater than that of the gate trench 8.

[0133] Next, from n － The semiconductor surface 11 of the epitaxial layer 10 is selectively ion-implanted with p-type impurities. For example, p-type impurities are used for n-type epitaxial layers. － The semiconductor surface 11 of the epitaxial layer 10 is implanted in a vertical direction. This simultaneously forms a p-type layer 22, a p-type layer 23, a p-type layer 38, and a p-type guard ring 25. Alternatively, these layers 22, 23, 38, and 25 can also be formed through their respective ion implantation processes.

[0134] Next, from n － p-type impurities are selectively ion-implanted onto the semiconductor surface 11 of the epitaxial layer 10. This simultaneously forms p-type impurities. ＋ Type-type channel contact area 34 and p ＋ Trap contact area 24.

[0135] Next, for example, at 1400℃~2000℃, n － The epitaxial layer 10 is heat-treated. Thus, it is implanted into the n... － The ions of p-type and n-type impurities in the epitaxial layer 10 are activated.

[0136] Next, for example, the gate insulating film 17 and the source trench insulating film 39 are formed simultaneously by thermal oxidation. Alternatively, when the gate insulating film 17 and the source trench insulating film 39 are composed of a high-k dielectric film, the film material can be deposited by CVD.

[0137] Next, for example, using CVD, polycrystalline silicon material doped with n-type impurities is transformed from n... － The polysilicon material is deposited above the epitaxial layer 10. Deposition of the polysilicon material continues until at least the gate trench 8 and source trench 33 are completely filled. Then, the deposited polysilicon material is patterned, thereby removing the polysilicon material outside the gate trench 8 (inner trench 13 and outer trench 14) and the source trench 33 in the cell portion 2, leaving polysilicon material in the peripheral portion 3 as a masking portion 18. At this time, the polysilicon material in the buried low-order portion 12 is completely removed. Thus, the gate electrode 16 and the trench buried layer 40 are simultaneously formed.

[0138] Next, for example, through CVD, insulating materials such as SiO2 are obtained from n － A surface insulating film 26 is deposited on top of the epitaxial layer 10.

[0139] Next, the surface insulating film 26 is selectively etched to form contact holes 29-31.

[0140] Next, for example, by sputtering, the metallic material is extracted from n － A type epitaxial layer 10 is deposited on top of it. Furthermore, by patterning this material, source pads 4, gate pads 5, and gate fingers 6 are simultaneously formed. Through the above processes, a... Figure 1-7 Semiconductor device 1 is shown.

[0141] As described above, according to the semiconductor device 1, the semiconductor surface 11 on which the p-type layer 23 and the p-type guard ring 25 are formed is a low surface 11L at a depth equal to or greater than the depth of the gate trench 8. This allows for a depth from the bottom of the gate trench 8 to the n... － The n up to the back side of the epitaxial layer 10 － The thickness of the p-type epitaxial layer 10 is greater than the thickness from the p-type layer 23 and the p-type protective ring 25 to the back surface. As a result, the p-type layer 23 and the p-type protective ring 25 of the outer peripheral portion 3 can stably share the force applied to the n-type epitaxial layer. － The electric field between the surface side and the back side of the epitaxial layer 10. Therefore, it is independent of the depth of the gate trench 8 and can achieve n － The epitaxial layer 10 forms a stable electric field distribution, thus effectively buffering the concentration of the electric field at the bottom of the gate trench 8.

[0142] In addition, such as Figure 2 As shown, although a gate trench 8 is formed in the region below the gate finger 6, it is only a linear contact trench 15 formed in a manner that crosses the gate finger 6, and the end of the contact trench 15 is disposed on the outer side than the gate finger 6. That is, since the corners of the trenches that are prone to concentrate electric field when a gate voltage is applied (e.g., the corners of the intersection of the inner trenches 13, etc.) are not disposed below the gate finger 6, the reliability and withstand voltage of the gate insulating film 17 can be improved.

[0143] In addition, such as Figure 7 As shown, the p-type layer 38 is formed by extending across the outer periphery of the outer trench 14 from its bottom. Therefore, the p-type layer 38 and the n-type layer can be combined. － Type epitaxial layer 10 (n) － A depletion layer is generated in the pn junction of the drain region 20. Furthermore, this depletion layer keeps the equipotential surface away from the outer trench 14, thus buffering the electric field applied to the bottom of the outer trench 14. Therefore, damage to the bottom of the outer trench 14 can be prevented.

[0144] In addition, such as Figure 5 and Figure 6 As shown, in the region below gate finger 6, in n － The semiconductor surface 11 (base surface 11B) of the epitaxial layer 10 has an n ＋ Type region 21. n ＋The oxidation rate of the semiconductor region of type n is higher than that of type n. － Because the semiconductor region is fast, when the gate insulating film 17 is formed by thermal oxidation, a thicker oxide film can be selectively formed on the upper part of the gate trench 8 (contact trench 15) in the region below the gate finger 6. As a result, the electric field applied to the upper edge of the contact trench 15 is reduced when the gate voltage is applied, thereby preventing the insulation of the gate insulating film 17 from being damaged.

[0145] In addition, such as Figure 7 As shown, a trench embedment layer 40 is embedded into the source trench 33 through the source trench insulating film 39. Therefore, in n － The surface of the epitaxial layer 10 (device surface) can reduce the step difference (unevenness) between the source portion 41 exposed from the contact hole 29 and other portions. This improves the flatness of the source pad 4 on the device surface. Therefore, for example, when bonding leads to the surface of the source pad 4, the adhesion between the source pad 4 and the leads can be improved. As a result, the leads can be bonded well, thus improving the reliability of the lead bonding. Furthermore, because the source pad 4 has good flatness, it can prevent damage to the device from ultrasonic vibration and pressure during lead bonding, and can prevent a decrease in assembly yield.

[0146] On the other hand, the source trench 33 prevents the concentration of the equipotential surface near the bottom of the gate trench 8, thereby mitigating the potential gradient near the bottom. Therefore, it buffers the concentration of the electric field at the bottom of the gate trench 8. Furthermore, p ＋ The channel contact region 34 is formed at the top of the columnar portion 36, positioned higher than the bottom of the source trench 33. Therefore, even if the source trench 33 is formed, the contact region 34 can still be connected via this contact region. ＋ The p-type channel contact region 34 reliably achieves contact with the p-type channel region 35. That is, while improving the flatness of the source pad 4, it is possible to prevent the degradation of device performance such as gate withstand voltage and contact with the p-type channel region 35.

[0147] Furthermore, in this embodiment, since a p-type layer 38 is formed around the source trench 33, the p-type layer 38 and the n-type layer 38 can interact. － A depletion layer is generated in the junction (pn junction) of the drain region 20. Moreover, since this depletion layer moves the equipotential surface away from the gate trench 8, it can further buffer the electric field applied to the bottom of the gate trench 8.

[0148] Furthermore, in this embodiment, a SiC device, which is less prone to latch-up than a Si device, is used, thus enabling p ＋ The p-type channel contact region 34 and the p-type channel region 35 are located at positions where they are separated from each other by the source trench 33. That is, in Si devices, since latch-up is more likely to occur, it is preferable to place the p-type channel contact region 34.＋ The p-type channel contact region 34 is positioned near the p-type channel region 35 to minimize the distance between these regions 34 and 35, thereby reducing the base resistance between these regions 34 and 35. On the other hand, in SiC devices such as this semiconductor device 1, latch-up is relatively difficult to cause, and considering the lower importance of the base resistance between regions 34 and 35, it is also possible to omit the p-type channel contact region 35. ＋ Type 34 channel contact area. Therefore, p ＋ The p-type channel contact region 34 and the p-type channel region 35 are located at positions separated from each other by the source trench 33, and these regions 34 and 35 can be electrically connected via a path through the bottom of the source trench 33.

[0149] Furthermore, since the source trench insulating film 39 is disposed on the outside of the trench embedding layer 40, it can prevent n － A cutoff leakage current flows between the p-type epitaxial layer 10 and the source pad 4. Specifically, because ions have difficulty entering the side portion of the source trench 33 during ion implantation, the p-type layer 38 is thinner on the side portion of the source trench 33 than at the bottom portion. Therefore, if a higher voltage is applied at cutoff, there is a concern that the cutoff leakage current may flow through the thinner portion of the p-type layer 38. Therefore, by forming a source trench insulating film 39, even if the cutoff leakage current flows through the p-type layer 38, the source trench insulating film 39 can reliably cut off the leakage current.

[0150] Furthermore, if the trench embedment layer 40 embedded in the source trench 33 is polysilicon, then when the contact hole 29 is formed by the surface insulating film 26 composed of SiO2, the trench embedment layer 40 (polysilicon layer) can be used as an etch barrier layer. Therefore, the control of the etching process of this contact portion can be simplified.

[0151] Furthermore, since the source trench 33 and the gate trench 8 are formed simultaneously, no additional manufacturing steps are required, and the source trench 33 can be formed easily and without misalignment. Moreover, if the widths of the source trench 33 and the gate trench 8 are the same, the etching rate of the source trench 33 can be made the same as that of the gate trench 8, thus enabling stable control of the etching used to form the source trench 33.

[0152] Next, refer to Figure 8-12 A modified example of unit part 2 will be explained.

[0153] Figure 8-12 This diagram shows the first to fifth variations of unit section 2. Figure 8-12 In the middle, regarding the aforementioned Figure 7 The parts shown are labeled with the same reference numbers.

[0154] existFigure 7 In this method, the trench embedment portion of the source trench 33 is composed of a source trench insulating film 39 and a trench embedment layer 40 (polysilicon layer), but as... Figure 8 As shown, it can also consist solely of an insulating layer 42 that backfills the source trench 33.

[0155] As the material for insulating layer 42, SiO2 can be used, and SiO2 containing phosphorus (P) or boron (B) is more preferred. As such SiO2, PSG (phosphosilicate glass) or PBSG (phosphosbobosilicate glass) can be used.

[0156] Figure 8 The manufacturing process of the semiconductor device shown is substantially the same as that described above. However, after forming the gate electrode 16 and the trench buried layer 40, the trench buried layer 40 is selectively etched away, resulting in voids in the source trench 33. Furthermore, by using n... － A surface insulating film 26 is formed on the epitaxial layer 10, and a portion of the surface insulating film 26 is used to backfill the source trench 33. Thus, the source trench insulating film 39 and the surface insulating film 26 are integrated within the source trench 33 to form an insulating layer 42.

[0157] Based on this structure, since the source trench 33 is filled with the insulating layer 42, it can effectively prevent n － A cutoff leakage current flows between the epitaxial layer 10 and the source pad 4.

[0158] In addition, if the insulating layer 42 is SiO2 containing phosphorus or boron, the melting point of SiO2 is reduced, thus simplifying the embedding process of the insulating layer 42.

[0159] In addition, such as Figure 9 As shown, the trench embedment portion of the source trench 33 can also be composed solely of a polysilicon layer 43 backfilled into the source trench 33. As the material for the polysilicon layer 43, p-type polysilicon is preferably used. ＋ Polycrystalline silicon.

[0160] Figure 8 The manufacturing process of the semiconductor device shown is substantially the same as that described above. However, after forming the gate insulating film 17 and the source trench insulating film 39, the source trench insulating film 39 is selectively etched away, resulting in voids in the source trench 33. Furthermore, polysilicon is removed from the n... － The polysilicon is deposited on top of the epitaxial layer 10 to fill the source trench 33. Thus, the gate electrode 16 and the polysilicon layer 43 are formed simultaneously.

[0161] Based on this structure, since the polysilicon layer 43 is buried in the source trench 33, the polysilicon layer 43 can be used as an etch barrier layer when the surface insulating film 26 made of SiO2 forms the contact hole 29. Therefore, the control of the etching process of the contact portion can be simplified.

[0162] Additionally, if polysilicon layer 43 is p ＋ In the case of polycrystalline silicon, the polycrystalline silicon layer 43 can be used to electrically connect p ＋ The two channels are a p-type channel contact region 34 and a p-type channel region 35. This shortens the current path length between regions 34 and 35, thus reducing the base resistance between them. Consequently, latch-up is effectively prevented. Furthermore, p... ＋ The channel contact region 34 is connected to the polysilicon layer 43 on the side of the source trench 33, thus reducing the contact resistance between them. This reduction in contact resistance also contributes to a reduction in the base resistance between regions 34 and 35.

[0163] in addition, Figure 7 In this method, the source trench 33 is surrounded by annular n ＋ The region surrounded by the source pole region 32 is formed in a ring shape, but as Figure 10 As shown, it can also be in the case of n ＋ The region surrounded by the p-type source region 32 forms a pit-shaped source trench 44, which is square in plan view. In this case, a p-type layer 38 can also be formed at the bottom surface of the source trench 44. ＋ Contact area of ​​the channel is 45.

[0164] in addition, Figure 7 In this method, the gate electrode 16 is a layer made solely of polysilicon filling the inner side of the gate insulating film 17, but as... Figure 11 As shown, it can also be composed of a polysilicon substrate film 46 formed on the gate insulating film 17 such that one surface and the other surface are along the inner surface of the gate trench 8, and a buried metal 47 containing at least one of Mo, W, Al, Pt, Ni, and Ti embedded inside the substrate film 46. In this case, the trench buried portion in the source trench 33 can also be composed of a polysilicon substrate film 48 formed on the source trench insulating film 39 such that one surface and the other surface are along the inner surface of the source trench 33, and a buried metal 49 made of the same material as the buried metal 47 embedded inside the substrate film 48.

[0165] Based on this structure, by using a metal gate with embedded metal 47, the gate resistance can be made relatively lower than that of a polysilicon gate, thus enabling the transistor to switch at a higher speed.

[0166] In addition, Figure 7The cell portion 2 is formed with a trench gate structure MISFET, but as Figure 12 As shown, a planar structure MISFET can also be formed in unit section 2. Furthermore, Figure 12 The construction described herein is not intended to illustrate the embodiments of the invention as set forth in the claims, but rather to show a reference mode of the invention.

[0167] That is, in Figure 12 In the arrangement shown, p-type wells 19 are arranged in a matrix (row-column) manner in unit section 2 in a manner corresponding to each unit unit 9. On the surface of each p-type well 19, an annular n-shaped structure is formed such that it is exposed on the base surface 11B. ＋ The source region is 50. Furthermore, it is aligned with the outer periphery of each p-type well 19 and the n-type source region. ＋ The gate electrode 51 is disposed between the outer peripheries of the source region 50 and the gate insulating film 52. The surface insulating film 26 covers the gate electrode 51.

[0168] <Second Implementation>

[0169] Figure 13 and Figure 14 This is a schematic cross-sectional view of a semiconductor device according to the second embodiment of the present invention, showing the semiconductor device as described above. Figure 3 and Figure 4 The corresponding cross-sectional structure. In Figure 13 and Figure 14 In the middle, regarding the aforementioned Figure 3 and Figure 4 The corresponding parts shown are labeled with the same reference numbers and are indicated.

[0170] In the first embodiment described above, the boundary between the base surface 11B and the low surface 11L formed by the low-order portion 12 is set further inward than the contact position of the source pad 4 of the p-type well 19 spanning the unit portion 2 and the outer peripheral portion 3, but as Figure 13 and Figure 14 As shown, it can also be set on the outside. In this case, p ＋ The p-type well contact region 24 is formed in the internal region of the p-type well 19 relative to the n-type well. ＋ Type 21 is located at the outermost interval.

[0171] Based on this structure, p can be formed on the base surface 11B. ＋ Type-type channel contact area 34 and p ＋ Because of these two trap contact regions 24, mask alignment can be easily performed during ion implantation when forming these regions 24 and 34. Of course, the same effect as in the first embodiment can also be achieved.

[0172] <Reference Method>

[0173] Figure 15 and Figure 16 This is a schematic cross-sectional view of a semiconductor device according to the reference embodiment of the present invention, showing the semiconductor device as described above. Figure 3 and Figure 4 The corresponding cross-sectional structure. In Figure 15 and Figure 16 In the middle, regarding the aforementioned Figure 3 and Figure 4 The corresponding parts shown are labeled with the same reference numbers and are indicated.

[0174] In the first embodiment described above, the surface insulating film 26 makes the inner portion 27 on the unit portion 2 have the same thickness as the outer portion 28 on the outer peripheral portion 3, but as... Figure 15 and Figure 16 As shown, it is also possible to form the inner portion 27 thinner than the outer portion 28. In this reference configuration, the thickness of the inner portion 27 is less than 5000 Å, and the thickness of the outer portion 28 is approximately 5500 Å to 20000 Å. Such a difference in film thickness can be achieved, for example, by using n － After forming a surface insulating film 25 of the same thickness on the epitaxial layer 13, a portion of the unit portion 2 of the surface insulating film 25 is selectively etched to form the film.

[0175] In addition, in this reference configuration, a low-order portion 21 is not formed in the outer peripheral portion 3, and the outer peripheral portion 3 has a semiconductor surface 11 at the same height position as the base surface 11B of the unit portion 2.

[0176] According to this reference method, by selectively thinning the surface insulating film 26 (inner portion 27) of the unit portion 2, the step difference (unevenness) between the semiconductor surface 11 (device surface) in the source portion 41 within the contact hole 29 and the surface of the surface insulating film 26 can be reduced. As a result, when the source pad 4 is embedded into the contact hole 29 and formed on the surface insulating film 26, the flatness of the source pad 4 can be further improved.

[0177] On the other hand, the thickness of the surface insulating film 26 (outer portion 28) of the outer peripheral portion 3 can be designed separately from the thickness of the inner portion 27. Therefore, by designing a thickness that does not affect the electric field distribution of the outer peripheral portion 3, the withstand voltage characteristics can be maintained. That is, according to this structure, when improving the flatness of the source pad 4, it is possible to prevent changes in the withstand voltage characteristics or the withstand voltage failure caused by such changes.

[0178] <Third Implementation>

[0179] Figure 17 and Figure 18 This is a schematic cross-sectional view of a semiconductor device according to the third embodiment of the present invention, showing the semiconductor device as described above. Figure 3 and Figure 4The corresponding cross-sectional structure. In Figure 17 and Figure 18 In the middle, regarding the aforementioned Figure 3 and Figure 4 The corresponding parts shown are labeled with the same reference numbers and are indicated.

[0180] Figure 17 and Figure 18 The structure described herein is an example of a structure that combines the structure of the first embodiment with the thickness difference of the surface insulating film 26 of the aforementioned reference embodiment. Based on this structure, the effects of both the first embodiment and the reference embodiment can be achieved simultaneously.

[0181] <Fourth Implementation>

[0182] Figure 19 and Figure 20 This is a schematic cross-sectional view of the semiconductor device according to the fourth reference embodiment of the present invention, showing the semiconductor device as described above. Figure 3 and Figure 4 The corresponding cross-sectional structure. In Figure 19 and Figure 20 In the middle, regarding the aforementioned Figure 3 and Figure 4 The corresponding parts shown are labeled with the same reference numbers and are indicated.

[0183] Figure 19 and Figure 20 The structure described is an example of a structure that combines the structure of the second embodiment with the thickness difference of the surface insulating film 26 of the aforementioned reference embodiment. Based on this structure, the effects of the first embodiment, the second embodiment, and the reference embodiment can be achieved simultaneously.

[0184] <Fifth Implementation>

[0185] Figure 21 This is a schematic cross-sectional view of a semiconductor device according to the fifth embodiment of the present invention, showing the relationship with... Figure 3 The corresponding cross-sectional structure. In Figure 21 In the middle, regarding the aforementioned Figure 3 The corresponding parts shown are labeled with the same reference numbers and are indicated.

[0186] In the first embodiment described above, the voltage-resistant structure of the outer peripheral portion 3, such as the p-type layer 23 and the p-type guard ring 25, is composed only of a p-type semiconductor region. However, as in... Figure 21As shown, the configuration can also include a trench formed on the lower surface 11L and a p-type semiconductor region formed at the bottom of the trench. In this case, a conductive material can also be embedded in the trench through an insulating film. In this embodiment, a protective ring 55 is formed, which includes: an annular trench 53 formed on the lower surface 11L and surrounding the unit portion 2; and a p-type layer 54 formed at the bottom and sides of the trench 53 and whose internal region is in contact with the trench 53. A polysilicon layer 57 is embedded in the trench 53 through a trench insulating film 56.

[0187] This structure can achieve the same effect as the first embodiment.

[0188] The above describes the embodiments of the present invention, but the present invention can also be implemented in other ways.

[0189] For example, the conductivity type of each semiconductor portion of the inverting semiconductor device 1 can also be used. For example, in semiconductor device 1, the p-type portion can be n-type, and the n-type portion can be p-type.

[0190] Furthermore, in semiconductor device 1, the layers constituting the semiconductor layer are not limited to those made of SiC. － The epitaxial layer can also be a layer composed of GaN, diamond, Si, etc.

[0191] In addition, each unit 9 is not limited to a square (quadrilateral shape) when viewed from above. For example, other polygonal shapes when viewed from above, such as triangles, pentagons, hexagons, etc., can also be viewed from above.

[0192] The semiconductor device of the present invention can be incorporated into a power module used in an inverter circuit that constitutes a drive circuit for driving an electric motor, for example, as a power source for electric vehicles (including hybrid vehicles), trams, industrial robots, etc. Additionally, it can also be incorporated into a power module for an inverter circuit that converts electricity generated by solar cells, wind turbines, and other power generation devices (especially home power generation devices) to match the power from commercial power sources.

[0193] Furthermore, the features disclosed in the foregoing embodiments can be combined with each other in different embodiments. Additionally, the constituent elements appearing in each embodiment can be combined within the scope of this invention.

[0194] The embodiments of the present invention are merely specific examples used to clarify the technical content of the present invention, and the present invention should not be interpreted as limited to these specific examples. The spirit and scope of the present invention are defined only by the appended claims.

[0195] This application corresponds to Japan Patent Office Patent Application No. 2013-43406, filed on March 5, 2013, the entire disclosure of which is incorporated herein by reference.

[0196] Label Explanation

[0197] 1 Semiconductor device; 2 Cell section; 3 Peripheral section; 4 Source pad; 5 Gate pad; 6 Gate finger; 7 Removal area; 8 Gate trench; 9 Unit cell; 10 n － 11. Epitaxial layer; 11. Semiconductor surface; 11B. Base surface; 11L. Low-level surface; 12. Low-level portion; 13. Inner trench; 14. Outer trench; 15. Contact trench; 16. Gate electrode; 17. Gate insulating film; 18. Masking portion; 19. p-type well; 20. n － Type-type drain region; 21 n ＋ Type region; 22 p-type layer; 23 p-type layer; 24 p-type layer ＋ 25. Type-A trap contact area; 26. Type-B protection ring; 27. Surface insulating film; 28. Inner portion; 29. ​​Outer portion; 30. Contact hole; 31. Contact hole; 32. N ＋ Type-3 source region; 33 source trench; 34 p ＋ 35 p-type channel contact area; 36 columnar portion; 37 annular portion; 38 p-type layer; 39 source trench insulating film; 40 trench embedding layer; 41 source portion; 42 insulating layer; 43 polysilicon layer; 44 source trench; 45 p ＋ Type-type channel contact area; 46 Basement membrane; 47 Embedded metal; 48 Basement membrane; 49 Embedded metal; 50 n ＋ 51. P-type source region; 52. Gate electrode; 53. Gate insulating film; 54. Trench; 55. P-type layer; 56. Guard ring; 57. Trench insulating film; 58. Polysilicon layer.

Claims

1. A semiconductor device comprising: a semiconductor layer of a first conductivity type having a cell portion and a peripheral portion disposed around the cell portion, and a gate trench formed on a surface side of the cell portion; a gate electrode embedded in the gate trench through a gate insulating film; and a gate finger for taking contact with the gate electrode, the gate finger being disposed at least in the peripheral portion, the gate trench including a linear trench reaching the peripheral portion and intersecting the gate finger below the gate finger, the semiconductor layer having a thickness of 3 μm to 20 μm.

2. The semiconductor device according to claim 1, wherein the peripheral portion has a semiconductor surface disposed at a depth position above a depth of the gate trench, the semiconductor device further comprising a voltage-withstanding structure having a semiconductor region of a second conductivity type formed on the semiconductor surface of the peripheral portion.

3. The semiconductor device according to claim 1, further comprising a surface insulating film disposed so as to span the cell portion and the peripheral portion, a first portion of the surface insulating film on the cell portion having a thickness identical to that of a second portion of the surface insulating film on the peripheral portion.

4. The semiconductor device according to claim 1, wherein the gate trench includes an inner trench having a channel formed on a side portion thereof when turned on, and an outer trench constituted by an extension of the inner trench and disposed outward of the inner trench, the semiconductor device further comprising a layer of a second conductivity type formed on a side portion and a bottom portion of the outer trench.

5. The semiconductor device according to claim 1, wherein the gate trench is selectively formed in a region below the gate finger, the semiconductor device further comprising a high-concentration layer of a first conductivity type formed on a semiconductor surface of the semiconductor layer in the region below the gate finger where the gate trench is not formed, the high-concentration layer containing an impurity at a higher concentration than the semiconductor layer.

6. The semiconductor device according to claim 1, wherein the cell portion includes: a source region of a first conductivity type disposed so as to be exposed on a surface of the semiconductor layer; a channel region of a second conductivity type disposed so as to be in contact with the source region and form the channel when turned on; a drain region of the first conductivity type disposed so as to be in contact with the channel region; a second trench selectively formed on a source portion divided so as to include the source region on the surface of the semiconductor layer; and a channel contact region of the second conductivity type selectively disposed on a bottom portion of the second trench and electrically connected to the channel region.

7. The semiconductor device according to claim 1, wherein the cell portion includes: a source region of a first conductivity type disposed so as to be exposed on a surface of the semiconductor layer; a channel region of a second conductivity type disposed so as to be in contact with the source region and form the channel when turned on; a drain region of the first conductivity type disposed so as to be in contact with the channel region. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ a second trench formed selectively in the surface of the semiconductor layer in a manner so as to include the source region; a trench-embedded portion embedded to the second trench; and a channel contact region of a second conductivity type which is disposed selectively in the source portion at a position higher than a bottom portion of the second trench and which is electrically connected to the channel region.

8. The semiconductor device according to claim 7, wherein the trench-embedded portion is composed of an insulating film formed on an inner surface of the second trench and a polysilicon layer embedded to an inner side of the insulating film.

9. The semiconductor device according to claim 8, wherein the insulating film is composed of any one of SiO2, AlON, Al2O3, SiO2 / AlON, SiO2 / AlON / SiO2, SiO2 / SiN, and SiO2 / SiN / SiO2.

10. The semiconductor device according to claim 8, wherein the insulating film has a SiO2 film containing nitrogen (N).

11. The semiconductor device according to claim 8, wherein the insulating film is formed to be thicker at the bottom portion of the second trench than at a portion of a side portion of the second trench.

12. The semiconductor device according to claim 8, wherein The polysilicon layer is composed of n ＋ type polysilicon.

13. The semiconductor device according to claim 7, wherein the trench-embedded portion is composed of an insulating layer backfilled to the second trench.

14. The semiconductor device according to claim 13, wherein the insulating layer is composed of SiO2.

15. The semiconductor device according to claim 14, wherein the insulating layer is composed of SiO2 containing phosphorus (P) or boron (B).

16. The semiconductor device according to claim 7, wherein the trench-embedded portion is composed of a polysilicon layer backfilled to the second trench.

17. The semiconductor device according to claim 16, wherein The polysilicon layer is composed of p ＋ type polysilicon.

18. The semiconductor device according to claim 6, further comprising a layer of a second conductivity type formed at the bottom portion and the side portion of the second trench in a manner so as to be continuous with the channel region and the channel contact region.

19. The semiconductor device according to claim 1, wherein the gate electrode includes a base film composed of polysilicon formed on an inner surface of the gate trench, and an embedded metal containing at least one of Mo, W, Al, Pt, Ni, and Ti embedded to an inner side of the base film.

20. The semiconductor device according to claim 1, wherein the semiconductor device further includes a surface metal layer composed of a metal containing copper (Cu) disposed on a surface side of the semiconductor layer.

21. The semiconductor device according to claim 20, wherein the surface metal layer contains an Al-Cu-based alloy.

22. The semiconductor device according to claim 1, wherein a plurality of unit cells divided by the gate trench in a lattice shape are formed in the cell portion.

23. The semiconductor device according to claim 1, wherein a plurality of unit cells divided by the gate trench in a stripe shape are formed in the cell portion.

24. The semiconductor device according to claim 1, wherein the semiconductor layer is composed of SiC, GaN, or diamond.

25. The semiconductor device according to claim 3, wherein the first portion and the second portion of the surface insulating film have a thickness of 5500 A to 20000 A.

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