A voltage reference circuit, component and device

Abstract

The invention discloses a voltage reference circuit, components and equipment, wherein the source of a first PMOS tube and the source of a second PMOS tube are connected to a power supply end; one end of a capacitor, the gate and drain of the first PMOS tube, the gate of the second PMOS tube, and the drain of a first NMOS tube are connected to each other; the drain of the second PMOS tube, the drain and gate of the second NMOS tube, and the gate of the first NMOS tube are connected to each other; the source of the second NMOS tube is connected to the source of a third PMOS tube as the output end of the voltage reference circuit; the drain of the third PMOS tube is connected to one end of a second resistor; the source of the first NMOS tube is connected to one end of a first resistor; the other end of the capacitor, the other end of the first resistor, the other end of the second resistor and the gate of the third PMOS tube are grounded.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a voltage reference circuit, components and equipment. Background Art

[0002] With the rapid development of information technology, the line width of semiconductor processes has been continuously reduced, and the requirements for integrated circuit performance have become increasingly higher. As a basic module of integrated circuits, voltage reference circuits provide accurate and stable reference voltages and bias currents for other functional circuits in the circuit system. The stability of the reference voltage under the influence of temperature and power supply voltage directly determines the performance of the circuit system. It is one of the most important core modules in analog integrated circuits and hybrid integrated circuits.

[0003] The prior art provides a bandgap reference circuit, which uses the positive temperature coefficient voltage and the negative temperature coefficient base-emitter junction voltage of the transistor to perform summation compensation, thereby obtaining an output reference voltage with a zero temperature coefficient. However, as the CMOS process develops towards smaller line widths and lower operating voltages, when the power supply operating voltage of nanometer small line width devices (such as 90nm devices and below) is lower than 1.2V, the bandgap reference circuit composed of transistors will not work properly and is incompatible with the CMOS process. Summary of the invention

[0004] The embodiments of the present application provide a voltage reference circuit, components and equipment, thereby solving the problem that the voltage reference circuit in the prior art cannot be used normally in small line width devices, achieving a wider range of applications and the technical effect of being compatible with CMOS processes.

[0005] In the first aspect, the present application provides the following technical solution through an embodiment of the present application:

[0006] A voltage reference circuit, comprising:

[0007] A first branch circuit and a second branch circuit;

[0008] The first branch circuit includes: a first PMOS transistor, a first NMOS transistor, a first resistor and a capacitor;

[0009] The second branch circuit includes: a second PMOS transistor, a second NMOS transistor, a third PMOS transistor and a second resistor;

[0010] Among them, the source of the first PMOS tube and the source of the second PMOS tube are connected to the power supply end; one end of the capacitor, the gate and drain of the first PMOS tube, the gate of the second PMOS tube, and the drain of the first NMOS tube are connected to each other; the drain of the second PMOS tube, the drain and gate of the second NMOS tube, and the gate of the first NMOS tube are connected to each other; the source of the second N tube is connected to the source of the third P tube as the output end of the voltage reference circuit; the drain of the third P tube is connected to one end of the second resistor; the source of the first N tube is connected to one end of the first resistor; the other end of the capacitor, the other end of the first resistor, the other end of the second resistor and the gate of the third P tube are grounded.

[0011] Optionally, the third PMOS tube operates at a zero temperature coefficient operating point and at a drain pinch-off point.

[0012] Optionally, when the third PMOS tube operates at a zero temperature coefficient operating point, the drain current is determined based on the following formula:

[0013]

[0014] Among them, I Dp_ZTC is the drain current of the third PMOS tube at the zero temperature coefficient DC operating point, C OX is the gate oxide capacitance per unit area of ​​the third PMOS tube, W is the channel width of the third PMOS tube, L is the channel length of the third PMOS tube, is a constant, α p is the speed saturation index of the third PMOS tube, η p is the temperature coefficient of the threshold voltage of the third PMOS tube.

[0015] Optionally, the resistance of the first resistor is determined based on the following formula:

[0016]

[0017] Wherein, R1 is the resistance value of the first resistor, V THp0 is the threshold voltage of the third PMOS tube at absolute zero, I Dp_ZTC is the drain current of the third PMOS tube at the zero temperature coefficient DC operating point.

[0018] Optionally, the resistance of the second resistor is determined based on the following formula:

[0019]

[0020] Wherein, R2 is the resistance value of the second resistor; Dp_ZTCis the drain current of the third PMOS tube at the zero temperature coefficient DC operating point; V THp (T 0 ) is room temperature T 0 The threshold voltage of the third PMOS tube is lowered, and the room temperature T 0 dV GSp_ZTC / dT=0 temperature, V GSp_ZTC It is the gate-source voltage of the NMOS tube at the zero temperature coefficient DC operating point.

[0021] Optionally, the first P transistor, the second P transistor, the first N transistor and the second N transistor in the first branch circuit and the second branch circuit are in an equal-proportional mirror relationship, so that the voltage of the first resistor is equal to the gate-source voltage V THp0 .

[0022] Optionally, the first PMOS tube and the second PMOS tube are PMOS tubes of the same type, and the channel width-to-length ratio of the first PMOS tube is the same as the channel width-to-length ratio of the second PMOS tube; the first NMOS tube and the second NMOS tube are NMOS tubes of the same type, and the channel width-to-length ratio of the first NMOS tube is the same as the channel width-to-length ratio of the second NMOS tube.

[0023] Optionally, the first resistor and the second resistor are of the same type and width, so that the resistance value can be adjusted by adjusting the length of the resistor.

[0024] In a second aspect, the present application provides a component, including the circuit described above.

[0025] In a third aspect, the present application provides a device comprising the circuit described above.

[0026] One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:

[0027] The present invention discloses a voltage reference circuit, components and equipment, wherein the source of a first PMOS tube and the source of a second PMOS tube are connected to a power supply terminal; one end of a capacitor, the gate and drain of the first PMOS tube, the gate of the second PMOS tube, and the drain of the first NMOS tube are connected to each other; the drain of the second PMOS tube, the drain and gate of the second NMOS tube, and the gate of the first NMOS tube are connected to each other; the source of the second NMOS tube is connected to the source of the third PMOS tube as the output end of the voltage reference circuit; the drain of the third PMOS tube is connected to one end of the second resistor; the source of the first NMOS tube is connected to one end of the first resistor; the other end of the capacitor, the other end of the first resistor, the other end of the second resistor and the gate of the third PMOS tube are grounded. Thus, a reference voltage lower than that of a voltage reference source composed of a triode can be output. The problem that the voltage reference circuit in the prior art cannot be used normally in a small line width device is solved, and a wider application is achieved, as well as the technical effect of being compatible with CMOS technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 Schematic diagram of a voltage reference circuit according to an embodiment of the present invention;

[0030] Figure 2 A structural diagram of components in an embodiment of the present invention;

[0031] Figure 3 1 is a structural diagram of a device in an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The embodiments of the present application provide a voltage reference circuit, components and equipment, thereby solving the problem that the voltage reference circuit in the prior art cannot be used normally in small line width devices, achieving a wider range of applications and the technical effect of being compatible with CMOS processes.

[0033] The technical solution of the embodiment of the present application is to solve the above technical problems, and the overall idea is as follows:

[0034] A voltage reference circuit, comprising:

[0035] A first branch circuit and a second branch circuit;

[0036] The first branch circuit includes: a first PMOS transistor, a first NMOS transistor, a first resistor and a capacitor;

[0037] The second branch circuit includes: a second PMOS transistor, a second NMOS transistor, a third PMOS transistor and a second resistor;

[0038] Among them, the source of the first PMOS tube and the source of the second PMOS tube are connected to the power supply end; one end of the capacitor, the gate and drain of the first PMOS tube, the gate of the second PMOS tube, and the drain of the first NMOS tube are connected to each other; the drain of the second PMOS tube, the drain and gate of the second NMOS tube, and the gate of the first NMOS tube are connected to each other; the source of the second N tube is connected to the source of the third P tube as the output end of the voltage reference circuit; the drain of the third P tube is connected to one end of the second resistor; the source of the first N tube is connected to one end of the first resistor; the other end of the capacitor, the other end of the first resistor, the other end of the second resistor and the gate of the third P tube are grounded.

[0039] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0040] First of all, the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0041] Embodiment 1

[0042] like Figure 1 A voltage reference circuit is provided, comprising:

[0043] A first branch circuit A and a second branch circuit B;

[0044] The first branch circuit A includes: a first PMOS transistor MP1, a first NMOS transistor MN1, a first resistor R1 and a capacitor C;

[0045] The second branch circuit B includes: a second PMOS transistor MP2, a second NMOS transistor MN2, a third PMOS transistor MP3 and a second resistor R2;

[0046] Among them, the source of the first PMOS tube MP1 and the source of the second PMOS tube MP2 are connected to the power supply end; one end of the capacitor C, the gate and drain of the first PMOS tube MP1, the gate of the second PMOS tube MP2, and the drain of the first NMOS tube MN1 are connected to each other; the drain of the second PMOS tube MP2, the drain and gate of the second NMOS tube MN2, and the gate of the first NMOS tube MN1 are connected to each other; the source of the second NMOS tube MN2 is connected to the source of the third PMOS tube MP3 as the output end VREF of the voltage reference circuit; the drain of the third PMOS tube MP3 is connected to one end of the second resistor R2; the source of the first NMOS tube MN1 is connected to one end of the first resistor R1; the other end of the capacitor C, the other end of the first resistor R1, the other end of the second resistor R2, and the gate of the third PMOS tube MP3 are grounded.

[0047] In an optional embodiment, the third PMOS tube MP3 operates at a zero temperature coefficient operating point and at a drain pinch-off point. At this DC operating point, the gate-source voltage and drain current of the PMOS device are not affected by temperature, and the values ​​remain constant within the operating temperature range, with the characteristic of temperature self-compensation. Thus, the output terminal VREF of the voltage reference circuit of the present application can output a constant reference voltage. Moreover, when the third PMOS tube MP3 operates at the drain pinch-off point, the drain current is least affected by the change in the drain voltage, that is, the DC operating point of the third PMOS tube MP3 is least affected.

[0048] In the specific implementation process, for the zero temperature coefficient operating point of the third PMOS tube MP3, the PMOS transfer characteristic curves at different temperatures can be simulated, and the drain current at the intersection of the simulation curve can be found, and then the value of R1 in the circuit can be adjusted to set a suitable drain bias current of the third PMOS tube MP3 (which is the zero temperature coefficient DC operating point leakage current I Dp_ZTC ).

[0049] When the third PMOS tube MP3 is operated at the drain pinch-off point, the source-drain voltage of the third PMOS tube MP3 can be determined based on the drain current formula of the PMOS tube in the linear region and the saturation region, and the gate-source voltage of the PMOS tube at the zero temperature coefficient DC bias operating point. Then, the source-drain voltage V of the third PMOS tube MP3 is obtained. DSp =(V GSp_ZTC -V THp (T 0 ))=V Dsat (T 0 ), where V Dsat (T 0 ) is T 0 Driving voltage at temperature; V THp (T 0 ) is T0 Threshold voltage at temperature; T 0 dV GSp_ZTC / dT = 0, usually room temperature. At this time, the PMOS channel is pinched off at the drain, and the drain current is controlled by V DSp The change has the smallest impact, that is, the impact on the PMOS DC operating point is the smallest.

[0050] Thus, the gate-source voltage V of the third PMOS tube MP3 is obtained. GSp_ZTC =Threshold voltage V of the third PMOS tube MP3 at absolute zero THp0 Thus, a reference voltage whose output is not affected by temperature is realized.

[0051] In an optional implementation, when the third PMOS transistor MP3 operates at a zero temperature coefficient operating point, the drain current is determined based on the following formula:

[0052]

[0053] Among them, I Dp_ZTC is the drain current of the third PMOS tube at the zero temperature coefficient DC operating point, C OX is the gate oxide capacitance per unit area of ​​the third PMOS tube, W is the channel width of the third PMOS tube, L is the channel length of the third PMOS tube, is a constant, α p is the speed saturation index of the third PMOS tube, η p is the temperature coefficient of the threshold voltage of the third PMOS tube.

[0054] In an optional implementation, the first P transistor, the second P transistor, the first N transistor and the second N transistor in the first branch circuit A and the second branch circuit B are in a proportional mirror relationship so that the voltage of the first resistor R1 is equal to the gate-source voltage of the third PMOS transistor MP3.

[0055] In a specific implementation process, the first PMOS tube MP1 and the second PMOS tube MP2 are PMOS tubes of the same type, and the channel width-to-length ratio of the first PMOS tube MP1 is the same as the channel width-to-length ratio of the second PMOS tube MP2. The first NMOS tube MN1 and the second NMOS tube MN2 are NMOS tubes of the same type, and the channel width-to-length ratio of the first NMOS tube MN1 is the same as the channel width-to-length ratio of the second NMOS tube MN2. Among them, the same type of PMOS tube and NMOS tube can be both enhancement type or both depletion type.

[0056] In an optional implementation, the source-drain voltage of the third PMOS transistor MP3 can be adjusted by setting the resistance values ​​of the first resistor R1 and the second resistor R2, so that the third PMOS transistor MP3 operates at the drain pinch-off point under zero temperature coefficient DC bias.

[0057] In a specific implementation process, the resistance value of the first resistor is determined based on the following formula:

[0058]

[0059] Where R1 is the resistance of the first resistor, V THp0 is the threshold voltage of the third PMOS tube MP3 at absolute zero, I Dp_ZTC It is the drain current of the third PMOS tube MP3 at the zero temperature coefficient DC operating point.

[0060] The resistance value of the second resistor is determined based on the following formula:

[0061]

[0062] Wherein, R2 is the resistance value of the second resistor; I Dp_ZTC is the drain current of the third PMOS tube MP3 at the zero temperature coefficient DC operating point; V THp (T 0 ) is room temperature T 0 The threshold voltage of the third PMOS tube MP3 is 0 dV GSp_ZTC / dT=0 temperature, V GSp_ZTC It is the gate-source voltage of the PMOS tube at the zero temperature coefficient DC operating point.

[0063] In an optional embodiment, the first resistor R1 and the second resistor R2 have the same type and width, so that the resistance value can be adjusted by adjusting the length of the resistor. Specifically, adjustable resistors of the same type and width can be used. Of course, other resistors can also be used, and this embodiment is not limited thereto.

[0064] Embodiment 2

[0065] Based on the same inventive concept, Figure 2 As shown, this embodiment provides a component, including the circuit described in any one of the embodiments.

[0066] Since the components introduced in this embodiment are components used to implement the voltage reference circuit in the embodiment of the present application, based on the voltage reference circuit introduced in the embodiment of the present application, those skilled in the art can understand the specific implementation of the components of the present embodiment and its various variations, so how the components implement the method in the embodiment of the present application is not described in detail here. As long as those skilled in the art implement the components used in the voltage reference circuit in the embodiment of the present application, they all fall within the scope of protection of this application.

[0067] Embodiment 3

[0068] Based on the same inventive concept, Figure 3 As shown, this embodiment provides a device, including the circuit described in any one of the first embodiments.

[0069] Since the device introduced in this embodiment is a device used to implement the voltage reference circuit in the embodiment of the present application, based on the voltage reference circuit introduced in the embodiment of the present application, a person skilled in the art can understand the specific implementation of the electronic device of the present embodiment and its various variations, so how the device implements the method in the embodiment of the present application is not described in detail here. As long as a person skilled in the art implements the device used in the voltage reference circuit in the embodiment of the present application, it belongs to the scope of protection of this application.

[0070] The technical solutions in the above embodiments of the present application have at least the following technical effects or advantages:

[0071] The present invention discloses a voltage reference circuit, components and equipment, wherein the source of a first PMOS tube and the source of a second PMOS tube are connected to a power supply terminal; one end of a capacitor, the gate and drain of the first PMOS tube, the gate of the second PMOS tube, and the drain of the first NMOS tube are connected to each other; the drain of the second PMOS tube, the drain and gate of the second NMOS tube, and the gate of the first NMOS tube are connected to each other; the source of the second NMOS tube is connected to the source of the third PMOS tube as the output end of the voltage reference circuit; the drain of the third PMOS tube is connected to one end of the second resistor; the source of the first NMOS tube is connected to one end of the first resistor; the other end of the capacitor, the other end of the first resistor, the other end of the second resistor and the gate of the third PMOS tube are grounded. Thus, a temperature-compensated reference voltage can be output. A solution is provided for the technical bottleneck that the voltage reference circuit in the prior art cannot be used normally in a small line width device, and a wider application is achieved, as well as a technical effect of being compatible with CMOS technology.

[0072] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0073] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A voltage reference circuit, characterized in that: include: A first branch circuit and a second branch circuit; The first branch circuit includes: a first PMOS transistor, a first NMOS transistor, a first resistor and a capacitor; The second branch circuit includes: a second PMOS transistor, a second NMOS transistor, a third PMOS transistor and a second resistor; Wherein, the source of the first PMOS tube and the source of the second PMOS tube are connected to the power supply end; one end of the capacitor, the gate and drain of the first PMOS tube, the gate of the second PMOS tube, and the drain of the first NMOS tube are connected to each other; the drain of the second PMOS tube, the drain and gate of the second NMOS tube, and the gate of the first NMOS tube are connected to each other; the source of the second NMOS tube is connected to the source of the third PMOS tube as the output end of the voltage reference circuit; the drain of the third PMOS tube is connected to one end of the second resistor; the source of the first NMOS tube is connected to one end of the first resistor; the other end of the capacitor, the other end of the first resistor, the other end of the second resistor, and the gate of the third PMOS tube are grounded; The third PMOS tube operates at a zero temperature coefficient operating point and at a drain pinch-off point; The resistance value of the second resistor is determined based on the following formula: Wherein, R2 is the resistance value of the second resistor; Dp_ZTC is the drain current of the third PMOS tube at the zero temperature coefficient DC operating point; V THp (T0) is the threshold voltage of the third PMOS tube at room temperature T0, and the room temperature T0 is dV GSp_ZTC / Temperature when dT=0, V GSp_ZTC is the gate-source voltage of the third PMOS tube at the zero temperature coefficient DC operating point.

2. The voltage reference circuit according to claim 1, wherein: When the third PMOS tube operates at a zero temperature coefficient operating point, the drain current is determined based on the following formula: Among them, I Dp_ZTC is the drain current of the third PMOS tube at the zero temperature coefficient DC operating point, is the gate oxide capacitance per unit area of ​​the third PMOS tube, W is the channel width of the third PMOS tube, L is the channel length of the third PMOS tube, is a constant, α p is the speed saturation index of the third PMOS tube, η p is the temperature coefficient of the threshold voltage of the third PMOS tube.

3. The voltage reference circuit according to claim 1, wherein: The resistance value of the first resistor is determined based on the following formula: Wherein, R1 is the resistance value of the first resistor, V THp0 is the threshold voltage of the third PMOS tube at absolute zero, I Dp_ZTC is the drain current of the third PMOS tube at the zero temperature coefficient DC operating point.

4. The voltage reference circuit according to claim 1, wherein: The first PMOS transistor, the second PMOS transistor, the first NMOS transistor and the second NMOS transistor in the first branch circuit and the second branch circuit are in a proportional mirror relationship so that the voltage of the first resistor is equal to the gate-source voltage of the third PMOS transistor.

5. The voltage reference circuit according to claim 4, wherein: include: The first PMOS tube and the second PMOS tube are of the same type, and the channel width-to-length ratio of the first PMOS tube is the same as the channel width-to-length ratio of the second PMOS tube; The first NMOS tube and the second NMOS tube are NMOS tubes of the same type, and the channel width-to-length ratio of the first NMOS tube is the same as the channel width-to-length ratio of the second NMOS tube.

6. The voltage reference circuit according to claim 1, wherein: The first resistor and the second resistor are of the same type and width, so that the resistance value can be adjusted by adjusting the length of the resistor.

7. A component, characterized in that: The invention comprises the voltage reference circuit described in any one of claims 1 to 6.

8. A voltage reference electronic device, characterized in that: Comprising the voltage reference circuit as described in any one of claims 1-6.

Images