Semiconductor packaging structure and method for forming the same

Abstract

The present invention relates to the field of packaging technology, and in particular to a semiconductor packaging structure and a method for forming the same. The method for forming the packaging structure comprises the following steps: providing a substrate; forming a plurality of mutually independent conductive traces on the substrate, with grooves exposing the substrate between adjacent conductive traces; oxidizing the sidewalls of the conductive traces to form a barrier layer; and forming a solder resist layer that at least fills the grooves. The present invention forms a barrier layer by oxidizing the sidewalls of the conductive traces. On the one hand, the barrier layer can block the electrical migration of conductive particles in the conductive traces, thereby reducing the probability of short circuits between adjacent conductive traces. On the other hand, the barrier layer is formed directly by oxidizing the conductive traces, which is simple in process, simplifies the process steps of the semiconductor packaging structure, and improves the production efficiency of the semiconductor packaging structure.

Description

Technical Field

[0001] The present invention relates to the field of packaging technology, and in particular to a semiconductor packaging structure and a forming method thereof. Background Art

[0002] In order to improve semiconductor performance, high-speed digital substrates need to be designed with equal line lengths during the packaging process. In order to keep the delay difference of each signal transmitted in the substrate within a certain range, thereby ensuring the validity of reading data inside the packaging substrate in the same cycle, the requirements for packaging substrate design are becoming more and more stringent, and the requirements for various restrictions inside the packaging substrate are also becoming higher and higher. For example, the requirements for the line width and line length of the wiring layer inside the packaging substrate are getting higher and higher. However, as the wiring density on the packaging substrate increases, the spacing between adjacent traces becomes smaller and smaller. Under HAST (reliability test environment), electromigration occurs between traces, resulting in short circuits between adjacent traces, leading to packaging failure.

[0003] Therefore, how to avoid short circuits between adjacent traces on a packaging substrate and improve the performance reliability of the packaging structure is a technical problem that needs to be solved urgently. Summary of the invention

[0004] The present invention provides a semiconductor packaging structure and a forming method thereof, which are used to solve the problem that adjacent wirings in the existing packaging structure are prone to short circuits, so as to improve the performance of the packaging structure and enhance the reliability of the packaging structure.

[0005] In order to solve the above problems, the present invention provides a method for forming a semiconductor packaging structure, comprising the following steps:

[0006] providing a substrate;

[0007] Forming a plurality of mutually independent conductive traces on the substrate, with grooves exposing the substrate between adjacent conductive traces;

[0008] Oxidizing the sidewalls of the conductive trace to form a barrier layer;

[0009] A solder resist layer is formed to at least fill the groove.

[0010] Optionally, the specific steps of forming a plurality of mutually independent conductive traces on the substrate include:

[0011] forming a conductive material on a first surface of the substrate and a second surface opposite to the first surface;

[0012] The conductive material is etched to form a plurality of mutually independent conductive traces.

[0013] Optionally, the specific step of etching the conductive material includes:

[0014] Attaching a photosensitive film to the surface of the conductive material;

[0015] Forming a patterned mask layer on the surface of the photosensitive film, wherein the mask layer has an opening exposing the photosensitive film;

[0016] Etching the photosensitive film and the conductive material along the opening to form a plurality of mutually independent conductive traces;

[0017] The mask layer is removed.

[0018] Optionally, before oxidizing the sidewall of the conductive trace, the following steps are further included:

[0019] The substrate is etched along the groove to form a recess in the substrate that is connected to the groove.

[0020] Optionally, the specific step of etching the substrate along the groove includes:

[0021] Using a first gas to clean the substrate to remove impurities on the surface of the substrate;

[0022] The substrate is etched along the groove using a second gas.

[0023] Optionally, the first gas is argon, and the second gas is oxygen.

[0024] Optionally, the depth of the depression is 0.5 μm to 3 μm.

[0025] Optionally, the conductive material is a metal material; the specific steps of forming the barrier layer include:

[0026] Thermally treating the conductive trace to form a barrier layer on the sidewall of the conductive trace;

[0027] The photosensitive film is removed.

[0028] Optionally, the specific steps of forming a solder resist layer that at least fills the groove include:

[0029] Forming a solder resist layer that fills the groove, the recess and covers the barrier layer and the surface of the conductive trace;

[0030] The solder resist layer is etched to form a contact hole exposing a portion of the conductive trace.

[0031] Optionally, the distance between adjacent conductive traces is less than or equal to 20 μm.

[0032] In order to solve the above problem, the present invention further provides a semiconductor packaging structure, comprising:

[0033] substrate;

[0034] A plurality of mutually independent conductive traces are located on the substrate, and grooves exposing the substrate are provided between adjacent conductive traces;

[0035] A barrier layer covering the sidewalls of the conductive trace;

[0036] The solder resist layer is located on the substrate and at least fills the groove.

[0037] Optionally, the material of the conductive trace is a metal material, and the material of the barrier layer is a metal oxide material.

[0038] Optionally, the substrate has a depression located between adjacent conductive traces and connected to the groove;

[0039] The solder resist layer fills the groove and the recess and covers the barrier layer and a portion of the surface of the conductive trace.

[0040] Optionally, the depth of the depression is 0.5 μm to 3 μm.

[0041] Optionally, the distance between adjacent conductive traces is less than or equal to 20 μm.

[0042] The semiconductor packaging structure and the method for forming the same provided by the present invention form a barrier layer by oxidizing the side walls of a conductive trace. On the one hand, the barrier layer can block the electrical migration of conductive particles in the conductive trace, thereby reducing the probability of a short circuit between adjacent conductive traces. On the other hand, the barrier layer is formed directly by oxidizing the conductive trace, which is a simple process, simplifies the process steps of the semiconductor packaging structure, and improves the production efficiency of the semiconductor packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Attached Figure 1 is a flow chart of a method for forming a semiconductor packaging structure in a specific embodiment of the present invention;

[0044] Attached Figures 2A-2J It is a schematic cross-sectional view of the main processes in the process of forming a semiconductor packaging structure according to a specific embodiment of the present invention;

[0045] Attached Figure 3 is a schematic top view of a semiconductor packaging structure formed in a specific embodiment of the present invention;

[0046] Attached Figure 4 It is the migration path of the conductive particles in the semiconductor packaging structure formed by the specific embodiment of the present invention. DETAILED DESCRIPTION

[0047] The specific implementation of the semiconductor packaging structure and the method for forming the same provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0048] This specific embodiment provides a method for forming a semiconductor packaging structure. Figure 1 is a flow chart of a method for forming a semiconductor packaging structure in a specific embodiment of the present invention, Figures 2A-2J is a schematic cross-sectional view of the main processes in forming a semiconductor packaging structure in a specific embodiment of the present invention, Figure 3 FIG. 1 is a schematic diagram of a top view of a semiconductor packaging structure formed by a specific embodiment of the present invention. Figure 1 , Figure 2A-2J and Figure 3 As shown, the method for forming a semiconductor packaging structure provided in this specific embodiment includes the following steps:

[0049] Step S11, providing a substrate 20, such as Figure 2A shown.

[0050] The material of the substrate 20 may be, but is not limited to, insulating materials such as resin. A wiring layer may be formed on the surface of the substrate 20 and inside the substrate 20 , and the wiring layer is used for signal conduction.

[0051] Step S12, forming a plurality of mutually independent conductive traces 212 on the substrate 20, with grooves 211 exposing the substrate 20 between adjacent conductive traces 212, such as Figure 2E shown.

[0052] Optionally, the specific steps of forming a plurality of mutually independent conductive traces 212 on the substrate 20 include:

[0053] A conductive material 21 is formed on a first surface of the substrate 20 and a second surface opposite to the first surface. Figure 2A As shown;

[0054] The conductive material 21 is etched to form a plurality of mutually independent conductive traces 212, such as Figure 2E shown.

[0055] Optionally, the specific step of etching the conductive material 21 includes:

[0056] A photosensitive film 22 is attached to the surface of the conductive material 21, such as Figure 2B As shown;

[0057] Forming a patterned mask layer 23 on the surface of the photosensitive film 22, wherein the mask layer 23 has an opening for exposing the photosensitive film 22;

[0058] Etching the photosensitive film 22 and the conductive material 21 along the opening to form a plurality of mutually independent conductive traces 212;

[0059] The mask layer 23 is removed.

[0060] The conductive material 21 may be, but is not limited to, a metal material. The following description will be made by taking the conductive material 21 as copper as an example. Specifically, the substrate 20 includes a first surface and a second surface that are relatively distributed, and a copper foil (i.e., the conductive material 21) is formed on the first surface and the second surface of the substrate 20, and the surface of the copper foil away from the substrate 20 is roughened, washed, dried, etc., so as to achieve surface modification of the copper foil and improve the adhesion between the copper foil and the subsequently formed photosensitive film 22, such as Figure 2A The thickness of the copper foil can be determined according to the height of the conductive traces in the preformed wiring layer. Afterwards, the preformed photosensitive film 22 is preheated and attached to the surface of the copper foil, so that the photosensitive film 22 and the copper foil are closely attached to avoid positional offset between the two in subsequent processes, thereby avoiding affecting the final wiring pattern, such as Figure 2B As shown. Next, a patterned mask layer 23 is formed on the surface of the photosensitive film 22. The mask layer 23 can be a positive photoresist layer or a negative photoresist layer. This specific embodiment is described by taking the mask layer 23 as a positive photoresist layer as an example. The positive photoresist layer has an opening that penetrates the positive photoresist layer in a direction perpendicular to the surface of the substrate 20. Figure 2C The positive photoresist layer is illuminated and developed in the direction of the arrow in the figure to form an etching window 221 in the photosensitive film 22. After removing the positive photoresist layer, the following is obtained: Figure 2D The etching window 221 penetrates the photosensitive film 22 in a direction perpendicular to the surface of the substrate 20. Then, the copper foil is etched along the etching window in the photosensitive film 22 to form a plurality of grooves 211 that separate the conductive material 21 into a plurality of conductive traces 212, as shown in FIG. Figure 2E The groove 211 penetrates the copper foil in a direction perpendicular to the surface of the substrate 20 .

[0061] Step S13, oxidizing the sidewalls of the conductive trace 212 to form a barrier layer 24, such as Figure 2H shown.

[0062] Optionally, before oxidizing the sidewall of the conductive trace 212, the following steps are further included:

[0063] The substrate 20 is etched along the groove 211 to form a recess 201 in the substrate 20 that is connected to the groove 211. Figure 2G shown.

[0064] Optionally, the specific step of etching the substrate 20 along the groove 211 includes:

[0065] The substrate 20 is cleaned with a first gas to remove impurities on the surface of the substrate 20. Figure 2F As shown;

[0066] The substrate 20 is etched along the groove 211 using a second gas, such as Figure 2G shown.

[0067] Optionally, the first gas is argon, and the second gas is oxygen.

[0068] Specifically, in the process of etching the conductive material 21 to form the conductive trace 212, impurities including etchants and etching byproducts (such as metal ions, chloride ions, sulfur ions and organic impurities, etc.) will be generated. In order to avoid the influence of impurities on subsequent processes, argon gas can be used as an etching gas and combined with a plasma etching process to remove the impurities remaining on the substrate 20 to achieve the cleaning of the substrate 20. In the process of using argon gas for cleaning etching, the flow rate of argon gas can be 1000sccm to 2000sccm, the etching temperature can be 400°C, the pressure during the etching process is 3torr, and the RF power is 300W. Afterwards, oxygen is used as an etching gas and combined with a plasma etching process to micro-etch the substrate 20. Oxygen etching can effectively remove the organic impurities generated in the process of etching the conductive material 21 to form the conductive trace 212, and form the recess 201. In the process of micro-etching with oxygen, the flow rate of oxygen can be 4000 sccm, the etching temperature can be 550° C., the pressure during the etching process can be 5 torr, and the radio frequency power can be 1000W.

[0069] Attached Figure 4 It is the migration path of the conductive particles in the semiconductor packaging structure formed by the specific embodiment of the present invention. In this specific embodiment, the substrate 20 is micro-etched to form the recess 201 in the substrate 20, so that the migration path of the conductive particles can be changed. Specifically: when the barrier layer 24 and the recess 201 are not formed, once the conductive particles migrate in the conductive trace 212, the migration path of the conductive particles is along the inner diameter direction of the groove 211, and the migration path is short, resulting in a higher probability of short circuit between adjacent conductive traces. After the barrier layer 24 and the recess 201 are formed, once the conductive particles migrate, the migration path of the conductive particles changes to first transmitting downward in a direction perpendicular to the substrate 20 (that is, the direction in which the conductive trace 212 points to the substrate 20), and then transmitting in a radial direction along the recess 201, as shown in FIG. Figure 4 As shown, the migration path is long and has corners, and the probability of short circuit between adjacent conductive traces is further reduced after the conductive particles migrate.

[0070] In a direction perpendicular to the surface of the substrate 20, the projection of the recess 201 is located between two adjacent conductive traces 212. The width (i.e., inner diameter) of the recess 201 may be equal to the width of the groove 211. In order not to affect the wiring layer structure inside the substrate 20, optionally, the depth of the recess 201 is 0.5 μm to 3 μm.

[0071] Optionally, the conductive material 21 is a metal material; the specific steps of forming the barrier layer 24 include:

[0072] The conductive trace 212 is thermally treated to form a barrier layer 24 on the sidewall of the conductive trace 212. Figure 2H As shown;

[0073] Remove the photosensitive film 22, such as Fig.2I shown.

[0074] Specifically, after the recess 201 is formed in the substrate 20, the substrate 20 having the conductive trace 212 and the photosensitive film 22 is subjected to heat treatment such as baking, and the metal material on the side wall of the conductive trace 212 undergoes an oxidation reaction at high temperature to generate an oxide, and the oxide is used as the barrier layer 24. During the high-temperature baking process, since the top surface of the conductive trace 212 (i.e., the surface of the conductive trace 212 away from the substrate 20) is covered with the photosensitive film 22, it can be ensured that the top surface of the conductive trace 212 is not oxidized. During the baking process, the thickness of the barrier layer 24 can be adjusted by controlling the baking time, the flow rate of oxygen during the baking process, and the baking temperature. In one embodiment, the baking temperature can be set to 150°C and the baking time can be set to 1h to ensure the formation of a stable barrier layer. Those skilled in the art can adjust the thickness of the barrier layer 24 according to actual needs, for example, by controlling the baking time, the flow rate of oxygen during the baking process, etc.

[0075] Step S14, forming a solder resist layer 25 that at least fills the groove 211, such as Figure 2J shown.

[0076] Optionally, the specific steps of forming the solder resist layer 25 that at least fills the groove 211 include:

[0077] Forming a solder resist layer 25 that fills the groove 211 and the recess 201 and covers the barrier layer 24 and the surface of the conductive trace 212;

[0078] The solder resist layer 25 is etched to form a contact hole 251 exposing a portion of the conductive trace 212 .

[0079] Specifically, after forming the barrier layer 24 and removing the photosensitive film 22, the solder resist layer 25 is deposited so that the solder resist layer 25 fills the groove 211 and the recess 201 and covers the barrier layer 24 and the surface of the conductive trace 212. Then, according to the needs of welding, part of the solder resist layer 25 is etched away to form a contact hole 251 exposing the conductive trace 212, as shown in FIG. Figure 2J and Figure 3 The solder resist layer 25 is used to ensure the morphology of the conductive trace 212, ensure the electrical insulation between adjacent conductive traces, and prevent the soldering surface (ie, the top surface) of the conductive trace 212 from being oxidized.

[0080] Optionally, the distance between adjacent conductive traces 212 is less than or equal to 20 μm. The method for forming a semiconductor package structure provided in this specific embodiment is also applicable to the case where the distance between adjacent conductive traces 212 is greater than 20 μm.

[0081] In addition, the present embodiment also provides a semiconductor packaging structure. The semiconductor packaging structure provided in the present embodiment can be used as follows Figure 1 , Figure 2A-2J The schematic diagram of the semiconductor packaging structure provided in this embodiment can be seen in Figure 2J and Figure 3 .like Figure 2A-2J ,as well as Figure 3 As shown, the semiconductor packaging structure includes:

[0082] substrate 20;

[0083] A plurality of mutually independent conductive traces 212 are located on the substrate 20, and grooves 211 exposing the substrate 20 are provided between adjacent conductive traces 212;

[0084] A barrier layer 24 covering the sidewalls of the conductive trace 212;

[0085] The solder resist layer 25 is located on the substrate 20 and at least fills the groove 211 .

[0086] Specifically, the conductive trace 212 is used for transmitting electrical signals in a semiconductor. The solder resist layer 25 is used to ensure the morphology of the conductive trace 212, ensure electrical insulation between adjacent conductive traces, and prevent the soldering surface (i.e., the top surface) of the conductive trace 212 from being oxidized. The barrier layer 24 can block the electrical migration of conductive particles in the conductive trace 212, thereby preventing short circuits between adjacent conductive traces 212.

[0087] Optionally, the conductive trace 212 is made of a metal material, and the barrier layer 24 is made of a metal oxide material.

[0088] In this specific embodiment, the barrier layer 24 is generated by oxidizing the sidewalls of the conductive trace 212 .

[0089] Optionally, the substrate 20 has a recess 201 located between adjacent conductive traces 212 and connected to the groove 211;

[0090] The solder resist layer 25 fills the groove 211 and the recess 201 and covers the surface of the barrier layer 24 and a portion of the conductive trace 212 .

[0091] Optionally, the depth of the recess 201 is 0.5 μm to 3 μm.

[0092] The recess 201 is used to change the electrical migration path of the conductive particles in the conductive trace 212. Specifically, when the barrier layer 24 and the recess 201 are not formed, once the conductive particles migrate in the conductive trace 212, the migration path of the conductive particles is along the inner diameter direction of the groove 211. The migration path is short, resulting in a high probability of short circuit between adjacent conductive traces. After the barrier layer 24 and the recess 201 are formed, once the conductive particles migrate, the migration path of the conductive particles changes to first transmitting downward in a direction perpendicular to the substrate 20 (i.e., the direction in which the conductive trace 212 points to the substrate 20), and then transmitting in a radial direction along the recess 201, as shown in FIG. Figure 4 As shown, the migration path is long and has corners, and the probability of short circuit between adjacent conductive traces is further reduced after the conductive particles migrate.

[0093] Optionally, the distance between adjacent conductive traces 211 is less than or equal to 20 μm.

[0094] In other specific implementations, the distance between adjacent conductive traces 211 is greater than 20 μm.

[0095] The semiconductor packaging structure and the method for forming the same provided in this specific embodiment form a barrier layer by oxidizing the side walls of the conductive traces. On the one hand, the barrier layer can block the electrical migration of conductive particles in the conductive traces, thereby reducing the probability of short circuits between adjacent conductive traces. On the other hand, the barrier layer is formed directly by oxidizing the conductive traces, which is a simple process, simplifies the process steps of the semiconductor packaging structure, and improves the production efficiency of the semiconductor packaging structure.

[0096] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for forming a semiconductor packaging structure, characterized in that: The steps include: providing a substrate; Forming a plurality of mutually independent conductive traces on the substrate, with grooves exposing the substrate between adjacent conductive traces; Oxidizing the sidewalls of the conductive trace to form a barrier layer; forming a solder resist layer that at least fills the groove; Before oxidizing the sidewall of the conductive trace, the following steps are also included: Etching the substrate along the groove to form a recess in the substrate that communicates with the groove; The specific steps of etching the substrate along the grooves include: Using a first gas to clean the substrate to remove impurities on the surface of the substrate; The substrate is etched along the groove using a second gas.

2. The method for forming a semiconductor package structure according to claim 1, wherein: The specific steps of forming a plurality of mutually independent conductive traces on the substrate include: forming a conductive material on a first surface of the substrate and a second surface opposite to the first surface; The conductive material is etched to form a plurality of mutually independent conductive traces.

3. The method for forming a semiconductor package structure according to claim 2, wherein: The specific steps of etching the conductive material include: Attaching a photosensitive film to the surface of the conductive material; Forming a patterned mask layer on the surface of the photosensitive film, wherein the mask layer has an opening exposing the photosensitive film; Etching the photosensitive film and the conductive material along the opening to form a plurality of mutually independent conductive traces; The mask layer is removed.

4. The method for forming a semiconductor package structure according to claim 1, wherein: The first gas is argon, and the second gas is oxygen.

5. The method for forming a semiconductor package structure according to claim 1, wherein: The depth of the depression is 0.5 μm to 3 μm.

6. The method for forming a semiconductor package structure according to claim 3, wherein: The conductive material is a metal material; the specific steps of forming the barrier layer include: Thermally treating the conductive trace to form a barrier layer on the sidewall of the conductive trace; The photosensitive film is removed.

7. The method for forming a semiconductor package structure according to claim 6, wherein: The specific steps of forming a solder resist layer that at least fills the groove include: Forming a solder resist layer that fills the groove, the recess and covers the barrier layer and the surface of the conductive trace; The solder resist layer is etched to form a contact hole exposing a portion of the conductive trace.

8. The method for forming a semiconductor package structure according to claim 1, wherein: The distance between adjacent conductive traces is less than or equal to 20 μm.

9. A semiconductor package structure, formed by the method for forming a semiconductor package structure according to any one of claims 1 to 8, characterized in that: include: substrate; A plurality of mutually independent conductive traces are located on the substrate, and grooves exposing the substrate are provided between adjacent conductive traces; A barrier layer covering the sidewalls of the conductive trace; The solder resist layer is located on the substrate and at least fills the groove.

10. The semiconductor package structure according to claim 9, wherein: The material of the conductive trace is a metal material, and the material of the barrier layer is a metal oxide material.

11. The semiconductor package structure according to claim 9, wherein: The substrate has a depression located between adjacent conductive traces and connected to the groove; The solder resist layer fills the groove and the recess and covers the barrier layer and a portion of the surface of the conductive trace.

12. The semiconductor package structure according to claim 11, characterized in that: The depth of the depression is 0.5 μm to 3 μm.

13. The semiconductor package structure according to claim 9, wherein: The distance between adjacent conductive traces is less than or equal to 20 μm.

Images