A back passivated contact heterojunction solar cell and its preparation method

Abstract

The invention discloses a back passivated contact heterojunction solar cell and a preparation method thereof. The cell comprises a crystalline silicon substrate, and the back side of the crystalline silicon substrate is provided with a back contact passivation structure composed of a tunneling oxide layer, a P+ doped nanocrystalline silicon / microcrystalline silicon layer, a nanocrystalline silicon / microcrystalline silicon layer and an N+ doped nanocrystalline silicon / microcrystalline silicon layer arranged alternately, and a back anti-reflection passivation layer. The preparation method comprises the steps of injecting boron ions and phosphorus ions into the nanocrystalline silicon / microcrystalline silicon film in an ion implantation manner and performing annealing to form P+ doped regions and N+ doped regions arranged alternately. The back passivated contact heterojunction solar cell of the invention has the characteristics of high conversion efficiency, which can be as high as 25% or more. The preparation method thereof also has the advantages of simple process, convenient operation, low cost, etc., which is beneficial to the conversion efficiency and yield of the cell, suitable for large-scale preparation, and beneficial to industrial application. It is of great significance to promote the industrial application of HBC cells.

Description

Technical Field

[0001] The invention belongs to the technical field of solar cells, and relates to a back passivated contact heterojunction solar cell and a preparation method thereof. Background Art

[0002] From the perspective of global new energy forms, photovoltaic power generation is the focus of new energy development. As an emerging industry, the photovoltaic industry is continuing to develop rapidly, and cost reduction and efficiency improvement are the key to promoting the development of the photovoltaic industry. For solar cells, especially the back passivated contact heterojunction solar cells (HBC cells) combined with the full back passivated contact heterojunction solar cells (IBC cells) and heterojunction solar cells (HJT cells), they have very high conversion efficiency and are the key development target of the photovoltaic industry in the future. However, the existing HBC cell manufacturing technology has problems such as complicated process routes and high equipment investment costs. For example, some researchers have proposed a method for making a cross-finger back contact cell. However, in this method, only the first silicon nitride layer and the second silicon nitride layer are formed as anti-reflection layers on the back of the cell by plasma enhanced chemical vapor deposition, and no tunneling layer or amorphous silicon layer is used as a passivation layer, which is not conducive to the open circuit voltage, so that the cell conversion efficiency is still poor. In this regard, researchers proposed a HBC solar cell with a back contact passivation structure and a preparation method thereof. A tunneling oxide layer is introduced into the back of the HBC solar cell, but a wide laser groove area is used on the tunneling oxide layer to separate the N+ doped area and the P+ doped area, which is not conducive to improving the migration ability of carriers in the N+ doped area and the P+ doped area. Therefore, such a structure is also not conducive to improving the conversion efficiency of the battery. At the same time, its preparation method still has the defect of a relatively complicated preparation process, and when the laser groove method is used to remove the intermediate back passivation layer and the polysilicon layer, since the thickness of the tunneling oxide layer is only 1-2nm, the above laser groove method is difficult to achieve the complete retention of the tunneling oxide layer, and there is still a possibility that the tunneling oxide layer is burned through, resulting in a decrease in the conversion efficiency and yield of the battery. Therefore, how to obtain a back passivation contact heterojunction solar cell with high conversion efficiency and a matching preparation method with simple process, convenient operation and low cost is of great significance for promoting the industrial application of back passivation contact heterojunction solar cells. Summary of the invention

[0003] The technical problem to be solved by the present invention is to overcome the deficiencies of the prior art, provide a back-passivated contact heterojunction solar cell with high conversion efficiency, and also provide a preparation method of the back-passivated contact heterojunction solar cell with simple process, convenient operation and low cost.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0005] A back-passivated contact heterojunction solar cell comprises a crystalline silicon substrate, wherein the front side of the crystalline silicon substrate is provided with a front passivation layer and a front anti-reflection passivation layer in sequence from the inside to the outside; a tunneling oxide layer is provided on the back side of the crystalline silicon substrate; a P+ doped nanocrystalline silicon / microcrystalline silicon layer, a nanocrystalline silicon / microcrystalline silicon layer and an N+ doped nanocrystalline silicon / microcrystalline silicon layer are alternately arranged on the tunneling oxide layer, and the nanocrystalline silicon / microcrystalline silicon layer is located between the P+ doped nanocrystalline silicon / microcrystalline silicon layer and the N+ doped nanocrystalline silicon / microcrystalline silicon layer; a back anti-reflection passivation layer is provided on the P+ doped nanocrystalline silicon / microcrystalline silicon layer, the nanocrystalline silicon / microcrystalline silicon layer and the N+ doped nanocrystalline silicon / microcrystalline silicon layer; a metal negative electrode and a metal positive electrode are also provided on the back anti-reflection passivation layer; the metal negative electrode passes through the back anti-reflection passivation layer to form an ohmic contact with the N+ doped nanocrystalline silicon / microcrystalline silicon layer; the metal positive electrode passes through the back anti-reflection passivation layer to form an ohmic contact with the P+ doped nanocrystalline silicon / microcrystalline silicon layer.

[0006] The above-mentioned back-passivated contact heterojunction solar cell is further improved, wherein the P+ doped nanocrystalline silicon / microcrystalline silicon layer is obtained by mixing P+ doped nanocrystalline silicon and P+ doped microcrystalline silicon; the nanocrystalline silicon / microcrystalline silicon layer is obtained by mixing impure nanocrystalline silicon and impure microcrystalline silicon; the width of the nanocrystalline silicon / microcrystalline silicon layer is 1μm to 5μm; and the N+ doped nanocrystalline silicon / microcrystalline silicon layer is obtained by mixing N+ doped nanocrystalline silicon and N+ doped microcrystalline silicon.

[0007] The above-mentioned back passivated contact heterojunction solar cell is further improved, wherein the square resistance of the P+ doped nanocrystalline silicon / microcrystalline silicon layer is 30Ω / □~80Ω / □; the thickness of the P+ doped nanocrystalline silicon / microcrystalline silicon layer is 20nm~150nm; the square resistance of the N+ doped nanocrystalline silicon / microcrystalline silicon layer is 70Ω / □~120Ω / □; the thickness of the N+ doped nanocrystalline silicon / microcrystalline silicon layer is 20nm~150nm.

[0008] The above-mentioned back passivated contact heterojunction solar cell is further improved in that the crystalline silicon substrate is N-type single crystal silicon or P-type single crystal silicon; the resistivity of the crystalline silicon substrate is 1Ω / □ to 10Ω / □.

[0009] The above-mentioned back-passivated contact heterojunction solar cell is further improved in that the front passivation layer is a silicon oxide film; the thickness of the front passivation layer is 50nm to 100nm.

[0010] The above-mentioned back passivated contact heterojunction solar cell is further improved in that the front anti-reflection passivation layer is composed of two layers of SiN with different refractive indices. x The front anti-reflection passivation layer has a bottom layer of SiN with a refractive index of 2.1 to 2.2. xThe film is 30nm thick, and the top layer is SiN with a refractive index of 1.6 to 1.6 x Film with a thickness of 45nm to 55nm.

[0011] The above-mentioned back-passivated contact heterojunction solar cell is further improved in that the tunneling oxide layer is a silicon oxide film; the thickness of the tunneling oxide layer is 0.5nm to 2nm.

[0012] The above-mentioned back passivated contact heterojunction solar cell is further improved, wherein the back anti-reflection passivation layer is SiN x Film; the thickness of the back anti-reflection passivation layer is 80nm to 90nm.

[0013] The above-mentioned back passivated contact heterojunction solar cell is further improved in that the metal negative electrode is an Ag electrode or a Cu electrode.

[0014] The above-mentioned back passivated contact heterojunction solar cell is further improved in that the metal positive electrode is an Ag electrode or a Cu electrode.

[0015] As a technical concept, the present invention also provides a method for preparing a back passivated contact heterojunction solar cell, comprising the following steps:

[0016] S1, polishing the back side of the crystalline silicon substrate;

[0017] S2, sequentially depositing a tunneling oxide layer and an intrinsic amorphous silicon layer on the back side of the crystalline silicon substrate;

[0018] S3, performing texturing on the front side of the crystalline silicon substrate to form a pyramid texture surface;

[0019] S4, performing thermal oxygen annealing on the crystalline silicon substrate on which the tunneling oxide layer and the intrinsic amorphous silicon layer are deposited, so as to form a front passivation layer on the front side of the crystalline silicon substrate and form a nanocrystalline silicon / microcrystalline silicon thin film on the back side of the crystalline silicon substrate;

[0020] S5, using ion implantation to alternately implant phosphorus ions and boron ions into the nanocrystalline silicon / microcrystalline silicon film;

[0021] S6, annealing the nanocrystalline silicon / microcrystalline silicon film implanted with phosphorus ions and boron ions to form a P+-doped nanocrystalline silicon / microcrystalline silicon layer, a nanocrystalline silicon / microcrystalline silicon layer, and an N+-doped nanocrystalline silicon / microcrystalline silicon layer that are alternately arranged;

[0022] S7, depositing an anti-reflection passivation layer on the front and back sides of the crystalline silicon substrate;

[0023] S8. Prepare a metal negative electrode and a metal positive electrode on the anti-reflection passivation layer on the back side of the crystalline silicon substrate respectively, and complete the preparation of the back-passivated contact heterojunction solar cell.

[0024] The above-mentioned method for preparing a back-passivated contact heterojunction solar cell is further improved, in which in step S5, phosphorus ions and boron ions are alternately implanted into the nanocrystalline silicon / microcrystalline silicon film by any of the following methods;

[0025] Method 1 includes the following steps:

[0026] (1) preparing a mask on the surface of the P+ region on the back side of the crystalline silicon substrate;

[0027] (2) using ion implantation to implant phosphorus ions into the nanocrystalline silicon / microcrystalline silicon film in the N+ region;

[0028] (3) preparing a mask on the surface of the N+ region;

[0029] (4) removing the mask on the surface of the P+ region and implanting boron ions into the nanocrystalline silicon / microcrystalline silicon film in the P+ region by ion implantation;

[0030] (5) Remove the mask on the surface of the N+ region.

[0031] Method 2 includes the following steps:

[0032] (a) preparing a mask on the surface of the N+ region on the back side of the crystalline silicon substrate;

[0033] (b) Boron ions are implanted into the nanocrystalline silicon / microcrystalline silicon film in the P+ region by ion implantation;

[0034] (c) preparing a mask on the surface of the P+ region;

[0035] (d) removing the mask on the surface of the N+ region, and implanting phosphorus ions into the nanocrystalline silicon / microcrystalline silicon film in the N+ region by ion implantation;

[0036] (e) Remove the mask on the surface of the P+ region.

[0037] The above-mentioned method for preparing a back-passivated contact heterojunction solar cell is further improved in that in step (1), a mask is prepared on the surface of the N+ region on the back side of the crystalline silicon substrate by using exposure, development and etching processes; the mask is a diazo compound positive photoresist.

[0038] The above-mentioned method for preparing a back passivated contact heterojunction solar cell is further improved, wherein in step (2), during the phosphorus ion implantation process, the implantation dose is 5×10 14 cm -2 ~2×10 15 cm -2 , the injection energy is 5keV~50keV.

[0039] The above-mentioned method for preparing a back-passivated contact heterojunction solar cell is further improved in that in step (3), a mask is prepared on the surface of the N+ region by using an exposure, development, and etching process; the mask is a diazo compound positive photoresist.

[0040] The above-mentioned method for preparing a back-passivated contact heterojunction solar cell is further improved, wherein in step (4), the mask on the surface of the P+ region is removed by laser grooving; during the boron ion implantation, the implantation dose is 5×10 14 cm -2 ~2×10 15 cm -2 , the injection energy is 5keV~50keV.

[0041] The above-mentioned method for preparing a back-passivated contact heterojunction solar cell is further improved in that in step (5), the mask on the surface of the N+ region is removed by laser grooving.

[0042] The above-mentioned method for preparing a back-passivated contact heterojunction solar cell is further improved. In step (a), a mask is prepared on the surface of the P+ region on the back side of the crystalline silicon substrate by using exposure, development and etching processes; the mask is a diazo compound positive photoresist.

[0043] The above-mentioned method for preparing a back passivated contact heterojunction solar cell is further improved, wherein in step (b), during the implantation of boron ions, the implantation dose is 5×10 14 cm -2 ~2×10 15 cm -2 , the injection energy is 5keV~50keV.

[0044] The above-mentioned method for preparing a back-passivated contact heterojunction solar cell is further improved in that in step (c), a mask is prepared on the surface of the N+ region on the back side of the crystalline silicon substrate by using exposure, development and etching processes; the mask is a diazo compound positive photoresist.

[0045] The above-mentioned method for preparing a back-passivated contact heterojunction solar cell is further improved, wherein in step (d), the mask of the N+ region is removed by laser grooving; during the phosphorus ion implantation, the implantation dose is 5×10 14 cm -2 ~2×10 15 cm -2 , the injection energy is 5keV~50keV.

[0046] The above-mentioned method for preparing a back-passivated contact heterojunction solar cell is further improved in that in step (e), the mask of the P+ region is removed by laser grooving.

[0047] The above-mentioned method for preparing a back-passivated contact heterojunction solar cell is further improved. In step S1, an alkaline solution is used to polish the back side of the crystalline silicon substrate; the alkaline solution is a sodium hydroxide solution; the mass concentration of the alkaline solution is 2% to 10%; and the thickness of the crystalline silicon substrate is 100μm to 180μm.

[0048] The above-mentioned method for preparing a back-passivated contact heterojunction solar cell is further improved. In step S2, a tunneling oxide layer and an intrinsic amorphous silicon layer are sequentially deposited on the back side of a crystalline silicon substrate using a PECVD process; during the deposition of the tunneling oxide layer, the process parameters of the PECVD process are: a temperature of 250°C to 600°C, a spacing between parallel plates of 20mm to 60mm, a process chamber pressure of 15Pa to 200Pa, a radio frequency power of 50W to 400W, a deposition time of 20s to 120s, a SiH4 flow rate of 25sccm to 2400sccm, and an argon flow rate of 0sccm to 1000sccm. 20000sccm, the flow rate of N2O is 0sccm~20000sccm; during the deposition process of the intrinsic amorphous silicon layer, the process parameters of the PECVD process are: process chamber pressure 30Pa~80pa, temperature 450℃~600℃, RF power 50W~1200W, deposition time 100s~600s, SiH4 flow rate 25sccm~2400sccm, argon flow rate 0sccm~20000sccm, N2O flow rate 0sccm~20000sccm; H2 flow rate is 0sccm~20000sccm.

[0049] The above-mentioned method for preparing a back-passivated contact heterojunction solar cell is further improved, in which in step S3, a mixed solution of hydrogen peroxide, deionized water, additives and sodium hydroxide is used to texture the front surface of the crystalline silicon substrate;

[0050] The above-mentioned method for preparing a back-passivated contact heterojunction solar cell is further improved, in which in step S4, the thermal oxygen annealing is performed in an oxygen atmosphere; during the thermal oxygen annealing, the pressure is maintained at 40-80 kPa and the temperature is maintained at 600° C.-700° C.

[0051] The above-mentioned method for preparing a back-passivated contact heterojunction solar cell is further improved. In step S6, the annealing treatment is: first heating to 560°C to 600°C in a nitrogen atmosphere, maintaining for 60min to 90min, and then heating to 900°C to 1000°C in an oxygen atmosphere, maintaining for 25min to 30min.

[0052] The above-mentioned method for preparing a back-passivated contact heterojunction solar cell is further improved. In step S7, a PECVD process is used to deposit an anti-reflection passivation layer on the front and back sides of the crystalline silicon substrate; during the deposition of the anti-reflection passivation layer on the front side of the crystalline silicon substrate, the process parameters of the PECVD process are: a deposition temperature of 450°C, and a flow ratio of SiH4 to NH3 of 1:4 and 1:8; during the deposition of the anti-reflection passivation layer on the back side of the crystalline silicon substrate, the process parameters of the PECVD process are: a deposition temperature of 450°C, and a flow ratio of SiH4 to NH3 of 1:8.

[0053] The above-mentioned method for preparing a back-passivated contact heterojunction solar cell is further improved. In step S8, a metal negative electrode and a metal positive electrode are respectively prepared on the anti-reflection passivation layer on the back side of the crystalline silicon substrate by screen printing and sintering or electroplating.

[0054] The above-mentioned method for preparing a back-passivated contact heterojunction solar cell is further improved, wherein the back-passivated contact heterojunction solar cell comprises a crystalline silicon substrate, wherein the front surface of the crystalline silicon substrate is provided with a front passivation layer and a front anti-reflection passivation layer in sequence from the inside to the outside; the back surface of the crystalline silicon substrate is provided with a tunneling oxide layer; the tunneling oxide layer is alternately arranged with a P+ doped nanocrystalline silicon / microcrystalline silicon layer, a nanocrystalline silicon / microcrystalline silicon layer and an N+ doped nanocrystalline silicon / microcrystalline silicon layer, wherein the nanocrystalline silicon / microcrystalline silicon layer is located between the P+ doped nanocrystalline silicon / microcrystalline silicon layer and the nanocrystalline silicon / microcrystalline silicon layer. A back anti-reflection passivation layer is provided on the P+ doped nanocrystalline silicon / microcrystalline silicon layer, the nanocrystalline silicon / microcrystalline silicon layer and the N+ doped nanocrystalline silicon / microcrystalline silicon layer; a metal negative electrode and a metal positive electrode are also provided on the back anti-reflection passivation layer; the metal negative electrode passes through the back anti-reflection passivation layer to form an ohmic contact with the N+ doped nanocrystalline silicon / microcrystalline silicon layer; the metal positive electrode passes through the back anti-reflection passivation layer to form an ohmic contact with the P+ doped nanocrystalline silicon / microcrystalline silicon layer.

[0055] The above-mentioned method for preparing a back-passivated contact heterojunction solar cell is further improved, wherein the P+ doped nanocrystalline silicon / microcrystalline silicon layer is obtained by mixing P+ doped nanocrystalline silicon and P+ doped microcrystalline silicon; the nanocrystalline silicon / microcrystalline silicon layer is obtained by mixing impure nanocrystalline silicon and impure microcrystalline silicon; the width of the nanocrystalline silicon / microcrystalline silicon layer is 1μm to 5μm; and the N+ doped nanocrystalline silicon / microcrystalline silicon layer is obtained by mixing N+ doped nanocrystalline silicon and N+ doped microcrystalline silicon.

[0056] The above-mentioned method for preparing a back-passivated contact heterojunction solar cell is further improved, wherein the square resistance of the P+ doped nanocrystalline silicon / microcrystalline silicon layer is 30Ω / □~80Ω / □; the thickness of the P+ doped nanocrystalline silicon / microcrystalline silicon layer is 20nm~150nm; the square resistance of the N+ doped nanocrystalline silicon / microcrystalline silicon layer is 70Ω / □~120Ω / □; the thickness of the N+ doped nanocrystalline silicon / microcrystalline silicon layer is 20nm~150nm.

[0057] The above-mentioned method for preparing a back-passivated contact heterojunction solar cell is further improved in that the crystalline silicon substrate is N-type single crystal silicon or P-type single crystal silicon; the resistivity of the crystalline silicon substrate is 1Ω / □ to 10Ω / □.

[0058] The above-mentioned method for preparing a rear-passivated contact heterojunction solar cell is further improved in that the front passivation layer is a silicon oxide film; the thickness of the front passivation layer is 50nm to 100nm.

[0059] The above-mentioned method for preparing a rear passivated contact heterojunction solar cell is further improved in that the front anti-reflection passivation layer is composed of two layers of SiN with different refractive indices. x The front anti-reflection passivation layer has a bottom layer of SiN with a refractive index of 2.1 to 2.2. x The film is 30nm thick, and the top layer is SiN with a refractive index of 1.6 to 1.6 x Film with a thickness of 45nm to 55nm.

[0060] The above-mentioned method for preparing a back-passivated contact heterojunction solar cell is further improved in that the tunneling oxide layer is a silicon oxide film; the thickness of the tunneling oxide layer is 0.5nm to 2nm.

[0061] The above-mentioned method for preparing a back-passivated contact heterojunction solar cell is further improved, wherein the back-side anti-reflection passivation layer is SiN x Film; the thickness of the back anti-reflection passivation layer is 80nm to 90nm.

[0062] The above-mentioned method for preparing a back-passivated contact heterojunction solar cell is further improved in that the metal negative electrode is an Ag electrode or a Cu electrode.

[0063] The above-mentioned method for preparing a back-passivated contact heterojunction solar cell is further improved in that the metal positive electrode is an Ag electrode or a Cu electrode.

[0064] Compared with the prior art, the advantages of the present invention are:

[0065] (1) Aiming at the defects of low conversion efficiency still existing in the existing HBC cells, the present invention creatively provides a back passivated contact heterojunction solar cell, wherein a tunneling oxide layer is provided on the back of the cell, and a P+ doped nanocrystalline silicon / microcrystalline silicon layer, a nanocrystalline silicon / microcrystalline silicon layer and an N+ doped nanocrystalline silicon / microcrystalline silicon layer are alternately arranged on the tunneling oxide layer, and the nanocrystalline silicon / microcrystalline silicon layer is located between the P+ doped nanocrystalline silicon / microcrystalline silicon layer and the N+ doped nanocrystalline silicon / microcrystalline silicon layer, and a back anti-reflection passivation layer is provided on the P+ doped nanocrystalline silicon / microcrystalline silicon layer, the nanocrystalline silicon / microcrystalline silicon layer and the N+ doped nanocrystalline silicon / microcrystalline silicon layer, and the back passivated contact structure constructed in this way can effectively improve the short-circuit current density and opening voltage of the cell, and thus can significantly improve the conversion efficiency of the cell. The back passivated contact heterojunction solar cell of the present invention has the advantages of high conversion efficiency, is a new type of solar cell with excellent performance, high use value and good application prospects, and is of great significance for promoting the industrial application of back passivated contact heterojunction solar cells.

[0066] (2) In view of the defects of the existing HBC battery preparation methods, such as complex process, difficult operation, difficulty in completely retaining the back passivation contact structure, and the resulting low battery conversion efficiency and low yield, the present invention creatively proposes a method for preparing a back passivation contact heterojunction solar cell, which adopts ion implantation to prepare the N+ doping layer and the P+ doping layer, which can not only accurately control the doping concentration, but also selectively implant phosphorus ions and boron ions into the nanocrystalline silicon / microcrystalline silicon film on the back to form an N+ doped layer separated by the nanocrystalline silicon / microcrystalline silicon film. The invention discloses a back passivation contact structure of a silicon wafer and a P+ doped region, which has the characteristics of high control accuracy and good diffusion uniformity, and can also adjust the spacing distance between the N+ doped region and the P+ doped region. At the same time, after ion implantation, annealing treatment is continued to be performed to activate impurities and push them into the silicon wafer. Not only can a back passivation contact structure constructed by a tunneling oxide layer, a P+ doped nanocrystalline silicon / microcrystalline silicon layer, a nanocrystalline silicon / microcrystalline silicon layer and an N+ doped nanocrystalline silicon / microcrystalline silicon layer, and a back anti-reflection passivation layer be formed on the back, but also the lattice damage on the silicon wafer surface caused by ion implantation can be repaired, which is beneficial to improving the conversion efficiency of the battery. Compared with the HBC battery prepared by the conventional method, the conversion efficiency of the back passivation contact heterojunction solar cell prepared by the preparation method of the invention can be increased from 24.5% to more than 25%, and the open circuit voltage can be increased from 0.705V to 0.735V, showing very excellent electrical performance. In addition, the preparation method of the invention also has the advantages of simple process, convenient operation, low cost, etc., which is beneficial to the conversion efficiency and yield of the battery, suitable for large-scale preparation, and conducive to industrial application. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] In order to make the purpose, technical solution and advantages of the embodiments of the present invention more clear, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention.

[0068] Figure 1 It is a schematic diagram of the partial structure of the back-passivated contact heterojunction solar cell in Example 1 of the present invention.

[0069] Figure 2 This is a process flow chart for preparing a back-passivated contact heterojunction solar cell in Example 1 of the present invention.

[0070] Legend: 10, crystalline silicon substrate; 11, front passivation layer; 12, front anti-reflection passivation layer; 20, tunneling oxide layer; 30, P+ doped nanocrystalline silicon / microcrystalline silicon layer; 40, N+ doped nanocrystalline silicon / microcrystalline silicon layer; 50, back anti-reflection passivation layer; 60, metal negative electrode; 70, metal positive electrode. DETAILED DESCRIPTION

[0071] The present invention is further described below in conjunction with the accompanying drawings and specific preferred embodiments, but the protection scope of the present invention is not limited thereby.

[0072] Example

[0073] A back-passivated contact heterojunction solar cell comprises a crystalline silicon substrate, wherein a front passivation layer and a front anti-reflection passivation layer are sequentially arranged on the front side of the crystalline silicon substrate from the inside to the outside; a tunneling oxide layer is arranged on the back side of the crystalline silicon substrate; a P+ doped nanocrystalline silicon / microcrystalline silicon layer, a nanocrystalline silicon / microcrystalline silicon layer and an N+ doped nanocrystalline silicon / microcrystalline silicon layer are alternately arranged on the tunneling oxide layer, and the nanocrystalline silicon / microcrystalline silicon layer is located between the P+ doped nanocrystalline silicon / microcrystalline silicon layer and the N+ doped nanocrystalline silicon / microcrystalline silicon layer; a back anti-reflection passivation layer is arranged on the P+ doped nanocrystalline silicon / microcrystalline silicon layer, the nanocrystalline silicon / microcrystalline silicon layer and the N+ doped nanocrystalline silicon / microcrystalline silicon layer; a metal negative electrode and a metal positive electrode are also arranged on the back anti-reflection passivation layer; the metal negative electrode passes through the back anti-reflection passivation layer to form an ohmic contact with the N+ doped nanocrystalline silicon / microcrystalline silicon layer; the metal positive electrode passes through the back anti-reflection passivation layer to form an ohmic contact with the P+ doped nanocrystalline silicon / microcrystalline silicon layer.

[0074] In the present embodiment, it is further improved that the P+ doped nanocrystalline silicon / microcrystalline silicon layer is obtained by mixing P+ doped nanocrystalline silicon and P+ doped microcrystalline silicon; the nanocrystalline silicon / microcrystalline silicon layer is obtained by mixing impure nanocrystalline silicon and impure microcrystalline silicon; the width of the nanocrystalline silicon / microcrystalline silicon layer is 1μm to 5μm; the N+ doped nanocrystalline silicon / microcrystalline silicon layer is obtained by mixing N+ doped nanocrystalline silicon and N+ doped microcrystalline silicon.

[0075] In this embodiment, the square resistance of the P+ doped nanocrystalline silicon / microcrystalline silicon layer is 30Ω / □~80Ω / □; the thickness of the P+ doped nanocrystalline silicon / microcrystalline silicon layer is 20nm~150nm; the square resistance of the N+ doped nanocrystalline silicon / microcrystalline silicon layer is 70Ω / □~120Ω / □; the thickness of the N+ doped nanocrystalline silicon / microcrystalline silicon layer is 20nm~150nm.

[0076] In this embodiment, the crystalline silicon substrate is N-type single crystal silicon or P-type single crystal silicon; the resistivity of the crystalline silicon substrate is 1Ω / □ to 10Ω / □.

[0077] In this embodiment, the front passivation layer is a silicon oxide film; the thickness of the front passivation layer is 50nm-100nm.

[0078] In this embodiment, the front anti-reflection passivation layer is composed of two layers of SiN with different refractive indices. x The front anti-reflection passivation layer is composed of SiN with a refractive index of 2.1 to 2.2. x The film is 30nm thick, and the top layer is SiN with a refractive index of 1.6 to 1.6 x Film with a thickness of 45nm to 55nm.

[0079] In this embodiment, the tunneling oxide layer is a silicon oxide film; the thickness of the tunneling oxide layer is 0.5 nm to 2 nm.

[0080] In this embodiment, the back anti-reflection passivation layer is SiN x Film; the thickness of the back anti-reflection passivation layer is 80nm to 90nm.

[0081] In this embodiment, the metal negative electrode is an Ag electrode or a Cu electrode.

[0082] In this embodiment, the metal positive electrode is an Ag electrode or a Cu electrode.

[0083] In this embodiment, a method for preparing a back-passivated contact heterojunction solar cell is also provided, comprising the following steps:

[0084] S1, polishing the back side of the crystalline silicon substrate;

[0085] S2, sequentially depositing a tunneling oxide layer and an intrinsic amorphous silicon layer on the back side of the crystalline silicon substrate;

[0086] S3, performing texturing on the front side of the crystalline silicon substrate to form a pyramid texture surface;

[0087] S4, performing thermal oxygen annealing on the crystalline silicon substrate on which the tunneling oxide layer and the intrinsic amorphous silicon layer are deposited, so as to form a front passivation layer on the front side of the crystalline silicon substrate and form a nanocrystalline silicon / microcrystalline silicon thin film on the back side of the crystalline silicon substrate;

[0088] S5, using ion implantation to alternately implant phosphorus ions and boron ions into the nanocrystalline silicon / microcrystalline silicon film;

[0089] S6, annealing the nanocrystalline silicon / microcrystalline silicon film implanted with phosphorus ions and boron ions to form a P+-doped nanocrystalline silicon / microcrystalline silicon layer, a nanocrystalline silicon / microcrystalline silicon layer, and an N+-doped nanocrystalline silicon / microcrystalline silicon layer that are alternately arranged;

[0090] S7, depositing an anti-reflection passivation layer on the front and back sides of the crystalline silicon substrate;

[0091] S8. Prepare a metal negative electrode and a metal positive electrode on the anti-reflection passivation layer on the back side of the crystalline silicon substrate respectively, and complete the preparation of the back-passivated contact heterojunction solar cell.

[0092] In this embodiment, in step S5, phosphorus ions and boron ions are alternately implanted into the nanocrystalline silicon / microcrystalline silicon film by any of the following methods:

[0093] Method 1 includes the following steps:

[0094] (1) preparing a mask on the surface of the P+ region on the back side of the crystalline silicon substrate;

[0095] (2) using ion implantation to implant phosphorus ions into the nanocrystalline silicon / microcrystalline silicon film in the N+ region;

[0096] (3) preparing a mask on the surface of the N+ region;

[0097] (4) removing the mask on the surface of the P+ region and implanting boron ions into the nanocrystalline silicon / microcrystalline silicon film in the P+ region by ion implantation;

[0098] (5) Remove the mask on the surface of the N+ region.

[0099] Method 2 includes the following steps:

[0100] (a) preparing a mask on the surface of the N+ region on the back side of the crystalline silicon substrate;

[0101] (b) Boron ions are implanted into the nanocrystalline silicon / microcrystalline silicon film in the P+ region by ion implantation;

[0102] (c) preparing a mask on the surface of the P+ region;

[0103] (d) removing the mask on the surface of the N+ region, and implanting phosphorus ions into the nanocrystalline silicon / microcrystalline silicon film in the N+ region by ion implantation;

[0104] (e) Remove the mask on the surface of the P+ region.

[0105] In this embodiment, in step (1), a mask is prepared on the surface of the N+ region on the back side of the crystalline silicon substrate by using an exposure, development, and etching process; the mask is a diazo compound positive photoresist.

[0106] In this embodiment, in step (2), during the phosphorus ion implantation, the implantation dose is 5×10 14 cm -2 ~2×10 15 cm -2 , the injection energy is 5keV~50keV.

[0107] In this embodiment, in step (3), a mask is prepared on the surface of the N+ region by using a process of exposure, development, and etching; the mask is a diazo compound positive photoresist.

[0108] In this embodiment, in step (4), the mask on the surface of the P+ region is removed by laser grooving; during the implantation of boron ions, the implantation dose is 5×10 14 cm -2 ~2×10 15 cm -2 , the injection energy is 5keV~50keV.

[0109] In this embodiment, in step (5), the mask on the surface of the N+ region is removed by laser grooving.

[0110] In this embodiment, in step (a), a mask is prepared on the surface of the P+ region on the back side of the crystalline silicon substrate by using an exposure, development, and etching process; the mask is a diazo compound positive photoresist.

[0111] In this embodiment, in step (b), during the implantation of boron ions, the implantation dose is 5×10 14 cm -2 ~2×10 15 cm -2 , the injection energy is 5keV~50keV.

[0112] In this embodiment, in step (c), a mask is prepared on the surface of the N+ region on the back side of the crystalline silicon substrate by using exposure, development and etching processes; the mask is a diazo compound positive photoresist.

[0113] In this embodiment, in step (d), the mask of the N+ region is removed by laser grooving; during the phosphorus ion implantation, the implantation dose is 5×10 14 cm -2 ~2×10 15 cm -2 , the injection energy is 5keV~50keV.

[0114] In this embodiment, in step (e), the mask of the P+ region is removed by laser grooving.

[0115] In this embodiment, in step S1, an alkaline solution is used to polish the back side of the crystalline silicon substrate; the alkaline solution is a sodium hydroxide solution; the mass concentration of the alkaline solution is 2% to 10%; and the thickness of the crystalline silicon substrate is 100 μm to 180 μm.

[0116] In this embodiment, in step S2, a tunneling oxide layer and an intrinsic amorphous silicon layer are sequentially deposited on the back side of the crystalline silicon substrate using a PECVD process; during the deposition of the tunneling oxide layer, the process parameters of the PECVD process are: a temperature of 250°C to 600°C, a spacing between parallel plates of 20mm to 60mm, a process chamber pressure of 15Pa to 200Pa, a radio frequency power of 50W to 400W, a deposition time of 20s to 120s, a SiH4 flow rate of 25sccm to 2400sccm, an argon flow rate of 0sccm to 20000sccm, and N 2O flow rate is 0sccm~20000sccm; during the deposition of the intrinsic amorphous silicon layer, the process parameters of the PECVD process are: process chamber pressure 30Pa~80pa, temperature 450℃~600℃, RF power 50W~1200W, deposition time 100s~600s, SiH4 flow rate is 25sccm~2400sccm, argon flow rate is 0sccm~20000sccm, N2O flow rate is 0sccm~20000sccm; H2 flow rate is 0sccm~20000sccm.

[0117] In this embodiment, in step S3, a mixed solution of hydrogen peroxide, deionized water, additives and sodium hydroxide is used to texture the front surface of the crystalline silicon substrate;

[0118] In this embodiment, in step S4, thermal oxygen annealing is performed in an oxygen atmosphere; during the thermal oxygen annealing, the pressure is maintained at 40-80 kPa and the temperature is maintained at 600° C.-700° C.

[0119] In this embodiment, in step S6, the annealing treatment is: first heating to 560°C to 600°C in a nitrogen atmosphere, maintaining for 60min to 90min, and then heating to 900°C to 1000°C in an oxygen atmosphere, maintaining for 25min to 30min.

[0120] In this embodiment, in step S7, a PECVD process is used to deposit an anti-reflection passivation layer on the front and back sides of the crystalline silicon substrate; during the deposition of the anti-reflection passivation layer on the front side of the crystalline silicon substrate, the process parameters of the PECVD process are: a deposition temperature of 450°C, and a flow ratio of SiH4 to NH3 of 1:4 and 1:8; during the deposition of the anti-reflection passivation layer on the back side of the crystalline silicon substrate, the process parameters of the PECVD process are: a deposition temperature of 450°C, and a flow ratio of SiH4 to NH3 of 1:8.

[0121] In this embodiment, in step S8, a metal negative electrode and a metal positive electrode are respectively prepared on the anti-reflection passivation layer on the back side of the crystalline silicon substrate by screen printing and sintering or electroplating.

[0122] In this embodiment, a back-passivated contact heterojunction solar cell is prepared, including a crystalline silicon substrate, wherein a front passivation layer and a front anti-reflection passivation layer are sequentially arranged on the front side of the crystalline silicon substrate from the inside to the outside; a tunneling oxide layer is arranged on the back side of the crystalline silicon substrate; a P+ doped nanocrystalline silicon / microcrystalline silicon layer, a nanocrystalline silicon / microcrystalline silicon layer and an N+ doped nanocrystalline silicon / microcrystalline silicon layer are alternately arranged on the tunneling oxide layer, and the nanocrystalline silicon / microcrystalline silicon layer is located between the P+ doped nanocrystalline silicon / microcrystalline silicon layer and the N+ doped nanocrystalline silicon / microcrystalline silicon layer; a back anti-reflection passivation layer is arranged on the P+ doped nanocrystalline silicon / microcrystalline silicon layer, the nanocrystalline silicon / microcrystalline silicon layer and the N+ doped nanocrystalline silicon / microcrystalline silicon layer; a metal negative electrode and a metal positive electrode are also arranged on the back anti-reflection passivation layer; the metal negative electrode passes through the back anti-reflection passivation layer to form an ohmic contact with the N+ doped nanocrystalline silicon / microcrystalline silicon layer; the metal positive electrode passes through the back anti-reflection passivation layer to form an ohmic contact with the P+ doped nanocrystalline silicon / microcrystalline silicon layer.

[0123] In this embodiment, the P+ doped nanocrystalline silicon / microcrystalline silicon layer is obtained by mixing P+ doped nanocrystalline silicon and P+ doped microcrystalline silicon; the nanocrystalline silicon / microcrystalline silicon layer is obtained by mixing impure nanocrystalline silicon and impure microcrystalline silicon; the width of the nanocrystalline silicon / microcrystalline silicon layer is 1μm to 5μm; the N+ doped nanocrystalline silicon / microcrystalline silicon layer is obtained by mixing N+ doped nanocrystalline silicon and N+ doped microcrystalline silicon.

[0124] In this embodiment, the square resistance of the P+ doped nanocrystalline silicon / microcrystalline silicon layer is 30Ω / □~80Ω / □; the thickness of the P+ doped nanocrystalline silicon / microcrystalline silicon layer is 20nm~150nm; the square resistance of the N+ doped nanocrystalline silicon / microcrystalline silicon layer is 70Ω / □~120Ω / □; the thickness of the N+ doped nanocrystalline silicon / microcrystalline silicon layer is 20nm~150nm.

[0125] In this embodiment, the crystalline silicon substrate is N-type single crystal silicon or P-type single crystal silicon; the resistivity of the crystalline silicon substrate is 1Ω / □ to 10Ω / □.

[0126] In this embodiment, the front passivation layer is a silicon oxide film; the thickness of the front passivation layer is 50nm-100nm.

[0127] In this embodiment, the front anti-reflection passivation layer is composed of two layers of SiN with different refractive indices. x The front anti-reflection passivation layer is composed of SiN with a refractive index of 2.1 to 2.2. x The film is 30nm thick, and the top layer is SiN with a refractive index of 1.6 to 1.6 x Film with a thickness of 45nm to 55nm.

[0128] In this embodiment, the tunneling oxide layer is a silicon oxide film; the thickness of the tunneling oxide layer is 0.5 nm to 2 nm.

[0129] In this embodiment, the back anti-reflection passivation layer is SiN x Film; the thickness of the back anti-reflection passivation layer is 80nm to 90nm.

[0130] In this embodiment, the metal negative electrode is an Ag electrode or a Cu electrode.

[0131] In this embodiment, the metal positive electrode is an Ag electrode or a Cu electrode.

[0132] Embodiment 1:

[0133] like Figure 1 As shown, a back-passivated contact heterojunction solar cell comprises a crystalline silicon substrate 10, wherein a front passivation layer 11 and a front anti-reflection passivation layer 12 are sequentially arranged on the front side of the crystalline silicon substrate 10 from the inside to the outside; a tunneling oxide layer 20 is arranged on the back side of the crystalline silicon substrate 10, and a P+ doped nanocrystalline silicon / microcrystalline silicon layer 30, a nanocrystalline silicon / microcrystalline silicon layer and an N+ doped nanocrystalline silicon / microcrystalline silicon layer 40 are alternately arranged on the tunneling oxide layer 20, and the nanocrystalline silicon / microcrystalline silicon layer is located between the P+ doped nanocrystalline silicon / microcrystalline silicon layer and the N+ doped nanocrystalline silicon / microcrystalline silicon layer. A back anti-reflection passivation layer 50 is provided between the crystalline silicon layers, on the P+ doped nanocrystalline silicon / microcrystalline silicon layer 30, the nanocrystalline silicon / microcrystalline silicon layer and the N+ doped nanocrystalline silicon / microcrystalline silicon layer 40, and a metal negative electrode 60 and a metal positive electrode are also provided on the back anti-reflection passivation layer 50. The metal negative electrode 60 passes through the back anti-reflection passivation layer 50 to form an ohmic contact with the N+ doped nanocrystalline silicon / microcrystalline silicon layer 40, and the metal positive electrode 70 passes through the back anti-reflection passivation layer 50 to form an ohmic contact with the P+ doped nanocrystalline silicon / microcrystalline silicon layer 30.

[0134] In this embodiment, the alternately arranged P+ doped nanocrystalline silicon / microcrystalline silicon layer 30, nanocrystalline silicon / microcrystalline silicon layer and N+ doped nanocrystalline silicon / microcrystalline silicon layer 40 present an "interdigitated structure", also known as an interdigitated structure.

[0135] In this embodiment, the P+ doped nanocrystalline silicon / microcrystalline silicon layer 30 is obtained by mixing P+ doped nanocrystalline silicon and P+ doped microcrystalline silicon; the nanocrystalline silicon / microcrystalline silicon layer is obtained by mixing impure nanocrystalline silicon and impure microcrystalline silicon, and the width of the nanocrystalline silicon / microcrystalline silicon layer is 3μm, that is, the spacing distance between the P+ doped nanocrystalline silicon / microcrystalline silicon layer 30 and the N+ doped nanocrystalline silicon / microcrystalline silicon layer 40 is 3μm, which is much smaller than the width of the laser groove area. Generally speaking, the width of the laser groove area is as high as 100μm or more; the N+ doped nanocrystalline silicon / microcrystalline silicon layer 40 is obtained by mixing N+ doped nanocrystalline silicon and N+ doped microcrystalline silicon.

[0136] In this embodiment, the square resistance of the P+ doped nanocrystalline silicon / microcrystalline silicon layer 30 is 40Ω / □; the square resistance of the N+ doped nanocrystalline silicon / microcrystalline silicon layer 40 is 110Ω / □.

[0137] In this embodiment, the thickness of the P+ doped nanocrystalline silicon / microcrystalline silicon layer 30 is 80 nm; the thickness of the N+ doped nanocrystalline silicon / microcrystalline silicon layer 40 is 80 nm.

[0138] In this embodiment, the crystalline silicon substrate 10 is N-type single crystal silicon, and the resistivity is 10Ω / □.

[0139] In this embodiment, the front passivation layer 11 is a silicon oxide film with a thickness of 100 nm.

[0140] In this embodiment, the front anti-reflection passivation layer 12 is composed of two layers of SiN with different refractive indices. x The bottom layer is SiN with a refractive index of 2.1 to 2.2. x The film is 30nm thick, and the top layer is SiN with a refractive index of 1.6 to 1.6 x The film thickness is 55nm and the total thickness is 85nm.

[0141] In this embodiment, the tunnel oxide layer 20 is a silicon oxide film with a thickness of 2 nm.

[0142] In this embodiment, the back anti-reflection passivation layer 50 is SiN x The film thickness is 80nm.

[0143] In this embodiment, the metal negative electrode 60 is a Ag electrode.

[0144] In this embodiment, the metal positive electrode 70 is a Ag electrode.

[0145] A method for preparing a rear passivated contact heterojunction solar cell in the present embodiment, the schematic diagram of the preparation process is as follows: Figure 2 As shown, the following steps are included:

[0146] S1: polishing the back side of a single crystal N-type silicon wafer with an alkaline solution using a tank-type alkaline polishing device, wherein the alkaline solution is a sodium hydroxide solution with a mass concentration of 10%.

[0147] S2: Using a flat-plate PECVD device, SiH4 and N2O are passed to grow a silicon oxide tunneling oxide layer with a thickness of 2nm on the back of the N-type polished wafer. The process parameters of the PECVD process are: temperature of 450°C, a spacing between parallel plates of 20mm, a process chamber pressure of 100Pa, an RF power of 200W, a deposition time of 60s, a SiH4 flow rate of 400sccm, an argon flow rate of 5000sccm, and an N2O flow rate of 1000sccm; then SiH4 and H2 are passed to deposit an intrinsic amorphous silicon layer with a thickness of 100nm on the outer surface of the tunneling oxide layer. The process parameters of the PECVD process are: process chamber pressure of 50pa, temperature of 450°C, RF power of 150W, deposition time of 600s, SiH4 flow rate of 400sccm, argon flow rate of 5000sccm, and H2 flow rate of 1000sccm.

[0148] S3: The front side of the silicon wafer is subjected to texturing treatment, and the solution used is a mixed solution of hydrogen peroxide, deionized water, an additive (polyvinyl pyrrolidone) and sodium hydroxide, wherein the mass ratio of hydrogen peroxide, deionized water, an additive (polyvinyl pyrrolidone) and sodium hydroxide in the mixed solution is 5:74:1:20, to produce a pyramid velvet surface.

[0149] S4: Perform thermal oxygen annealing on the N-type polished silicon wafer to grow a 100nm thick silicon oxide passivation layer on the front side, wherein the thermal oxygen annealing is performed under oxygen conditions, maintaining a pressure of 80kPa and a temperature of 600°C, while ensuring that the intrinsic amorphous silicon layer on the back side of the silicon wafer is transformed into a nanocrystalline silicon / microcrystalline silicon film.

[0150] S5: Phosphorus ions and boron ions are implanted into the nanocrystalline silicon / microcrystalline silicon film in an intermittent manner by ion implantation, specifically:

[0151] (1) A mask is prepared on the surface of the P+ region on the back side of the crystalline silicon substrate by using an exposure, development, and etching process. The mask is a diazo compound (DQN) positive photoresist.

[0152] (2) Phosphorus ions are implanted into the nanocrystalline silicon / microcrystalline silicon film in the N+ region by ion implantation. During the phosphorus ion implantation process, the implantation dose is 5×10 14 cm -2 ~2×10 15 cm -2 , the injection energy is 5keV~50keV.

[0153] (3) A mask is prepared on the surface of the N+ region by using an exposure, development, and etching process. The mask is a diazo compound (DQN) positive photoresist.

[0154] (4) The mask on the surface of the P+ region is removed by laser grooving, and boron ions are implanted into the nanocrystalline silicon / microcrystalline silicon film in the P+ region by ion implantation. During the boron ion implantation process, the implantation dose is 5×10 14 cm -2 ~2×10 15 cm -2 , the injection energy is 5keV~50keV.

[0155] (5) Use laser grooving to remove the mask on the surface of the N+ region.

[0156] S6: A two-step annealing method of first low temperature and then high temperature is used to anneal the nanocrystalline silicon / microcrystalline silicon film implanted with phosphorus ions and boron ions, specifically: first heating to 560°C in a nitrogen atmosphere, maintaining for 90 minutes, and then heating to 1000°C in an oxygen atmosphere, maintaining for 25 minutes, to form a P+ doped nanocrystalline silicon / microcrystalline silicon layer with a square resistance of 40Ω / □, a nanocrystalline silicon / microcrystalline silicon layer, and an N+ doped nanocrystalline silicon / microcrystalline silicon layer with a square resistance of 110Ω / □. In the present invention, the square resistance of the N+ region and the P+ region is precisely controlled by controlling the implantation dose and the annealing time.

[0157] S7: Using flat PECVD equipment, anti-reflection passivation film is applied to both the front and back surfaces of the crystalline silicon substrate. x The film is made into two layers with different refractive indices, and SiH4 and NH3 are introduced. The deposition temperature is 450℃, the flow ratio of SiH4 and NH3 in the high-fold film layer is 1:4, and the flow ratio of SiH4 and NH3 in the low-fold film layer is 1:8. The total thickness of the two layers is controlled at 85nm; the back SiN x The flow ratio of SiH4 and NH3 in the low-fold film layer is 1:8, and the film thickness is controlled at 80nm.

[0158] S8: Printing metal Ag in the P+ region; printing metal Ag in the N+ region, placing in a sintering device for sintering, forming a metal positive electrode and a metal negative electrode, and completing the preparation of a back passivated contact heterojunction solar cell.

[0159] Embodiment 2:

[0160] like Figure 1As shown, a back-passivated contact heterojunction solar cell comprises a crystalline silicon substrate 10, wherein a front passivation layer 11 and a front anti-reflection passivation layer 12 are sequentially arranged on the front side of the crystalline silicon substrate 10 from the inside to the outside; a tunneling oxide layer 20 is arranged on the back side of the crystalline silicon substrate 10, and a P+ doped nanocrystalline silicon / microcrystalline silicon layer 30, a nanocrystalline silicon / microcrystalline silicon layer and an N+ doped nanocrystalline silicon / microcrystalline silicon layer 40 are alternately arranged on the tunneling oxide layer 20, and the nanocrystalline silicon / microcrystalline silicon layer is located between the P+ doped nanocrystalline silicon / microcrystalline silicon layer and the N+ doped nanocrystalline silicon / microcrystalline silicon layer. A back anti-reflection passivation layer 50 is provided between the crystalline silicon layers, on the P+ doped nanocrystalline silicon / microcrystalline silicon layer 30, the nanocrystalline silicon / microcrystalline silicon layer and the N+ doped nanocrystalline silicon / microcrystalline silicon layer 40, and a metal negative electrode 60 and a metal positive electrode are also provided on the back anti-reflection passivation layer 50. The metal negative electrode 60 passes through the back anti-reflection passivation layer 50 to form an ohmic contact with the N+ doped nanocrystalline silicon / microcrystalline silicon layer 40, and the metal positive electrode 70 passes through the back anti-reflection passivation layer 50 to form an ohmic contact with the P+ doped nanocrystalline silicon / microcrystalline silicon layer 30.

[0161] In this embodiment, the alternately arranged P+ doped nanocrystalline silicon / microcrystalline silicon layer 30, nanocrystalline silicon / microcrystalline silicon layer and N+ doped nanocrystalline silicon / microcrystalline silicon layer 40 present an "interdigitated structure", also known as an interdigitated structure.

[0162] In this embodiment, the P+ doped nanocrystalline silicon / microcrystalline silicon layer 30 is obtained by mixing P+ doped nanocrystalline silicon and P+ doped microcrystalline silicon; the nanocrystalline silicon / microcrystalline silicon layer is obtained by mixing impure nanocrystalline silicon and impure microcrystalline silicon, and the width of the nanocrystalline silicon / microcrystalline silicon layer is 4μm, that is, the spacing distance between the P+ doped nanocrystalline silicon / microcrystalline silicon layer 30 and the N+ doped nanocrystalline silicon / microcrystalline silicon layer 40 is 4μm, which is much smaller than the width of the laser groove area. Generally speaking, the width of the laser groove area is as high as 100μm or more; the N+ doped nanocrystalline silicon / microcrystalline silicon layer 40 is obtained by mixing N+ doped nanocrystalline silicon and N+ doped microcrystalline silicon.

[0163] In this embodiment, the square resistance of the P+ doped nanocrystalline silicon / microcrystalline silicon layer 30 is 35Ω / □; the square resistance of the N+ doped nanocrystalline silicon / microcrystalline silicon layer 40 is 100Ω / □.

[0164] In this embodiment, the thickness of the P+ doped nanocrystalline silicon / microcrystalline silicon layer 30 is 90 nm; the thickness of the N+ doped nanocrystalline silicon / microcrystalline silicon layer 40 is 90 nm.

[0165] In this embodiment, the crystalline silicon substrate 10 is N-type single crystal silicon, and the resistivity is 10Ω / □.

[0166] In this embodiment, the front passivation layer 11 is a silicon oxide film with a thickness of 100 nm.

[0167] In this embodiment, the front anti-reflection passivation layer 12 is composed of two layers of SiN with different refractive indices.x The bottom layer is SiN with a refractive index of 2.1 to 2.2. x The film is 30nm thick, and the top layer is SiN with a refractive index of 1.6 to 1.6 x The film thickness is 55nm and the total thickness is 85nm.

[0168] In this embodiment, the tunnel oxide layer 20 is a silicon oxide film with a thickness of 1 nm.

[0169] In this embodiment, the back anti-reflection passivation layer 50 is SiN x The film thickness is 90nm.

[0170] In this embodiment, the metal negative electrode 60 is a Cu electrode.

[0171] In this embodiment, the metal positive electrode 70 is a Cu electrode.

[0172] A method for preparing a rear passivated contact heterojunction solar cell in the present embodiment comprises the following steps:

[0173] S1: polishing the back side of a single crystal N-type silicon wafer with an alkaline solution using a tank-type alkaline polishing device, wherein the alkaline solution is a sodium hydroxide solution with a mass concentration of 10%.

[0174] S2: Using a flat-plate PECVD device, SiH4 and N2O are passed to grow a silicon oxide tunneling oxide layer with a thickness of 1nm on the back of the N-type polished wafer. The process parameters of the PECVD process are: temperature of 500°C, a spacing between parallel plates of 30mm, a process chamber pressure of 100Pa, an RF power of 200W, a deposition time of 50s, a SiH4 flow rate of 400sccm, an argon flow rate of 5000sccm, and an N2O flow rate of 1000sccm; then SiH4 and H2 are passed to deposit an intrinsic amorphous silicon layer with a thickness of 100nm on the outer surface of the tunneling oxide layer. The process parameters of the PECVD process are: process chamber pressure of 50pa, temperature of 450°C, RF power of 150W, deposition time of 600s, SiH4 flow rate of 400sccm, argon flow rate of 5000sccm, and H2 flow rate of 1000sccm.

[0175] S3: The front side of the silicon wafer is subjected to texturing treatment, and the solution used is a mixed solution of hydrogen peroxide, deionized water, an additive (polyvinyl pyrrolidone) and sodium hydroxide, wherein the mass ratio of hydrogen peroxide, deionized water, an additive (polyvinyl pyrrolidone) and sodium hydroxide in the mixed solution is 5:74:1:20, to produce a pyramid velvet surface.

[0176] S4: Perform thermal oxygen annealing on the N-type polished silicon wafer to grow a silicon oxide passivation layer with a thickness of 100 nm on the front side, wherein the thermal oxygen annealing is performed under oxygen conditions, maintaining a pressure of 80 kPa and a temperature of 600° C., while ensuring that the intrinsic amorphous silicon layer on the back side of the silicon wafer is transformed into a nanocrystalline silicon film or a microcrystalline silicon film.

[0177] S5: Phosphorus ions and boron ions are implanted into the nanocrystalline silicon / microcrystalline silicon film in an intermittent manner by ion implantation, specifically:

[0178] (1) A mask is prepared on the surface of the P+ region on the back side of the crystalline silicon substrate by using an exposure, development, and etching process. The mask is a diazo compound (DQN) positive photoresist.

[0179] (2) Phosphorus ions are implanted into the nanocrystalline silicon / microcrystalline silicon film in the N+ region by ion implantation. During the phosphorus ion implantation process, the implantation dose is 5×10 14 cm -2 ~2×10 15 cm -2 , the injection energy is 5keV~50keV.

[0180] (3) A mask is prepared on the surface of the N+ region by using an exposure, development, and etching process. The mask is a diazo compound (DQN) positive photoresist.

[0181] (4) The mask on the surface of the P+ region is removed by laser grooving, and boron ions are implanted into the nanocrystalline silicon / microcrystalline silicon film in the P+ region by ion implantation. During the boron ion implantation process, the implantation dose is 5×10 14 cm -2 ~2×10 15 cm -2 , the injection energy is 5keV~50keV.

[0182] (5) Use laser grooving to remove the mask on the surface of the N+ region.

[0183] S6: A two-step annealing method of first low temperature and then high temperature is used to anneal the nanocrystalline silicon / microcrystalline silicon film implanted with phosphorus ions and boron ions. Specifically, the temperature is first raised to 600°C in a nitrogen atmosphere and maintained for 60 minutes, and then the temperature is raised to 900°C in an oxygen atmosphere and maintained for 30 minutes to form a P+ doped nanocrystalline silicon / microcrystalline silicon layer with a square resistance of 35Ω / □, a nanocrystalline silicon / microcrystalline silicon layer and an N+ doped nanocrystalline silicon / microcrystalline silicon layer with a square resistance of 100Ω / □.

[0184] S7: Using flat PECVD equipment, anti-reflection passivation film is applied to both the front and back surfaces of the crystalline silicon substrate. xThe film is made into two layers with different refractive indices, and SiH4 and NH3 are introduced. The deposition temperature is 450℃, the flow ratio of SiH4 and NH3 in the high-fold film layer is 1:4, and the flow ratio of SiH4 and NH3 in the low-fold film layer is 1:8. The total thickness of the two layers is controlled at 85nm; the back SiN x The flow ratio of SiH4 and NH3 in the low-fold film layer is 1:8, and the film thickness is controlled at 90nm.

[0185] S8: electroplating metal Cu in the P+ region and electroplating metal Cu in the N+ region to form a metal positive electrode and a metal negative electrode, thereby completing the preparation of a back-passivated contact heterojunction solar cell.

[0186] The electrical properties of the back-passivated contact heterojunction solar cells prepared in Example 1 and Example 2 were tested, and the results are shown in Table 1.

[0187] Table 1 Electrical performance data of heterojunction solar cells with different back passivation contacts

[0188]

[0189]

[0190] It can be seen from Table 1 that, compared with conventional HBC cells, the back-passivated contact heterojunction solar cell prepared by the present invention has more excellent electrical performance, wherein the conversion efficiency of the cell is increased from 24.5% to 25.0%, with an increase of up to 0.5%, which is a very large increase.

[0191] It can be seen from the above results that, compared with the prior art, the back-passivated contact heterojunction solar cell of the present invention has a passivated contact structure in which a tunneling oxide layer is deposited on the back of the cell, a tunneling oxide layer is provided on the back of the cell, P+ doped nanocrystalline silicon / microcrystalline silicon layer, nanocrystalline silicon / microcrystalline silicon layer and N+ doped nanocrystalline silicon / microcrystalline silicon layer are alternately arranged on the tunneling oxide layer, and the nanocrystalline silicon / microcrystalline silicon layer is located between the P+ doped nanocrystalline silicon / microcrystalline silicon layer and the N+ doped nanocrystalline silicon / microcrystalline silicon layer, a back anti-reflection passivation layer is provided on the P+ doped nanocrystalline silicon / microcrystalline silicon layer, the nanocrystalline silicon / microcrystalline silicon layer and the N+ doped nanocrystalline silicon / microcrystalline silicon layer, the back-passivated contact structure thus constructed can effectively improve the short-circuit current density and the opening voltage of the cell, thereby significantly improving the conversion efficiency of the cell. At the same time, in the method for preparing a back passivated contact heterojunction solar cell of the present invention, not only can the doping concentration be accurately controlled, but also phosphorus ions and boron ions can be selectively implanted into the nanocrystalline silicon / microcrystalline silicon film at the back to form an N+ doped region and a P+ doped region separated by the nanocrystalline silicon / microcrystalline silicon film, which has the characteristics of high control accuracy and good diffusion uniformity, and the spacing distance between the N+ doped region and the P+ doped region can be adjusted. At the same time, after the ion implantation, the annealing treatment is continued to be performed, so that the impurities can be activated and pushed into the silicon wafer, and not only a back passivated contact structure constructed by a tunneling oxide layer, a P+ doped nanocrystalline silicon / microcrystalline silicon layer, a nanocrystalline silicon / microcrystalline silicon layer and an N+ doped nanocrystalline silicon / microcrystalline silicon layer, and a back anti-reflection passivation layer can be formed on the back, but also the lattice damage on the surface of the silicon wafer caused by the ion implantation can be repaired, which is beneficial to improving the battery conversion efficiency. Compared with HBC cells prepared by conventional methods, the conversion efficiency of the back-passivated contact heterojunction solar cell prepared by the preparation method of the present invention can be increased from 24.5% to more than 25%, and the open circuit voltage can be increased from 0.705V to 0.735V, showing very excellent electrical performance. In addition, the preparation method of the present invention also has the advantages of simple process, convenient operation, low cost, etc., which is beneficial to the conversion efficiency and yield of the battery, suitable for large-scale preparation, and conducive to industrial application. It is of great significance to promote the industrial application of back-passivated contact heterojunction solar cells.

[0192] The above embodiments are only preferred implementations of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A method for preparing a back-passivated contact heterojunction solar cell, characterized in that: The following steps are involved: S1, polishing the back side of the crystalline silicon substrate; S2, sequentially depositing a tunneling oxide layer and an intrinsic amorphous silicon layer on the back side of the crystalline silicon substrate; S3, performing texturing on the front side of the crystalline silicon substrate to form a pyramid texture surface; S4, performing thermal oxygen annealing on the crystalline silicon substrate deposited with the tunneling oxide layer and the intrinsic amorphous silicon layer to form a front passivation layer on the front side of the crystalline silicon substrate and a nanocrystalline silicon / microcrystalline silicon thin film on the back side of the crystalline silicon substrate; the thermal oxygen annealing is performed in an oxygen atmosphere; during the thermal oxygen annealing, the pressure is maintained at 40-80 kPa and the temperature is maintained at 600° C.-700° C.; S5, using ion implantation to alternately implant phosphorus ions and boron ions into the nanocrystalline silicon / microcrystalline silicon film; S6, annealing the nanocrystalline silicon / microcrystalline silicon film implanted with phosphorus ions and boron ions to form an alternating arrangement of a P+ doped nanocrystalline silicon / microcrystalline silicon layer, a nanocrystalline silicon / microcrystalline silicon layer and an N+ doped nanocrystalline silicon / microcrystalline silicon layer; the P+ doped nanocrystalline silicon / microcrystalline silicon layer is obtained by mixing the P+ doped nanocrystalline silicon and the P+ doped microcrystalline silicon; The nanocrystalline silicon / microcrystalline silicon layer is obtained by mixing impure nanocrystalline silicon and impure microcrystalline silicon; the N+ doped nanocrystalline silicon / microcrystalline silicon layer is obtained by mixing N+ doped nanocrystalline silicon and N+ doped microcrystalline silicon; the annealing treatment is: firstly heating to 560°C to 600°C in a nitrogen atmosphere, maintaining for 60min to 90min, and then heating to 900°C to 1000°C in an oxygen atmosphere, maintaining for 25min to 30min; S7, depositing an anti-reflection passivation layer on the front and back sides of the crystalline silicon substrate; S8. Prepare a metal negative electrode and a metal positive electrode on the anti-reflection passivation layer on the back side of the crystalline silicon substrate respectively, and complete the preparation of the back-passivated contact heterojunction solar cell.

2. The method for preparing a back-passivated contact heterojunction solar cell according to claim 1, characterized in that: In step S5, phosphorus ions and boron ions are alternately implanted into the nanocrystalline silicon / microcrystalline silicon film by any of the following methods; Method 1 includes the following steps: (1) Preparing a mask on the surface of the P+ region on the back side of the crystalline silicon substrate; (2) Phosphorus ions are implanted into the nanocrystalline silicon / microcrystalline silicon film in the N+ region by ion implantation; (3) Preparing a mask on the surface of the N+ region; (4) removing the mask on the surface of the P+ region and implanting boron ions into the nanocrystalline silicon / microcrystalline silicon film in the P+ region by ion implantation; (5) Remove the mask on the surface of the N+ region; Method 2 includes the following steps: (a) Preparing a mask on the surface of the N+ region on the back side of the crystalline silicon substrate; (b) Boron ions are implanted into the nanocrystalline silicon / microcrystalline silicon film in the P+ region by ion implantation; (c) preparing a mask on the surface of the P+ region; (d) removing the mask on the surface of the N+ region, and implanting phosphorus ions into the nanocrystalline silicon / microcrystalline silicon film in the N+ region by ion implantation; (e) Remove the mask on the surface of the P+ region.

3. The method for preparing a back-passivated contact heterojunction solar cell according to claim 2, characterized in that: In step (1), a mask is prepared on the surface of the N+ region on the back side of the crystalline silicon substrate by using an exposure, development, and etching process; the mask is a diazo compound positive photoresist; In step (2), during the phosphorus ion implantation, the implantation dose is 5×10 14 cm -2 ~2×10 15 cm -2 , the injection energy is 5 keV~50 keV; In step (3), a mask is prepared on the surface of the N+ region by using a process of exposure, development, and etching; the mask is a diazo compound positive photoresist; In step (4), the mask on the surface of the P+ region is removed by laser grooving; during the boron ion implantation, the implantation dose is 5×10 14 cm -2 ~2×10 15 cm -2 , the injection energy is 5 keV~50 keV; In step (5), the mask on the surface of the N+ region is removed by laser grooving; In step (a), a mask is prepared on the surface of the P+ region on the back side of the crystalline silicon substrate by using exposure, development and etching processes; the mask is a diazo compound positive photoresist; In step (b), during the implantation of boron ions, the implantation dose is 5×10 14 cm -2 ~2×10 15 cm -2 , the injection energy is 5 keV~50 keV; In step (c), a mask is prepared on the surface of the N+ region on the back side of the crystalline silicon substrate by using exposure, development and etching processes; the mask is a diazo compound positive photoresist; In step (d), the mask of the N+ region is removed by laser grooving; during the phosphorus ion implantation, the implantation dose is 5×10 14 cm -2 ~2×10 15 cm -2 , the injection energy is 5 keV~50 keV; In step (e), the mask of the P+ region is removed by laser grooving.

4. The method for preparing a back-passivated contact heterojunction solar cell according to any one of claims 1 to 3, characterized in that: In step S1, the back side of the crystalline silicon substrate is polished with an alkaline solution; the alkaline solution is a sodium hydroxide solution; the mass concentration of the alkaline solution is 2% to 10%; the thickness of the crystalline silicon substrate is 100 μm to 180 μm; In step S2, a tunneling oxide layer and an intrinsic amorphous silicon layer are sequentially deposited on the back side of the crystalline silicon substrate by using a PECVD process; during the deposition of the tunneling oxide layer, the process parameters of the PECVD process are: a temperature of 250°C to 600°C, a spacing between parallel plates of 20mm to 60mm, a process chamber pressure of 15Pa to 200Pa, a radio frequency power of 50W to 400W, a deposition time of 20s to 120s, a SiH4 flow rate of 25sccm to 2400sccm, an argon flow rate of 0sccm to 20000sccm, and a N2O flow rate of 0sccm to 20000sccm; during the deposition of the intrinsic amorphous silicon layer, the process parameters of the PECVD process are: a process chamber pressure of 30 Pa~80pa, temperature 450℃~600℃, RF power 50W~1200W, deposition time 100s~600s, SiH4 flow rate 25sccm~2400sccm, argon flow rate 0sccm~20000sccm, N2O flow rate 0sccm~20000sccm; H2 flow rate 0sccm~20000sccm; In step S3, a mixed solution of hydrogen peroxide, deionized water, additives and sodium hydroxide is used to texture the front surface of the crystalline silicon substrate; In step S7, a PECVD process is used to deposit an anti-reflection passivation layer on the front and back sides of the crystalline silicon substrate; during the deposition of the anti-reflection passivation layer on the front side of the crystalline silicon substrate, the process parameters of the PECVD process are: a deposition temperature of 450° C., a flow ratio of SiH4 to NH3 of 1:4 and 1:8; during the deposition of the anti-reflection passivation layer on the back side of the crystalline silicon substrate, the process parameters of the PECVD process are: a deposition temperature of 450° C., a flow ratio of SiH4 to NH3 of 1:8; In step S8, a metal negative electrode and a metal positive electrode are respectively prepared on the anti-reflection passivation layer on the back side of the crystalline silicon substrate by screen printing and sintering or electroplating.

5. The method for preparing a back-passivated contact heterojunction solar cell according to claim 4, characterized in that: The back-passivated contact heterojunction solar cell comprises a crystalline silicon substrate, wherein a front passivation layer and a front anti-reflection passivation layer are sequentially arranged on the front side of the crystalline silicon substrate from the inside to the outside; a tunneling oxide layer is arranged on the back side of the crystalline silicon substrate; a P+ doped nanocrystalline silicon / microcrystalline silicon layer, a nanocrystalline silicon / microcrystalline silicon layer and an N+ doped nanocrystalline silicon / microcrystalline silicon layer are alternately arranged on the tunneling oxide layer, and the nanocrystalline silicon / microcrystalline silicon layer is located between the P+ doped nanocrystalline silicon / microcrystalline silicon layer and the N+ doped nanocrystalline silicon / microcrystalline silicon layer; a back anti-reflection passivation layer is arranged on the P+ doped nanocrystalline silicon / microcrystalline silicon layer, the nanocrystalline silicon / microcrystalline silicon layer and the N+ doped nanocrystalline silicon / microcrystalline silicon layer; a metal negative electrode and a metal positive electrode are also arranged on the back anti-reflection passivation layer; the metal negative electrode passes through the back anti-reflection passivation layer to form an ohmic contact with the N+ doped nanocrystalline silicon / microcrystalline silicon layer; the metal positive electrode passes through the back anti-reflection passivation layer to form an ohmic contact with the P+ doped nanocrystalline silicon / microcrystalline silicon layer.

6. The method for preparing a back-passivated contact heterojunction solar cell according to claim 5, characterized in that: The width of the nanocrystalline silicon / microcrystalline silicon layer is 1 μm to 5 μm; The square resistance of the P+ doped nanocrystalline silicon / microcrystalline silicon layer is 30Ω / □ to 80Ω / □; the thickness of the P+ doped nanocrystalline silicon / microcrystalline silicon layer is 20nm to 150nm; the square resistance of the N+ doped nanocrystalline silicon / microcrystalline silicon layer is 70Ω / □ to 120Ω / □; the thickness of the N+ doped nanocrystalline silicon / microcrystalline silicon layer is 20nm to 150nm; The crystalline silicon substrate is N-type single crystal silicon or P-type single crystal silicon; the resistivity of the crystalline silicon substrate is 1Ω / □ to 10Ω / □; The front passivation layer is a silicon oxide film; the thickness of the front passivation layer is 50nm to 100nm; The front anti-reflection passivation layer is composed of two layers of SiN with different refractive indices. x The front anti-reflection passivation layer has a bottom layer of SiN with a refractive index of 2.1 to 2.

2. x The film is 30nm thick, and the top layer is SiN with a refractive index of 1.6 to 1.6 x Membrane, thickness 45 nm to 55 nm; The tunneling oxide layer is a silicon oxide film; the thickness of the tunneling oxide layer is 0.5nm to 2nm; The back anti-reflection passivation layer is SiN x The thickness of the back anti-reflection passivation layer is 80nm to 90nm; The metal negative electrode is an Ag electrode or a Cu electrode; The metal positive electrode is an Ag electrode or a Cu electrode.

Images