Control circuit and control method for waking up low power consumption mode

Abstract

The present invention discloses a control circuit and a control method for waking up a low power consumption mode. The control circuit for waking up a low power consumption mode includes: a communication detection circuit, a mode control circuit, a serial data line and a serial clock line; the output end of the communication detection circuit is electrically connected to the mode control circuit, and the communication detection circuit is also connected between a master device and a slave device through a serial data line and a serial clock line. The control end of the communication detection circuit is connected to a trigger signal, and the output end of the mode control circuit is electrically connected to a control module of a control system. In this embodiment, when the control system is in a low power consumption mode through the above circuit control, the signal on the serial clock line maintains a second potential, so that the serial clock line cannot transmit the addressing signal of the master device, thereby avoiding the problem that the master device mistakenly determines that the slave device is in an abnormal state due to the inability of the slave device to recognize the addressing signal in the low power consumption mode.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a control circuit and a control method for waking up a low power consumption mode. Background Art

[0002] Electronic devices all include control systems to control the electronic devices to implement various functions. The control system generally includes a working mode and a low power consumption mode. During certain periods of time, the control system can be configured to enter the low power consumption mode to reduce power consumption.

[0003] The existing I2C receiving communication wakes up the low power mode, and uses the GPIO mapped by I2C to generate a wake-up event by reversing in the low power mode. However, in the process of waking up the low power mode, if the master device sends an addressing signal, the slave device cannot recognize the addressing signal in the process of waking up the low power mode, which leads to an addressing error. Summary of the invention

[0004] The present invention provides a control circuit and a control method for waking up a low power consumption mode, so as to realize successful waking up of the low power consumption mode and also ensure the correct addressing response of a master device to a slave device.

[0005] According to one aspect of the present invention, a control circuit for waking up a low power consumption mode is provided, which is applied to a control system, and the control circuit for waking up a low power consumption mode comprises: a communication detection circuit, a mode control circuit, a serial data line and a serial clock line;

[0006] The output end of the communication detection circuit is electrically connected to the mode control circuit, the communication detection circuit is also connected between the master device and the slave device through the serial data line and the serial clock line, the control end of the communication detection circuit is connected to the trigger signal, and the communication detection circuit is used to generate a first detection signal according to the signal on the serial data line, the signal on the serial clock line and the trigger signal when the trigger signal is a first potential; the trigger signal is a first potential when the control system is configured in a low power consumption mode, and the trigger signal is a second potential when the control system is configured in a normal mode;

[0007] The output end of the mode control circuit is electrically connected to the control module of the control system, and the mode control circuit is used to control the signal on the serial clock line to maintain a second potential according to the wake-up enable signal, the trigger signal, the signal on the serial clock line and the first detection signal, and to control the control system to enter a low power consumption mode through the control module, wherein the trigger signal is a first potential.

[0008] Optionally, the mode control circuit includes a low-power wake-up circuit and a clock line control circuit, the input end of the low-power wake-up circuit is electrically connected to the output end of the communication detection circuit, the output end of the low-power wake-up circuit is electrically connected to the control module of the control system, and the low-power wake-up circuit is used to generate a wake-up signal according to a wake-up enable signal, the trigger signal and the first detection signal so that the control module controls the control system to enter a low-power mode; the wake-up enable signal is a first potential when the control system is configured in a low-power mode;

[0009] The input end of the clock line control circuit is electrically connected to the output end of the communication detection circuit. The clock line control circuit is used to generate a first clock control signal according to the signal on the serial clock line and the first detection signal when the trigger signal received is a first potential, so as to control the signal on the serial clock line to maintain a second potential.

[0010] Optionally, the communication detection circuit is further configured to generate a second detection signal when the trigger signal is at a second potential;

[0011] The low-power wake-up circuit is used to generate a wake-up exit signal when the trigger signal is at the second potential so that the control module controls the control system to enter the low-power mode;

[0012] The clock line control circuit is further configured to generate a second clock control signal when the trigger signal is at a second potential, so as to control the serial clock line to transmit the addressing signal of the master device.

[0013] Optionally, the communication detection circuit includes a first register, a first selection unit and a first AND gate;

[0014] The input end of the first selection unit is electrically connected to the serial data line, the output end of the first selection unit is electrically connected to the clock end of the first register, the control end of the first selection unit is connected to the trigger signal, and the first selection unit is used to output a first clock control signal when the trigger signal is a first potential, and the first clock control signal is opposite to the signal on the serial data line;

[0015] The input end of the first register is electrically connected to the serial clock line, the output end of the first register is electrically connected to the first input end of the first AND gate, and the first register is used to generate a control signal according to the first clock control signal and the signal on the serial clock line when the trigger signal is a first potential;

[0016] The second input end of the first AND gate is connected to the trigger signal, and the output end of the first AND gate is electrically connected to the low-power wake-up circuit and the clock line control circuit respectively. The first AND gate is used to generate a first detection signal according to the control signal when the trigger signal is a first potential, and is also used to generate a second detection signal when the trigger signal is a second potential.

[0017] Optionally, the first selection unit includes a first inverter and a first selector, the input end of the first inverter is electrically connected to the serial data line, the output end of the first inverter is electrically connected to the first input end of the first selector, the second input end of the first selector is connected to the second potential, the control end of the first selector is connected to the trigger signal, and the output end of the first selector is electrically connected to the clock end of the first register.

[0018] Optionally, the low-power wake-up circuit includes a second AND gate and a second selector, the first input end of the second AND gate is connected to the wake-up enable signal, the second input end of the second AND gate is connected to the trigger signal, the output end of the second AND gate is electrically connected to the control end of the second selector, the first input end of the second selector is electrically connected to the output end of the communication detection circuit, the second input end of the second selector is connected to the second potential, and the output end of the second selector is electrically connected to the control module.

[0019] Optionally, the clock line control circuit includes a second selection unit, a second register and a third selection unit;

[0020] The input end of the second selection unit is electrically connected to the serial clock line, the control end of the second selection unit is connected to the trigger signal, the output end of the second selection unit is electrically connected to the clock end of the second register, and the second selection unit is used to output a second clock control signal when the trigger signal is a first potential, and the second clock control signal is opposite to the signal on the serial clock line;

[0021] The input end of the second register is electrically connected to the output end of the communication detection circuit, and the output end of the second register is electrically connected to the input end of the third selection unit. The second register is used to generate a second control signal according to the second clock control signal and the first detection signal output by the communication detection circuit when the trigger signal is a first potential. The control end of the third selection unit is connected to the trigger signal, and the output end of the third selection unit is electrically connected to the control module. The third selection unit is used to output the first clock control signal according to the second control signal when the trigger signal is a first potential. The first clock control signal is opposite to the second control signal when the trigger signal is a first potential. The third selection unit is also used to generate a second clock control signal when the trigger signal is a second potential.

[0022] Optionally, the second selection unit includes a second inverter and a third selector, the input end of the second inverter is electrically connected to the serial clock line, the output end of the second inverter is electrically connected to the first input end of the third selector, the second input end of the third selector is connected to the second potential, the control end of the third selector is connected to the trigger signal, and the output end of the third selector is electrically connected to the clock end of the second register;

[0023] The third selection unit includes a third inverter and a fourth selector, the input end of the third inverter is electrically connected to the output end of the second register, the output end of the third inverter is electrically connected to the first input end of the fourth selector, the second input end of the fourth selector is connected to the first potential, the control end of the fourth selector is connected to the trigger signal, and the output end of the fourth selector is electrically connected to the control module.

[0024] According to another aspect of the present invention, a control method for waking up a low power consumption mode is provided, the method being applicable to any one of the control circuits for waking up a low power consumption mode described above, the control circuit for waking up a low power consumption mode being applied to a control system, the low power consumption wake-up circuit comprising: a communication detection circuit, a mode control circuit, a serial data line and a serial clock line; the output end of the communication detection circuit is electrically connected to the mode control circuit, the communication detection circuit is also connected between a master device and a slave device through the serial data line and the serial clock line, the control end of the communication detection circuit is connected to a trigger signal, and the output end of the mode control circuit is electrically connected to a control module of the control system;

[0025] The control method for waking up the low power consumption mode comprises:

[0026] The communication detection circuit generates a first detection signal according to the signal on the serial data line, the signal on the serial clock line and the trigger signal when the trigger signal is at the first potential; the trigger signal is at the first potential when the control system is configured in the low power consumption mode, and is at the second potential when the control system is configured in the normal mode;

[0027] The mode control circuit controls the signal on the serial clock line to maintain a second potential according to the wake-up enable signal, the trigger signal, the signal on the serial clock line and the first detection signal, and controls the control system to enter a low power consumption mode through a control module, wherein the trigger signal is a first potential.

[0028] Optionally, the mode control circuit includes a low-power wake-up circuit and a clock line control circuit, the input end of the low-power wake-up circuit is electrically connected to the output end of the communication detection circuit, the output end of the low-power wake-up circuit is electrically connected to the control module of the control system, the input end of the clock line control circuit is electrically connected to the output end of the communication detection circuit, and the control method for waking up the low-power mode also includes:

[0029] The communication detection circuit generates a second detection signal when the trigger signal is at a second potential;

[0030] The low-power wake-up circuit generates a wake-up exit signal when the trigger signal is at the second potential so that the control module controls the control system to enter the low-power mode;

[0031] When the trigger signal is at a second potential, the clock line control circuit generates a second clock control signal to control the serial clock line to transmit the addressing signal of the master device.

[0032] The control circuit for waking up the low power consumption mode of the present invention is applied to the control system, and the control circuit for waking up the low power consumption mode includes: a communication detection circuit, a mode control circuit, a serial data line and a serial clock line; the output end of the communication detection circuit is electrically connected to the mode control circuit, and the communication detection circuit is also connected between the master device and the slave device through the serial data line and the serial clock line, the control end of the communication detection circuit is connected to the trigger signal, and the output end of the mode control circuit is electrically connected to the control module of the control system. The communication detection circuit is used to generate a first detection signal according to the signal on the serial data line, the signal on the serial clock line and the trigger signal when the trigger signal is the first potential; the mode control circuit is used to control the signal on the serial clock line to maintain the second potential according to the wake-up enable signal, the trigger signal, the signal on the serial clock line and the first detection signal, and control the control system to enter the low power consumption mode through the control module, wherein the trigger signal is the first potential. In this embodiment, when the control system is in the low power consumption mode through the communication detection circuit and the mode control circuit, the signal on the serial clock line is always controlled to maintain the second potential, so that the serial clock line cannot transmit the addressing signal of the master device, thereby avoiding the problem that the master device mistakenly determines that the slave device is in an abnormal state due to the inability of the slave device to recognize the addressing signal in the low power consumption mode.

[0033] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0035] Figure 1 It is a structural schematic diagram of a control circuit for waking up a low power consumption mode provided by an embodiment of the present invention;

[0036] Figure 2 is a schematic structural diagram of another control circuit for waking up a low power consumption mode provided by an embodiment of the present invention;

[0037] Figure 3 is a schematic structural diagram of another control circuit for waking up a low power consumption mode provided by an embodiment of the present invention;

[0038] Figure 4 is a schematic structural diagram of another control circuit for waking up a low power consumption mode provided by an embodiment of the present invention;

[0039] Figure 5 is a schematic structural diagram of another control circuit for waking up a low power consumption mode provided by an embodiment of the present invention;

[0040] Figure 6 This is a driving timing diagram of a control circuit for waking up a low power consumption mode provided by an embodiment of the present invention;

[0041] Figure 7 This is a flow chart of a control method for waking up a low power consumption mode provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0042] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0043] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0044] Figure 1 A schematic diagram of a control circuit for waking up a low power consumption mode according to an embodiment of the present invention is provided. Figure 1 , a control circuit for waking up the low power consumption mode is applied to a control system 6, and the control circuit for waking up the low power consumption mode includes: a communication detection circuit 1, a mode control circuit 02, a serial data line SDA and a serial clock line SCL.

[0045] The output end of the communication detection circuit 1 is electrically connected to the mode control circuit 02. The communication detection circuit 1 is also connected between the master device 4 and the slave device 5 through the serial data line SDA and the serial clock line SCL. The control end of the communication detection circuit 1 is connected to the trigger signal. The communication detection circuit 1 is used to generate a first detection signal according to the signal on the serial data line SDA, the signal on the serial clock line SCL and the trigger signal when the trigger signal is a first potential; the trigger signal is the first potential when the control system 6 is configured to the low power consumption mode, and the trigger signal is the second potential when the control system 6 is configured to the normal mode.

[0046] The output end of the mode control circuit 02 is electrically connected to the control module of the control system 6. The mode control circuit 02 is used to control the signal on the serial clock line SCL to maintain the second potential according to the wake-up enable signal, the trigger signal, and the signal on the serial clock line SCL, and to control the control system 6 to enter the low power consumption mode through the control module, wherein the trigger signal is the first potential.

[0047] The communication in this embodiment is all I2C communication, that is, information is transmitted between devices connected to the bus through the serial data line SDA and the serial clock line SCL. Both the master device 4 and the slave device 5 are devices that can accept I2C communication. In low-power mode, the clock of the I2C system and the clock of the control system 6 are turned off. If in low-power mode, the master device 4 sends an addressing signal to the slave device 5 through the serial clock line, the slave device 5 cannot respond. When the master device 4 sends an addressing signal for the first time and does not receive a response from the slave device 5, the master device 4 will think that the slave device 5 is in an abnormal situation, and then give up the addressing operation of the slave device 5, affecting the communication between the master device 4 and the slave device 5. In normal mode, the slave device can respond normally to the addressing signal of the master device 4. The control system 6 can be an MCU system. When the control system 6 receives a demand to wake up the low-power mode, the control trigger signal and the wake-up enable signal are the first potential. When the control system 6 receives a request that the system needs to switch to normal mode, the control trigger signal is the second potential. The first potential can be a high level, and the second potential can be a low level. It is worth noting that when the control system 6 receives a signal to switch to the normal mode, it can control the wake-up enable signal to be either the first potential or the second potential. The signal transmitted on the serial clock line SCL is controlled by the mode control circuit 02. When the mode control circuit 02 controls the signal on the serial clock line SCL to be the second potential, the serial clock line SCL cannot transmit the signal sent by the master device 4. When the mode control circuit 02 controls the signal on the serial clock line SCL to be the first potential, the signal on the serial clock line SCL is also controlled by the master device 4. The signal on the serial clock line SCL is the addressing signal sent by the master device 4, and the serial clock line SCL can transmit the addressing signal of the master device 4.

[0048] This embodiment controls the signal on the serial clock line to maintain the second potential at all times when the control system is in low power consumption mode through the communication detection circuit and the mode control circuit, so that the serial clock line cannot transmit the addressing signal of the master device, thereby avoiding the problem that in low power consumption mode, after the master device sends an addressing signal, the slave device cannot recognize the addressing signal, resulting in the master device being unable to receive the response of the slave device.

[0049] Continue to refer Figure 1 Optionally, the mode control circuit 02 includes a low-power wake-up circuit 2 and a clock line control circuit 3, the input end of the low-power wake-up circuit 2 is electrically connected to the output end of the communication detection circuit 1, and the output end of the low-power wake-up circuit 2 is electrically connected to the control module of the control system 6, and the low-power wake-up circuit 2 is used to generate a wake-up signal according to the wake-up enable signal, the trigger signal and the first detection signal so that the control module controls the control system 6 to enter the low-power mode; the wake-up enable signal is a first potential when the control system 6 is configured in the low-power mode;

[0050] The input end of the clock line control circuit 3 is electrically connected to the output end of the communication detection circuit 1. The clock line control circuit 3 is used to generate a first clock control signal according to the signal on the serial clock line SCL and the first detection signal when the trigger signal received is a first potential, so as to control the signal on the serial clock line SCL to maintain a second potential.

[0051] The working process of the control circuit for waking up the low power consumption mode in this embodiment is as follows: the communication detection circuit 1 is used to generate a first detection signal according to the signal on the serial data line SDA, the signal on the serial clock line SCL and the trigger signal when the trigger signal is the first potential, wherein the first detection signal can be a high level. The low power consumption wake-up circuit 2 is used to generate a wake-up signal according to the wake-up enable signal, the trigger signal and the first detection signal so that the control module controls the control system 6 to enter the low power consumption mode, wherein the wake-up signal can be a high level. The clock line control circuit 3 is used to generate a first clock control signal according to the signal on the serial clock line SCL and the first detection signal when the trigger signal is received as the first potential, so as to control the signal on the serial clock line SCL to maintain a low level, thereby preventing the signal on the serial clock line SCL from receiving the addressing signal of the master device 4 in the low power consumption mode. When the master device 4 sends an addressing signal to the slave device 5, if the control system 6 is in the low power consumption mode, the slave device 5 cannot respond to the addressing signal, thereby causing the master device 4 to abandon the addressing operation of the slave device 5, affecting the normal communication between the master device 4 and the slave device 5. In this embodiment, in the low power consumption mode, the serial clock line SCL is prohibited from transmitting the addressing signal to avoid the above situation.

[0052] Continue to refer Figure 1, Optionally, the communication detection circuit 1 is further used to generate a second detection signal when the trigger signal is a second potential;

[0053] The low-power wake-up circuit 2 is used to generate a wake-up exit signal when the trigger signal is the second potential so that the control module controls the control system 6 to enter the normal mode;

[0054] The clock line control circuit 3 is further configured to generate a second clock control signal when the trigger signal is at a second potential, so as to control the serial clock line SCL to transmit the addressing signal of the master device 4 .

[0055] The potential of the second detection signal can be opposite to that of the first detection signal. When the first detection signal is at a high level, the second detection signal is at a low level. The potential of the wake-up exit signal can be opposite to that of the wake-up signal. When the wake-up signal is at a high level, the wake-up exit signal is at a low level. The potential of the second clock control signal is opposite to that of the first clock control signal. When the first clock control signal is at a low level, the second clock control signal is at a high level. When the control system 6 receives a demand to switch to normal mode, the control trigger signal is controlled to be the second potential. When the trigger signal is the second potential, the communication detection circuit 1 generates a second detection signal, the low-power wake-up circuit 2 generates a wake-up exit signal, and the clock line control circuit 3 generates a second clock control signal. When the clock line control circuit 3 generates the second clock control signal, the serial clock line SCL is controlled by the master device 4, starts to receive the addressing signal of the master device 4, and transmits it to the slave device 5, so that the master device 4 and the slave device 5 communicate.

[0056] In this embodiment, the control circuit for waking up the low power consumption mode releases the control over the signal transmitted by the serial clock line SCL when the control system 6 exits the low power consumption mode and switches to the normal mode, so that the serial clock line SCL normally transmits the addressing signal of the master device 4, thereby ensuring the normal communication between the master device 4 and the slave device 5.

[0057] Figure 2 A schematic diagram of another control circuit for waking up a low power consumption mode according to an embodiment of the present invention is provided. Figure 2 , Optionally, the communication detection circuit 1 includes a first register 11, a first selection unit 12 and a first AND gate 13;

[0058] The input end of the first selection unit 12 is electrically connected to the serial data line SDA, the output end of the first selection unit 12 is electrically connected to the clock end CLK1 of the first register, the control end of the first selection unit 12 is connected to the trigger signal LP_MODE, and the first selection unit 12 is used to output a first clock control signal when the trigger signal LP_MODE is a first potential, and the first clock control signal is opposite to the signal on the serial data line SDA;

[0059] An input terminal D1 of the first register 11 is electrically connected to the serial clock line SCL, an output terminal Q1 of the first register 11 is electrically connected to a first input terminal of the first AND gate 13, and the first register 11 is used to generate a control signal according to the first clock control signal and the signal on the serial clock line SCL when the trigger signal LP_MODE is at the first potential;

[0060] The second input terminal of the first AND gate 13 is connected to the trigger signal LP_MODE, and the output terminal A1 of the first AND gate 13 is electrically connected to the low-power wake-up circuit 2 and the clock line control circuit 3 respectively. The first AND gate 13 is used to generate a first detection signal according to the control signal when the trigger signal LP_MODE is a first potential, and is also used to generate a second detection signal when the trigger signal is a second potential.

[0061] The first register 11 collects the signal inputted from its input terminal D1 and outputs it to the output terminal Q1 at the rising edge of the signal connected to its clock terminal CLK1, and at other times, the signal of the output terminal Q1 remains unchanged. In this embodiment, when the control system receives the requirement that the system needs to enter the low power consumption mode, the trigger signal LP_MODE is controlled to be the first potential, that is, the high level, and the first register 11 collects the signal on the serial clock line SCL at the falling edge of the signal on the serial data line SDA and outputs it to the first AND gate 13. Since the trigger signal LP_MODE inputted to the second input terminal of the first AND gate 13 is the first potential, the signal at the output terminal A1 of the first AND gate 13 is only related to the signal on the collected serial clock line SCL. In the low power consumption mode, the signal on the collected serial clock line SCL is at a high level, and the first detection signal generated is at a high level. When the control system receives a request to switch the system to normal mode, the control trigger signal LP_MODE is set to the second potential, i.e., a low level. Since the signal input to the second input terminal of the first AND gate 13 is a low level, no matter what signal is outputted by the output terminal Q1 of the first register 11, the output terminal A1 of the first AND gate 13 outputs a low level, i.e., a second detection signal.

[0062] Continue to refer Figure 2 Optionally, the first selection unit 12 includes a first inverter 121 and a first selector 122, the input end of the first inverter 121 is electrically connected to the serial data line SDA, the output end of the first inverter 121 is electrically connected to the first input end of the first selector 122, the second input end of the first selector 122 is connected to the second potential V1, the control end of the first selector 122 is connected to the trigger signal LP_MODE, and the output end of the first selector 122 is electrically connected to the clock end CLK1 of the first register 11.

[0063] When the trigger signal LP_MODE connected to the control end of the first selector 122 is the first potential, the first selector 122 outputs the signal input to the first input end, that is, outputs the inverse signal of the signal on the serial data line SDA. When the trigger signal LP_MODE connected to the control end of the first selector 122 is the second potential, the first selector 122 outputs the signal input to the second input end, that is, the second potential V1.

[0064] Figure 3 A schematic diagram of another control circuit for waking up a low power consumption mode according to an embodiment of the present invention is provided. Figure 3 Optionally, the low-power wake-up circuit 2 includes a second AND gate 21 and a second selector 22, the first input end of the second AND gate 21 is connected to the wake-up enable signal WKUP_EN, the second input end of the second AND gate 21 is connected to the trigger signal LP_MODE, the output end of the second AND gate 21 is electrically connected to the control end of the second selector 22, the first input end of the second selector 22 is electrically connected to the output end of the communication detection circuit 1, the second input end of the second selector 22 is connected to the second potential V1, and the output end WKUP of the second selector 22 is electrically connected to the control module 7.

[0065] After the control system receives the requirement to enter the low power mode, the control trigger signal LP_MODE and the wake-up enable signal WKUP_EN are both the first potential, then the second AND gate 21 outputs a high level, and the second selector 22 outputs the first detection signal input at its first input end to the control module 7, so that the control module 7 controls the control system to enter the low power mode. After the control system receives the requirement to enter the normal mode, the control trigger signal LP_MODE changes to the second potential, i.e., a low level, then the output end of the second AND gate 21 outputs a low level, and the second selector 22 outputs the second potential V1 input at its second input end, i.e., a low level, to the control module 7. The control module 7 controls the control system to exit the low power mode according to the low level received from the low power wake-up circuit 2 to enter the normal mode.

[0066] Figure 4 A schematic diagram of another control circuit for waking up a low power consumption mode according to an embodiment of the present invention is provided. Figure 4 , Optionally, the clock line control circuit 3 includes a second selection unit 31, a second register 32 and a third selection unit 33;

[0067] The input end of the second selection unit 31 is electrically connected to the serial clock line SCL, the control end of the second selection unit 31 is connected to the trigger signal LP_MODE, the output end of the second selection unit 31 is electrically connected to the clock end CLK2 of the second register 32, and the second selection unit 31 is used to output a second clock control signal when the trigger signal LP_MODE is at the first potential, and the second clock control signal is opposite to the signal on the serial clock line SCL;

[0068] The input end D2 of the second register 32 is electrically connected to the output end of the communication detection circuit 1, and the output end Q2 of the second register 32 is electrically connected to the input end of the third selection unit 33. The second register 32 is used to generate a second control signal according to the second clock control signal and the first detection signal output by the communication detection circuit 1 when the trigger signal LP_MODE is the first potential. The control end of the third selection unit 33 is connected to the trigger signal LP_MODE, and the output end of the third selection unit 33 is electrically connected to the control module 7. The third selection unit 33 is used to output a first clock control signal according to the second control signal when the trigger signal LP_MODE is the first potential. The first clock control signal is opposite to the second control signal when the trigger signal LP_MODE is the first potential. The third selection unit is also used to generate a second clock control signal when the trigger signal LP_MODE is the second potential.

[0069] The second selection unit 31 is used for outputting a signal which is the inverse signal on the serial clock line SCL at its output end when the trigger signal LP_MODE is the first potential. The second register 32 samples the first detection signal inputted by the input end D2 of the second register 32 at the rising edge of the second clock control signal, i.e., the falling edge of the signal on the serial clock line SCL, and outputs the sampled signal to the input end of the third selection unit 33, until the falling edge of the signal on the next serial clock line SCL, the sampled signal will change. When the trigger signal LP_MODE is the first potential, the third selection unit 33 outputs the inverse signal of the sampled signal, i.e., the low level, to the control module 7, so that the control module 7 controls the signal on the serial clock line SCL to always maintain the low level. When the trigger signal LP_MODE is the second potential, the third selection unit 33 directly outputs the first potential V2, i.e., the high level, to the control module 7, thereby causing the control module to release the control of the serial clock line SCL, so that the serial clock line SCL can be controlled by the master device and transmit the addressing signal sent by the master device.

[0070] Continue to refer Figure 4 Optionally, the second selection unit 31 includes a second inverter 311 and a third selector 312, the input end of the second inverter 311 is electrically connected to the serial clock line SCL, the output end of the second inverter 311 is electrically connected to the first input end of the third selector 312, the second input end of the third selector 312 is connected to the second potential V1, the control end of the third selector 312 is connected to the trigger signal LP_MODE, and the output end of the third selector 312 is electrically connected to the clock end CLK2 of the second register 32.

[0071] The third selection unit 33 includes a third inverter 331 and a fourth selector 332, the input end of the third inverter 331 is electrically connected to the output end Q2 of the second register 32, the output end of the third inverter 331 is electrically connected to the first input end of the fourth selector 332, the second input end of the fourth selector 332 is connected to the first potential V2, the control end of the fourth selector 332 is connected to the trigger signal LP_MODE, and the output end SCL_CTRL of the fourth selector 332 is electrically connected to the control module 7.

[0072] The third selector 312 outputs the inverse signal of the signal inputted from the serial clock line SCL to the clock terminal CLK2 of the second register 32 when the trigger signal LP_MODE is the first potential, i.e., the high level. The third selector 312 outputs the second potential V1 to the clock terminal CLK2 of the second register 32 when the trigger signal LP_MODE is the second potential, i.e., the low level. The fourth selector 332 outputs the inverse signal of the signal outputted from the output terminal Q2 of the second register 32 to the control module 7 when the trigger signal LP_MODE is the first potential, i.e., the high level. The fourth selector 332 outputs the first potential V2, i.e., the high level, to the control module 7 when the trigger signal LP_MODE is the second potential, i.e., the low level.

[0073] The second selection unit 31 only includes a second inverter 311 and a third selector 312, which has a simple structure and is conducive to reducing costs. The third selection unit 33 only includes a third inverter 331 and a fourth selector 332, which has a simple structure and is conducive to reducing costs.

[0074] Figure 5 A schematic diagram of the structure of another control circuit for waking up a low power consumption mode provided by an embodiment of the present invention, Figure 6 A driving timing diagram of a control circuit for waking up a low power consumption mode is provided in an embodiment of the present invention. When the control system is in the low power consumption mode, the clock of the control system is turned off, so that the clock line CLK of the control system is at a low level. Figure 6 The drive timing diagram shown is applicable to Figure 5 The circuit shown, reference Figure 5 and Figure 6 ,The working process of waking up the control circuit in the low power consumption mode includes a low power consumption phase t1 and a normal phase t2 .

[0075] In the low power consumption stage t1, after the control system receives the requirement to enter the low power consumption mode, the control trigger signal LP_MODE and the wake-up enable signal WKUP_EN are controlled to be the first potential, i.e., high level, the serial clock line SCL and the serial data line SDA are both high level, and the first selector 122 transmits the inverted signal on the serial data line SDA, i.e., low level, to the clock terminal CLK1 of the first register 11. At the first moment n1, the signal on the serial data line SDA jumps to a low level, and the signal input to the clock terminal CLK1 of the first register 11 jumps to a high level. At this time, the first register 11 samples the signal on the serial clock line SCL, i.e., a high level, and outputs it to the first input terminal of the first AND gate 13. Since the first input terminal and the second input terminal of the first AND gate 13 are both high level, the output terminal A1 of the first AND gate 13 outputs a high level to the first input terminal of the second selector 22. Since the trigger signal LP_MODE and the wake-up enable signal WKUP_EN input to the two input terminals of the second AND gate 21 are both high level, the output terminal of the second AND gate 21 outputs a high level to the control terminal of the second selector 22. Since the signal connected to the control end of the second selector 22 is at a high level, the output end WKUP of the second selector 22 outputs a high level to the control module 7 of the control system, so that the control system switches to the low power mode. The control end of the third selector 312 is at a high level, and the third selector 312 transmits the inverse signal of the signal of the serial clock line SCL, i.e., the low level, to the clock end CLK2 of the second register 32. When the clock end CLK2 of the second register 32 does not jump from a low level to a high level, the output end Q2 of the second register 32 outputs the low level of the previous sampling moment, and the control end of the fourth selector 332 is at a high level, and the output end of the fourth selector 332 outputs the inverse signal of the output end Q2 of the second register 32, i.e., the high level. At the second moment n2, the signal on the serial clock line SCL jumps to a low level, which has no effect on the signal output by the output end A1 of the first AND gate 13 and the signal output by the output end WKUP of the low power wake-up circuit 2. The second selection unit 31 jumps the signal on the serial clock line SCL, so that the signal inputted by the clock terminal CLK2 of the second register 32 jumps from a low level to a high level. The second register 32 samples the high level outputted by the output terminal A1 of the first AND gate 13 to the input terminal of the third inverter 331, so that the output terminal of the fourth selector 332 outputs a low level. The low level outputted by the output terminal of the fourth selector 332 controls the signal on the serial clock line SCL to be a low level, so as to prevent the serial clock line SCL from transmitting the addressing signal of the master device. At the third moment n3, after the control system receives the requirement to switch to the normal working mode, the control trigger signal LP_MODE is controlled to become a low level. Then, no matter what level signal is outputted by the output terminal A1 of the first AND gate 13, because the second AND gate 21 outputs a low level, the second selector 22 outputs the second potential V1, i.e., a low level, to the control module 7, so as to control the control system to exit the low power consumption mode.At the same time, no matter what signal is outputted by the output terminal Q2 of the second register 32, since the control terminal of the fourth selector 332 is at a low level, the fourth selector 332 outputs the first potential V2, i.e., a high level, to the control module 7 to release the control of the serial clock line SCL, so that the serial clock line SCL normally receives the addressing signal of the master device and sends it to the slave device to ensure the normal communication between the master device and the slave device. That is, in the low power consumption mode, the present embodiment pulls down the signal of the serial clock line SCL so that the master device does not send the addressing signal to the slave device. After exiting the low power consumption mode, the control of the serial clock line SCL is released so that the serial clock line receives the addressing signal sent by the master device to ensure the normal communication between the master device and the slave device.

[0076] The embodiment of the present invention also provides a control method for waking up a low power consumption mode. Figure 7 A flowchart of a control method for waking up a low power consumption mode provided by an embodiment of the present invention, referring to Figure 7 , this embodiment can be applied to the case of waking up the low power consumption mode of the control system, the method is applicable to the control circuit for waking up the low power consumption mode described above, the control circuit for waking up the low power consumption mode is applied to the control system, the low power consumption wake-up circuit comprises: a communication detection circuit, a mode control circuit, a serial data line and a serial clock line; the output end of the communication detection circuit is electrically connected to the mode control circuit, the communication detection circuit is also connected between the master device and the slave device through the serial data line and the serial clock line, the control end of the communication detection circuit is connected to the trigger signal, and the output end of the mode control circuit is electrically connected to the control module of the control system;

[0077] The control methods for waking up low power mode include:

[0078] S10: When the trigger signal is at the first potential, the communication detection circuit generates a first detection signal according to the signal on the serial data line, the signal on the serial clock line and the trigger signal; the trigger signal is at the first potential when the control system is configured as a low power consumption mode, and the trigger signal is at the second potential when the control system is configured as a normal mode.

[0079] S20: The mode control circuit controls the signal on the serial clock line to maintain a second potential according to the wake-up enable signal, the trigger signal, the signal on the serial clock line and the first detection signal, and controls the control system to enter a low power consumption mode through the control module, wherein the trigger signal is the first potential.

[0080] The mode control circuit includes a low-power wake-up circuit and a clock line control circuit, the input end of the low-power wake-up circuit is electrically connected to the output end of the communication detection circuit, the output end of the low-power wake-up circuit is electrically connected to the control module of the control system, the input end of the clock line control circuit is electrically connected to the output end of the communication detection circuit, and the control method for waking up the low-power mode also includes:

[0081] The communication detection circuit generates a second detection signal when the trigger signal is at a second potential;

[0082] When the trigger signal is at the second potential, the low power consumption wake-up circuit generates a wake-up exit signal so that the control module controls the control system to enter the low power consumption mode;

[0083] When the trigger signal is at the second potential, the clock line control circuit generates a second clock control signal to control the serial clock line to transmit the addressing signal of the master device.

[0084] The beneficial effects of the control method for waking up the low power consumption mode in this embodiment are the same as the beneficial effects of the control circuit for waking up the low power consumption mode, and this embodiment will not be described in detail here.

[0085] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0086] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A control circuit for waking up a low power consumption mode, characterized in that: Applied to a control system, the control circuit for waking up the low power consumption mode comprises: a communication detection circuit, a mode control circuit, a serial data line and a serial clock line; The output end of the communication detection circuit is electrically connected to the mode control circuit, the communication detection circuit is also connected between the master device and the slave device through the serial data line and the serial clock line, the control end of the communication detection circuit is connected to the trigger signal, and the communication detection circuit is used to generate a first detection signal according to the signal on the serial data line, the signal on the serial clock line and the trigger signal when the trigger signal is a first potential; the trigger signal is a first potential when the control system is configured in a low power consumption mode, and the trigger signal is a second potential when the control system is configured in a normal mode; The output end of the mode control circuit is electrically connected to the control module of the control system, and the mode control circuit is used to control the signal on the serial clock line to maintain a second potential according to the wake-up enable signal, the trigger signal, the signal on the serial clock line and the first detection signal, and control the control system to enter a low power consumption mode through the control module, wherein the trigger signal is a first potential; The mode control circuit includes a low-power wake-up circuit and a clock line control circuit, the input end of the low-power wake-up circuit is electrically connected to the output end of the communication detection circuit, the output end of the low-power wake-up circuit is electrically connected to the control module of the control system, and the low-power wake-up circuit is used to generate a wake-up signal according to a wake-up enable signal, the trigger signal and the first detection signal so that the control module controls the control system to enter a low-power mode; the wake-up enable signal is a first potential when the control system is configured in a low-power mode; The input end of the clock line control circuit is electrically connected to the output end of the communication detection circuit, and the clock line control circuit is used to generate a first clock control signal according to the signal on the serial clock line and the first detection signal when the trigger signal is received as the first potential, so as to control the signal on the serial clock line to maintain the second potential; The communication detection circuit is further configured to generate a second detection signal when the trigger signal is at a second potential; The low-power wake-up circuit is used to generate a wake-up exit signal when the trigger signal is at the second potential so that the control module controls the control system to enter the low-power mode; The clock line control circuit is further configured to generate a second clock control signal when the trigger signal is at a second potential, so as to control the serial clock line to transmit the addressing signal of the master device.

2. The control circuit for waking up the low power consumption mode according to claim 1, characterized in that: The communication detection circuit includes a first register, a first selection unit and a first AND gate; The input end of the first selection unit is electrically connected to the serial data line, the output end of the first selection unit is electrically connected to the clock end of the first register, the control end of the first selection unit is connected to the trigger signal, and the first selection unit is used to output a first clock control signal when the trigger signal is a first potential, and the first clock control signal is opposite to the signal on the serial data line; The input end of the first register is electrically connected to the serial clock line, the output end of the first register is electrically connected to the first input end of the first AND gate, and the first register is used to generate a control signal according to the first clock control signal and the signal on the serial clock line when the trigger signal is a first potential; The second input end of the first AND gate is connected to the trigger signal, and the output end of the first AND gate is electrically connected to the low-power wake-up circuit and the clock line control circuit respectively. The first AND gate is used to generate a first detection signal according to the control signal when the trigger signal is a first potential, and is also used to generate a second detection signal when the trigger signal is a second potential.

3. The control circuit for waking up the low power consumption mode according to claim 2, characterized in that: The first selection unit includes a first inverter and a first selector, the input end of the first inverter is electrically connected to the serial data line, the output end of the first inverter is electrically connected to the first input end of the first selector, the second input end of the first selector is connected to the second potential, the control end of the first selector is connected to the trigger signal, and the output end of the first selector is electrically connected to the clock end of the first register.

4. The control circuit for waking up the low power consumption mode according to claim 1, characterized in that: The low-power wake-up circuit includes a second AND gate and a second selector, the first input end of the second AND gate is connected to the wake-up enable signal, the second input end of the second AND gate is connected to the trigger signal, the output end of the second AND gate is electrically connected to the control end of the second selector, the first input end of the second selector is electrically connected to the output end of the communication detection circuit, the second input end of the second selector is connected to the second potential, and the output end of the second selector is electrically connected to the control module.

5. The control circuit for waking up the low power consumption mode according to claim 1, characterized in that: The clock line control circuit includes a second selection unit, a second register and a third selection unit; The input end of the second selection unit is electrically connected to the serial clock line, the control end of the second selection unit is connected to the trigger signal, the output end of the second selection unit is electrically connected to the clock end of the second register, and the second selection unit is used to output a second clock control signal when the trigger signal is a first potential, and the second clock control signal is opposite to the signal on the serial clock line; The input end of the second register is electrically connected to the output end of the communication detection circuit, and the output end of the second register is electrically connected to the input end of the third selection unit. The second register is used to generate a second control signal according to the second clock control signal and the first detection signal output by the communication detection circuit when the trigger signal is a first potential. The control end of the third selection unit is connected to the trigger signal, and the output end of the third selection unit is electrically connected to the control module. The third selection unit is used to output the first clock control signal according to the second control signal when the trigger signal is a first potential. The first clock control signal is opposite to the second control signal when the trigger signal is a first potential. The third selection unit is also used to generate a second clock control signal when the trigger signal is a second potential.

6. The control circuit for waking up the low power consumption mode according to claim 5, characterized in that: The second selection unit includes a second inverter and a third selector, the input end of the second inverter is electrically connected to the serial clock line, the output end of the second inverter is electrically connected to the first input end of the third selector, the second input end of the third selector is connected to the second potential, the control end of the third selector is connected to the trigger signal, and the output end of the third selector is electrically connected to the clock end of the second register; The third selection unit includes a third inverter and a fourth selector, the input end of the third inverter is electrically connected to the output end of the second register, the output end of the third inverter is electrically connected to the first input end of the fourth selector, the second input end of the fourth selector is connected to the first potential, the control end of the fourth selector is connected to the trigger signal, and the output end of the fourth selector is electrically connected to the control module.

7. A control method for waking up a low power consumption mode, characterized in that: A control circuit for waking up a low power mode according to any one of claims 1 to 6, wherein the control circuit for waking up a low power mode is applied to a control system, and the low power wake-up circuit comprises: a communication detection circuit, a mode control circuit, a serial data line, and a serial clock line; the output end of the communication detection circuit is electrically connected to the mode control circuit, and the communication detection circuit is also connected between a master device and a slave device through the serial data line and the serial clock line, the control end of the communication detection circuit is connected to a trigger signal, and the output end of the mode control circuit is electrically connected to a control module of the control system; The control method for waking up the low power consumption mode comprises: The communication detection circuit generates a first detection signal according to the signal on the serial data line, the signal on the serial clock line and the trigger signal when the trigger signal is at the first potential; the trigger signal is at the first potential when the control system is configured in the low power consumption mode, and is at the second potential when the control system is configured in the normal mode; The mode control circuit controls the signal on the serial clock line to maintain a second potential according to the wake-up enable signal, the trigger signal, the signal on the serial clock line and the first detection signal, and controls the control system to enter a low power consumption mode through a control module, wherein the trigger signal is a first potential.

8. The control method for waking up the low power consumption mode according to claim 7, characterized in that: The mode control circuit includes a low-power wake-up circuit and a clock line control circuit, the input end of the low-power wake-up circuit is electrically connected to the output end of the communication detection circuit, the output end of the low-power wake-up circuit is electrically connected to the control module of the control system, the input end of the clock line control circuit is electrically connected to the output end of the communication detection circuit, and the control method for waking up the low-power mode also includes: The communication detection circuit generates a second detection signal when the trigger signal is at a second potential; The low-power wake-up circuit generates a wake-up exit signal when the trigger signal is at the second potential so that the control module controls the control system to enter the low-power mode; When the trigger signal is at a second potential, the clock line control circuit generates a second clock control signal to control the serial clock line to transmit the addressing signal of the master device.

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