Laser frame ranging method

Abstract

The present invention discloses a laser frame ranging method, wherein a front-stage photoelectric conversion module converts a laser signal into an electrical signal, and then recovers the clock and parallel data through a phase-locked loop, and uses a frame synchronization module to perform frame synchronization on the parallel data according to a synchronization header, generating a frame header synchronization decision pulse and a synchronization delay, and a ranging frame information processing module extracts ranging information from a frame data center, and then uses a clock phase calculation module to calculate the phase difference between the recovered clock and the local clock, and after the synchronization decision pulse arrives, a high-precision receiving time is calculated according to the phase difference and the synchronization delay. The laser ranging method of the present invention does not require the use of a high-precision ADC and a DDS, is simple to implement, and has low cost.

Description

Technical Field

[0001] The invention relates to the field of lasers, and in particular to a laser frame distance measurement method. Background Art

[0002] Laser ranging is a method of measuring distance using laser characteristics (such as pulses, phases, etc.), and is widely used between satellites and between satellites and the ground. With the rapid development of intersatellite networking and satellite navigation technology, a single ranging method cannot meet the growing communication and ranging needs. High-speed laser communication solves the bottleneck of communication rate between networked satellites. The high-precision ranging performance achieved based on laser communication signals is of great significance to satellite positioning or navigation and positioning systems.

[0003] In the existing research literature, many of them use the principle of two-way one-way ranging to realize the distance measurement between two terminals. Sun Jianfeng used ranging code and clock phase difference to realize coarse ranging and fine ranging in "High-speed laser communication method and high-precision laser ranging integrated method", 2019-02-01, but the received ranging code needs to be correlated with the local ranging code, which is very complicated. Funan Zhu also used coarse ranging and fine ranging in "Inter-satellite laser-ranging based on intradynecoherent detection", 2021:8930-8938. It uses high-speed ADC for sampling and uses DDS (Direct Digital Synthesis) technology to compare the local clock and the recovered clock phase difference to achieve fine ranging, which has high implementation cost. Summary of the invention

[0004] In view of the above-mentioned defects of the prior art, the technical problem to be solved by the present invention is that the existing laser communication and ranging integrated technology has high cost, complex operation, and is not easy to promote and implement. Therefore, the present invention provides a laser ranging method, which uses frame synchronization, ranging frame information processing and clock phase calculation modules, recovers communication data through the frame synchronization module, transmits the communication data to the ranging frame information processing module to extract the ranging information, and obtains a rough ranging value. The clock phase calculation module calculates the phase difference between the local clock and the recovered clock to obtain an accurate ranging value, without the need to use high-precision ADC and DDS, and is simple to implement and low in cost.

[0005] To achieve the above purpose, the present invention provides a laser frame ranging method, in which a front-stage photoelectric conversion module converts a laser signal into an electrical signal, and then recovers the clock and parallel data through a phase-locked loop, and uses a frame synchronization module to perform frame synchronization on the parallel data according to a synchronization header, generating a frame header synchronization decision pulse and a synchronization delay, and a ranging frame information processing module extracts the ranging information of the sending time from the frame data center, and then uses a clock phase calculation module to calculate the phase difference between the recovered clock and the local clock. After the synchronization decision pulse arrives, a high-precision receiving time is calculated according to the phase difference and the synchronization delay, and a data interaction module receives the sending time and the receiving time, calculates the ranging value, and hands it over to a subsequent host computer for further processing.

[0006] Furthermore, the frame synchronization module performs shift synchronization according to the frame header. After identifying the frame header, it performs frame alignment on the parallel data, generates a synchronization decision pulse and a synchronization delay, and sends them to the clock phase calculation module, wherein the synchronization decision pulse serves as a trigger signal, and the synchronization delay is used to compensate for the error caused by the synchronization module.

[0007] Furthermore, the ranging information includes the second count and the ranging frame sending time. The ranging frame processing module extracts the second count, processing delay, and the local ranging value of the other end from the ranging frame, and sends these data as the sending time of the other end to the data interaction module.

[0008] Furthermore, the clock phase calculation module compares the local clock and the recovered clock by using a high-frequency clock counter aligned with the local clock to calculate the phase difference.

[0009] Furthermore, the high-frequency clock counter includes a frame count and a phase count. The frame count is driven by the TX clock of the SERDES module. The phase count includes several sub-counters. Each sub-counter operates at m times the TX clock. The operating clocks of each sub-counter have equal phase differences.

[0010] Furthermore, each sub-counter exists in each sub-clock, and counts by means of a circular shift register.

[0011] Furthermore, at each rising edge of the clock to be tested, the frame count value and the sub-clock count value that have been Gray-coded are tapped to the clock domain of the clock to be tested, and then Gray code decoding is performed. Then, the phase count value is calculated in the clock domain to be tested, the average of the phase count values ​​is obtained, and the frame count value is corrected by the phase count value.

[0012] Furthermore, the phase count value includes the accumulated sum of several sub-counter count values, which are alternately called by at least two accumulators to eliminate accumulation and zeroing errors.

[0013] Furthermore, the frame count value and the phase count value include the following three relationships: the phase count reset is basically synchronized with the frame count increment, the phase count reset lags behind the frame count increment, and the phase count reset precedes the frame count increment.

[0014] Furthermore, the receiving time is obtained by calculating the frame count and the phase count, and the receiving time value needs to be corrected according to the above three situations.

[0015] Technical Effects

[0016] A laser frame ranging method of the present invention uses communication frames to carry ranging information, has low overhead, does not need to change the communication frame structure for ranging, is simple to implement clock phase calculation, does not need to perform frequency domain conversion, is implemented entirely in the electrical domain, does not need to change the optical domain structure, and has accurate ranging results and low cost.

[0017] The concept, specific structure and technical effects of the present invention will be further described below in conjunction with the accompanying drawings to fully understand the purpose, characteristics and effects of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of a laser frame ranging method of a preferred embodiment of the present invention;

[0019] Figure 2 The figure is a simplified distance measurement flow chart of a laser frame distance measurement method according to a preferred embodiment of the present invention.

[0020] Figure 3 The present invention is a simple ranging timing diagram of a receiving end of a laser frame ranging method according to a preferred embodiment of the present invention.

[0021] Figure 4 It is a structural diagram of a clock phase calculation module of a laser frame ranging method according to a preferred embodiment of the present invention.

[0022] Figure 5 The present invention is a simplified timing diagram of a phase-locked loop clock generation in a laser frame ranging method according to a preferred embodiment of the present invention.

[0023] Figure 6 The present invention is a simplified timing diagram of a phase clock of a laser frame ranging method according to a preferred embodiment of the present invention.

[0024] Figure 7 It is a simplified timing diagram of a laser frame ranging method in which the phase count leads the frame count in a preferred embodiment of the present invention.

[0025] Figure 8 It is a simplified timing diagram of phase counting delayed frame counting of a laser frame ranging method according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0027] In the following description, specific details such as specific internal procedures and techniques are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present invention. However, it should be clear to those skilled in the art that the present invention may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present invention.

[0028] like Figure 1 As shown, the present invention provides a laser frame ranging method, the front-stage photoelectric conversion module converts the laser signal into an electrical signal, and then recovers the clock and parallel data through a phase-locked loop, and uses a frame synchronization module to perform frame synchronization on the parallel data according to a synchronization header to generate a frame header synchronization decision pulse and a synchronization delay, the ranging frame information processing module extracts the ranging information from the frame data center, and then uses a clock phase calculation module to calculate the phase difference between the recovered clock and the local clock, and after the synchronization decision pulse arrives, a high-precision receiving time is calculated based on the phase difference and the synchronization delay.

[0029] The embodiment of the present invention provides a laser frame ranging method. In this embodiment, a two-way one-way ranging test is used to illustrate the specific process and principle of a laser frame ranging method provided by the present invention. In the two-way one-way ranging process, the ranging process of laser terminal A sending and laser terminal B receiving is the same as the ranging process of laser terminal A receiving and laser terminal B sending. Here, terminal A sends and terminal B receives as an example. The ranging process is as follows: Figure 2 shown.

[0030] A laser frame ranging method of this embodiment includes the following process:

[0031] 1) In laser terminal A, after the arrival of the waiting PPS_A_1, the time of the first bit leading edge of the frame header of the first complete laser link frame is recorded, and the offset relative to PPS_A_1 is recorded as the local timestamp Δt of the sender. A1 , which is the sending time, in units of 0.1ns. Fill it into the frame header of the laser link frame and mark this frame as a valid ranging frame.

[0032] 2) In laser terminal B, after waiting for PPS_B_1 to arrive, record the time of the first bit leading edge of the first ranging valid frame header that arrives subsequently, and the offset relative to PPS_B_1, recorded as the local timestamp Δt of the receiving endB1 , which is the receiving time, the unit is 0.1ns.

[0033] 3) Laser terminal B obtains the local timestamp Δt of the sender from the frame header of the received ranging valid frame A1 .

[0034] 4) Laser terminal B calculates and obtains the local distance measurement value T1 = Δt of laser terminal B B1 -Δt A1 .

[0035] 5) The transmitter of laser terminal B fills the same ranging cycle second count T in the subsequent 100 frames of laser link frame headers. B1 , and the local ranging value T1 of laser terminal B. At other times, fill in the default values ​​0xFFFFFF and 0xFFFFFFFF. The second count in the ranging week is used to identify the time of the local ranging value. In every second, laser terminals A and B each have a local ranging value.

[0036] 6) After PPS_A_1, the receiving end of laser terminal A receives the valid ranging week second count T B1 , and the local distance measurement value T1 of laser terminal B, according to T B1 , retrieve the corresponding local distance measurement value T2 of laser terminal A. Package T1 and T2 and upload them for software use.

[0037] In the above process, the key to ranging is the sending time Δt A1 and receiving time Δt B1 The clock phase calculation module is used in the embodiment of the present invention to realize the sending time Δt A1 and receiving time Δt B accurate acquisition.

[0038] In particular, at the receiving end, the clock phase calculation module is located after the frame synchronization module. Frame synchronization will introduce random delays, interfering with the measurement accuracy of the receiving time. The receiving time output by the clock phase calculation module needs to be compensated by subtracting the synchronization delay output by the frame synchronization module.

[0039] The clock phase calculation module compares the local clock and the recovered clock through a high-frequency clock counter aligned with the local clock to calculate the phase difference. Taking the receiving end (laser terminal B) as an example, after the ranging frame arrives, a ranging pulse is generated, and the local timestamp in the local clock domain (Serdes TX clock) is obtained by beating, and Δt B1 ,like Figure 3 shown.

[0040] The local timestamp is achieved by building a high-frequency clock counter in the local clock domain to calculate the phase difference between the received clock and the local clock to obtain the high-precision receiving time. Figure 4 shown.

[0041] The high-frequency clock counter consists of two parts: frame count and phase count. The frame clock count is driven by the tx clock of the SERDES module, with a frequency of f. It returns to zero when the count reaches 1s. The phase clock consists of n sub-clocks, each of which is m times the frame clock, that is, the frequency is mf. The count reaches f. -1 The second is reset to zero, and there is a 2π×n gap between n sub-clocks -1 The phase difference together constitutes a virtual clock with a frequency of mnf.

[0042] by Figure 5 For example, the frame clock is 156.25MHz, which is composed of 8 sub-clocks. The frequency of the sub-clock is 4 times the frequency of the frame clock, which is 625MHz. There is a phase difference of π / 4 between the sub-clocks, forming a virtual clock with a frequency of 5GHz, that is, at each rising edge of the 5GHz clock, there is a corresponding rising edge of the 625MHz clock.

[0043] There is a sub-counter under each sub-clock, which realizes the cumulative counting from 0 to 2m-1 through the circular shift register. The output of the counter count value is divided into k paths, and the count value between each path differs by 2mk -1 , which is used to avoid errors caused by the sub-counter count value returning to zero when calculating the phase count value. The sub-counter output uses Gray coding to limit the count value jitter generated across clock domains to no more than ±1.

[0044] by Figure 6 For example, the phase count consists of 8 sub-counters, each of which counts from 0 to 7. The sub-counter outputs are divided into two channels, A and B, which are called alternately, and the count values ​​of A and B differ by 4.

[0045] At each rising edge of the clock to be tested, the Gray-encoded frame count value and the sub-clock count value are tapped to the clock domain of the clock to be tested, and then Gray code decoding is performed. Then, the phase count value is calculated in the clock domain to be tested, and the frame count value is corrected by the phase count value.

[0046] The count value of the phase count is obtained by accumulating the count values ​​of the 8 sub-counters, and the output includes the count value and the synchronization bit. Figure 6 For example, under the 5GHz virtual clock, the count value range is 0-62, the unit is 0.1ns, the resolution is 0.2ns, and the synchronization bit is a single bit, indicating whether the accumulator is called for A path. The synchronization bit corresponds to the lowest bit of the frame count.

[0047] The specific process of obtaining the count value is as follows:

[0048] 1. Accumulate the count values ​​of each sub-counter of A and B to get sum_a and sum_b;

[0049] 2. If sum_a is in the range of 16-47, the output count value is (sum_a-16)*2, and the synchronization position is 1;

[0050] 3. If sum_b is less than 16, the output count value is (sum_b+16)*2, and the synchronization position is 1;

[0051] 4. If sum_b is greater than 47, the output count value is (sum_b-48)*2, and the synchronization position is 1;

[0052] 5. In the remaining cases, the output count value is (sum_b-16)*2, and the synchronization position is 0.

[0053] Due to the cross-clock domain beat, under Gray coding, the frame counter has a jitter of ±1 (±6.4ns), and each sub-counter has a jitter of ±1 (±0.2ns). Through the above phase count calculation module, the maximum jitter of the phase count value caused by the sub-counter jitter is ±16 (±1.6ns).

[0054] To further improve the stability of phase counting, it is necessary to average the output of multiple phase counting values ​​(fast clock counting) to reduce the error to less than 0.1ns. This step is completed by the averager, such as Figure 4 shown.

[0055] The workflow of the averager is as follows:

[0056] 1. Latch the first input ranging value and its synchronization bit;

[0057] 2. The subsequent input distance measurement value is compared with the first distance measurement value. If there is a carry or a borrow, the cycle is extended;

[0058] 3. Find the average value;

[0059] 4. Correct the synchronization bit based on the near-degenerate relationship between the average value and the first ranging value.

[0060] For frame counting, the ±6.4ns error of the frame counting value can be eliminated through the synchronization identification bit of the phase counting. The principle is as follows:

[0061] Assume that the phase count synchronization flag is A f The lowest bit of the frame count value is Cs0, and the synchronization flag is A. f After XOR operation with Cs0, we get:

[0062]

[0063] Among them A f It will flip when the phase count returns to zero, at which time the frame count value will increase, and Cs0 will also flip at the same time. Therefore, when the system is running, the count value of the clock counting module is sampled from any clock domain, and A should be a fixed value.

[0064] The relationship between the frame count value and the phase count value includes the following three types: the phase count reset is basically synchronized with the frame count increment (the frame count value has no error), the phase count reset is ahead of the frame count increment (the frame count value error is -6.4ns, such as Figure 7 As shown), the phase count returns to zero lags behind the frame count increment (frame count value error + 6.4ns, such as Figure 8 As shown in FIG. 1 , the advance (delay) will cause the inversion of the synchronization flag A. Therefore, by determining whether the synchronization flag A is inverted, the frame count error can be corrected.

[0065] Whether the synchronization flag A is flipped requires a reference. The Serdes TX clock can be used as the clock to be tested. At this time, the clock to be tested and the frame count value are in the same clock domain, which meets the clock constraint. The obtained frame count value has no error, and the frame clock and the sub-clock are phase-locked through the phase-locked loop, so the phase count value does not return to zero. The synchronization flag A obtained in this state is stable and can be used as a reference state, recorded as A s .

[0066] Therefore, when obtaining the timestamp in other clock domains, it is only necessary to compare the synchronization flag bit A with the reference state A. s , the frame counting error can be corrected. The correction formula is as follows:

[0067]

[0068] Among them, C r The local timestamp obtained for the signal to be tested; C s is the frame count value in the clock domain of the signal to be tested; C f is the phase count value in the clock domain of the signal to be tested; A is the synchronization flag in the clock domain of the signal to be tested; A s It is the reference synchronization flag in the SerdesTX clock domain, and this flag remains constant.

[0069] like Figure 7 As shown, the phase count returns to zero and the leading frame count increases. When A flips, the count value generates a -64 error. After correction according to the formula, the count value before and after A flips is continuous; Figure 8 As shown, the frame count increases after the phase count returns to zero. When A flips, the count value generates a +64 error. After correction according to the formula, the count values ​​before and after A flip are continuous. The verification is established.

[0070] In addition, the frame synchronization, ranging frame information processing and clock phase calculation modules in this embodiment are all implemented in Verilog language and burned on the FPGA board. The FPGA board is connected to a host. The frame synchronization, ranging frame information processing and clock phase calculation modules in the embodiment of the present invention realize the interaction between the local (FPGA) and the host through the interaction between the FPGA and the host. The data transmission method of the present invention is easy to implement and promote.

[0071] The preferred specific embodiments of the present invention are described in detail above. It should be understood that a person skilled in the art can make many modifications and changes based on the concept of the present invention without creative work. Therefore, any technical solution that can be obtained by a person skilled in the art through logical analysis, reasoning or limited experiments based on the concept of the present invention on the basis of the prior art should be within the scope of protection determined by the claims.

Claims

1. A laser frame ranging method, characterized in that: The front-stage photoelectric conversion module converts the laser signal into an electrical signal, and then recovers the clock and parallel data through a phase-locked loop. The frame synchronization module performs frame synchronization on the parallel data according to the synchronization header, generates a frame header synchronization decision pulse and a synchronization delay, and the ranging frame information processing module extracts the ranging information of the sending time from the frame data center, and then uses the clock phase calculation module to calculate the phase difference between the recovered clock and the local clock. After the synchronization decision pulse arrives, the high-precision receiving time is calculated according to the phase difference and the synchronization delay. The data interaction module receives the sending time and the receiving time, calculates the ranging value, and hands it over to the subsequent host computer for further processing; The frame synchronization module performs shift synchronization according to the frame header, and after identifying the frame header, performs frame alignment on the parallel data, and generates a synchronization decision pulse and a synchronization delay, which are sent to the clock phase calculation module, wherein the synchronization decision pulse is used as a trigger signal, and the synchronization delay is used to compensate for the error caused by the synchronization module; the ranging information includes a second count and a ranging frame sending time, and the ranging frame processing module extracts the second count, processing delay, and the local ranging value of the opposite end from the ranging frame, and sends these data as the opposite end sending time to the data interaction module; the clock phase calculation module compares the local clock and the recovered clock through a high-frequency clock counter aligned with the local clock to calculate the phase difference; the high-frequency clock counter includes a frame count and a phase count, and the frame count is driven by the TX clock of the SERDES module, and the phase count includes a plurality of sub-counters, each of which works at the m-multiple frequency of the TX clock, and the working clock of each sub-counter has an equal phase difference; each of the sub-counters exists under each sub-clock, and counting is realized by a circular shift register.

2. A laser frame ranging method as claimed in claim 1, characterized in that: At each rising edge of the clock to be measured, the frame count value that has been Gray encoded and the sub-clock count value are tapped to the clock domain of the clock to be measured, and then Gray code decoding is performed. Then, the phase count value is calculated in the clock domain to be measured, the average of the phase count values ​​is obtained, and the frame count value is corrected by the phase count value.

3. A laser frame ranging method as claimed in claim 2, characterized in that: The phase count value includes the cumulative sum of several sub-counter count values, which is called alternately by at least two accumulators to eliminate accumulation and zeroing errors.

4. A laser frame ranging method as claimed in claim 3, characterized in that: The frame count value and the phase count value include the following three relationships: the phase count reset is basically synchronized with the frame count self-increment, the phase count reset lags behind the frame count self-increment, and the phase count reset is ahead of the frame count self-increment.

5. A laser frame ranging method as claimed in claim 4, characterized in that: The frame count value and the phase count value are calculated under the triggering of the synchronization decision pulse to obtain the receiving time. The receiving time needs to correct the value according to the three relationships.

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