A package including a substrate, an integrated device, and a package layer having an undercut

Abstract

A package includes: a substrate, an integrated device, a first encapsulation layer, and a void. The substrate includes a first surface. The integrated device is coupled to the first surface of the substrate. The first encapsulation layer is located over the first surface of the substrate and the integrated device. The first encapsulation layer includes an undercut with respect to a side surface of the integrated device. The void is located between the integrated device and the first surface of the substrate. The void is laterally surrounded by the undercut of the encapsulation layer.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority and the benefit of U.S. Non - Provisional Application No. 17 / 066,049, filed on October 8, 2020, and U.S. Provisional Application No. 63 / 032,177, filed on May 29, 2020, the contents of which are hereby expressly incorporated herein by reference in their entirety and for all applicable purposes as if fully set forth below. Technical Field

[0003] Various features relate to packages including a substrate and an integrated device, but more particularly to packages including a substrate, an integrated device, and a package layer. Background Art

[0004] Figure 1 Illustrated is a package 100 including a substrate 102 and an integrated device 104. The integrated device 104 is coupled to a first surface of the substrate 102 by a plurality of solder interconnects 140. The substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 121, a first solder mask layer 124, and a second solder mask layer 126. A plurality of solder interconnects 130 are coupled to a second surface of the substrate 102. The package 100 further includes a package layer 160 that encapsulates the integrated device 104. The process of forming the package layer 160 can cause at least a portion of the package layer 160 to flow beneath the integrated device 104 and form between the integrated device 104 and the substrate 102. For certain types of integrated devices, having a package layer 160 between the integrated device 104 and the substrate 102 may limit and / or impair the performance of the integrated device 104 and / or the package 100.

[0005] There is a continuing need to improve the performance of packages and integrated devices located within the packages. Summary of the Invention

[0006] Various features relate to packages including a substrate and an integrated device, but more particularly to packages including a substrate, an integrated device, and a package layer.

[0007] One example provides a package including: a substrate, an integrated device, a first package layer, and a void. The substrate includes a first surface. The integrated device is coupled to the first surface of the substrate. The first package layer is located over the first surface of the substrate and the integrated device. The first package layer includes an undercut relative to a side surface of the integrated device. The void is located between the integrated device and the first surface of the substrate. The void is laterally surrounded by the undercut of the package layer.

[0008] Another example provides an apparatus, comprising: a substrate, an integrated device, components for a first package, and a void. The substrate includes a first surface. The integrated device is coupled to the first surface of the substrate. The components for the first package are located over the first surface of the substrate and the integrated device. The components for the first package include an undercut relative to a side surface of the integrated device. The void is located between the integrated device and the first surface of the substrate. The void is laterally surrounded by the undercut of the components for the first package.

[0009] Another example provides a method for manufacturing a package. The method provides a substrate including a first surface. The method couples an integrated device to the first surface of the substrate. The method forms a first encapsulation layer over the first surface of the substrate and the integrated device. The first encapsulation layer includes an undercut relative to a side surface of the integrated device. Forming the first encapsulation layer forms a void located between the integrated device and the first surface of the substrate, wherein the void is laterally surrounded by the undercut of the first encapsulation layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Various features, properties, and advantages become apparent from the detailed description set forth below in conjunction with the drawings, in which like reference characters identify corresponding parts throughout the drawings.

[0011] Figure 1 A cross-sectional view of a package including a substrate and an integrated device is illustrated.

[0012] Figure 2 A cross-sectional view of a package including a substrate, an integrated device, and an encapsulation layer with a controlled undercut is illustrated.

[0013] Figure 3 A cross-sectional view of a package including a substrate, an integrated device, and an encapsulation layer with a controlled undercut is illustrated.

[0014] Figure 4 A close-up view of a package including a substrate, an integrated device, and an encapsulation layer with a controlled undercut is illustrated.

[0015] Figure 5 A cross-sectional view of another package including a substrate, an integrated device, and an encapsulation layer with a controlled undercut is illustrated.

[0016] Figure 6 A cross-sectional view of another package including a substrate, an integrated device, and an encapsulation layer with a controlled undercut is illustrated.

[0017] Figure 7 A cross-sectional view of another package including a substrate, an integrated device, and an encapsulation layer with a controlled undercut is illustrated.

[0018] Figure 8 A cross-sectional view of another package including a substrate, an integrated device, and an encapsulation layer with a controlled undercut is illustrated.

[0019] Figure 9 A cross - sectional view of another package including a substrate, an integrated device, and a package layer with a controlled undercut is illustrated.

[0020] Figure 10 A cross - sectional view of another package including a substrate, an integrated device, and a package layer with a controlled undercut is illustrated.

[0021] Figure 11 A cross - sectional view of another package including a substrate, a stacked device, and a package layer with a controlled undercut is illustrated.

[0022] Figure 12 A cross - sectional view of another package including a substrate, a stacked device, and a package layer with a controlled undercut is illustrated.

[0023] Figures 13A - 13D An exemplary sequence for manufacturing a die including a frame is illustrated.

[0024] Figure 14 An exemplary flow chart of a method for manufacturing a package including a substrate, an integrated device, and a package layer with a controlled undercut is illustrated.

[0025] Figures 15A - 15C An exemplary sequence for manufacturing a substrate is illustrated.

[0026] Figures 16A - 16B An exemplary sequence for manufacturing a device including stacked integrated devices is illustrated.

[0027] Figures 17A - 17B An exemplary sequence for manufacturing a device including stacked integrated devices is illustrated.

[0028] Figure 18 Various electronic devices that can integrate the die, integrated device, integrated passive device (IPD), passive component, package, and / or device package described herein are illustrated. Detailed Description

[0029] In the following description, specific details are given to provide a thorough understanding of various aspects of the present disclosure. However, one of ordinary skill in the art will understand that the aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring the aspects with unnecessary details. In other instances, well - known circuits, structures, and techniques may not be shown in detail to avoid obscuring the aspects of the present disclosure.

[0030] The present disclosure describes a package that includes a substrate, an integrated device, a first encapsulation layer, and a void. The substrate includes a first surface. The integrated device is coupled to the first surface of the substrate. The first encapsulation layer is located over the first surface of the substrate and the integrated device. The first encapsulation layer includes an undercut with respect to a side surface of the integrated device. The first encapsulation layer may have a uniform thickness over a top surface and the side surface of the integrated device. The void is located between the integrated device and the first surface of the substrate. The void is laterally surrounded by the undercut of the first encapsulation layer. A second encapsulation layer may be formed and located over the first encapsulation layer. The package may be without a foil (e.g., an adhesive foil, a glue foil) and / or a sealing film between the integrated device and the first encapsulation layer, which helps to reduce the manufacturing cost of the package. Using the first encapsulation layer and the second encapsulation layer may help to provide a package with an encapsulation layer having a controllable undercut, which can more accurately and precisely control the void between the integrated device and the substrate. The integrated device may be configured as a filter. Additionally, materials used for the substrate and the (multiple) encapsulation layers may be selected such that a coefficient of thermal expansion (CTE) mismatch between the substrate and the rest of the package is minimized, thereby providing a more robust and reliable package.

[0031] Exemplary package including a substrate, an integrated device, and an encapsulation layer with a controllable undercut

[0032] Figure 2 FIG. shows a cross-sectional view of a package 200 that includes a substrate 202, an integrated device 204, an integrated device 206, an encapsulation layer 207, an encapsulation layer 209, and an electromagnetic interference (EMI) shield 250. In some implementations, the package 200 may be an integrated circuit (IC) package, such as a system-in-package (SiP) or a chip-scale package (CSP). In some implementations, the package 200 may be configured as a radio frequency front-end (RFFE) package that includes a radio frequency (RF) filter.

[0033] The substrate 202 includes at least one dielectric layer 220, a plurality of interconnects 221 (e.g., traces, pads, vias), a solder mask layer 224, and a solder mask layer 226. The solder mask layer 224 may be formed and located over a first surface of the at least one dielectric layer 220. The solder mask layer 226 may be formed and located over a second surface of the at least one dielectric layer 220. The substrate 202 may be a coreless substrate, a laminated substrate, or a substrate that includes a core layer. The at least one dielectric layer 220 may include different materials, such as a prepreg layer, polyimide (e.g., a photo-etchable dielectric layer), an organic layer, and / or a ceramic. A plurality of solder interconnects 230 are coupled to the plurality of interconnects 221 through a second surface (e.g., a bottom surface) of the substrate 202.

[0034] The integrated device 204 is coupled to the first surface (e.g., the top surface) of the substrate 202 via a plurality of solder interconnects 240. A void 242 is located between the integrated device 204 and the first surface of the substrate 202. The integrated device 206 is coupled to the first surface (e.g., the top surface) of the substrate 202 via a plurality of solder interconnects 260. A void 262 is located between the integrated device 206 and the first surface of the substrate 202. The voids (e.g., 242, 262) can be at least one region without solid material. The voids can include cavities. The voids can be occupied by a gas (e.g., air).

[0035] The integrated device (e.g., 204, 206) can include a die (e.g., a semiconductor die). The integrated device can include radio frequency (RF) devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon carbide (SiC)-based integrated devices, GaAs-based integrated devices, GaN-based integrated devices, processors, memories, and / or combinations thereof. The integrated device (e.g., 204, 206) can include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc...).

[0036] For example, when the integrated device (e.g., 204, 206) is configured as a semiconductor integrated circuit die, the integrated device can include a substrate and a device layer that includes transistors configured to perform operations (e.g., logic operations). In another example, when the integrated device (e.g., 204, 206) is configured as a die filter (e.g., a SAW filter, a BAW filter), the integrated device can include a piezoelectric substrate and at least one metal layer formed on and located above the piezoelectric substrate, the at least one metal layer being configured as at least one transducer (e.g., an interdigital transducer (IDT)). Examples of die filters are further illustrated and described at least in Figure 11 , Figure 12 , Figures 16A - 16B and Figures 17A - 17B When the integrated device is configured as a filter, the voids between the integrated device and the substrate can help improve the performance of the integrated device configured as a filter.

[0037] Figure 2 It is illustrated that the encapsulation layer 207 is coupled to, formed on, and located above the first surface of the substrate 202, the integrated device 204, and the integrated device 206 such that (i) the void 242 is located between the integrated device 204 and the substrate 202, and (ii) the void 262 is located between the integrated device 206 and the substrate 202. Figure 2Illustrated is that the encapsulation layer 207 has a neutral undercut with the sidewall or side surface of the integrated device. The undercut of the encapsulation layer describes (and / or quantifies) the position of the encapsulation layer (or a part of the encapsulation layer) relative to the void under the component (e.g., the integrated device) and relative to another reference point (e.g., a vertical line aligned with the sidewall or side surface of the integrated device). The undercut of the encapsulation layer can describe and / or quantify how far the encapsulation layer is located in the void under the integrated device, or how far the encapsulation layer is from the void under the integrated device. The neutral undercut may mean that the encapsulation layer 207 can be vertically aligned with the sidewall or side surface of the integrated device (e.g., 204, 206) located above the void. However, as will be further described at least in Figure 3 and Figure 4 below, the encapsulation layer 207 can have a positive undercut or a negative undercut with the integrated device. The undercut value of the encapsulation layer can range between approximately -20 micrometers (μm) and 50 micrometers (μm). A negative undercut value may mean that the encapsulation layer is positioned away from the integrated device and away from an imaginary line (or reference) that extends vertically from the side surface or sidewall of the integrated device. A positive undercut value may mean that the encapsulation layer is located under the integrated device, towards the void under the integrated device, and away from an imaginary line that extends vertically from the side surface or sidewall of the integrated device located above the void. However, the positive undercut and the negative undercut can be defined differently. The undercut value can represent the maximum undercut value (e.g., how far from the imaginary line (or reference) is the farthest part of the encapsulation layer). For an integrated device with multiple sides, each side of the integrated device may have a corresponding undercut. That is, for each side of the integrated device, the encapsulation layer can have an undercut value. The undercut values for each side of the integrated device can be different or the same. In some implementations, at least one side of the integrated device can have a variable undercut value.

[0038] As Figure 2 shown, each void under the corresponding integrated device is laterally surrounded by the corresponding undercut of the encapsulation layer 207 defined by the corresponding integrated device. For example, the void 242 is laterally surrounded by at least one undercut of the encapsulation layer 207 defined by the side surface of the integrated device 204. Similarly, the void 262 is laterally surrounded by at least one undercut of the encapsulation layer 207 defined by the side surface of the integrated device 206.

[0039] The present disclosure describes a package that has an accurately and precisely controlled undercut for the encapsulation layer near at least one void located between the integrated device and the substrate, which may result in better performance from the integrated device and / or the package because the area between the integrated device and the substrate is not blocked by the encapsulation layer.

[0040] The encapsulation layer 207 can be a first encapsulation layer (e.g., for components of a first encapsulation). The encapsulation layer 207 can include a mold, resin, and / or epoxy resin. The encapsulation layer 207 can include isotropic materials and / or anisotropic materials. As will be further described below, a sheet molding process (e.g., vacuum lamination, compression molding) can be used to form the encapsulation layer 207.

[0041] The encapsulation layer 207 is formed over the substrate 202, the integrated device 204, and the integrated device 206 such that the encapsulation layer 207 has a generally uniform thickness because the encapsulation layer 207 generally follows the contours of the substrate 202, the integrated device 204, and / or the integrated device 206. The first encapsulation layer 207 can have a uniform thickness over the top surface and / or side surface of the integrated device 204, and / or over the top surface and / or side surface of the integrated device 206. In some implementations, the thickness of the first encapsulation layer 207 over the side surface(s) of the integrated device(s) 204 and / or 207 can be thinner than the thickness over the top surface(s) of the integrated device(s) 204 and / or 207. It should be noted that a uniform thickness does not necessarily mean that the encapsulation layer has exactly the same thickness everywhere. As used in this disclosure, a uniform thickness means that the thickness of a component (e.g., the encapsulation layer) is generally the same within a certain tolerance. For example, a uniform thickness can mean that the thickness is the same within a certain percentage of the average thickness of the material. For example, if the encapsulation layer 207 has an average thickness (Tavg), then the encapsulation layer 207 can be considered to have a uniform thickness if the thickness at any part of the encapsulation layer 207 is 10% or less (e.g., 5% or less) of the average thickness (Tavg) of the encapsulation layer 207. In another example, a component (e.g., the encapsulation layer) can have a uniform thickness when the difference between the thickest part and the thinnest part of the component (e.g., the encapsulation layer) is 16 micrometers (μm) or less. In some implementations, the encapsulation layer 207 can have a thickness of approximately 80 micrometers (μm) ± 8 micrometers (μm). However, different implementations can use an encapsulation layer 207 with different uniform thicknesses. The uniform thickness of the encapsulation layer 207 can apply to the portions of the surface of the encapsulation layer 207 that contact components (e.g., integrated devices, substrates). In some implementations, the uniformity of the encapsulation layer 207 may not apply to the portions of the encapsulation layer 207 adjacent to voids. The sheet molding process can allow for accurate and precise control of the undercuts of the encapsulation layer 207 near the integrated devices located over voids, which in turn allows for accurate and precise control of the voids (e.g., 242, 262) between the integrated devices and the substrate.

[0042] The encapsulation layer 207 can be provided and formed without the need for a foil and / or a sealing film that follows the contours of the substrate 202, the integrated device 204, and the integrated device 206. This can be achieved by using a sheet mold for the encapsulation layer 207 having a low viscosity value such that the encapsulation layer 207 will not substantially flow under the (multiple) integrated devices. For example, for a temperature range of 60°C - 140°C, the viscosity value of the encapsulation layer 207 can be between 0.01 - 100 mPa·s (millipascal seconds). Thus, Figure 2 And other figures of the present disclosure illustrate an encapsulation without a sealing film between the encapsulation layer 207 and the substrate 202, the integrated device 204, and the integrated device 206. One advantage of a foil-less or sealing-film-less encapsulation is that the manufacturing cost of the encapsulation is lower because there is at least one less step and at least one less material.

[0043] The encapsulation layer 209 is coupled to, formed on, and located on top of the encapsulation layer 207. The encapsulation layer 209 can be a second encapsulation layer (e.g., for a second encapsulation component). The encapsulation layer 209 can include a mold, a resin, and / or an epoxy resin. The encapsulation layer 209 can include an isotropic material and / or an anisotropic material. The encapsulation layer 209 can include a material different from that of the encapsulation layer 207. The encapsulation layer 209 can have at least one property different from that of the encapsulation layer 207. For example, the encapsulation layer 209 can have a different coefficient of thermal expansion (CTE) from that of the encapsulation layer 207. In some implementations, the encapsulation layer 209 can have a CTE higher / larger than that of the encapsulation layer 207 (e.g., 33 parts per million (ppm)). In some implementations, the encapsulation layer 209 can have a CTE smaller / lower than that of the encapsulation layer 207. A compression molding process, a transfer molding process, or a liquid molding process can be used to form the encapsulation layer 209. The encapsulation layer 209 can be photo-etched. There can be a boundary interface between the encapsulation layer 209 and the encapsulation layer 207. In addition, in addition to the molding process, the encapsulation layer 209 can also be laminated with the encapsulation layer 207 to form a single piece. This single piece including the encapsulation layer 207 and the encapsulation layer 209 can be applied to the substrate 202, the integrated device 204, and the integrated device 206 via vacuum lamination or compression molding.

[0044] The EMI shield 250 can be coupled to, formed on, and located on the side portions of the encapsulation layer 209 and the substrate 202. The EMI shield 250 can include a conductive layer. The EMI shield 250 can be configured to be coupled to ground. For example, the EMI shield 250 can be configured to be electrically coupled to a ground interconnect (e.g., a ground interconnect from the substrate 202). The EMI shield 250 can be a component for electromagnetic interference (EMI) shielding.

[0045] To increase and improve the reliability of package 200 (or any package described in this disclosure), the designs of the various components of package 200 can be selected such that the maximum CTE mismatch between substrate 202 and the remainder of package 200 is 15 parts per million per Kelvin (ppm / K) or less. For example, the maximum difference between the effective CTE of substrate 202 (e.g., substrate CTE) and the effective and collective CTE of the (multiple) integrated devices (e.g., 204, 206), the solder interconnects (e.g., 240, 260) coupling the (multiple) integrated devices, package layer 207, package layer 209, and / or EMI shield 250 can be about 15 ppm / K or less. Thus, substrate 202 can have a substrate CTE within about 15 ppm / K of the effective CTE of the remainder of package 200. The substrate CTE of substrate 202 can represent the effective and collective CTE of at least one dielectric layer 220, multiple interconnects 221, solder mask layer 224, and / or solder mask layer 226. In some implementations, the substrate CTE of substrate 202 can be in the range of about 5 - 20 parts per million per Kelvin (ppm / K).

[0046] Figure 3 Illustrated is a package 300 that includes a package layer that includes a positive undercut and a negative undercut. Package 300 is similar to Figure 2 package 200 and includes components similar or identical to those of package 200. Figure 3 Illustrated is that package layer 207 includes a positive undercut 304 and a negative undercut 306. Figure 4 Illustrated is a close-up view of package 300. As Figure 4 shown, package layer 207 can be formed such that package layer 207 has a positive undercut 304 relative to integrated device 204 and void 242 and a negative undercut relative to integrated device 206 and void 262. However, it should be noted that package layer 207 can have a positive undercut, a neutral undercut, and / or a negative undercut with respect to the integrated device. For example, package layer 207 can have a positive undercut on one side of the integrated device and a negative undercut on the other side of the integrated device. In some implementations, package layer 207 can have a variable undercut with respect to the integrated device. In some implementations, one side of package layer 207 can have a positive undercut, a neutral undercut, and / or a negative undercut. As mentioned above, the undercut value of package layer 207 near the integrated device located above the void can be in the range of -20 - 50 micrometers (μm) (e.g., a range between negative 20 micrometers and positive 50 micrometers). Thus, package layer 207 can have a negative undercut, a neutral undercut, a positive undercut, or a combination thereof with respect to at least one integrated device (e.g., 204, 206). The undercut value can represent the maximum undercut value (e.g., how far from an imaginary line is the farthest part of the package layer). At least a portion of package layer 207 can have a uniform thickness, as Figure 2 described.

[0047] Figure 5 Illustrated is a package 500 including a package layer having various undercuts. The package 500 is similar to Figure 3 package 300 and includes components similar or identical to those of package 300. Package 500 also includes an integrated device 506, a package layer 509, and a plurality of solder interconnects 560. The integrated device 506 is coupled to a second surface (e.g., bottom surface) of the substrate 202 via the plurality of solder interconnects 560. The package layer 509 is located over and coupled to the second surface of the substrate 202. The package layer 509 encapsulates portions of the integrated device 506 and the plurality of solder interconnects 230. The package layer 509 may be similar to package layer 207 and / or package layer 209. The package layer 509 may be a third package layer (e.g., a component for a third package). The package layer 509 may include a mold, a resin, and / or an epoxy resin. A compression molding process, a transfer molding process, or a liquid molding process may be used to form the package layer 509. The package layer 509 may be photo-etched.

[0048] The effective collective CTE of the integrated device 506, the package layer 509, the plurality of solder interconnects 560, and the plurality of solder interconnects 230 may be selected such that the maximum CTE mismatch with the substrate 202 is 15 ppm / K or less. At least a portion of the package layer 207 may have a uniform thickness, as Figure 2 described in

[0049] Figure 6 Illustrated is a package 600 including a package layer that includes various undercuts. The package 600 is similar to Figure 5 package 500 and includes components similar or identical to those of package 500. Package 600 also includes an integrated device 606, a void 662, and a substrate 202 including a cavity. The void 662 is located between the integrated device 206 and the substrate 202. The void 662 may include a cavity in the substrate 202. The integrated device 606 is located in the cavity of the substrate 202. The integrated device 606 is coupled to the substrate 202 via a plurality of solder interconnects 660. The back side of the integrated device 606 faces the front side of the integrated device 206. Similar to other packages in this disclosure, for various integrated devices located over the void, the package layer 207 may have an undercut value in the range of -20 - 50 micrometers (μm). For integrated devices (e.g., 204, 206) located over the void, the (multiple) undercut values of the package layer 207 may be variable. At least a portion of the package layer 207 may have a uniform thickness, as Figure 2 described in

[0050] Figure 7 Illustrated is a package 700 including a package layer that includes various underlying layers. The package 700 is similar toFigure 6 package 600, and includes components similar or identical to those of package 600. Package 700 includes integrated device 706, integrated device 606, void 662, and substrate 202 including a cavity. Integrated device 706 is located within void 662. Integrated device 706 is coupled to integrated device 206 (e.g., in a face-to-face configuration). The back side of integrated device 606 faces the back side of integrated device 706. Similar to other packages in this disclosure, for various integrated devices located above the void, the encapsulation layer 207 may have an undercut value in the range of -20 - 50 micrometers (μm). The (multiple) undercut values of encapsulation layer 207 for the integrated devices may be variable. At least a portion of encapsulation layer 207 may have a uniform thickness, as Figure 2 described in

[0051] Figure 8 FIG. illustrates package 800 including an encapsulation layer that includes various undercuts. Package 800 is similar to Figure 6 package 600, and includes components similar or identical to those of package 600. Package 800 includes passive device 806, void 662, and substrate 202 including a cavity. Void 662 is located between integrated device 206 and substrate 202. Void 662 may include a cavity in substrate 202. Passive device 806 is located within the cavity of substrate 202. Passive device 806 is coupled to substrate 202 by a plurality of solder interconnects 660. Passive device 806 may be a capacitor (e.g., a surface-mounted capacitor). Similar to other packages of this disclosure, for various integrated devices located above the void, the encapsulation layer 207 may have an undercut value in the range of -20 - 50 micrometers (μm). The (multiple) undercut values of encapsulation layer 207 for the integrated devices may be variable. At least a portion of encapsulation layer 207 may have a uniform thickness, as Figure 2 described in

[0052] Figure 9 FIG. illustrates package 900 including an encapsulation layer that includes various undercuts. Package 900 is similar to Figure 6package 600, and includes components similar or identical to those of package 600. Package 900 includes integrated device 906, integrated device 606, void 662, and substrate 202 including a cavity. Integrated device 906 is located within void 662. Integrated device 906 is coupled to integrated device 606 (e.g., in a front-to-back configuration) by a plurality of solder interconnects 960. The back side of integrated device 906 faces the front side of integrated device 206. Similar to other packages in the present disclosure, for various integrated devices located above the void, the encapsulation layer 207 may have an undercut value in the range of -20 - 50 micrometers (μm). The (multiple) undercut values of the encapsulation layer 207 for the integrated devices may be variable. At least a portion of the encapsulation layer 207 may have a uniform thickness, as Figure 2 described in

[0053] Figure 10 FIG. shows package 1000 including an encapsulation layer that includes various undercuts. Package 1000 is similar to Figure 6 package 600, and includes components similar or identical to those of package 600. Package 1000 includes integrated device 1006, void 662, and substrate 202 including a cavity. Integrated device 1006 is located within void 662. Integrated device 1006 is coupled to integrated device 206 (e.g., in a front-to-front configuration) by a plurality of solder interconnects 1060. The back side of integrated device 1006 is coupled to substrate 202 by an adhesive 1005. Similar to other packages in the present disclosure, for various integrated devices located above the void, the encapsulation layer 207 may have an undercut value in the range of -20 - 50 micrometers (μm). The undercut value of the encapsulation layer 207 for the integrated devices may be variable. At least a portion of the encapsulation layer 207 may have a uniform thickness, as Figure 2 described in

[0054] Figure 11 FIG. shows package 1100 including an encapsulation layer that includes various undercuts. Package 1100 is similar to Figure 6Package 600, and includes components similar or identical to Package 600. Package 1100 includes stacked device 1104, void 1162, and substrate 202 including a cavity. Stacked device 1104 may include stacked filters. Stacked device 1104 includes first integrated device 1114 configured as a first filter (e.g., a first signal filtering component), second integrated device 1116 configured as a second filter (e.g., a second signal filtering component), polymer frame 1118, and a plurality of interconnects 1119. First integrated device 1114 may be a top filter, and second integrated device 1116 may be a bottom filter. First integrated device 1114 is coupled to a first surface of polymer frame 1118. Second integrated device 1116 is coupled to a second surface of polymer frame 1118. Void 1120 may be located between first integrated device 1114, second integrated device 1116, and polymer frame 1118. A plurality of interconnects 1119 may be located on surfaces of first integrated device 1114, polymer frame 1118, and second integrated device 1116. Stacked device 1104 is coupled to substrate 202 via a plurality of solder interconnects 1140. At least a portion of stacked device 1104 is located in the cavity of substrate 202. Void 1162 includes the cavity of substrate 202.

[0055] A package layer 207 is formed over substrate 202, integrated device 204, and stacked device 1104 such that package layer 207 has a generally uniform thickness as package layer 207 generally follows the contours of substrate 202, integrated device 204, and stacked device 1104. First package layer 207 may have a uniform thickness over the top and side surfaces of stacked device 1104, and / or over the top and side surfaces of integrated device 1114. Package layer 207 may have a thickness of approximately 80 micrometers (μm) ± 8 micrometers (μm). The undercut of package layer 207 of stacked device 1104 may be defined relative to the side surface or sidewall of first integrated device 1114. Similar to other packages of the present disclosure, for various devices located over a void, package layer 207 may have an undercut value in the range of -20 - 50 micrometers (μm). The (multiple) undercut values of package layer 207 for an integrated device and / or a stacked device may be variable. At least a portion of package layer 207 may have a uniform thickness, as Figure 2 described.

[0056] Figure 12 illustrates Package 1200 including a package layer that includes various undercuts. Package 1200 is similar to Figure 11Package 1100, and includes components similar or identical to package 1100. Package 1200 includes stacked device 1204, void 1162, and substrate 202 including a cavity. Stacked device 1204 may include stacked filters. Stacked device 1204 includes first integrated device 1114 configured as a first filter (e.g., a component for first signal filtering), second integrated device 1116 configured as a second filter (e.g., a component for second signal filtering), interconnect frame 1218, and a plurality of interconnects 1219. First integrated device 1114 may be a top filter, and second integrated device 1116 may be a bottom filter. First integrated device 1114 is coupled to interconnect frame 1218. Second integrated device 1116 is coupled to interconnect frame 1218. Void 1120 may be located between first integrated device 1114, second integrated device 1116, and interconnect frame 1218. A plurality of interconnects 1219 may be located in and on second integrated device 1116. The plurality of interconnects 1219 may include vias, wires, and / or pads. Stacked device 1204 is coupled to substrate 202 by a plurality of solder interconnects 1140. At least a portion of stacked device 1124 is located in the cavity of substrate 202. Void 1162 includes the cavity of substrate 202.

[0057] A package layer 207 is formed over substrate 202, integrated device 204, and stacked device 1204 such that the package layer 207 has a generally uniform thickness as the package layer 207 generally follows the contours of substrate 202, integrated device 204, and stacked device 1204. First package layer 207 may have a uniform thickness over the top and side surfaces of stacked device 1204, and / or over the top and side surfaces of integrated device 1114. Package layer 207 may have a thickness of about 80 micrometers (μm) ± 8 micrometers (μm). The undercut of package layer 207 of stacked device 1204 may be defined relative to the side surface or sidewall of first integrated device 1114. Similar to other packages of the present disclosure, for various devices located over a void, package layer 207 may have an undercut value in the range of -20 - 50 micrometers (μm). The (multiple) undercut values of package layer 207 for the integrated device and / or stacked device may be variable. At least a portion of package layer 207 may have a uniform thickness, as Figure 2 described.

[0058] Note that the various features in one package can be implemented in any package described in this disclosure. The undercuts shown for the encapsulation layer are exemplary. Different implementations of the package can include encapsulation layers with different and / or varying undercuts, including positive undercuts, negative undercuts, neutral undercuts, or combinations thereof. The range of undercut values is exemplary. Different implementations can have different numerical undercuts. The encapsulation layer surrounding the integrated device can have the same or different undercut values for different sides of the integrated device. Any integrated device and / or device illustrated and described in this disclosure can be surrounded by at least one encapsulation layer such that all sides of the integrated device and / or device can be surrounded by at least one encapsulation layer. All sides of the integrated device and / or device can be surrounded by the encapsulation layer such that for each specific side of the integrated device and / or device, the encapsulation layer can have a specific undercut value within the range of -20 - 50 micrometers (μm).

[0059] The various configurations of the packages shown in this disclosure can provide different technical advantages, including lower manufacturing costs, improved reliability (e.g., through better CTE mismatch), and improved performance (e.g., through reduced wiring paths between components, better defined voids).

[0060] After describing the various packages, a sequence for manufacturing the packages will now be described hereinafter.

[0061] Exemplary sequence for manufacturing a package including an encapsulation layer with a controlled undercut

[0062] Figures 13A - 13D An exemplary sequence for providing or manufacturing a package including an encapsulation layer with a controlled undercut is illustrated. In some implementations, Figures 13A - 13D the sequence can be used to provide or manufacture Figure 6 package 600 or any device described in this disclosure (e.g., 200, 300, 500, 700, 800, 900, 1000, 1100, 1200).

[0063] It should be noted that Figures 13A - 13D the sequence can incorporate one or more stages in order to simplify and / or clarify the sequence for providing or manufacturing the package. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more processes can be replaced or substituted without departing from the spirit of this disclosure.

[0064] As Figure 13A shown in, stage 1 illustrates the state after providing or manufacturing substrate 202. Substrate 202 includes at least one dielectric layer 220, a plurality of interconnects 222 (e.g., wires, pads, vias), cavity 1310, solder mask layer 224, and solder mask layer 226. Figures 15A - 15BExamples of manufacturing a substrate are shown and described. The manufacturing of the substrate may include a lamination process and an electroplating process. Examples of the process of manufacturing a substrate include a semi-additive process (SAP) and a modified semi-additive process (mSAP). However, different implementations may manufacture the substrate in different ways. Different implementations may provide different types of substrates (e.g., a coreless substrate, a laminated substrate).

[0065] Stage 2 illustrates the state after the integrated device 606 is coupled to the substrate 202 through a plurality of solder interconnects 660. The integrated device 606 may be placed in the cavity 1310 of the substrate 202 through a pick-and-place process. The integrated device 606 may be coupled to the plurality of interconnects 221 through a plurality of solder interconnects 660 using a reflow soldering process.

[0066] As Figure 13B shown, Stage 3 illustrates the state after the integrated device 204 is coupled to the first surface of the substrate 202 through a plurality of solder interconnects 240 and the integrated device 206 is coupled to the first surface of the substrate 202 through a plurality of solder interconnects 260. The integrated devices 204 and 206 may be placed on the first surface of the substrate 202 through a pick-and-place process. The integrated device 204 may be coupled to the plurality of interconnects 221 through a plurality of solder interconnects 240, and the integrated device 206 may be coupled to the plurality of interconnects 221 through a plurality of solder interconnects 260 using a reflow soldering process.

[0067] Stage 4 illustrates the state after a package layer 207 is formed over the substrate 202, the integrated device 204, and the integrated device 206. The package layer 207 may be a first package layer (e.g., a component for a first package). The package layer 207 may include a mold, a resin, and / or an epoxy resin. The package layer 207 may include an isotropic material and / or an anisotropic material. The package layer 207 may be formed using a sheet molding process (e.g., vacuum lamination, compression molding). For each integrated device, the package layer 207 may have an undercut value in the range of -20 - 50 micrometers (μm). The undercut value of the package layer 207 for the integrated device and / or the stacked device may be variable.

[0068] A package layer 207 is formed over a substrate 202, integrated device 204, and integrated device 206 such that the package layer 207 has a generally uniform thickness as the package layer 207 generally follows the contours of the substrate 202, integrated device 204, and integrated device 206. For example, the package layer 207 may have a thickness of approximately 80 micrometers (μm) ± 8 micrometers (μm). A sheet molding process may allow for accurate and precise control of undercuts of the package layer 207, which in turn allows for accurate and precise control of the voids (such as 242, 262, 662) between the integrated devices and the substrate. The package layer 207 may be formed without an aluminum foil and / or a sealing film that follows the contours of the substrate 202, integrated device 204, and integrated device 206. This may be accomplished by using a sheet mold for the package layer 207 having a low viscosity value such that the package layer 207 does not substantially flow under the integrated devices. Thus, a package may be manufactured that does not have a foil and / or a sealing film between the package layer 207 and the substrate 202, integrated device 204, and integrated device 206. One advantage of a foil-less package or a sealing-film-less package is that the manufacturing cost of the package is lower as there is at least one less step and at least one less material.

[0069] As Figure 13C shown in Phase 5 illustrates the state after a package layer 209 is formed over the package layer 207. The package layer 209 may be formed using a compression molding process, a transfer molding process, or a liquid molding process. The package layer 209 may be photo-etched. There may be a boundary interface between the package layer 209 and the package layer 207. The package layer 209 may include a mold, a resin, and / or an epoxy resin. Additionally, in addition to the molding process, the package layer 209 may be laminated with the package layer 207 to form a single piece. This single piece including the package layer 207 and the package layer 209 may be applied to the substrate 202, integrated device 204, and integrated device 206 via vacuum lamination or compression molding.

[0070] Phase 6 illustrates the state after an integrated device 506 is coupled to the second surface of the substrate 202 via a plurality of solder interconnects 560. The integrated device 506 may be placed on the second surface of the substrate 202 via a pick-and-place process. A reflow soldering process may be used to couple the integrated device 506 to the plurality of interconnects 221 via the plurality of solder interconnects 560. Phase 6 also illustrates a plurality of solder interconnects 230 coupled to the substrate 202. The plurality of solder interconnects 230 may be coupled to the substrate 202 using a reflow soldering process.

[0071] Phase 7, as Figure 13DAs shown, the state after forming the encapsulation layer 509 over the second surface of the substrate 202 is illustrated. The encapsulation layer 509 can be formed using a compression molding process, a transfer molding process, or a liquid molding process. The encapsulation layer 509 can be photo-etched. The encapsulation layer 509 can include a mold, a resin, and / or an epoxy resin. The encapsulation layer 509 can encapsulate the integrated device 506 and portions of the plurality of solder interconnects 230. In some implementations, the encapsulation layer 509 can be located over the back side of the integrated device 506.

[0072] Stage 8 illustrates the state after the EMI shield 250 is formed and located over the surface of the encapsulation layer 209 and the side surface of the substrate 202. The EMI shield 250 can be formed using a sputtering process, a spray coating, and / or an electroplating process. The EMI shield 250 can include a conductive layer. The EMI shield 250 can be configured to be coupled to ground. Stage 8 may illustrate Figure 6 the encapsulation 600.

[0073] Exemplary flowchart of a method for manufacturing an encapsulation including an encapsulation layer with a controlled undercut

[0074] In some implementations, manufacturing an encapsulation with an encapsulation layer having a controlled undercut includes several processes. Figure 14 Illustrated is an exemplary flowchart of a method 1400 for providing or manufacturing an encapsulation including an encapsulation layer with a controlled undercut. In some implementations, Figure 14 the method 1400 can be used to provide or manufacture the Figure 6 encapsulation 600 described in the present disclosure. However, the method 1400 can be used to provide or manufacture any device (e.g., 200, 300, 500, 700, 800, 900, 1000, 1100, 1200) described in the present disclosure.

[0075] It should be noted that Figure 14 the sequence can be combined with one or more processes in order to simplify and / or clarify the method of providing or manufacturing an encapsulation. In some implementations, the order of the processes can be changed or modified.

[0076] The method (at 1405) provides a substrate (e.g., 202). The substrate can be provided or manufactured. The substrate can include at least one dielectric layer 220, a plurality of interconnects 222 (e.g., wires, pads, vias), a cavity 1310, a solder mask layer 224, and a solder mask layer 226. Figures 15A - 15B Examples of manufacturing a substrate are shown and described. The manufacturing of the substrate can include a lamination process and an electroplating process. Examples of processes for manufacturing a substrate include a semi-additive process (SAP) and a modified semi-additive process (mSAP). However, different implementations can manufacture the substrate in different ways. Different implementations can provide different types of substrates (e.g., a coreless substrate, a laminated substrate).Figure 13A Stage 1 depicts and describes an example of a substrate.

[0077] The method (at 1410) couples at least one device (e.g., 204, 206, 606) to a substrate (e.g., 202). The device can be placed in a cavity of the substrate. The device can be coupled to a first surface of the substrate. A pick-and-place process can be used to place and couple the device(s) to the substrate. Figures 13A - 13B Stages 2 and 3 depict and describe examples of devices coupled to a substrate.

[0078] The method (at 1415) forms a package layer (e.g., 207) over a first surface of the substrate 202 and devices (e.g., 204, 206). The package layer 207 can be a first package layer (e.g., for components of a first package). The package layer 207 can include a mold, resin, and / or epoxy. The package layer 207 can include isotropic materials and / or anisotropic materials. A sheet molding process (e.g., vacuum lamination, compression molding) can be used to form the package layer 207. For each integrated device, the package layer 207 can have an undercut value in the range of -20 - 50 micrometers (μm). The undercut value of the package layer 207 for integrated devices and / or stacked devices can be variable.

[0079] A package layer 207 is formed (e.g., placed) over the substrate 202, integrated device 204, and integrated device 206 such that the package layer 207 has a substantially uniform thickness as the package layer 207 generally follows the contours of the substrate (e.g., 202) and devices (e.g., 204, 206). For example, the package layer 207 can have a thickness of approximately 80 micrometers (μm) ± 8 micrometers (μm). The sheet molding process can allow for accurate and precise control of the undercut of the package layer 207, which in turn allows for accurate and precise control of the voids (such as 242, 262, 662) between the devices and the substrate. The package layer 207 can be formed without an aluminum foil and / or a sealing film that follows the contours of the substrate 202, integrated device 204, and integrated device 206. This can be accomplished by using a sheet mold for the package layer 207 having a low viscosity value such that the package layer 207 does not substantially flow under the integrated device(s). Figure 13C Stage 4 depicts and describes an example of a package layer formed over a substrate and at least one device.

[0080] The method (at 1420) forms a second encapsulation layer (e.g., 209) over a first encapsulation layer (e.g., 207). A compression molding process, a transfer molding process, or a liquid molding process can be used to form encapsulation layer 209. Encapsulation layer 209 can be photoetched. A boundary interface can exist between encapsulation layer 209 and encapsulation layer 207. Encapsulation layer 209 can include a mold, a resin, and / or an epoxy resin. Figure 13C Stage 5 of [description] illustrates and describes an example of a second encapsulation layer formed over a first encapsulation layer.

[0081] The method (at 1425) couples at least one device (e.g., 506) and a plurality of solder interconnects (e.g., 560) to a second surface (e.g., bottom surface) of a substrate (e.g., 202). A pick-and-place process and a reflow soldering process can be used to couple integrated device 506 to substrate 202. The reflow soldering process can be used to couple a plurality of solder interconnects 230 to substrate 202. Figure 13C Stage 6 of [description] illustrates and describes an example of a device and solder interconnects coupled to a substrate.

[0082] The method (at 1430) forms an encapsulation layer (e.g., 509) over the second surface of substrate 202. A compression molding process, a transfer molding process, or a liquid molding process can be used to form encapsulation layer 509. Encapsulation layer 509 can be photoetched. Encapsulation layer 509 can include a mold, a resin, and / or an epoxy resin. Encapsulation layer 509 can encapsulate portions of integrated device 506 and a plurality of solder interconnects 230. Figure 13D Stage 7 of [description] illustrates and describes an example of an encapsulation layer formed over the second surface of a substrate.

[0083] The method (at 1435) forms an EMI shield (e.g., 250) over the surface of encapsulation layer 209 and the side surface of substrate 202. A sputtering process, a spray coating, and / or an electroplating process can be used to form EMI shield 250. EMI shield 250 can include a conductive layer. EMI shield 250 can be configured to be coupled to ground. Figure 13D Stage 8 of [description] illustrates and describes an example of forming an EMI shield.

[0084] Exemplary sequence for manufacturing a substrate

[0085] Figures 15A - 15C Illustrates an exemplary sequence for providing or manufacturing a substrate. In some implementations, Figures 15A - 15C the sequence of [description] can be used to provide or manufacture Figure 6 substrate 202 or any substrate described in the present disclosure. As described above, different implementations can use different substrates, including laminated substrates and coreless substrates (e.g., embedded trace substrates). Figures 15A - 15CThe substrate shown is an example of a possible substrate that can be used.

[0086] It should be noted that Figures 15A - 15C The sequence of [[ ]] can be combined with one or more stages in order to simplify and / or clarify the sequence used to provide or fabricate the substrate. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more processes can be replaced or substituted without departing from the spirit of the present disclosure.

[0087] As Figure 15A shown in [[ ]], Stage 1 illustrates the state after providing the carrier 1500. The carrier 1500 can be a substrate.

[0088] Stage 2 illustrates the state after forming the interconnect 1502 on the carrier 1500. The interconnect 1502 can be an interconnect from among a plurality of interconnects 221. An electroplating process can be used to form the interconnect 1502.

[0089] Stage 3 illustrates the state after forming the dielectric layer 1520 on the interconnect 1502 and the carrier 1500. A deposition and / or lamination process can be used to form the dielectric layer 1520.

[0090] Stage 4 illustrates the state after forming one or more cavities 1503 in the dielectric layer 1520. A laser process (e.g., laser ablation) or a photoetching process (e.g., photolithography process) can be used to form one or more cavities 1503.

[0091] Stage 5 illustrates the state after forming the interconnect 1504 on the dielectric layer 1520. The interconnect 1504 can be an interconnect from among a plurality of interconnects 221. An electroplating process can be used to form the interconnect 1504.

[0092] Stage 6, as Figure 15B shown in [[ ]], illustrates the state after forming the dielectric layer 1540 on the dielectric layer 1520. The dielectric layer 1540 can be made of the same material as the dielectric layer 1520. A deposition and / or lamination process can be used to form the dielectric layer 1540. The dielectric layer 1540 can be formed such that the cavity 1310 is formed.

[0093] Stage 7 illustrates the state after forming the interconnect 1542 on the dielectric layer 1540. The interconnect 1542 can be an interconnect from among a plurality of interconnects 221. An electroplating process can be used to form the interconnect 1542. In some implementations, one or more cavities may have been formed in the dielectric layer 1540, and the interconnect 1542 can be formed over the cavities of the dielectric layer 1540.

[0094] Stage 8 illustrates the state after dielectric layer 1560 is formed over dielectric layer 1540. Dielectric layer 1560 can be the same material as dielectric layer 1520 and / or 1540. Deposition and / or lamination processes can be used to form dielectric layer 1560. Dielectric layer 1560 can be formed to form cavity 1310.

[0095] As Figure 15C shown, stage 9 illustrates the state after interconnects 1562 and 1564 are formed over dielectric layer 1560. Interconnect 1562 can be an interconnect from among multiple interconnects 221. An electroplating process can be used to form interconnect 1562. In some implementations, one or more cavities may have been formed in dielectric layer 1560, and interconnect 1562 can be formed over the cavities of dielectric layer 1560.

[0096] Stage 10 illustrates the state after carrier 1500 is removed. Stage 10 can illustrate a portion of substrate 202. Dielectric layer 220 can represent dielectric layers 1520, 1540, and 1560. Interconnects 221 can represent interconnects 1502, 1504, 1542, and 1562 as well as 1564.

[0097] Exemplary sequence for manufacturing a stacked device

[0098] Figures 16A - 16B illustrates an exemplary sequence for providing or manufacturing a device including a stacked integrated device (e.g., a stacked filter). In some implementations, Figures 16A - 16B the sequence can be used to provide or manufacture Figure 11 the stacked device 1104 or any stacked device described in the present disclosure.

[0099] It should be noted that Figures 16A - 16B the sequence can combine one or more stages in order to simplify and / or clarify the sequence for providing or manufacturing a device including a stacked integrated device. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more processes can be replaced or substituted without departing from the spirit of the present disclosure.

[0100] As Figure 16AAs shown, Stage 1 illustrates the state after the integrated device 1114 is provided. The integrated device 1114 can be configured as a filter. The integrated device 1114 can be a die filter (e.g., SAW filter, BAW filter). The integrated device 1114 includes a substrate 1610 and at least one metal layer 1614. The substrate 1610 can be a piezoelectric substrate. For example, the substrate 1610 can include a piezoelectric material (e.g., aluminum nitride (AlN), quartz, lithium niobate, lithium tantalate). In another example, the substrate 1610 can include a piezoelectric layer that is formed and located on the surface of the substrate 1610. For example, the substrate 1610 can include glass having a piezoelectric layer that is formed and located on the surface of the glass. Other materials can also be used instead of glass. The piezoelectric substrate used in the present disclosure can mean a substrate including a piezoelectric material and / or a substrate including a piezoelectric layer coupled to and located on the surface of the substrate. Different implementations can use different materials for the piezoelectric material and / or the piezoelectric layer.

[0101] At least one metal layer 1614 is formed on the substrate 1610. In the case where the substrate 1610 includes a piezoelectric layer that is formed and located on the surface of the substrate 1610, at least one metal layer 1614 can be formed and located on the piezoelectric layer. At least one metal layer 1614 can include a conductive material such as copper (Cu). At least one metal layer 1614 can be patterned and / or configured as an interconnect, electrode, and / or transducer of the integrated device 1114. In some implementations, the metal layer 1614 can include a first metal layer and a second metal layer. The first metal layer can be configured to operate as at least one transducer, while the second metal layer can be configured as at least one interconnect coupled to the transducer. In some implementations, the first metal layer of the metal layer 1614 can be formed first, and then the second metal layer of the metal layer 1614 can be formed.

[0102] Stage 2 illustrates the state after the polymer frame 1118 is coupled to the integrated device 1114. A deposition process can be used to form the polymer frame 1118 and couple it to the integrated device 1114.

[0103] Stage 3 illustrates the state after the integrated device 1116 is provided. The integrated device 1116 can be configured as a filter. The integrated device 1116 can be a die filter (e.g., SAW filter, BAW filter). The integrated device 1116 includes a substrate 1620 and at least one metal layer 1624. The substrate 1620 can be a piezoelectric substrate. For example, the substrate 1610 can include a piezoelectric material (e.g., aluminum nitride (AlN), quartz, lithium niobate, lithium tantalate). In another example, the substrate 1620 can include a piezoelectric layer formed and located on the surface of the substrate 1620. For example, the substrate 1620 can include glass having a piezoelectric layer formed and located on the surface of the glass. Other materials can also be used instead of glass. The piezoelectric substrate used in the present disclosure can mean a substrate including a piezoelectric material and / or a substrate including a piezoelectric layer coupled to and located on the surface of the substrate. Different implementations can use different materials for the piezoelectric material and / or the piezoelectric layer.

[0104] At least one metal layer 1624 is formed on the substrate 1620. In the case where the substrate 1620 includes a piezoelectric layer formed and located on the surface of the substrate 1620, at least one metal layer 1624 can be formed and located on the piezoelectric layer. At least one metal layer 1624 can include a conductive material such as copper (Cu). At least one metal layer 1624 can be patterned and / or configured as an interconnect, electrode, and / or transducer of the integrated device 1116. In some implementations, the metal layer 1624 can include a first metal layer and a second metal layer. The first metal layer can be configured to operate as at least one transducer, while the second metal layer can be configured as at least one interconnect coupled to the transducer. In some implementations, the first metal layer of the metal layer 1624 can be formed first, and then the second metal layer of the metal layer 1624 can be formed.

[0105] Stage 4 illustrates the state after an optional protective layer 1630 is formed on the substrate 1620 and at least one metal layer 1624. The protective layer 1630 can be deposited on the substrate 1620 and at least one metal layer 1624.

[0106] As Figure 16B shown, stage 5 illustrates the state after the integrated device 1114 is coupled to the integrated device 1116 such that a void 1120 is formed between the integrated device 1114, the integrated device 1116, and the polymer frame 1118. The integrated device 1114 can be coupled to the integrated device 1116 using a thermal compression process. If the protective layer 1630 is formed, the protective layer 1630 can be removed after the integrated device 1114 is coupled to the integrated device 1116.

[0107] Stage 6 illustrates the state after forming a plurality of interconnects 1119 over the surfaces of integrated device 1114, integrated device 1116, and polymer frame 1118. The plurality of interconnects 1119 can be coupled to at least one metal layer 1614 and at least one metal layer 1624. A plating process, a sputtering process, and / or a spraying process can be used to form the plurality of interconnects 1119.

[0108] Stage 7 illustrates the state after a plurality of solder interconnects 1140 are coupled to the plurality of interconnects 1119. The plurality of solder interconnects 1140 can be coupled to the plurality of interconnects 1119 using a reflow soldering process. Stage 7 can illustrate the stacked device 1104 as shown in Figure 11 below.

[0109] Exemplary sequence for fabricating a stacked device

[0110] Figures 17A - 17B illustrates an exemplary sequence for providing or fabricating a device including stacked integrated devices (e.g., stacked filters). In some implementations, Figures 17A - 17B the sequence of Figure 12 can be used to provide or fabricate the stacked device 1204 of

[0111] or any stacked device described in this disclosure. Figures 17A - 17B It should be noted that the sequence of

[0112] can combine one or more stages in order to simplify and / or clarify the sequence for providing or fabricating a device including stacked integrated devices. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more processes can be replaced or substituted without departing from the spirit of this disclosure.

[0112] As Figure 17A shown in Figure 17A below, stage 1 illustrates the state after providing integrated device 1114. Integrated device 1114 can be configured as a filter. Integrated device 1114 includes substrate 1610 and at least one metal layer 1614. Figure 17A The integrated device 1114 of Figure 16A is similar to or the same as the integrated device 1114 of

[0113] Stage 2 illustrates the state after interconnect frame 1218 is coupled to integrated device 1114. Interconnect frame 1218 can be coupled to at least one metal layer 1614. A plating process can be used to form interconnect frame 1218 and couple interconnect frame 1218 to integrated device 1114. However, different implementations can form and couple interconnect frame 1218 in different ways.

[0114] Stage 3 illustrates the state after providing the integrated device 1116. The integrated device 1116 can be configured as a filter. The integrated device 1216 can be a die filter (e.g., SAW filter, BAW filter). The integrated device 1116 includes a substrate 1620, at least one metal layer 1624, and at least one via 1217. Figure 17A The integrated device 1116 similar to Figure 16A the integrated device 1116. At least one via 1217 can pass through the substrate 1620.

[0115] Stage 4 illustrates the state after forming an optional protective layer 1630 over the substrate 1620 and at least one metal layer 1624. The protective layer 1630 can be deposited over the substrate 1620 and at least one metal layer 1624.

[0116] As Figure 17B shown, Stage 5 illustrates the state after the integrated device 1114 is coupled to the integrated device 1116 such that a void 1120 is formed between the integrated device 1114, the integrated device 1216, and the interconnect frame 1218. The interconnect frame 1218 can be coupled to at least one via 1217. As mentioned above, the interconnect frame 1218 can be coupled to at least one metal layer 1614. The integrated device 1114 can be coupled to the integrated device 1216 using a thermocompression process. If the protective layer 1630 is formed, the protective layer 1630 can be removed after the integrated device 1114 is coupled to the integrated device 1216.

[0117] Stage 6 illustrates the state after forming a plurality of interconnects 1219 over the surface of the integrated device 1216. The plurality of interconnects 1219 can be coupled to at least one via 1217 and at least one metal layer 1624. At least one via 1217 can be coupled to at least one metal layer 1624. The plurality of interconnects 1219 can be formed using an electroplating process, a sputtering process, and / or a spraying process.

[0118] Stage 7 illustrates the state after a plurality of solder interconnects 1140 are coupled to the plurality of interconnects 1219. The plurality of solder interconnects 1140 can be coupled to the plurality of interconnects 1219 using a reflow soldering process. Stage 7 can illustrate the stacked device 1204 as Figure 12 shown.

[0119] Exemplary electronic device

[0120] Figure 18Illustrated are various electronic devices that can be integrated with any one of the above-described devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, connectors, packages, package - on - package (PoP), system - in - package (SiP), or system - on - chip (SoC). For example, a mobile phone device 1802, a notebook computer device 1804, a fixed - location terminal device 1806, a wearable device 1808, or an automotive vehicle 1810 can include the device 1800 as described herein. The device 1800 can be, for example, any device and / or integrated circuit (IC) package as described herein. Figure 18 The devices 1802, 1804, 1806, and 1808 and the vehicle 1810 illustrated in Figure 18 are merely exemplary. Other electronic devices can also have the device 1800, including but not limited to a group of devices (e.g., electronic devices) including: mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set - top boxes, music players, video players, entertainment units, fixed - location data units such as meter - reading devices, communication devices, smart phones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in automotive vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions or any combination thereof.

[0121] Figures 2 - 12 , Figures 13A - 13D , Figure 14 , Figures 15A - 15C , Figures 16A - 16B , Figures 17A - 17B and / or Figure 18 One or more of the components, processes, features, and / or functions illustrated in Figure 18 can be rearranged and / or combined into a single component, process, feature, or function, or embodied in several components, processes, or functions. Without departing from the present disclosure, other elements, components, processes, and / or functions can also be added. It should also be noted that the Figures 2 - 12 , Figures 13A - 13D , Figure 14 , Figures 15A - 15C , Figures 16A - 16B , Figures 17A - 17B and / or Figure 18 and their corresponding descriptions are not limited to dies and / or integrated circuits. In some implementations, Figures 2 - 12 , Figures 13A - 13D , Figure 14 , Figures 15A - 15C , Figures 16A - 16B , 1 Figure 7 A - 17B and / or Figure 18And its corresponding description can be used to manufacture, create, provide, and / or produce devices and / or ICs. In some implementations, the devices may include dies, integrated devices, integrated passive devices (IPDs), die packages, integrated circuit (IC) devices, device packages, integrated circuit (IC) packages, wafers, semiconductor devices, package-on-package (PoP) devices, heat dissipation devices, and / or connectors.

[0122] It should be noted that the drawings in this disclosure may represent actual representations and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, these drawings may not be to scale. In some instances, not all components and / or parts may be shown for clarity. In some instances, the orientation, position, size, and / or shape of various parts and / or components in the drawings may be exemplary. In some implementations, various components and / or parts in the drawings may be optional.

[0123] The term "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as more preferred or advantageous than other aspects of the present disclosure. Similarly, the term "aspect" does not require that all aspects of the present disclosure include the feature, advantage, or mode of operation being discussed. The term "coupled" is used herein to refer to a direct or indirect coupling between two objects (e.g., a mechanical coupling). For example, if object A physically contacts object B, and object B contacts object C, then objects A and C can still be considered to be coupled to each other—even if they do not directly physically contact each other. The term "electrically coupled" can mean that two objects are directly or indirectly coupled together such that an electric current (e.g., a signal, power supply, ground) can propagate between the two objects. There may or may not be an electric current transmission between two electrically coupled objects. The use of the terms "first", "second", "third", and "fourth" (and / or anything above the fourth) is arbitrary. Any of the components described can be the first component, the second component, the third component, or the fourth component. For example, a component referred to as the second component can be the first component, the second component, the third component, or the fourth component. The term "surround" means that the object can partially surround or completely surround another object. The term "encapsulate" means that the object can partially encapsulate or completely encapsulate another object. The terms "top" and "bottom" are arbitrary. A component located at the top can be above a component located at the bottom. The top component can be considered the bottom component, and vice versa. As described in the present disclosure, a first component located "above" a second component may mean that the first component is above or below the second component, depending on how the bottom or top is arbitrarily defined. In another example, a first component can be above (e.g., higher than) a first surface of a second component, and a third component can be above (e.g., lower than) a second surface of the second component, where the second surface is opposite the first surface. It should also be noted that the term "over" as used in this application in the case where one component is above another component can be used to mean that one component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Thus, for example, a first component located over a second component can mean: (1) the first component is above the second component but does not directly contact the second component, (2) the first component is on the second component (e.g., on the surface of the second component), and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component located "in" a second component can be partially in the second component or completely in the second component. As used in the present disclosure, the term "about 'value X'", or "substantially value X" means within 10% of "value X". For example, a value of about 1 or substantially 1 will mean a value in the range of 0.9 - 1.1.

[0124] In some implementations, an interconnect is an element or component of a device or package that allows or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include traces, vias, pads, pillars, redistribution metal layers, and / or under-bump metallization (UBM) layers. In some implementations, an interconnect is a conductive material that can be configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. An interconnect may be part of a circuit. Different implementations may use different processes and / or sequences for forming an interconnect. In some implementations, chemical vapor deposition (CVD) processes, physical vapor deposition (PVD) processes, sputtering processes, spray coating, and / or electroplating processes may be used to form an interconnect.

[0125] Additionally, note that the various disclosures contained herein may be described as processes, which are depicted as flowcharts, flow diagrams, structure diagrams, or block diagrams. Although a flowchart may describe operations as a sequential process, many operations may be performed in parallel or concurrently. Additionally, the order of operations may be rearranged. When the operations of a process are completed, the process is terminated.

[0126] The various features of the present disclosure described herein may be implemented in different systems without departing from the present disclosure. It should be noted that the foregoing aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the aspects of the present disclosure is intended to be illustrative and not to limit the scope of the claims. As such, the teachings can be readily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art.

Claims

1. An encapsulation, comprising: a substrate including a first surface; an integrated device coupled to the first surface of the substrate; a first encapsulation layer located over the first surface of the substrate and the integrated device, wherein the first encapsulation layer includes an undercut relative to a side surface of the integrated device, wherein the undercut is not a vertical undercut, and a void located between the integrated device and the first surface of the substrate, wherein the void is laterally surrounded by the undercut of the first encapsulation layer.

2. The encapsulation according to claim 1, wherein the undercut of the first encapsulation layer relative to the side surface of the integrated device is in the range of -20 - 50 micrometers (μm).

3. The encapsulation according to claim 1, wherein there is no sealing film between the first encapsulation layer and the integrated device.

4. The encapsulation according to claim 1, further comprising a second encapsulation layer located over the first encapsulation layer, wherein the first encapsulation layer has a uniform thickness over the top surface of the integrated device.

5. The encapsulation according to claim 4, wherein the second encapsulation layer has properties different from those of the first encapsulation layer.

6. The encapsulation according to claim 4, wherein the second encapsulation layer has a second coefficient of thermal expansion (CTE), and the second CTE (i) is greater than a first CTE of the first encapsulation layer, or (ii) is lower than the first CTE of the first encapsulation layer.

7. The encapsulation according to claim 1, wherein the substrate has a substrate CTE within 15 parts per million per Kelvin (ppm / K) of the effective CTE of the integrated device and the first encapsulation layer.

8. The encapsulation according to claim 1, wherein the substrate has a substrate CTE within 15 parts per million per Kelvin (ppm / K) of the effective CTE of the remainder of the encapsulation.

9. The encapsulation according to claim 1: wherein the substrate includes a cavity; wherein the integrated device is located over the cavity of the substrate; wherein the void includes the cavity of the substrate, and wherein the encapsulation includes a second integrated device located in the cavity of the substrate.

10. The encapsulation according to claim 1, further comprising: a stacked device coupled to the substrate; and a second void located between the stacked device and the substrate; wherein the substrate includes a cavity; wherein the second void includes the cavity of the substrate, and wherein the stacked device is located over the cavity of the substrate.

11. The encapsulation according to claim 10, wherein the stacked device includes a first die filter and a second die filter.

12. The encapsulation according to claim 1, wherein the integrated device includes a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a processor, a memory, and / or a combination thereof.

13. The encapsulation according to claim 1, further comprising: a second encapsulation layer located over the first encapsulation layer; and An electromagnetic interference (EMI) shield, located above the second encapsulation layer.

14. The encapsulation according to claim 13, further comprising: A second integrated device, coupled to a second surface of the substrate; and A third encapsulation layer, coupled to the second surface of the substrate and encapsulating the second integrated device.

15. A device, comprising: A substrate, including a first surface; An integrated device, coupled to the first surface of the substrate; Components for a first encapsulation, located above the first surface of the substrate and the integrated device, wherein the components for the first encapsulation include an undercut relative to a side surface of the integrated device, wherein the undercut is not a vertical undercut, and A void, located between the integrated device and the first surface of the substrate, wherein the void is laterally surrounded by the undercut of the components for the first encapsulation.

16. The device according to claim 15, wherein the undercut of the components for the first encapsulation relative to the side surface of the integrated device is in the range of -20 - 50 micrometers (μm).

17. The device according to claim 15, wherein there is no sealing film between the components for the first encapsulation and the integrated device in the device.

18. The device according to claim 15, further comprising components for a second encapsulation located above the components for the first encapsulation, wherein the components for the second encapsulation have properties different from those of the components for the first encapsulation.

19. The device according to claim 18, wherein the components for the second encapsulation have a second coefficient of thermal expansion (CTE), and the second CTE is greater than the first CTE of the components for the first encapsulation.

20. The device according to claim 15, wherein the substrate has a substrate CTE, and the substrate CTE is within 15 parts per million per Kelvin (ppm / K) of the effective CTE of the integrated device and the components for the first encapsulation.

21. The device according to claim 15, wherein the substrate has a substrate CTE between 5 - 20 parts per million per Kelvin (ppm / K).

22. The device according to claim 15, wherein the substrate includes a cavity; wherein the integrated device is located above the cavity of the substrate; wherein the void includes the cavity of the substrate, and wherein the device includes a second integrated device located in the cavity of the substrate.

23. The device according to claim 15, further comprising: A stacked device, coupled to the substrate; and A second void, located between the stacked device and the substrate; wherein the substrate includes a cavity; wherein the second void includes the cavity of the substrate, and wherein the stacked device is located above the cavity of the substrate.

24. The device according to claim 23, wherein the stacked device includes components for first signal filtering and components for second signal filtering.

25. The apparatus according to claim 15, wherein the integrated device includes a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a processor, a memory, and / or a combination thereof.

26. The apparatus according to claim 15, further comprising: components for a second package, located above the components for the first package; and components for electromagnetic interference (EMI) shielding, located above the components for the second package.

27. The apparatus according to claim 26, further comprising: a second integrated device, coupled to a second surface of the substrate; and components for a third package, coupled to the second surface of the substrate and encapsulating the second integrated device.

28. The apparatus according to claim 15, wherein the apparatus includes a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in an automotive vehicle.

29. A method for manufacturing a package, comprising: providing a substrate including a first surface; coupling an integrated device to the first surface of the substrate; and forming a first encapsulation layer over the first surface of the substrate and the integrated device; wherein the first encapsulation layer includes an undercut with respect to a side surface of the integrated device, wherein the undercut is not a vertical undercut, and wherein forming the first encapsulation layer forms a void between the integrated device and the first surface of the substrate, wherein the void is laterally surrounded by the undercut of the first encapsulation layer.

30. The method according to claim 29, wherein the undercut of the first encapsulation layer with respect to the side surface of the integrated device is in the range of -20 - 50 micrometers (μm).

31. The method according to claim 29, wherein there is no sealing film between the first encapsulation layer and the integrated device.

32. The method according to claim 29, further comprising forming a second encapsulation layer over the first encapsulation layer.

33. The method according to claim 32, wherein the second encapsulation layer has properties different from those of the first encapsulation layer.

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