A DRAM aging test data analysis system

Abstract

The application discloses a DRAM aging test data analysis system and relates to the technical field of DRAM aging test; in order to quickly lock the possible failure reason; including a historical test database, a test data input module, a yield data judgment module, a Bin Map concentration analysis module, a Slot correlation analysis module, a BIB correlation analysis module, an OVEN correlation analysis module, a program Bin Gap analysis module, a program failure item analysis module, a failure model analysis module, a failure model input module, an analysis report and early warning module. The application establishes the corresponding connection through the correlation of the yield and the machine, automatically compares whether abnormal points appear in the test process in the production process, such as low yield, failure concentration, Bin Gap and continuous fail, so that abnormal data can be found in time, and the timeliness of data analysis is improved.

Description

Technical Field

[0001] This invention relates to the technical field of integrated circuit testing, and in particular to a DRAM aging test data analysis system. Background Technology

[0002] In existing technologies, during DRAM aging tests, in addition to chip failures, due to the high-stress nature of the test, even minor hardware issues can significantly impact the test results. During testing, we often rely on personal experience to set foolproof measures to prevent problems from escalating due to hardware-related issues. However, analyzing the root cause of anomalies often requires extensive experimental verification and data collection, and by the time problems are discovered, many false tests have already occurred. We aim to quickly identify whether test failures are concentrated across different devices and, by analyzing test logs, provide feedback on the concentration of chip test failures to the client, thereby quickly pinpointing potential causes of failure. This facilitates rapid problem-solving and improves chip yield.

[0003] Initially, when hardware problems occurred, the frequency of these problems was not very high, and the impact on yield was not significant. However, when the anomalies were discovered, the problems had already occurred for some time, requiring the tracing of a large amount of data and resulting in untimely feedback.

[0004] When processing and analyzing data, due to the large volume of data, it takes a long time to process it without proper organization. Furthermore, the analyst needs to have a good understanding of the aging test station and be able to make effective judgments on the data. This process is inefficient and requires a high level of training for personnel, which is not conducive to the analysis of test data. Based on this, a DRAM aging test data analysis system is proposed. Summary of the Invention

[0005] The purpose of this invention is to address the shortcomings of existing technologies by proposing a DRAM aging test data analysis system.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] A DRAM aging test data analysis system includes a historical test database, a test data input module, a yield data judgment module, a Bin Map centralization analysis module, a Slot correlation analysis module, a BIB correlation analysis module, an OVEN correlation analysis module, a program Bin Gap analysis module, a program failure item analysis module, a failure model analysis module, a failure model input module, and an analysis report and early warning module. This system, in one direction, determines the correlation between hardware yield and hardware through centralized analysis of hardware yield; in another direction, based on the program test results, it determines the correlation of abnormal failure particles concentrated on a certain test item, and the test item is used to reverse-engineer the cause of failure.

[0008] Preferably, the yield data judgment module performs data judgment on the test data input module. Based on the yield control set by the system, it compares the historical production yield of the same type of program and judges the standard of yield. When no abnormality is found, the yield is judged to be normal. If an abnormality is found during the judgment process, the abnormal situation is summarized and the Lot is marked as Normal, Abnormal, or New Program. If the Lot is not in the Normal state, the corresponding Oven will be marked as Abnormal and hardware and program analysis will be performed.

[0009] Preferably, the Bin Map centralized analysis module analyzes the yield abnormality from two aspects after the yield data judgment module detects it.

[0010] (1) Enter the Bin Map centralized analysis module. The system will capture the test results and generate the corresponding Bin Map according to the BIB Dut.

[0011] (2) Analyze whether there is a concentrated failure in the Bin distribution, observe whether there are continuous failures and concentrated failures, and mark the abnormal Oven, Slot, and BIB as Abnormal in abnormal cases. Then output the summary results and enter the Slot correlation analysis module.

[0012] As a preferred embodiment of the present invention: the Slot correlation analysis module analyzes the Bin Map concentration problem. If the Slot correlation analysis module does not find a Bin Map concentration problem, it compares the yield of each slot to see if there is any abnormality. If so, it marks the slot as abnormal. The Slot correlation module will capture the historical test information of the abnormal slot, compare the yield of the abnormal slot with the yield of other slots in the same oven, determine whether it belongs to the abnormality of the slot, and output the judgment result. If it is normal, the abnormal Slot mark is removed and the process proceeds to the BIB correlation analysis module.

[0013] As a preferred embodiment of the present invention: the BIB correlation analysis module receives abnormal BIB inputs, and the BIB correlation analysis module performs analysis from two aspects.

[0014] (1) Capture historical test information of abnormal BIBs and compare the yield of abnormal BIBs with that of other BIBs in the same Oven based on the test information;

[0015] (2) Capture the historical Fail Bin distribution of BIB, and then overlay the Fail Bins to check if there are any fixed consecutive Fails;

[0016] The BIB analysis module outputs a judgment result based on these two aspects. If there are no abnormalities in either aspect, the BIBabnormal flag is removed, and the module proceeds to the Oven correlation analysis module.

[0017] As a preferred embodiment of the present invention: when the Oven is marked as Abnormal, the Oven correlation analysis module retrieves the historical test data of the Oven and compares it with the yield of other identical programs. The system captures the temperature curve during the test process and calculates whether the heating and cooling time is within the allowable range. If both are within the acceptable range, the abnormal mark of the Oven will be removed, and the hardware summary will be given to the failure model analysis module.

[0018] Furthermore: the program's Bin Gap analysis module, if not marked as Normal in yield analysis, performs program analysis, automatically compares the Fail Bin Gap of the same test, analyzes the yield anomalies caused by the specific number of Fail Bins, analyzes the failed items of the Fail Bins based on the corresponding Bin Gap analysis results and test logs, finds the main failure causes, analyzes whether there are failures of a certain Bin concentrated on a certain board, and outputs a Bin Fail report to the failure model analysis module.

[0019] As a further aspect of the present invention: the failure item analysis module analyzes the failed test items based on the test data, captures the top 3 failure items in the Fail Bin, calculates whether the top 3 failures are concentrated on a certain board with more than 30%, and outputs the analysis results to the failure model analysis module.

[0020] As a further aspect of the present invention: the failure model analysis module is maintained through a database. For the analysis results that appear, after the cause is investigated, the relevant root cause will be entered through personal maintenance. In subsequent analysis, for the analysis results of failure item analysis and centralized analysis, it is provided whether there are similar analysis cases in history, providing analysis reference. Finally, an analysis report is output, and engineers are required to provide root cause maintenance after investigating the final cause.

[0021] The beneficial effects of this invention are as follows:

[0022] 1. By establishing a correlation between yield and machine, the system can automatically compare and test for anomalies during production, such as low yield, concentrated failures, bin gaps, and continuous failures, thereby enabling timely detection of abnormal data.

[0023] 2. It can also generate correlations and clusters of different hardware on the comparison machine, thereby helping to quickly determine the possible causes of failure and thus improving the timeliness of data analysis.

[0024] 3. After ruling out hardware issues, we can analyze the test data to promptly confirm with the customer whether there were any problems with the memory chip in the preceding steps. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the yield analysis structure of a DRAM aging test data analysis system proposed in this invention;

[0026] Figure 2 This is a schematic diagram of the yield data judgment module structure of a DRAM aging test data analysis system proposed in this invention;

[0027] Figure 3 This is a schematic diagram of the Bin Map centralized analysis structure of a DRAM aging test data analysis system proposed in this invention;

[0028] Figure 4 This is a schematic diagram of the slot correlation analysis structure of a DRAM aging test data analysis system proposed in this invention;

[0029] Figure 5 This is a schematic diagram of the BIB correlation analysis module structure of a DRAM aging test data analysis system proposed in this invention;

[0030] Figure 6 This is a schematic diagram of the Oven correlation analysis module structure of a DRAM aging test data analysis system proposed in this invention;

[0031] Figure 7This is a schematic diagram of the Bin Gap analysis structure of a DRAM aging test data analysis system proposed in this invention;

[0032] Figure 8 This is a schematic diagram of the failure item analysis structure of a DRAM aging test data analysis system proposed in this invention;

[0033] Figure 9 This is a schematic diagram of the failure model analysis structure of a DRAM aging test data analysis system proposed in this invention. Detailed Implementation

[0034] The technical solution of this patent will be further described in detail below with reference to specific embodiments.

[0035] The embodiments of this patent are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this patent, and should not be construed as limiting this patent.

[0036] In the description of this patent, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "setting" should be interpreted broadly. For example, they can refer to a fixed connection or setting, a detachable connection or setting, or an integral connection or setting. Those skilled in the art can understand the specific meaning of the above terms in this patent according to the specific circumstances.

[0037] Example 1:

[0038] A DRAM aging test data analysis system, such as Figure 1 As shown, the system includes a historical test database, a test data input module, a yield data judgment module, a Bin Map centralization analysis module, a Slot correlation analysis module, a BIB correlation analysis module, an OVEN correlation analysis module, a program Bin Gap analysis module, a program failure item analysis module, a failure model analysis module, a failure model input module, and an analysis report and early warning module. One aspect of the system is to determine the correlation between hardware yield and hardware through centralized analysis of hardware yield. The other aspect is to determine the correlation between abnormal failure particles concentrated on a certain test item based on the program's test results, and to reverse-engineer the cause of failure based on the test item.

[0039] Example 2:

[0040] A DRAM aging test data analysis system, wherein after a lot is batched, the test data input module uses a yield data judgment module to perform data judgment, and the logic block diagram is as follows. Figure 2 As shown, based on the yield control set by the system, the historical production yield of the same type of program is compared to judge the standard of yield. When no abnormality occurs, the yield is judged to be normal. If an abnormality is found in the judgment process, the abnormal situation is summarized and the Lot is marked as Normal, Abnormal, New Program. If the Lot is not in the Normal state, the corresponding Oven will be marked as Abnormal for hardware and program analysis.

[0041] Preferably, when the test program is run for the first time, the system can generate an analysis report to identify and stop the spread of problems in abnormal situations.

[0042] Preferably, after the yield data judgment module detects an abnormal yield, it analyzes the data from two aspects.

[0043] (1) Enter the Bin Map centralized analysis module. The system will capture the test results and generate the corresponding Bin Map according to the BIB Dut.

[0044] (2) Analyze whether there is a concentrated failure in the Bin distribution, observe whether there are continuous failures and concentrated failures, and mark the abnormal Oven, Slot, and BIB as Abnormal in abnormal cases. Then output the summary results and enter the Slot correlation analysis module.

[0045] Preferably, the system block diagram of the Slot correlation analysis module is as follows: Figure 4 As shown; the Slot Correlation Analysis module analyzes the Bin Map concentration problem. If the Slot Correlation Analysis module does not find the Bin Map concentration problem, it compares the yield of each slot to see if there are any abnormalities. If so, it marks the slot as abnormal. The Slot Correlation Analysis module will capture the historical test information of the abnormal slot, compare the yield of the abnormal slot with the yield of other slots in the same oven, determine whether it belongs to the abnormality of the slot, and output the judgment result. If it is normal, the abnormal mark of the slot is removed, and it enters the BIB Correlation Analysis module.

[0046] Preferably, the system block diagram of the BIB correlation analysis module is as follows: Figure 5 As shown, in the preceding analysis module, abnormal BIBs are input into the BIB correlation analysis module. The BIB correlation analysis module performs analysis from two aspects.

[0047] (1) Capture historical test information of abnormal BIBs and compare the yield of abnormal BIBs with that of other BIBs in the same Oven based on the test information;

[0048] (2) Capture the historical Fail Bin distribution of BIB, and then overlay the Fail Bins to check if there are any fixed consecutive Fails;

[0049] The BIB analysis module outputs a judgment result based on these two aspects. If there are no abnormalities in either aspect, the BIBabnormal flag is removed, and the module proceeds to the Oven correlation analysis module.

[0050] Preferably, the system block diagram of the Oven correlation analysis module is as follows: Figure 6 As shown, when an Oven is marked as Abnormal, the system retrieves historical test data of the Oven and compares the yield with that of other identical programs. The system also captures the temperature curve during the test and calculates whether the heating and cooling times are within the allowable range. If both are within the acceptable range, the Abnormal mark of the Oven will be removed, and the hardware summary will be provided to the failure model analysis module.

[0051] Preferably, the failure model analysis module is maintained through a database, and the system block diagram is as follows: Figure 9 As shown, for the analysis results that appear, after the cause is investigated, the relevant root cause will be entered through personal maintenance. In subsequent analysis, for the analysis results of failure item analysis and centralized analysis, it is provided whether there are similar analysis cases in the past, providing analysis reference. Finally, an analysis report is output, and engineers are required to provide the root cause for maintenance after investigating the final cause.

[0052] Example 3:

[0053] A DRAM aging test data analysis system, for yield analysis where the value is not marked as "Normal", will also perform program analysis. First, "Normal" will enter the program's Bin Gap analysis module. The system block diagram is as follows: Figure 7 As shown, the Bin Gap analysis module automatically compares the Fail Bin Gap of the same test, analyzes the yield abnormality caused by the excessive number of specific Fail Bins, analyzes the failed items of the Fail Bin according to the corresponding Bin Gap analysis results and test logs, finds the main failure cause, analyzes whether the failure of a certain Bin is concentrated on a certain board, and outputs a Bin Fail report to the failed item analysis module.

[0054] Preferably, the failed item analysis module, the system block diagram is as follows: Figure 8As shown, based on the test data analysis, the failed test items are captured, the top 3 failed items in the Fail Bin are retrieved, and it is calculated whether the top 3 failures are concentrated on a certain board with more than 30% failure rate. The analysis results are then output to the failure model analysis module.

[0055] The above description represents a preferred embodiment of the present invention, but it is not the only embodiment of the present invention. Any modifications, equivalent substitutions, and improvements made by those skilled in the art within the scope of the technology disclosed in the present invention, combined with existing technology or common knowledge, and within the spirit and principles of the present invention, should be covered within the protection scope of the present invention.

Claims

1. A DRAM aging test data analysis system, comprising a historical test database, a test data input module, a yield data judgment module, a Bin Map centralization analysis module, a Slot correlation analysis module, a BIB correlation analysis module, an OVEN correlation analysis module, a program Bin Gap analysis module, a program failure item analysis module, a failure model analysis module, a failure model input module, and an analysis report and early warning module, characterized in that, One aspect of this system is to determine the correlation between hardware yield and hardware through centralized analysis. The other aspect is to determine the correlation between abnormal failure particles and failures concentrated on a certain test item based on the test results of the program, and to reverse-engineer the cause of failure in the test item. The yield data judgment module performs data judgment on the test data input module. Based on the yield control set by the system and the historical production yield comparison of the same type of program, it judges the yield standard. When no abnormality is found, the yield is judged to be normal. If an abnormality is found during the judgment process, the abnormal situation is summarized and the Lot is marked as Normal, Abnormal, or New Program. If the Lot is not in the Normal state, the corresponding OVEN will be marked as Abnormal and hardware and program analysis will be performed. The Bin Map centralized analysis module analyzes the yield data after the yield data judgment module detects yield anomalies, and then performs analysis from two aspects. (1) Enter the Bin Map centralized analysis module. The system will capture the test results and generate the corresponding Bin Map according to the BIB Dut. (2) Analyze whether there is a concentrated failure in the Bin distribution, observe whether there is a continuous failure and a concentrated failure, mark the abnormal OVEN, Slot, BIB as Abnormal in abnormal cases, then output the summary results and enter the Slot correlation analysis module. The Slot Correlation Analysis module analyzes Bin Map centralization issues. If no Bin Map centralization issues are found, the module compares the yield of each slot to see if there are any anomalies. If so, the slot is marked as abnormal (BIB). The Slot Correlation Analysis module retrieves historical test information for the abnormal slot and compares its yield with that of other slots in the same OVEN to determine if it is indeed an abnormal slot. The module outputs the result; if normal, the abnormal slot is removed from the list, and the process proceeds to the BIB Correlation Analysis module. When an OVEN is marked as Abnormal, the OVEN correlation analysis module retrieves historical test data and compares it with the yield of other identical programs. The system captures the temperature curve during the test and calculates whether the heating and cooling times are within the allowable range. If both are within the acceptable range, the abnormal mark of the OVEN will be removed, and the hardware summary will be provided to the failure model analysis module.

2. The DRAM aging test data analysis system according to claim 1, characterized in that, The BIB correlation analysis module receives abnormal BIBs and performs analysis from two aspects. (1) Capture historical test information of abnormal BIBs and compare the yield of abnormal BIBs with that of other BIBs in the same OVEN based on the test information; (2) Capture the historical Fail Bin distribution of BIB, and then overlay the Fail Bins to check if there are any fixed consecutive Fail Bins; The BIB analysis module outputs a judgment result based on these two aspects. If there are no abnormalities in either aspect, the BIB abnormal label is removed, and the module proceeds to the OVEN correlation analysis module.

3. The DRAM aging test data analysis system according to claim 2, characterized in that, The program's BinGap analysis module, if not marked as Normal in yield analysis, performs program analysis, automatically compares the Fail Bin Gap of the same test, analyzes the yield anomalies caused by the specific number of Fail Bins, analyzes the failed items of the Fail Bins based on the corresponding Bin Gap analysis results and test logs, finds the main failure causes, analyzes whether there are failures of a certain Bin concentrated on a certain board, and outputs a Bin Fail report to the failure model analysis module.

4. The DRAM aging test data analysis system according to claim 3, characterized in that, The failure model analysis module is maintained through a database. After investigating the cause of the analysis results, it will enter the relevant root cause through personal maintenance. In subsequent analysis, it will provide historical similar analysis results for the failure item analysis and cluster analysis results, and provide analysis reference. Finally, it will output an analysis report, and engineers need to provide the root cause for maintenance after investigating the final cause.

5. The DRAM aging test data analysis system according to claim 4, characterized in that, The program's BinGap analysis module will also perform program analysis if the yield analysis does not identify it as Normal. The BinGap analysis module automatically compares the Fail Bin Gap of the same test, analyzes the yield abnormality caused by an excessive number of specific Fail Bins, analyzes the failed items of the Fail Bins according to the corresponding Bin Gap analysis results and test logs, finds the main failure causes, analyzes whether there are failures of a certain Bin concentrated on a certain board, and outputs a Bin Fail report to the failed item analysis module.

6. The DRAM aging test data analysis system according to claim 5, characterized in that, The failure item analysis module analyzes the failed test items based on the test data, captures the top 3 failed items in the Fail Bin, calculates whether the top 3 failures are concentrated on a certain board with more than 30% failure rate, and outputs the analysis results to the failure model analysis module.

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