An asynchronous synchronous coexistence two-stage analog-to-digital converter and a working method thereof

Abstract

The application discloses a two-stage analog-digital converter for asynchronous synchronization coexistence, comprising a digital-analog conversion unit and a synchronization control unit; the digital-analog conversion unit is provided with two stages, and the synchronization control unit is arranged between the two-stage digital-analog conversion unit; the digital-analog conversion unit is controlled asynchronously; the synchronization control unit comprises an amplifier and an oscillator; the amplifier is connected to obtain a residual voltage on the digital-analog conversion unit of the first stage and is connected with a signal acquisition end on the digital-analog conversion unit of the second stage; and a synchronization clock generated by the oscillator is used for establishing time for the amplifier; through the timing control of the combination of the asynchronization and the synchronization, the overall processing speed can be improved obviously, and the power consumption can be reduced.

Description

Technical Field

[0001] This invention relates to the field of analog-to-digital conversion technology, and in particular to a two-stage analog-to-digital converter with asynchronous and synchronous coexistence and its working method. Background Technology

[0002] Two-stage analog-to-digital converters (ADCs) are a common design architecture, with two conventional design approaches: The first uses a synchronous clock to control the entire sampling and quantization process. In this approach, a capacitor may have already been set, but the next clock cycle is needed before the next capacitor can be compared and set. This method limits the ADC's sampling speed. The second approach uses asynchronous control of the entire sampling and quantization process. First, the system clock controls the ADC to sample. After sampling, the comparator begins comparison and toggling. The capacitor is set based on the comparator's result. After each capacitor is set, an edge signal is generated and provided to the comparator, which continues comparison. This method significantly improves the sampling speed. However, because the amplifiers in the two-stage ADC require settling time, a large amount of delay circuitry is needed to provide this time, resulting in significant power consumption waste. Summary of the Invention

[0003] Purpose of the invention: In order to overcome the shortcomings of the existing technology, the present invention provides a two-stage analog-to-digital converter with asynchronous and synchronous coexistence. The capacitor flips by controlling the asynchronous clock, and the amplifier is provided with the synchronous clock for the settling time, thereby improving the overall processing speed and reducing power consumption.

[0004] Technical Solution: To achieve the above objectives, the present invention provides a two-stage analog-to-digital converter (ADC) with asynchronous and synchronous coexistence, comprising an analog-to-digital conversion unit and a synchronization control unit; the analog-to-digital conversion unit is configured in two stages, and the synchronization control unit is disposed between the two stages of the analog-to-digital conversion unit; the analog-to-digital conversion unit is asynchronously controlled; the synchronization control unit includes an amplifier and an oscillator; the amplifier is connected to obtain the residual voltage on the first-stage analog-to-digital conversion unit and is connected to the signal acquisition terminal on the second-stage analog-to-digital conversion unit; the oscillator is connected to the amplifier, and the synchronization clock generated by the oscillator is used to provide the amplifier with setup time.

[0005] Furthermore, the digital-to-analog conversion unit includes a capacitor array and a digital control circuit, wherein the digital control circuit performs asynchronous control on the capacitor array.

[0006] Furthermore, the digital-to-analog conversion unit also includes a switch and a comparator; the switch is connected to the power supply path of the capacitor array; the comparator is connected to the digital control circuit, compares the voltage at the comparator input terminal, and sets the capacitor array according to the comparison structure.

[0007] Furthermore, the two-stage digital-to-analog conversion units are controlled by an asynchronous clock generated by a comparator.

[0008] The operation of a two-stage analog-to-digital converter with asynchronous and synchronous coexistence includes the following steps: Step 1: The first-stage digital-to-analog converter samples the input signal under the sampling clock. Step 2: After sampling in Step 1 is completed, the capacitors in the first-stage capacitor array are flipped. The asynchronous logic control comparator generates a feedback signal at the end of each conversion to proceed with the conversion of the next bit. After one capacitor is flipped, the next comparison begins, and the next capacitor is flipped in sequence. After the capacitor array comparison and setting are completed, the amplifier collects the residual voltage from the first-stage capacitor array. Step 3: After the quantization of the first-stage capacitor array is completed, the oscillator starts working to provide a synchronous clock for the amplifier. After several preset clock cycles, the second-stage capacitor array begins to sample the signal amplified by the amplifier. The two-stage capacitor arrays are controlled by the same asynchronous logic. After the quantization of both stages of the capacitor array is completed and the next sampling clock arrives, the two-stage digital-to-analog converters enter a new sampling cycle and repeat the above process.

[0009] Beneficial effects: (1) The present invention provides a two-stage analog-to-digital converter with asynchronous and synchronous coexistence, including a digital-to-analog conversion unit and a synchronous control unit; the digital-to-analog conversion unit is provided in two stages, and the synchronous control unit is provided between the two stages of the digital-to-analog conversion unit; the digital-to-analog conversion unit is asynchronously controlled; the synchronous control unit includes an amplifier and an oscillator; the amplifier is connected to obtain the residual voltage on the first stage of the digital-to-analog conversion unit and is connected to the signal acquisition terminal on the second stage of the digital-to-analog conversion unit; the oscillator is connected to the amplifier, and the synchronous clock generated by the oscillator is used to provide the amplifier with setup time; by controlling the capacitor to flip through the asynchronous clock and then providing the amplifier with setup time through the synchronous clock, the overall processing speed can be significantly improved and the power consumption reduced; (2) The present invention provides a two-stage analog-to-digital converter with asynchronous and synchronous coexistence, wherein the digital-to-analog conversion unit includes a capacitor array and a digital control circuit, and the digital control circuit performs asynchronous control on the capacitor array; the number of capacitors in the capacitor array can be set according to the task requirements of the analog-to-digital converter, and under asynchronous control, the capacitors cooperate with the comparator to be set step by step. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a binary capacitor array architecture; Figure 2 This is a schematic diagram of a single capacitor connection. Figure 3 This is a schematic diagram of a common architecture for a two-stage analog-to-digital converter; Figure 4 To simplify the amplifier's architecture diagram; Figure 5 A simplified circuit diagram of the comparator; Figure 6 This is a schematic diagram of the overall structure of the two-stage analog-to-digital converter with asynchronous and synchronous coexistence according to the present invention. Figure 7 This is a detailed structural diagram of the two-stage analog-to-digital converter with asynchronous and synchronous coexistence according to the present invention; Figure 8 This is a schematic diagram of the working cycle of the digital-to-analog converter of the present invention; Figure 9 This is a timing diagram of the digital-to-analog converter of the present invention.

[0011] The labels for the attached figures are as follows: 1. Digital-to-analog converter, 2. Synchronization control unit, 3. Amplifier, 4. Oscillator, 5. Capacitor array, 6. Digital control circuit, 7. Switch, 8. Comparator. Detailed Implementation

[0012] The invention will now be further described with reference to the accompanying drawings.

[0013] Analog-to-digital converters (ADCs) operate on the principle of charge redistribution, using a capacitor array (typically a binary equal-ratio capacitor array) to sample, quantize, and encode the input signal, thereby converting the analog signal into a digital signal. Traditional binary capacitor array architectures include... Figure 1 As shown. The capacitor is set via a switch on the lower-level board (connected to a reference high or low level), thus completing the charge flow. The connection method of individual capacitors in the capacitor array is as follows. Figure 2 As shown. During the sampling process, the upper-level board of the capacitor is connected to the analog input signal VIN via a sampling switch, and the lower-level board is connected to the reference high voltage (VREFP), reference low voltage (VREFN), and common-mode voltage (VCM) via three set switches, respectively. The following sampling process takes the upper-level board sampling as an example: During the sampling process, the upper-level board sampling switch S0 is turned on to sample the analog input signal VIN; the lower-level board sampling switch S1 is turned on to sample the common-mode voltage VCM. After sampling is completed, the upper-level board sampling switch is turned off, and the analog-to-digital converter begins quantization. First, the comparator compares the voltages at both ends. If the voltage at the positive terminal of the comparator is greater than the voltage at the negative terminal, the comparator outputs 1; otherwise, it outputs 0. Based on the comparison result, the digital control circuit sets the lower-level board of the capacitor via set switches S2 and S3, thereby causing a change in the potential of the upper-level board of the capacitor.

[0014] Based on the basic operating logic of the analog-to-digital converter described above, the general architecture of the original high-precision two-stage analog-to-digital converter is as follows: Figure 3As shown in the diagram. The first-stage capacitor array samples the input analog signal, and the remaining residual voltage serves as the input signal to the amplifier. The amplifier amplifies the residual voltage and provides it to the second stage as its input voltage. A simplified architecture of the differential output amplifier is shown below. Figure 4 As shown, the input signal is converted into current by the input transistor's gm, and then the current is amplified to achieve the function of voltage amplification. The simplified architecture of the comparator is as follows: Figure 5 As shown.

[0015] Based on the above architecture, refer to Figure 6 and Figure 7 The present invention discloses a two-stage analog-to-digital converter (ADC) with asynchronous and synchronous coexistence, comprising a digital-to-analog conversion unit 1 and a synchronization control unit 2; the digital-to-analog conversion unit 1 is configured in two stages, and the synchronization control unit 2 is disposed between the two stages of the digital-to-analog conversion unit 1; the digital-to-analog conversion unit 1 is asynchronously controlled; the synchronization control unit 2 includes an amplifier 3 and an oscillator 4; the amplifier 3 is connected to obtain the residual voltage on the first-stage digital-to-analog conversion unit 1 and is connected to the signal acquisition terminal on the second-stage digital-to-analog conversion unit 1; the oscillator 4 is connected to the amplifier 3, and the synchronization clock generated by the oscillator 4 is used to provide the amplifier 3 with setup time.

[0016] By combining amplifier 3 and oscillator 4, synchronous control of the signal can be achieved between the two stages of digital-to-analog converter 1, thereby greatly shortening the amplifier settling time under asynchronous control and improving signal transmission efficiency. When operating, oscillator 4 can oscillate repeatedly for three cycles, thus matching the amplifier settling time and efficiently connecting the first and second stages of digital-to-analog converter 1. The number of oscillator cycles can also be adjusted according to the characteristics of the processed signal, thereby matching the response speed of digital-to-analog converter 1 and amplifier.

[0017] The digital-to-analog converter 1 includes a capacitor array 5 and a digital control circuit 6, which asynchronously controls the capacitor array 5. The digital-to-analog converter 1 also includes a switch 7 and a comparator 8. The switch 7 is connected to the power supply path of the capacitor array 5. The comparator 8 is connected to the digital control circuit 6, and the voltage at the input terminal of the comparator 8 is compared to set the capacitor array 5 according to the comparison structure.

[0018] The number of capacitors in capacitor array 5 can be set according to the task requirements of the analog-to-digital converter. Under asynchronous control, the capacitors work in conjunction with the comparator to be set step by step. Switches are used to control the signal input and output of digital-to-analog converter unit 1.

[0019] The two-stage digital-to-analog conversion unit 1 is controlled by an asynchronous clock generated by comparator 8.

[0020] The operation of a two-stage analog-to-digital converter with asynchronous and synchronous coexistence includes the following steps: Step 1: The first-stage digital-to-analog converter 1 samples the input signal under the sampling clock. Step 2: After sampling in Step 1 is completed, the capacitors in the first-stage capacitor array 5 are flipped. The asynchronous logic control comparator 8 generates a feedback signal at the end of each conversion and performs the conversion of the next bit. After one capacitor is flipped, the next comparison begins, and the next capacitor is flipped in sequence. After the capacitor array comparison and setting are completed, the amplifier 3 collects the residual voltage from the first-stage capacitor array 5. Step 3: After the quantization of the first-stage capacitor array 5 is completed, the oscillator 4 starts working to provide a synchronous clock for the amplifier 3. After several preset clock cycles, the second-stage capacitor array 5 starts sampling the signal amplified by the amplifier 3. The two-stage capacitor array 5 is controlled by the same asynchronous logic. After the quantization of both stages of capacitor array 5 is completed and the next sampling clock arrives, the two-stage digital-to-analog converter enters a new sampling cycle and repeats the above process.

[0021] The above working methods are for reference. Figure 8 and Figure 9 The figure shows the timing of the asynchronous clock provided by the first clock and the synchronous clock provided by the second clock working together. In each working cycle, it goes through the asynchronous control of the first-stage digital-to-analog converter unit 1, the synchronous control of signal amplification, and the asynchronous control of the second-stage digital-to-analog converter unit 1, and so on.

[0022] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A two-stage analog-to-digital converter with asynchronous and synchronous coexistence, characterized in that: It includes a digital-to-analog converter (1) and a synchronization control unit (2); the digital-to-analog converter (1) is configured with two stages, and the synchronization control unit (2) is configured between the two stages of the digital-to-analog converter (1); the digital-to-analog converter (1) is asynchronously controlled; the synchronization control unit (2) includes an amplifier (3) and an oscillator (4); the amplifier (3) is connected to obtain the residual voltage on the first stage digital-to-analog converter (1) and is connected to the signal acquisition terminal on the second stage digital-to-analog converter (1); the oscillator (4) is connected to the amplifier (3), and the synchronization clock generated by the oscillator (4) is used to provide the amplifier (3) with setup time; The digital-to-analog converter (1) includes a capacitor array (5) and a digital control circuit (6), and the digital control circuit (6) performs asynchronous control on the capacitor array (5). The digital-to-analog converter (1) also includes a switch (7) and a comparator (8); the switch (7) is connected to the power supply path of the capacitor array (5); the comparator (8) is connected to the digital control circuit (6), compares the voltage at the input terminal of the comparator (8), and sets the capacitor array (5) according to the comparison structure; The two-stage digital-to-analog converter (1) is controlled by an asynchronous clock generated by a comparator (8); The operation of a two-stage analog-to-digital converter with asynchronous and synchronous coexistence includes the following steps: Step 1: The first-stage digital-to-analog converter (1) samples the input signal under the sampling clock. Step 2: After completing the sampling in Step 1, the capacitors in the first-stage capacitor array (5) are flipped. The asynchronous logic control comparator (8) generates a feedback signal at the end of each conversion and performs the conversion of the next bit. After the capacitor flipping is completed, the next comparison begins, and the next capacitor is flipped in sequence. After the capacitor array comparison and setting are completed, the amplifier (3) collects the residual voltage from the first-stage capacitor array (5). Step 3: After the quantization of the first-stage capacitor array (5) is completed, the oscillator (4) starts to work and provides a synchronous clock for the amplifier (3). After several preset clock cycles, the second-stage capacitor array (5) starts to sample the signal amplified by the amplifier (3). The two-stage capacitor arrays (5) are controlled by the same asynchronous logic. After the quantization of both stages of the capacitor arrays (5) is completed and the next sampling clock arrives, the two-stage digital-to-analog converters enter a new sampling cycle and repeat the above process.

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