Driving circuit and display device

Abstract

The present invention provides a driving circuit and a display device. The driving circuit includes a pull-up node, a first pull-up control node, a second pull-up control node, a first isolation circuit and a second isolation circuit; the first isolation circuit controls the connection or disconnection between the pull-up node and the first pull-up control node under the control of a first isolation control signal; the second isolation circuit controls the connection or disconnection between the pull-up node and the second pull-up control node under the control of a second isolation control signal. The present invention provides a first isolation circuit and a second isolation circuit to avoid mutual interference between the first pull-up control node and the second pull-up control node when two rows of pixel circuits are driven by one driving circuit.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a driving circuit and a display device. Background Art

[0002] At present, in order to reduce costs, driving circuits are used in panels. With the improvement of resolution and the requirement of narrow borders, the driving circuit is required to be as simple as possible, and the number of TFTs (thin film transistors) is as small as possible. Therefore, in the related art, a two-level driving signal is generated by a one-level driving circuit, but because the rising edges of the output clock signals connected to different output transistors included in the driving circuit are different, the gate potential of the output transistor is disturbed due to capacitive coupling, resulting in abnormal output, which appears as horizontal stripes on the display panel. Summary of the invention

[0003] The main purpose of the present invention is to provide a driving circuit and a display device to solve the problem that the rising edges of output clock signals connected to different output transistors included in the related multi-output driving circuit are different, which causes the gate potential of the output transistor to be disturbed due to capacitive coupling, resulting in abnormal output.

[0004] An embodiment of the present invention provides a driving circuit, including a pull-up node, a first pull-up control node, a second pull-up control node, a first isolation circuit, and a second isolation circuit;

[0005] The first isolation circuit is electrically connected to the first isolation control terminal, the pull-up node and the first pull-up control node respectively, and is used to control the connection or disconnection between the pull-up node and the first pull-up control node under the control of the first isolation control signal provided by the first isolation control terminal;

[0006] The second isolation circuit is electrically connected to the second isolation control terminal, the pull-up node and the second pull-up control node respectively, and is used to control the connection or disconnection between the pull-up node and the second pull-up control node under the control of a second isolation control signal provided by the second isolation control terminal.

[0007] Optionally, the first isolation circuit includes a first transistor, and the second isolation circuit includes a second transistor;

[0008] The gate of the first transistor is electrically connected to the first isolation control terminal, the first electrode of the first transistor is electrically connected to the pull-up node, and the second electrode of the first transistor is electrically connected to the first pull-up control node;

[0009] The gate of the second transistor is electrically connected to the second isolation control terminal, the first electrode of the second transistor is electrically connected to the pull-up node, and the second electrode of the first transistor is electrically connected to the second pull-up control node.

[0010] Optionally, the driving circuit described in at least one embodiment of the present invention includes an Nth cascade output terminal and a cascade output circuit;

[0011] The cascade output circuit is electrically connected to the Nth cascade output terminal, the first pull-up control node, the pull-down node, the cascade output clock signal terminal, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the Nth cascade output terminal and the cascade output clock signal terminal under the control of the potential of the first pull-up control node, and control the connection or disconnection between the Nth cascade output terminal and the first voltage terminal under the control of the potential of the pull-down node; N is a positive integer;

[0012] The driving circuit includes a pull-down node; or, the pull-down node includes a first pull-down node and a second pull-down node.

[0013] Optionally, the first isolation control terminal and the second isolation control terminal are reset terminals; or, the first isolation control terminal and the second isolation control terminal are second voltage terminals.

[0014] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a first node control circuit and a second node control circuit;

[0015] The first node control circuit is electrically connected to the input terminal and the first pull-up control node respectively, and is used to control the potential of the first pull-up control node according to an input signal provided by the input terminal;

[0016] The second node control circuit is electrically connected to the input terminal and the second pull-up control node respectively, and is used to control the potential of the second pull-up control node according to an input signal provided by the input terminal.

[0017] Optionally, the first node control circuit is further electrically connected to the frame reset terminal and the first voltage terminal, and is used to control the first pull-up control node to be connected to the first voltage terminal under the control of a frame reset signal provided by the frame reset terminal;

[0018] The second node control circuit is also electrically connected to the frame reset terminal and the first voltage terminal, and is used to control the connection between the second pull-up control node and the first voltage terminal under the control of a frame reset signal provided by the frame reset terminal.

[0019] Optionally, the first node control circuit includes a third transistor, and the second node control circuit includes a fourth transistor;

[0020] The gate of the third transistor and the first electrode of the third transistor are both electrically connected to the input terminal, and the second electrode of the third transistor is electrically connected to the first pull-up control node;

[0021] The gate of the fourth transistor and the first electrode of the fourth transistor are both electrically connected to the input terminal, and the second electrode of the fourth transistor is electrically connected to the second pull-up control node.

[0022] Optionally, the first node control circuit includes a fifth transistor and a sixth transistor;

[0023] The gate of the fifth transistor is electrically connected to the frame reset terminal, the first electrode of the fifth transistor is electrically connected to the first pull-up control node, and the second electrode of the fifth transistor is electrically connected to the first voltage terminal;

[0024] A gate of the sixth transistor is electrically connected to the frame reset terminal, a first electrode of the sixth transistor is electrically connected to the second pull-up control node, and a second electrode of the sixth transistor is electrically connected to the first voltage terminal.

[0025] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a first control node control circuit and a second control node control circuit;

[0026] The first control node control circuit is electrically connected to the enable terminal, the enable reset terminal and the first control node respectively, and is used to control the connection between the enable reset terminal and the first control node under the control of the enable signal provided by the enable terminal;

[0027] The second control node control circuit is electrically connected to the first clock signal end, the first control node, the second control node, the pull-up node, the first clock signal end, the second control node, the first pull-up control node and the second pull-up control node, respectively, and is used to control the connection between the first clock signal end and the second control node under the control of the potential of the first control node, and to control the connection between the second control node and the pull-up node under the control of the first clock signal provided by the first clock signal end, control the connection between the second control node and the first pull-up control node under the control of the first clock signal provided by the first clock signal end, and control the connection between the second control node and the second pull-up control node under the control of the first clock signal provided by the first clock signal end.

[0028] Optionally, the first control node control circuit includes a seventh transistor, and the second control node control circuit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a first capacitor;

[0029] The gate of the seventh transistor is electrically connected to the enable terminal, the first electrode of the seventh transistor is electrically connected to the enable reset terminal, and the second electrode of the seventh transistor is electrically connected to the first control node;

[0030] The gate of the eighth transistor is electrically connected to the first control node, the first electrode of the eighth transistor is electrically connected to the first clock signal terminal, and the second electrode of the eighth transistor is electrically connected to the second control node;

[0031] The gate of the ninth transistor is electrically connected to the first clock signal terminal, the first electrode of the ninth transistor is electrically connected to the second control node, and the second electrode of the ninth transistor is electrically connected to the pull-up node;

[0032] The gate of the tenth transistor is electrically connected to the first clock signal terminal, the first electrode of the tenth transistor is electrically connected to the second control node, and the second electrode of the tenth transistor is electrically connected to the first pull-up control node;

[0033] The gate of the eleventh transistor is electrically connected to the first clock signal terminal, the first electrode of the eleventh transistor is electrically connected to the second control node, and the second electrode of the eleventh transistor is electrically connected to the second pull-up control node;

[0034] The first end of the first capacitor is electrically connected to the first control node, and the second end of the first capacitor is electrically connected to the first voltage end.

[0035] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a pull-up node control circuit;

[0036] The pull-up node control circuit is electrically connected to the input terminal, the reset terminal, the frame reset terminal, the pull-down node, the pull-up node and the first voltage terminal, respectively, and is used to control the potential of the pull-up node under the control of the input signal provided by the input terminal, control the connection or disconnection between the pull-up node and the first voltage terminal under the control of the reset signal provided by the reset terminal, control the connection or disconnection between the pull-up node and the first voltage terminal under the control of the potential of the pull-down node, and control the connection or disconnection between the pull-up node and the first voltage terminal under the control of the potential of the frame reset signal provided by the frame reset terminal;

[0037] The driving circuit includes a pull-down node; or, the pull-down node includes a first pull-down node and a second pull-down node.

[0038] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a pull-down node control circuit;

[0039] The pull-down node control circuit is electrically connected to the second voltage terminal, the pull-down node, the pull-up node, the reset terminal and the first voltage terminal, respectively, and is used to control the connection between the pull-down node and the second voltage terminal under the control of the second voltage signal provided by the second voltage terminal, control the connection between the pull-down node and the first voltage terminal under the control of the potential of the pull-up node, and control the connection between the pull-down node and the first voltage terminal under the control of the reset signal provided by the reset terminal.

[0040] Optionally, when the pull-down node includes a first pull-down node and a second pull-down node,

[0041] The cascade output circuit includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor and a second capacitor;

[0042] The gate of the twelfth transistor is electrically connected to the first pull-up control node, the first electrode of the twelfth transistor is electrically connected to the cascade output clock signal terminal, and the second electrode of the twelfth transistor is electrically connected to the Nth cascade output terminal;

[0043] The gate of the thirteenth transistor is electrically connected to the first pull-down node, the first electrode of the thirteenth transistor is electrically connected to the Nth cascade output terminal, and the second electrode of the thirteenth transistor is electrically connected to the first voltage terminal;

[0044] The gate of the fourteenth transistor is electrically connected to the second pull-down node, the first electrode of the fourteenth transistor is electrically connected to the Nth cascade output terminal, and the second electrode of the fourteenth transistor is electrically connected to the first voltage terminal;

[0045] A first end of the second capacitor is electrically connected to the first pull-up control node, and a second end of the second capacitor is electrically connected to the cascade output end.

[0046] Optionally, the driving circuit described in at least one embodiment of the present invention further includes an Nth first driving output terminal, an Nth second driving output terminal, a first driving output circuit, and a second driving output circuit;

[0047] The first driver output circuit is electrically connected to the first pull-up control node, the pull-down node, the first first output clock signal terminal, the Nth first driver output terminal and the third voltage terminal respectively, and is used to control the connection or disconnection between the Nth first driver output terminal and the first first output clock signal terminal under the control of the potential of the first pull-up control node, and control the connection or disconnection between the Nth first driver output terminal and the third voltage terminal under the control of the potential of the pull-down node;

[0048] The second driver output circuit is electrically connected to the first pull-up control node, the pull-down node, the first second output clock signal terminal, the Nth second driver output terminal and the third voltage terminal, respectively, and is used to control the connection or disconnection between the Nth second driver output terminal and the first second output clock signal terminal under the control of the potential of the first pull-up control node, and to control the connection or disconnection between the Nth second driver output terminal and the third voltage terminal under the control of the potential of the pull-down node.

[0049] Optionally, the driving circuit described in at least one embodiment of the present invention further includes an N+1th first driving output terminal, an N+1th second driving output terminal, a third driving output circuit and a fourth driving output circuit;

[0050] The third driver output circuit is electrically connected to the second pull-up control node, the pull-down node, the second first output clock signal terminal, the N+1th first driver output terminal and the third voltage terminal respectively, and is used to control the connection or disconnection between the N+1th first driver output terminal and the second first output clock signal terminal under the control of the potential of the second pull-up control node, and control the connection or disconnection between the N+1th first driver output terminal and the third voltage terminal under the control of the potential of the pull-down node;

[0051] The fourth driver output circuit is electrically connected to the second pull-up control node, the pull-down node, the second second output clock signal terminal, the N+1th second driver output terminal and the third voltage terminal, respectively, and is used to control the connection or disconnection between the N+1th second driver output terminal and the second second output clock signal terminal under the control of the potential of the second pull-up control node, and to control the connection or disconnection between the N+1th second driver output terminal and the third voltage terminal under the control of the potential of the pull-down node.

[0052] Optionally, when the pull-down node includes a first pull-down node and a second pull-down node,

[0053] The first drive output circuit includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor and a third capacitor;

[0054] The gate of the fifteenth transistor is electrically connected to the first pull-up control node, the first electrode of the fifteenth transistor is electrically connected to the first first output clock signal terminal, and the second electrode of the fifteenth transistor is electrically connected to the Nth first driving output terminal;

[0055] The gate of the sixteenth transistor is electrically connected to the first pull-down node, the first electrode of the sixteenth transistor is electrically connected to the Nth first driving output terminal, and the second electrode of the sixteenth transistor is electrically connected to the third voltage terminal;

[0056] The gate of the seventeenth transistor is electrically connected to the second pull-down node, the first electrode of the seventeenth transistor is electrically connected to the Nth first driving output terminal, and the second electrode of the seventeenth transistor is electrically connected to the third voltage terminal;

[0057] A first end of the third capacitor is electrically connected to the first pull-up control node, and a second end of the third capacitor is electrically connected to the Nth first driving output terminal;

[0058] The second driving output circuit includes an eighteenth transistor, a nineteenth transistor, a twentieth transistor and a fourth capacitor;

[0059] The gate of the eighteenth transistor is electrically connected to the first pull-up control node, the first electrode of the eighteenth transistor is electrically connected to the first second output clock signal terminal, and the second electrode of the eighteenth transistor is electrically connected to the Nth second driving output terminal;

[0060] The gate of the nineteenth transistor is electrically connected to the first pull-down node, the first electrode of the nineteenth transistor is electrically connected to the Nth second driving output terminal, and the second electrode of the nineteenth transistor is electrically connected to the third voltage terminal;

[0061] The gate of the 20th transistor is electrically connected to the second pull-down node, the first electrode of the 20th transistor is electrically connected to the Nth second driving output terminal, and the second electrode of the 20th transistor is electrically connected to the third voltage terminal;

[0062] A first end of the fourth capacitor is electrically connected to the first pull-up control node, and a second end of the fourth capacitor is electrically connected to the Nth second driving output terminal.

[0063] Optionally, when the pull-down node includes a first pull-down node and a second pull-down node,

[0064] The third driving output circuit includes a twenty-first transistor, a twenty-second transistor, a twenty-third transistor and a fifth capacitor;

[0065] The gate of the 21st transistor is electrically connected to the second pull-up control node, the first electrode of the 21st transistor is electrically connected to the second first output clock signal terminal, and the second electrode of the 21st transistor is electrically connected to the N+1th first driving output terminal;

[0066] The gate of the 22nd transistor is electrically connected to the first pull-down node, the first electrode of the 22nd transistor is electrically connected to the N+1th first driving output terminal, and the second electrode of the 22nd transistor is electrically connected to the third voltage terminal;

[0067] A gate of the twenty-third transistor is electrically connected to the second pull-down node, a first electrode of the twenty-third transistor is electrically connected to the N+1th first driving output terminal, and a second electrode of the twenty-third transistor is electrically connected to the third voltage terminal;

[0068] The first end of the fifth capacitor is electrically connected to the second pull-up control node, and the second end of the fifth capacitor is electrically connected to the N+1th first driving output terminal;

[0069] The fourth driving output circuit includes a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor and a sixth capacitor;

[0070] The gate of the 24th transistor is electrically connected to the second pull-up control node, the first electrode of the 24th transistor is electrically connected to the second second output clock signal terminal, and the second electrode of the 24th transistor is electrically connected to the N+1th second driving output terminal;

[0071] The gate of the 25th transistor is electrically connected to the first pull-down node, the first electrode of the 25th transistor is electrically connected to the N+1th second driving output terminal, and the second electrode of the 25th transistor is electrically connected to the third voltage terminal;

[0072] The gate of the 26th transistor is electrically connected to the second pull-down node, the first electrode of the 26th transistor is electrically connected to the N+1th second driving output terminal, and the second electrode of the 26th transistor is electrically connected to the third voltage terminal;

[0073] A first end of the sixth capacitor is electrically connected to the second pull-up control node, and a second end of the sixth capacitor is electrically connected to the N+1th second driving output terminal.

[0074] Optionally, when the pull-down node includes a first pull-down node and a second pull-down node, the pull-up node control circuit includes a twenty-seventh transistor, a twenty-eighth transistor, a twenty-ninth transistor, a thirtieth transistor, and a thirty-first transistor;

[0075] The gate electrode of the twenty-seventh transistor and the first electrode of the twenty-seventh transistor are both electrically connected to the input terminal, and the second electrode of the twenty-seventh transistor is electrically connected to the pull-up node;

[0076] The gate of the 28th transistor is electrically connected to the frame reset terminal, the first electrode of the 28th transistor is electrically connected to the pull-up node, and the second electrode of the 28th transistor is electrically connected to the first voltage terminal;

[0077] The gate of the 29th transistor is electrically connected to the reset terminal, the first electrode of the 29th transistor is electrically connected to the pull-up node, and the second electrode of the 29th transistor is electrically connected to the first voltage terminal;

[0078] The gate of the 30th transistor is electrically connected to the first pull-down node, the first electrode of the 30th transistor is electrically connected to the pull-up node, and the second electrode of the 30th transistor is electrically connected to the first voltage terminal;

[0079] A gate of the thirty-first transistor is electrically connected to the second pull-down node, a first electrode of the thirty-first transistor is electrically connected to the pull-up node, and a second electrode of the thirty-first transistor is electrically connected to the first voltage terminal.

[0080] Optionally, the pull-down node control circuit includes a thirty-second transistor, a thirty-third transistor and a thirty-fourth transistor;

[0081] The gate electrode of the thirty-second transistor and the first electrode of the thirty-second transistor are both electrically connected to the second voltage terminal, and the second electrode of the thirty-second transistor is electrically connected to the pull-down node;

[0082] The gate of the thirty-third transistor is electrically connected to the pull-up node, the first electrode of the thirty-third transistor is electrically connected to the pull-down node, and the second electrode of the thirty-third transistor is electrically connected to the first voltage terminal;

[0083] A gate of the thirty-fourth transistor is electrically connected to the reset terminal, a first electrode of the thirty-fourth transistor is electrically connected to the pull-down node, and a second electrode of the thirty-fourth transistor is electrically connected to the first voltage terminal.

[0084] Optionally, the pull-down node includes a first pull-down node and a second pull-down node; the second voltage terminal includes a first control voltage terminal and a second control voltage terminal;

[0085] The pull-down node control circuit includes a thirty-second transistor, a thirty-third transistor, a thirty-fourth transistor, a thirty-fifth transistor, a thirty-sixth transistor, and a thirty-seventh transistor;

[0086] The gate electrode of the thirty-second transistor and the first electrode of the thirty-second transistor are both electrically connected to the first control voltage terminal, and the second electrode of the thirty-second transistor is electrically connected to the first pull-down node;

[0087] The gate of the thirty-third transistor is electrically connected to the pull-up node, the first electrode of the thirty-third transistor is electrically connected to the first pull-down node, and the second electrode of the thirty-third transistor is electrically connected to the first voltage terminal;

[0088] The gate of the thirty-fourth transistor is electrically connected to the reset terminal, the first electrode of the thirty-fourth transistor is electrically connected to the first pull-down node, and the second electrode of the thirty-fourth transistor is electrically connected to the first voltage terminal;

[0089] The gate electrode of the thirty-fifth transistor and the first electrode of the thirty-fifth transistor are both electrically connected to the second control voltage terminal, and the second electrode of the thirty-fifth transistor is electrically connected to the second pull-down node;

[0090] The gate of the thirty-sixth transistor is electrically connected to the pull-up node, the first electrode of the thirty-sixth transistor is electrically connected to the second pull-down node, and the second electrode of the thirty-sixth transistor is electrically connected to the first voltage terminal;

[0091] A gate of the thirty-seventh transistor is electrically connected to the reset terminal, a first electrode of the thirty-seventh transistor is electrically connected to the second pull-down node, and a second electrode of the thirty-seventh transistor is electrically connected to the first voltage terminal.

[0092] An embodiment of the present invention further provides a display device, comprising the above-mentioned driving circuit.

[0093] The driving circuit and the display device described in the embodiment of the present invention are provided with a first isolation circuit and a second isolation circuit to avoid mutual interference between the first pull-up control node and the second pull-up control node when two rows of pixel circuits are driven by one driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0094] Figure 1 is a structural diagram of a driving circuit according to an embodiment of the present invention;

[0095] Figure 2 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0096] Figure 3 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0097] Figure 4 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0098] Figure 5 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0099] Figure 6 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0100] Figure 7 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0101] Figure 8 yes Figure 7 An operation timing diagram of at least one embodiment of the driving circuit shown;

[0102] Fig. 9 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0103] Fig.10 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0104] Fig.11 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0105] Fig.12 is a schematic diagram of a first four-stage driving circuit included in at least one embodiment of a driving module including the driving circuit described in an embodiment of the present invention;

[0106] Fig.13 yes Fig.12 The working timing diagram of at least one embodiment of the driving module shown. DETAILED DESCRIPTION

[0107] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0108] The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two electrodes of the transistor except the gate, one electrode is called the first electrode and the other electrode is called the second electrode.

[0109] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0110] The driving circuit described in the embodiment of the present invention includes a pull-up node, a first pull-up control node, a second pull-up control node, a first isolation circuit and a second isolation circuit;

[0111] The first isolation circuit is electrically connected to the first isolation control terminal, the pull-up node and the first pull-up control node respectively, and is used to control the connection or disconnection between the pull-up node and the first pull-up control node under the control of the first isolation control signal provided by the first isolation control terminal;

[0112] The second isolation circuit is electrically connected to the second isolation control terminal, the pull-up node and the second pull-up control node respectively, and is used to control the connection or disconnection between the pull-up node and the second pull-up control node under the control of a second isolation control signal provided by the second isolation control terminal.

[0113] The driving circuit described in the embodiment of the present invention is provided with a first isolation circuit and a second isolation circuit so as to avoid mutual interference between the first pull-up control node and the second pull-up control node when two rows of pixel circuits are driven by one driving circuit, wherein the first pull-up control node may be a control node for controlling the output of a driving signal provided to one row of pixel circuits in the two rows, and the second pull-up control node is a control node for controlling the output of a driving signal provided to another row of pixel circuits in the two rows, thereby eliminating interference between the two rows of output units.

[0114] In at least one embodiment of the present invention, one of the two rows of output units may include a first drive output circuit and a second drive output circuit, and the other of the two rows of output units may include a third drive output circuit and a fourth drive output circuit.

[0115] like Figure 1 As shown, the driving circuit according to the embodiment of the present invention includes a pull-up node Q(N), a first pull-up control node Q1(N), a second pull-up control node Q2(N), a first isolation circuit 11 and a second isolation circuit 12;

[0116] The first isolation circuit 11 is electrically connected to the first isolation control terminal G1, the pull-up node Q(N) and the first pull-up control node Q1(N) respectively, and is used to control the connection or disconnection between the pull-up node Q(N) and the first pull-up control node Q1(N) under the control of the first isolation control signal provided by the first isolation control terminal G1;

[0117] The second isolation circuit 12 is electrically connected to the second isolation control terminal G2, the pull-up node Q(N) and the second pull-up control node Q2(N), respectively, and is used to control the connection or disconnection between the pull-up node Q(N) and the second pull-up control node Q2(N) under the control of the second isolation control signal provided by the second isolation control terminal G2.

[0118] Optionally, the first isolation circuit includes a first transistor, and the second isolation circuit includes a second transistor;

[0119] The gate of the first transistor is electrically connected to the first isolation control terminal, the first electrode of the first transistor is electrically connected to the pull-up node, and the second electrode of the first transistor is electrically connected to the first pull-up control node;

[0120] The gate of the second transistor is electrically connected to the second isolation control terminal, the first electrode of the second transistor is electrically connected to the pull-up node, and the second electrode of the first transistor is electrically connected to the second pull-up control node.

[0121] In at least one embodiment of the present invention, the driving circuit may further include an Nth cascade output terminal and a cascade output circuit;

[0122] The cascade output circuit is electrically connected to the Nth cascade output terminal, the first pull-up control node, the pull-down node, the cascade output clock signal terminal, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the Nth cascade output terminal and the cascade output clock signal terminal under the control of the potential of the first pull-up control node, and control the connection or disconnection between the Nth cascade output terminal and the first voltage terminal under the control of the potential of the pull-down node; N is a positive integer;

[0123] The driving circuit includes a pull-down node; or, the pull-down node includes a first pull-down node and a second pull-down node.

[0124] In a specific implementation, the driving circuit may include an Nth cascade output terminal and a cascade output circuit, and the cascade output circuit controls the output of an Nth cascade output signal through the Nth cascade output terminal.

[0125] In at least one embodiment of the present invention, the first voltage terminal may be a first low voltage terminal, but is not limited thereto.

[0126] Optionally, the first isolation control terminal and the second isolation control terminal are reset terminals; or, the first isolation control terminal and the second isolation control terminal are second voltage terminals.

[0127] In at least one embodiment of the present invention, the reset terminal may be the N+6th cascade output terminal, but is not limited thereto. In a specific implementation, the reset terminal may be the N+Mth cascade output terminal, and M may be a positive integer.

[0128] Optionally, the second voltage terminal may be a high voltage terminal, but is not limited thereto.

[0129] like Figure 2 As shown, in Figure 1 Based on the embodiment of the driving circuit shown, the driving circuit according to at least one embodiment of the present invention may further include an Nth cascade output terminal CR(N) and a cascade output circuit 20;

[0130] The cascade output circuit 20 is electrically connected to the Nth cascade output terminal CR(N), the first pull-up control node Q1(N), the first pull-down node QBA, the second pull-down node QBB, the cascade output clock signal terminal CLKDN, and the first voltage terminal V1, respectively, and is used to control the connection or disconnection between the Nth cascade output terminal CR(N) and the cascade output clock signal terminal CLKDN under the control of the potential of the first pull-up control node Q1(N), control the connection or disconnection between the Nth cascade output terminal CR(N) and the first voltage terminal V1 under the control of the potential of the first pull-down node QBA, and control the connection or disconnection between the Nth cascade output terminal CR(N) and the first voltage terminal V1 under the control of the potential of the second pull-down node QBB; N is a positive integer.

[0131] The driving circuit according to at least one embodiment of the present invention may further include a first node control circuit and a second node control circuit;

[0132] The first node control circuit is electrically connected to the input terminal and the first pull-up control node respectively, and is used to control the potential of the first pull-up control node according to an input signal provided by the input terminal;

[0133] The second node control circuit is electrically connected to the input terminal and the second pull-up control node respectively, and is used to control the potential of the second pull-up control node according to an input signal provided by the input terminal.

[0134] In a specific implementation, the driving circuit described in at least one embodiment of the present invention may also include a first node control circuit and a second node control circuit, wherein the first node control circuit controls the potential of the first pull-up control node according to an input signal, and the second node control circuit controls the potential of the second pull-up node according to the input signal.

[0135] In at least one embodiment of the present invention, the input end may be the N-2 th cascade output end, but is not limited thereto.

[0136] In at least one embodiment of the present invention, the first node control circuit is further electrically connected to the frame reset terminal and the first voltage terminal, and is used to control the first pull-up control node to be connected to the first voltage terminal under the control of a frame reset signal provided by the frame reset terminal;

[0137] The second node control circuit is also electrically connected to the frame reset terminal and the first voltage terminal, and is used to control the connection between the second pull-up control node and the first voltage terminal under the control of a frame reset signal provided by the frame reset terminal.

[0138] In a specific implementation, the first node control circuit can also control the potential of the first pull-up control node under the control of a frame reset signal, and the second node control circuit can also control the potential of the second pull-up control node under the control of a frame reset signal.

[0139] like Figure 3 As shown, in Figure 2 Based on at least one embodiment of the driving circuit shown in the figure, the driving circuit according to at least one embodiment of the present invention further includes a first node control circuit 31 and a second node control circuit 32;

[0140] The first node control circuit 31 is electrically connected to the input terminal I1 and the first pull-up control node Q1 (N) respectively, and is used to control the potential of the first pull-up control node Q1 (N) according to the input signal provided by the input terminal I1;

[0141] The second node control circuit 32 is electrically connected to the input terminal I1 and the second pull-up control node Q2 (N) respectively, and is used to control the potential of the second pull-up control node Q2 (N) according to the input signal provided by the input terminal I1;

[0142] The first node control circuit 31 is also electrically connected to the frame reset terminal TRST and the first voltage terminal V1, and is used to control the first pull-up control node Q1 (N) to be connected to the first voltage terminal V1 under the control of the frame reset signal provided by the frame reset terminal TRST;

[0143] The second node control circuit 32 is also electrically connected to the frame reset terminal TRST and the first voltage terminal V1, and is used to control the connection between the second pull-up control node Q2 (N) and the first voltage terminal V1 under the control of the frame reset signal provided by the frame reset terminal TRST.

[0144] Optionally, the first node control circuit includes a third transistor, and the second node control circuit includes a fourth transistor;

[0145] The gate of the third transistor and the first electrode of the third transistor are both electrically connected to the input terminal, and the second electrode of the third transistor is electrically connected to the first pull-up control node;

[0146] The gate of the fourth transistor and the first electrode of the fourth transistor are both electrically connected to the input terminal, and the second electrode of the fourth transistor is electrically connected to the second pull-up control node.

[0147] Optionally, the first node control circuit includes a fifth transistor and a sixth transistor;

[0148] The gate of the fifth transistor is electrically connected to the frame reset terminal, the first electrode of the fifth transistor is electrically connected to the first pull-up control node, and the second electrode of the fifth transistor is electrically connected to the first voltage terminal;

[0149] A gate of the sixth transistor is electrically connected to the frame reset terminal, a first electrode of the sixth transistor is electrically connected to the second pull-up control node, and a second electrode of the sixth transistor is electrically connected to the first voltage terminal.

[0150] The driving circuit according to at least one embodiment of the present invention further includes a first control node control circuit and a second control node control circuit;

[0151] The first control node control circuit is electrically connected to the enable terminal, the enable reset terminal and the first control node respectively, and is used to control the connection between the enable reset terminal and the first control node under the control of the enable signal provided by the enable terminal;

[0152] The second control node control circuit is electrically connected to the first clock signal end, the first control node, the second control node, the pull-up node, the first clock signal end, the second control node, the first pull-up control node and the second pull-up control node, respectively, and is used to control the connection between the first clock signal end and the second control node under the control of the potential of the first control node, and to control the connection between the second control node and the pull-up node under the control of the first clock signal provided by the first clock signal end, control the connection between the second control node and the first pull-up control node under the control of the first clock signal provided by the first clock signal end, and control the connection between the second control node and the second pull-up control node under the control of the first clock signal provided by the first clock signal end.

[0153] Optionally, the enable reset terminal may be an N+2th cascade output terminal, but is not limited thereto.

[0154] In a specific implementation, the driving circuit may also include a first control node control circuit, a second control node control circuit, a first pull-up control node control circuit and a second pull-up control node control circuit, wherein the first control node control circuit controls the connection between the enable reset terminal and the first control node under the control of an enable signal; and the second control node control circuit controls the potential of the second control node under the control of the potential of the first control node and the second clock signal.

[0155] like Figure 4 As shown, in Figure 3 Based on at least one embodiment of the driving circuit shown, the driving circuit according to at least one embodiment of the present invention may further include a first control node control circuit 41 and a second control node control circuit 42;

[0156] The first control node control circuit 41 is electrically connected to the enable terminal OE, the N+2 th cascade output terminal CR(N+2) and the first control node H respectively, and is used to control the connection between the first control node H and the N+2 th cascade output terminal CR(N+2) under the control of the enable signal provided by the enable terminal OE;

[0157] The second control node control circuit 42 is electrically connected to the first clock signal terminal CLKA, the first control node H, the second control node N, the pull-up node Q(N), the first clock signal terminal CLKA, the second control node N, the first pull-up control node Q1(N) and the second pull-up control node Q2(N) respectively, and is used to control the connection between the first clock signal terminal CLKA and the second pull-up control node Q2(N) under the control of the potential of the first control node H, and to control the connection between the second control node N and the pull-up node Q(N) under the control of the first clock signal provided by the first clock signal terminal CLKA, control the connection between the second control node N and the first pull-up control node Q1(N) under the control of the first clock signal provided by the first clock signal terminal CLKA, and control the connection between the second control node N and the second pull-up control node Q2(N) under the control of the first clock signal provided by the first clock signal terminal CLKA.

[0158] Optionally, the first control node control circuit includes a seventh transistor, and the second control node control circuit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a first capacitor;

[0159] The gate of the seventh transistor is electrically connected to the enable terminal, the first electrode of the seventh transistor is electrically connected to the enable reset terminal, and the second electrode of the seventh transistor is electrically connected to the first control node;

[0160] The gate of the eighth transistor is electrically connected to the first control node, the first electrode of the eighth transistor is electrically connected to the first clock signal terminal, and the second electrode of the eighth transistor is electrically connected to the second control node;

[0161] The gate of the ninth transistor is electrically connected to the first clock signal terminal, the first electrode of the ninth transistor is electrically connected to the second control node, and the second electrode of the ninth transistor is electrically connected to the pull-up node;

[0162] The gate of the tenth transistor is electrically connected to the first clock signal terminal, the first electrode of the tenth transistor is electrically connected to the second control node, and the second electrode of the tenth transistor is electrically connected to the first pull-up control node;

[0163] The gate of the eleventh transistor is electrically connected to the first clock signal terminal, the first electrode of the eleventh transistor is electrically connected to the second control node, and the second electrode of the eleventh transistor is electrically connected to the second pull-up control node;

[0164] The first end of the first capacitor is electrically connected to the first control node, and the second end of the first capacitor is electrically connected to the first voltage end.

[0165] The driving circuit described in at least one embodiment of the present invention may further include a pull-up node control circuit;

[0166] The pull-up node control circuit is electrically connected to the input terminal, the reset terminal, the frame reset terminal, the pull-down node, the pull-up node and the first voltage terminal, respectively, and is used to control the potential of the pull-up node under the control of the input signal provided by the input terminal, control the connection or disconnection between the pull-up node and the first voltage terminal under the control of the reset signal provided by the reset terminal, control the connection or disconnection between the pull-up node and the first voltage terminal under the control of the potential of the pull-down node, and control the connection or disconnection between the pull-up node and the first voltage terminal under the control of the potential of the frame reset signal provided by the frame reset terminal;

[0167] The driving circuit includes a pull-down node; or, the pull-down node includes a first pull-down node and a second pull-down node.

[0168] In a specific implementation, the driving circuit may further include a pull-up node control circuit, which controls the potential of the pull-up node under the control of an input signal, a reset signal, the potential of the pull-down node and a frame reset signal.

[0169] The driving circuit described in at least one embodiment of the present invention may further include a pull-down node control circuit;

[0170] The pull-down node control circuit is electrically connected to the second voltage terminal, the pull-down node, the pull-up node, the reset terminal and the first voltage terminal, respectively, and is used to control the connection between the pull-down node and the second voltage terminal under the control of the second voltage signal provided by the second voltage terminal, control the connection between the pull-down node and the first voltage terminal under the control of the potential of the pull-up node, and control the connection between the pull-down node and the first voltage terminal under the control of the reset signal provided by the reset terminal.

[0171] In at least one embodiment of the present invention, when the pull-down node includes a first pull-down node and a second pull-down node;

[0172] The pull-down node control circuit may be electrically connected to the second voltage terminal, the first pull-down node, the pull-up node, the reset terminal and the first voltage terminal, respectively, and is used to control the first pull-down node to be connected to the second voltage terminal under the control of the second voltage signal provided by the second voltage terminal, control the first pull-down node to be connected to the first voltage terminal under the control of the potential of the pull-up node, and control the first pull-down node to be connected to the first voltage terminal under the control of the reset signal provided by the reset terminal; or,

[0173] The pull-down node control circuit may be electrically connected to the second voltage terminal, the second pull-down node, the pull-up node, the reset terminal and the first voltage terminal, respectively, and is used to control the second pull-down node to be connected to the second voltage terminal under the control of the second voltage signal provided by the second voltage terminal, control the second pull-down node to be connected to the first voltage terminal under the control of the potential of the pull-up node, and control the second pull-down node to be connected to the first voltage terminal under the control of the reset signal provided by the reset terminal; or,

[0174] The pull-down node control circuit can be electrically connected to the first control voltage terminal, the second control voltage terminal, the first pull-down node, the second pull-down node, the pull-up node, the reset terminal and the first voltage terminal, respectively, and is used to control the connection between the first pull-down node and the second voltage terminal under the control of the first control voltage provided by the first control voltage terminal, control the connection between the first pull-down node and the first voltage terminal under the control of the potential of the pull-up node, control the connection between the first pull-down node and the first voltage terminal under the control of the reset signal provided by the reset terminal, control the connection between the second pull-down node and the second voltage terminal under the control of the second control voltage provided by the second control voltage terminal, control the connection between the second pull-down node and the first voltage terminal under the control of the potential of the pull-up node, and control the connection between the second pull-down node and the first voltage terminal under the control of the reset signal provided by the reset terminal.

[0175] In a specific implementation, the first control voltage provided by the first control voltage terminal and the second control voltage provided by the second control voltage terminal can be inverted to each other. When the first control voltage is a high voltage, the second control voltage can be a low voltage; when the first control voltage is a low voltage, the second control voltage terminal can be a high voltage; in this way, the first pull-down node and the second pull-down node can work alternately, and the output transistor controlled by the first pull-down node and the output transistor controlled by the second pull-down node can work alternately.

[0176] like Figure 5 As shown, in Figure 3Based on at least one embodiment of the driving circuit shown, the driving circuit according to at least one embodiment of the present invention may further include a pull-up node control circuit 51 and a pull-down node control circuit 52;

[0177] The pull-up node control circuit 51 is electrically connected to the input terminal I1, the reset terminal R1, the frame reset terminal TRST, the first pull-down node QBA, the second pull-down node QBB, the pull-up node Q(N) and the first voltage terminal V1, respectively, and is used to control the potential of the pull-up node Q(N) under the control of the input signal provided by the input terminal I1, control the connection or disconnection between the pull-up node Q(N) and the first voltage terminal V1 under the control of the reset signal provided by the reset terminal R1, control the connection or disconnection between the pull-up node Q(N) and the first voltage terminal V1 under the control of the potential of the first pull-down node QBA, control the connection or disconnection between the pull-up node Q(N) and the first voltage terminal V1 under the control of the potential of the second pull-down node QBB, and control the connection or disconnection between the pull-up node Q(N) and the first voltage terminal V1 under the control of the potential of the frame reset signal provided by the frame reset terminal TRST;

[0178] The pull-down node control circuit 52 is electrically connected to the second voltage terminal V2, the first pull-down node QBA, the pull-up node Q(N), the reset terminal R1 and the first voltage terminal V1, respectively, and is used to control the connection between the first pull-down node QBA and the second voltage terminal V2 under the control of the second voltage signal provided by the second voltage terminal V2, control the connection between the first pull-down node QBA and the first voltage terminal V1 under the control of the potential of the pull-up node Q(N), and control the connection between the second pull-down node and the first voltage terminal V1 under the control of the reset signal provided by the reset terminal R1.

[0179] Optionally, the cascade output circuit includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor and a second capacitor;

[0180] The gate of the twelfth transistor is electrically connected to the first pull-up control node, the first electrode of the twelfth transistor is electrically connected to the cascade output clock signal terminal, and the second electrode of the twelfth transistor is electrically connected to the Nth cascade output terminal;

[0181] The gate of the thirteenth transistor is electrically connected to the first pull-down node, the first electrode of the thirteenth transistor is electrically connected to the Nth cascade output terminal, and the second electrode of the thirteenth transistor is electrically connected to the first voltage terminal;

[0182] The gate of the fourteenth transistor is electrically connected to the second pull-down node, the first electrode of the fourteenth transistor is electrically connected to the Nth cascade output terminal, and the second electrode of the fourteenth transistor is electrically connected to the first voltage terminal;

[0183] A first end of the second capacitor is electrically connected to the first pull-up control node, and a second end of the second capacitor is electrically connected to the Nth cascade output end.

[0184] The driving circuit described in at least one embodiment of the present invention further includes an Nth first driving output terminal, an Nth second driving output terminal, a first driving output circuit and a second driving output circuit;

[0185] The first driver output circuit is electrically connected to the first pull-up control node, the first pull-down node, the second pull-down node, the first first output clock signal terminal, the Nth first driver output terminal and the third voltage terminal respectively, and is used to control the connection or disconnection between the Nth first driver output terminal and the first first output clock signal terminal under the control of the potential of the first pull-up control node, control the connection or disconnection between the Nth first driver output terminal and the third voltage terminal under the control of the potential of the first pull-down node, and control the connection or disconnection between the Nth first driver output terminal and the third voltage terminal under the control of the potential of the second pull-down node;

[0186] The second driver output circuit is electrically connected to the first pull-up control node, the first pull-down node, the second pull-down node, the first second output clock signal terminal, the Nth second driver output terminal and the third voltage terminal, respectively, and is used to control the connection or disconnection between the Nth second driver output terminal and the first second output clock signal terminal under the control of the potential of the first pull-up control node, control the connection or disconnection between the Nth second driver output terminal and the third voltage terminal under the control of the potential of the first pull-down node, and control the connection or disconnection between the Nth second driver output terminal and the third voltage terminal under the control of the potential of the second pull-down node.

[0187] In a specific implementation, the driving circuit may further include an Nth first driving output terminal, an Nth second driving output terminal, a first driving output circuit, and a second driving output circuit, wherein the first driving output circuit controls the Nth first driving output terminal to output an Nth first driving signal under the control of the potential of the first pull-up control node, the potential of the first pull-down node, and the potential of the second pull-down node;

[0188] The second driving output circuit controls the Nth second driving output terminal to output the Nth second driving signal under the control of the potential of the first pull-up control node, the potential of the first pull-down node and the potential of the second pull-down node.

[0189] The driving circuit described in at least one embodiment of the present invention further includes an N+1th first driving output terminal, an N+1th second driving output terminal, a third driving output circuit and a fourth driving output circuit;

[0190] The third driver output circuit is electrically connected to the second pull-up control node, the first pull-down node, the second pull-down node, the second first output clock signal terminal, the N+1th first driver output terminal and the third voltage terminal, respectively, and is used to control the connection or disconnection between the N+1th first driver output terminal and the second first output clock signal terminal under the control of the potential of the second pull-up control node, control the connection or disconnection between the N+1th first driver output terminal and the third voltage terminal under the control of the potential of the first pull-down node, and control the connection or disconnection between the N+1th first driver output terminal and the third voltage terminal under the control of the potential of the second pull-down node;

[0191] The fourth driver output circuit is electrically connected to the second pull-up control node, the first pull-down node, the second pull-down node, the second second output clock signal terminal, the N+1th second driver output terminal and the third voltage terminal, respectively, and is used to control the connection or disconnection between the N+1th second driver output terminal and the second second output clock signal terminal under the control of the potential of the second pull-up control node, control the connection or disconnection between the N+1th second driver output terminal and the third voltage terminal under the control of the potential of the first pull-down node, and control the connection or disconnection between the N+1th second driver output terminal and the third voltage terminal under the control of the potential of the second pull-down node.

[0192] In a specific implementation, the drive circuit may further include a third drive output circuit and a fourth drive output circuit; the third drive output circuit controls the N+1th first drive output terminal to output the N+1th first drive signal under the control of the potential of the second pull-up control node, the potential of the first pull-down node and the potential of the second pull-down node, and the fourth drive output circuit controls the N+1th second drive output terminal to output the N+1th second drive signal under the control of the potential of the second pull-up control node, the potential of the first pull-down node and the potential of the second pull-down node.

[0193] like Figure 6 As shown, in Figure 5 Based on at least one embodiment of the driving circuit shown in FIG. 1 , the driving circuit described in at least one embodiment of the present invention further includes an Nth first driving output terminal G1(N), an Nth second driving output terminal G2(N), a first driving output circuit 61, a second driving output circuit 62, an N+1th first driving output terminal G1(N+1), an N+1th second driving output terminal G2(N+1), a third driving output circuit 63, and a fourth driving output circuit 64;

[0194] The first driver output circuit 61 is electrically connected to the first pull-up control node Q1(N), the first pull-down node QBA, the second pull-down node QBB, the first first output clock signal terminal CLKEN, the Nth first driver output terminal G1(N) and the third voltage terminal V3, respectively, and is used to control the connection or disconnection between the Nth first driver output terminal G1(N) and the first first output clock signal terminal CLKEN under the control of the potential of the first pull-up control node Q1(N), control the connection or disconnection between the Nth first driver output terminal G1(N) and the third voltage terminal V3 under the control of the potential of the first pull-down node QBA, and control the connection or disconnection between the Nth first driver output terminal G1(N) and the third voltage terminal V3 under the control of the potential of the second pull-down node QBB;

[0195] The second driver output circuit 62 is electrically connected to the first pull-up control node Q1(N), the first pull-down node QBA, the second pull-down node QBB, the first second output clock signal terminal CLKFN, the Nth second driver output terminal G2(N) and the third voltage terminal V3, respectively, and is used to control the connection or disconnection between the Nth second driver output terminal G2(N) and the first second output clock signal terminal CLKFN under the control of the potential of the first pull-up control node Q1(N), control the connection or disconnection between the Nth second driver output terminal G2(N) and the third voltage terminal V3 under the control of the potential of the first pull-down node QBA, and control the connection or disconnection between the Nth second driver output terminal G2(N) and the third voltage terminal V3 under the control of the potential of the second pull-down node QBB;

[0196] The third driver output circuit 63 is electrically connected to the second pull-up control node Q2(N), the first pull-down node QBA, the second pull-down node QBB, the second first output clock signal terminal CLKEN+1, the N+1th first driver output terminal G1(N+1) and the third voltage terminal V3, respectively, and is used to control the connection or disconnection between the N+1th first driver output terminal G1(N+1) and the second first output clock signal terminal CLKEN+1 under the control of the potential of the second pull-up control node Q2(N), control the connection or disconnection between the N+1th first driver output terminal G1(N+1) and the third voltage terminal V3 under the control of the potential of the first pull-down node QBA, and control the connection or disconnection between the N+1th first driver output terminal G1(N+1) and the third voltage terminal V3 under the control of the potential of the second pull-down node QBB;

[0197] The fourth driver output circuit 64 is electrically connected to the second pull-up control node Q2(N), the first pull-down node QBA, the second pull-down node QBB, the second second output clock signal terminal CLKFN+1, the N+1th second driver output terminal G2(N+1) and the third voltage terminal V3, respectively, and is used to control the connection or disconnection between the N+1th second driver output terminal G2(N+1) and the second second output clock signal terminal CLKFN+1 under the control of the potential of the second pull-up control node Q2(N), control the connection or disconnection between the N+1th second driver output terminal G2(N+1) and the third voltage terminal V3 under the control of the potential of the first pull-down node QBA, and control the connection or disconnection between the N+1th second driver output terminal G2(N+1) and the third voltage terminal V3 under the control of the potential of the second pull-down node QBB.

[0198] Optionally, the first drive output circuit includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor and a third capacitor;

[0199] The gate of the fifteenth transistor is electrically connected to the first pull-up control node, the first electrode of the fifteenth transistor is electrically connected to the first first output clock signal terminal, and the second electrode of the fifteenth transistor is electrically connected to the Nth first driving output terminal;

[0200] The gate of the sixteenth transistor is electrically connected to the first pull-down node, the first electrode of the sixteenth transistor is electrically connected to the Nth first driving output terminal, and the second electrode of the sixteenth transistor is electrically connected to the third voltage terminal;

[0201] The gate of the seventeenth transistor is electrically connected to the second pull-down node, the first electrode of the seventeenth transistor is electrically connected to the Nth first driving output terminal, and the second electrode of the seventeenth transistor is electrically connected to the third voltage terminal;

[0202] A first end of the third capacitor is electrically connected to the first pull-up control node, and a second end of the third capacitor is electrically connected to the Nth first driving output terminal;

[0203] The second driving output circuit includes an eighteenth transistor, a nineteenth transistor, a twentieth transistor and a fourth capacitor;

[0204] The gate of the eighteenth transistor is electrically connected to the first pull-up control node, the first electrode of the eighteenth transistor is electrically connected to the first second output clock signal terminal, and the second electrode of the eighteenth transistor is electrically connected to the Nth second driving output terminal;

[0205] The gate of the nineteenth transistor is electrically connected to the first pull-down node, the first electrode of the nineteenth transistor is electrically connected to the Nth second driving output terminal, and the second electrode of the nineteenth transistor is electrically connected to the third voltage terminal;

[0206] The gate of the 20th transistor is electrically connected to the second pull-down node, the first electrode of the 20th transistor is electrically connected to the Nth second driving output terminal, and the second electrode of the 20th transistor is electrically connected to the third voltage terminal;

[0207] A first end of the fourth capacitor is electrically connected to the first pull-up control node, and a second end of the fourth capacitor is electrically connected to the Nth second driving output terminal.

[0208] Optionally, the third driving output circuit includes a twenty-first transistor, a twenty-second transistor, a twenty-third transistor and a fifth capacitor;

[0209] The gate of the 21st transistor is electrically connected to the second pull-up control node, the first electrode of the 21st transistor is electrically connected to the second first output clock signal terminal, and the second electrode of the 21st transistor is electrically connected to the N+1th first driving output terminal;

[0210] The gate of the 22nd transistor is electrically connected to the first pull-down node, the first electrode of the 22nd transistor is electrically connected to the N+1th first driving output terminal, and the second electrode of the 22nd transistor is electrically connected to the third voltage terminal;

[0211] A gate of the twenty-third transistor is electrically connected to the second pull-down node, a first electrode of the twenty-third transistor is electrically connected to the N+1th first driving output terminal, and a second electrode of the twenty-third transistor is electrically connected to the third voltage terminal;

[0212] The first end of the fifth capacitor is electrically connected to the second pull-up control node, and the second end of the fifth capacitor is electrically connected to the N+1th first driving output terminal;

[0213] The fourth driving output circuit includes a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor and a sixth capacitor;

[0214] The gate of the 24th transistor is electrically connected to the second pull-up control node, the first electrode of the 24th transistor is electrically connected to the second second output clock signal terminal, and the second electrode of the 24th transistor is electrically connected to the N+1th second driving output terminal;

[0215] The gate of the 25th transistor is electrically connected to the first pull-down node, the first electrode of the 25th transistor is electrically connected to the N+1th second driving output terminal, and the second electrode of the 25th transistor is electrically connected to the third voltage terminal;

[0216] The gate of the 26th transistor is electrically connected to the second pull-down node, the first electrode of the 26th transistor is electrically connected to the N+1th second driving output terminal, and the second electrode of the 26th transistor is electrically connected to the third voltage terminal;

[0217] A first end of the sixth capacitor is electrically connected to the second pull-up control node, and a second end of the sixth capacitor is electrically connected to the N+1th second driving output terminal.

[0218] Optionally, when the pull-down node includes a first pull-down node and a second pull-down node, the pull-up node control circuit includes a twenty-seventh transistor, a twenty-eighth transistor, a twenty-ninth transistor, a thirtieth transistor, and a thirty-first transistor;

[0219] The gate electrode of the twenty-seventh transistor and the first electrode of the twenty-seventh transistor are both electrically connected to the input terminal, and the second electrode of the twenty-seventh transistor is electrically connected to the pull-up node;

[0220] The gate of the 28th transistor is electrically connected to the frame reset terminal, the first electrode of the 28th transistor is electrically connected to the pull-up node, and the second electrode of the 28th transistor is electrically connected to the first voltage terminal;

[0221] The gate of the 29th transistor is electrically connected to the reset terminal, the first electrode of the 29th transistor is electrically connected to the pull-up node, and the second electrode of the 29th transistor is electrically connected to the first voltage terminal;

[0222] The gate of the 30th transistor is electrically connected to the first pull-down node, the first electrode of the 30th transistor is electrically connected to the pull-up node, and the second electrode of the 30th transistor is electrically connected to the first voltage terminal;

[0223] A gate of the thirty-first transistor is electrically connected to the second pull-down node, a first electrode of the thirty-first transistor is electrically connected to the pull-up node, and a second electrode of the thirty-first transistor is electrically connected to the first voltage terminal.

[0224] Optionally, the pull-down node control circuit includes a thirty-second transistor, a thirty-third transistor and a thirty-fourth transistor;

[0225] The gate electrode of the thirty-second transistor and the first electrode of the thirty-second transistor are both electrically connected to the second voltage terminal, and the second electrode of the thirty-second transistor is electrically connected to the pull-down node;

[0226] The gate of the thirty-third transistor is electrically connected to the pull-up node, the first electrode of the thirty-third transistor is electrically connected to the pull-down node, and the second electrode of the thirty-third transistor is electrically connected to the first voltage terminal;

[0227] A gate of the thirty-fourth transistor is electrically connected to the reset terminal, a first electrode of the thirty-fourth transistor is electrically connected to the pull-down node, and a second electrode of the thirty-fourth transistor is electrically connected to the first voltage terminal.

[0228] Optionally, the pull-down node includes a first pull-down node and a second pull-down node; the second voltage terminal includes a first control voltage terminal and a second control voltage terminal;

[0229] The pull-down node control circuit includes a thirty-second transistor, a thirty-third transistor, a thirty-fourth transistor, a thirty-fifth transistor, a thirty-sixth transistor, and a thirty-seventh transistor;

[0230] The gate electrode of the thirty-second transistor and the first electrode of the thirty-second transistor are both electrically connected to the first control voltage terminal, and the second electrode of the thirty-second transistor is electrically connected to the first pull-down node;

[0231] The gate of the thirty-third transistor is electrically connected to the pull-up node, the first electrode of the thirty-third transistor is electrically connected to the first pull-down node, and the second electrode of the thirty-third transistor is electrically connected to the first voltage terminal;

[0232] The gate of the thirty-fourth transistor is electrically connected to the reset terminal, the first electrode of the thirty-fourth transistor is electrically connected to the first pull-down node, and the second electrode of the thirty-fourth transistor is electrically connected to the first voltage terminal;

[0233] The gate electrode of the thirty-fifth transistor and the first electrode of the thirty-fifth transistor are both electrically connected to the second control voltage terminal, and the second electrode of the thirty-fifth transistor is electrically connected to the second pull-down node;

[0234] The gate of the thirty-sixth transistor is electrically connected to the pull-up node, the first electrode of the thirty-sixth transistor is electrically connected to the second pull-down node, and the second electrode of the thirty-sixth transistor is electrically connected to the first voltage terminal;

[0235] A gate of the thirty-seventh transistor is electrically connected to the reset terminal, a first electrode of the thirty-seventh transistor is electrically connected to the second pull-down node, and a second electrode of the thirty-seventh transistor is electrically connected to the first voltage terminal.

[0236] In a specific implementation, the second voltage terminal may also include a first control voltage terminal and a second control voltage terminal, but is not limited thereto.

[0237] like Figure 7 As shown, in Figure 6Based on at least one embodiment of the driving circuit shown, the first isolation circuit includes a first transistor M1, and the second isolation circuit includes a second transistor M2;

[0238] The gate of the first transistor M1 is electrically connected to the N+6th cascade output terminal CR(N+6), the source of the first transistor M1 is electrically connected to the pull-up node Q(N), and the drain of the first transistor M1 is electrically connected to the first pull-up control node Q1(N);

[0239] The gate of the second transistor M2 is electrically connected to the N+6th cascade output terminal CR(N+6), the source of the second transistor M2 is electrically connected to the pull-up node Q(N), and the second electrode of the first transistor is electrically connected to the second pull-up control node Q2(N);

[0240] The first node control circuit includes a third transistor M3, and the second node control circuit includes a fourth transistor M4;

[0241] The gate of the third transistor M3 and the source of the third transistor M3 are both electrically connected to the N-2 th cascade output terminal CR(N-2), and the drain of the third transistor M3 is electrically connected to the first pull-up control node Q1(N);

[0242] The gate of the fourth transistor M4 and the source of the fourth transistor M4 are both electrically connected to the N-2 th cascade output terminal CR(N-2), and the drain of the fourth transistor M4 is electrically connected to the second pull-up control node Q2(N);

[0243] The first node control circuit includes a fifth transistor M5 and a sixth transistor M6;

[0244] The gate of the fifth transistor M5 is electrically connected to the frame reset terminal TRST, the source of the fifth transistor M5 is electrically connected to the first pull-up control node Q1(N), and the drain of the fifth transistor M5 is electrically connected to the first low voltage terminal VGL1;

[0245] The gate of the sixth transistor M6 is electrically connected to the frame reset terminal TRST, the source of the sixth transistor M6 is electrically connected to the second pull-up control node Q2 (N), and the drain of the sixth transistor M6 is electrically connected to the first low voltage terminal VGL1;

[0246] The cascade output circuit includes a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14 and a second capacitor C2;

[0247] The gate of the twelfth transistor M12 is electrically connected to the first pull-up control node Q1(N), the source of the twelfth transistor M12 is electrically connected to the cascade output clock signal terminal CR(N), and the drain of the twelfth transistor M12 is electrically connected to the Nth cascade output terminal CR(N);

[0248] The gate of the thirteenth transistor M13 is electrically connected to the first pull-down node QBA, the source of the thirteenth transistor M13 is electrically connected to the Nth cascade output terminal CR(N), and the drain of the thirteenth transistor M13 is electrically connected to the first low voltage terminal VGL1;

[0249] The gate of the fourteenth transistor M14 is electrically connected to the second pull-down node QBB, the source of the fourteenth transistor M14 is electrically connected to the Nth cascade output terminal CR(N), and the drain of the fourteenth transistor M14 is electrically connected to the first low voltage terminal VGL1;

[0250] A first end of the second capacitor C2 is electrically connected to the first pull-up control node Q1(N), and a second end of the second capacitor C2 is electrically connected to the Nth cascade output terminal CR(N);

[0251] The first driving output circuit includes a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17 and a third capacitor C3;

[0252] The gate of the fifteenth transistor M15 is electrically connected to the first pull-up control node Q1(N), the source of the fifteenth transistor M15 is electrically connected to the first first output clock signal terminal CLKEN, and the drain of the fifteenth transistor M15 is electrically connected to the Nth first driving output terminal G1(N);

[0253] The gate of the sixteenth transistor M16 is electrically connected to the first pull-down node QBA, the source of the sixteenth transistor M16 is electrically connected to the Nth first driving output terminal G1(N), and the drain of the sixteenth transistor M16 is electrically connected to the second low voltage terminal VGL2;

[0254] The gate of the seventeenth transistor M17 is electrically connected to the second pull-down node QBB, the source of the seventeenth transistor M17 is electrically connected to the Nth first driving output terminal G1(N), and the drain of the seventeenth transistor M17 is electrically connected to the second low voltage terminal VGL2;

[0255] A first end of the third capacitor C3 is electrically connected to the first pull-up control node Q1(N), and a second end of the third capacitor C3 is electrically connected to the Nth first driving output terminal G1(N);

[0256] The second driving output circuit includes an eighteenth transistor M18, a nineteenth transistor M19, a twentieth transistor M20 and a fourth capacitor C4;

[0257] The gate of the eighteenth transistor M18 is electrically connected to the first pull-up control node Q1 (N), the source of the eighteenth transistor M18 is electrically connected to the first second output clock signal terminal CLKFN, and the drain of the eighteenth transistor M18 is electrically connected to the Nth second driving output terminal G2 (N);

[0258] The gate of the nineteenth transistor M19 is electrically connected to the first pull-down node QBA, the source of the nineteenth transistor M19 is electrically connected to the Nth second driving output terminal G2(N), and the drain of the nineteenth transistor M19 is electrically connected to the second low voltage terminal VGL2;

[0259] The gate of the 20th transistor M20 is electrically connected to the second pull-down node QBB, the source of the 20th transistor M20 is electrically connected to the Nth second driving output terminal G2(N), and the drain of the 20th transistor M20 is electrically connected to the second low voltage terminal VGL2;

[0260] A first end of the fourth capacitor C4 is electrically connected to the first pull-up control node Q1 (N), and a second end of the fourth capacitor is electrically connected to the Nth second driving output terminal G2 (N);

[0261] The third driving output circuit includes a twenty-first transistor M21, a twenty-second transistor M22, a twenty-third transistor M23 and a fifth capacitor C5;

[0262] The gate of the 21st transistor M21 is electrically connected to the second pull-up control node Q2(N), the source of the 21st transistor M21 is electrically connected to the second first output clock signal terminal CLKEN+1, and the drain of the 21st transistor M21 is electrically connected to the N+1th first driving output terminal G1(N+1);

[0263] A gate of the 22nd transistor M22 is electrically connected to the first pull-down node QBA, a source of the 22nd transistor M22 is electrically connected to the N+1th first driving output terminal G1(N+1), and a drain of the 22nd transistor M22 is electrically connected to the second low voltage terminal VGL2;

[0264] A gate of the 23rd transistor M23 is electrically connected to the second pull-down node QBB, a source of the 23rd transistor M23 is electrically connected to the N+1th first driving output terminal G1(N+1), and a drain of the 23rd transistor M23 is electrically connected to the second low voltage terminal VGL2;

[0265] A first end of the fifth capacitor C5 is electrically connected to the second pull-up control node Q2(N), and a second end of the fifth capacitor is electrically connected to the N+1th first driving output terminal G1(N+1);

[0266] The fourth driving output circuit includes a twenty-fourth transistor M24, a twenty-fifth transistor M25, a twenty-sixth transistor M26 and a sixth capacitor C6;

[0267] The gate of the 24th transistor M24 is electrically connected to the second pull-up control node Q2(N), the source of the 24th transistor M24 is electrically connected to the second second output clock signal terminal CLKFN+1, and the drain of the 24th transistor M24 is electrically connected to the N+1th second driving output terminal G2(N+1);

[0268] A gate of the twenty-fifth transistor M25 is electrically connected to the first pull-down node QBA, a source of the twenty-fifth transistor M25 is electrically connected to the N+1th second driving output terminal G2(N+1), and a drain of the twenty-fifth transistor M25 is electrically connected to the second low voltage terminal VGL2;

[0269] A gate of the 26th transistor M26 is electrically connected to the second pull-down node QBB, a source of the 26th transistor M26 is electrically connected to the N+1th second driving output terminal G2(N+1), and a drain of the 26th transistor M26 is electrically connected to the second low voltage terminal VGL2;

[0270] A first end of the sixth capacitor C6 is electrically connected to the second pull-up control node Q2(N), and a second end of the sixth capacitor C6 is electrically connected to the N+1th second driving output terminal G2(N+1);

[0271] The pull-up node control circuit includes a twenty-seventh transistor M27, a twenty-eighth transistor M28, a twenty-ninth transistor M29, a thirtieth transistor M30 and a thirty-first transistor M31;

[0272] The gate of the 27th transistor M27 and the source of the 27th transistor M27 are both electrically connected to the N-2 th cascade output terminal CR(N-2), and the drain of the 27th transistor M27 is electrically connected to the pull-up node Q(N);

[0273] A gate of the 28th transistor M28 is electrically connected to the frame reset terminal TRST, a source of the 28th transistor M28 is electrically connected to the pull-up node Q(N), and a drain of the 28th transistor M28 is electrically connected to the first low voltage terminal VGL1;

[0274] A gate of the 29th transistor M29 is electrically connected to the N+6th cascade output terminal CR(N+6), a source of the 29th transistor M29 is electrically connected to the pull-up node Q(N), and a drain of the 29th transistor M29 is electrically connected to the first low voltage terminal VGL1;

[0275] The gate of the 30th transistor M30 is electrically connected to the first pull-down node QBA, the source of the 30th transistor M30 is electrically connected to the pull-up node Q(N), and the drain of the 30th transistor M30 is electrically connected to the first low voltage terminal VGL1;

[0276] The gate of the thirty-first transistor M31 is electrically connected to the second pull-down node QBB, the source of the thirty-first transistor M31 is electrically connected to the pull-up node Q(N), and the drain of the thirty-first transistor M31 is electrically connected to the first low voltage terminal VGL1;

[0277] The pull-down node control circuit includes a thirty-second transistor M32, a thirty-third transistor M33 and a thirty-fourth transistor M34;

[0278] The gate of the thirty-second transistor M32 and the source of the thirty-second transistor M32 are both electrically connected to the high voltage terminal VDD, and the drain of the thirty-second transistor M32 is electrically connected to the first pull-down node QBA;

[0279] The gate of the thirty-third transistor M33 is electrically connected to the pull-up node Q(N), the source of the thirty-third transistor M33 is electrically connected to the first pull-down node QBA, and the drain of the thirty-third transistor M33 is electrically connected to the first low voltage terminal VGL1;

[0280] The gate of the thirty-fourth transistor M34 is electrically connected to the N-2 th cascade output terminal CR(N-2), the source of the thirty-fourth transistor M34 is electrically connected to the first pull-down node QBA, and the drain of the thirty-fourth transistor M34 is electrically connected to the first low voltage terminal VGL1.

[0281] In at least one embodiment of the present invention, the first isolation control terminal and the second isolation control terminal may be the N+6th cascade output terminal, the input terminal is the N-2th cascade output terminal, and the reset terminal is the N+6th cascade output terminal, but is not limited thereto.

[0282] exist Figure 7 In at least one embodiment of the driving circuit shown, M14, M17, M20, M23 and M26 may not be provided.

[0283] In at least one embodiment of the present invention, the voltage value of the first low voltage signal provided by the first low voltage terminal may be smaller than the voltage value of the second low voltage signal provided by the second low voltage terminal. For example, the voltage value of the first low voltage signal may be -10V, and the voltage value of the second low voltage signal may be -6V.

[0284] Optionally, the voltage value of the first low voltage signal may be greater than or equal to -12V and less than -8V, and the voltage value of the second low voltage signal may be greater than or equal to -8V and less than or equal to -5V, but not limited thereto.

[0285] like Figure 8 As shown, the present invention is Figure 7 At least one embodiment of the driving circuit shown in the figure is in operation.

[0286] In the input phase S1 included in the display cycle, CR(N-2) outputs a high voltage signal, M27, M3 and M4 are turned on, so that the potentials of Q(N), Q1(N) and Q2(N) are high voltages; CLKDN, CLKEN, CLKFN, CLKEN+1 and CLKFN+1 all output low voltage signals, and CR(N), G1(N), G1(N+1), G2(N) and G2(N+1) output low voltage signals;

[0287] In the first half of the output phase S2 included in the display cycle, CLKDN, CLKEN and CLKFN all provide high voltage signals. At this time, the potential of Q1(N) is bootstrapped to a higher potential due to the presence of C2, C3 and C4, and CR(N), G1(N) and G2(N) all output high voltage signals.

[0288] In the second half of the display cycle including the output phase S2, CLKEN+1 and CLKFN+1 both provide high voltage signals, the potential of Q2(N) is bootstrapped to a higher potential due to the presence of C5 and C6, and G1(N+1) and G2(N+1) both output high voltage signals;

[0289] In the output reset phase S3 included in the display cycle, CLKDN, CLKEN and CLKFN all output low voltage signals, and CR(N), G1(N) and G2(N) all output low voltage signals;

[0290] In the output reset phase S3 included in the display cycle, CLKDN+1, CLKEN+1 and CLKFN+1 all output low voltage signals, and G1(N+1) and G2(N+1) all output low voltage signals;

[0291] In the reset phase S4 included in the display cycle, CR(N+6) outputs a high voltage signal, M29, M1 and M2 are all turned on, and the potentials of Q(N), Q1(N) and Q2(N) are all low voltage.

[0292] In at least one embodiment of the present invention, the driving module may include a multi-stage driving circuit. After each stage of the driving circuit outputs the corresponding first driving signal and the second driving signal, it shifts in sequence to complete the display of all row display circuits in the Display interval, and then enters the Blank stage.

[0293] exist Figure 7 In at least one embodiment of the driving circuit shown, Q(N), Q1(N) and Q2(N) are independent of each other and do not interfere with each other, so the potential of Q1(N) is consistent with the potential of Q2(N), and the falling edges of G1(N) and G1(N+1) are consistent, and no horizontal stripes are generated;

[0294] Furthermore, in order to eliminate the forward stress of M1 and M2, the gate of M1 and the gate of M2 are electrically connected to CR (N+6), so that M1 and M2 can achieve a stress-free state when not working.

[0295] The present invention Figure 7 When at least one embodiment of the driving circuit shown is in operation, in the display stage, the driving circuits of each level included in the driving module sequentially provide the first driving signal and the second driving signal to the pixel circuits of each row, and a blank stage is provided after the display stage. In the partial time period included in the blank stage, TRST provides a high voltage signal, and M28, M5 and M6 are all turned on to control the connection between Q(N) and VGL1, control the connection between Q1(N) and VGL1, and control the connection between Q2(N) and VGL1 to reset the potential of Q(N), the potential of Q1(N) and the potential of Q2(N).

[0296] In the present invention Figure 7 In at least one embodiment of the driving circuit shown, all transistors are n-type transistors, but the present invention is not limited thereto.

[0297] The present invention Fig. 9 At least one embodiment of the driving circuit shown in the figure is consistent with the present invention Figure 7 The difference of at least one embodiment of the driving circuit shown is that the gate of M1 and the gate of M2 are both electrically connected to the high voltage terminal VDD.

[0298] exist Fig. 9 In at least one embodiment of the driving circuit shown, M14, M17, M20, M23 and M26 may not be provided.

[0299] The present invention Fig. 9In at least one embodiment of the driving circuit shown, when the potential of Q(N) and the potential of Q1(N) are low, M1 is turned on; when the potential of Q(N) and / or the potential of Q1(N) are high, so that the gate-source voltage of M1 is less than the threshold voltage of M1, M1 is turned off;

[0300] When the potential of Q(N) and the potential of Q2(N) are low, M2 is turned on; when the potential of Q(N) and / or the potential of Q2(N) are high, making the gate-source voltage of M2 less than the threshold voltage of M2, M2 is turned off.

[0301] The present invention Fig.10 At least one embodiment of the driving circuit shown in the figure is consistent with the present invention Figure 7 The difference of at least one embodiment of the driving circuit shown is that:

[0302] The present invention Fig.10 At least one embodiment of the driving circuit shown further includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11 and a first capacitor C1;

[0303] The gate of the seventh transistor M7 is electrically connected to the enable terminal OE, the source of the seventh transistor M7 is electrically connected to the N+2 th cascade output terminal CR(N+2), and the drain of the seventh transistor M7 is electrically connected to the first control node H;

[0304] The gate of the eighth transistor M8 is electrically connected to the first control node H, the source of the eighth transistor M8 is electrically connected to the first clock signal terminal CLKA, and the drain of the eighth transistor M8 is electrically connected to the second control node N;

[0305] The gate of the ninth transistor M9 is electrically connected to the first clock signal terminal CLKA, the source of the ninth transistor M9 is electrically connected to the second control node N, and the drain of the ninth transistor M9 is electrically connected to the pull-up node Q(N);

[0306] The gate of the tenth transistor M10 is electrically connected to the first clock signal terminal CLKA, the source of the tenth transistor M10 is electrically connected to the second control node N, and the drain of the tenth transistor M10 is electrically connected to the first pull-up control node Q1 (N);

[0307] The gate of the eleventh transistor M11 is electrically connected to the first clock signal terminal CLKA, the source of the eleventh transistor M11 is electrically connected to the second control node N, and the drain of the eleventh transistor M11 is electrically connected to the second pull-up control node Q2 (N);

[0308] A first end of the first capacitor C1 is electrically connected to the first control node H, and a second end of the first capacitor C1 is electrically connected to the first low voltage end VGL1.

[0309] The present invention Fig.10 When at least one embodiment of the driving circuit shown is in operation, when random compensation is required, during a portion of the display phase, CR(N+2) and OE both provide high voltage signals, M7 is turned on, the potential of H is a high voltage, and the potential of H is maintained at a high voltage by C1;

[0310] During the partial time period included in the blank phase, CLKA provides a high voltage signal, and M8, M9, M10 and M11 are all turned on to control the potential of Q(N), the potential of Q1(N) and the potential of Q2(N) to be high voltage, so as to control G1(N), G2(N), G1(N+1) and G2(N+1) to output low voltage signals.

[0311] In the present invention Fig.10 In at least one embodiment of the driving circuit shown, all transistors are n-type transistors, but the present invention is not limited thereto. In a specific implementation, the transistors may be p-type transistors.

[0312] exist Fig.10 In at least one embodiment of the driving circuit shown, M14, M17, M20, M23 and M26 may not be provided.

[0313] The present invention Fig.10 At least one embodiment of the driver circuit shown is a multi-output driver circuit with random sense compensation.

[0314] In at least one embodiment of the present invention, the driving circuit may be a gate driving circuit, but is not limited thereto.

[0315] The present invention Fig.11 At least one embodiment of the driving circuit shown in the figure is consistent with the present invention Figure 7 The difference of at least one embodiment of the driving circuit shown is that:

[0316] The present invention Fig.11 At least one embodiment of the driving circuit shown further includes a thirty-fifth transistor M35, a thirty-sixth transistor M36, and a thirty-seventh transistor M37;

[0317] The gate of the thirty-second transistor M32 and the source of the thirty-second transistor M32 are both electrically connected to the first control voltage terminal VDD1;

[0318] The gate of the thirty-second transistor M35 and the source of the thirty-fifth transistor M35 are both electrically connected to the second control voltage terminal VDD2, and the drain of the thirty-fifth transistor M35 is electrically connected to the second pull-down node QBB;

[0319] The gate of the thirty-sixth transistor M36 is electrically connected to the pull-up node Q(N), the source of the thirty-sixth transistor M36 is electrically connected to the second pull-down node QBB, and the drain of the thirty-sixth transistor M36 is electrically connected to the first low voltage terminal VGL1;

[0320] The gate of the thirty-seventh transistor M36 is electrically connected to the N-2 th cascade output terminal CR(N-2), the source of the thirty-seventh transistor M34 is electrically connected to the second pull-down node QBB, and the drain of the thirty-seventh transistor M37 is electrically connected to the first low voltage terminal VGL1.

[0321] exist Fig.11 In at least one embodiment of the driving circuit shown, a first control voltage provided by the first control voltage terminal VDD1 and a second control voltage provided by the second control voltage terminal VDD2 are in opposite phases.

[0322] exist Fig.11 In at least one embodiment of the driving circuit shown, all transistors are n-type transistors, but the present invention is not limited thereto.

[0323] The connection relationship between the first four driving circuits included in the driving module can be as follows: Fig.11 As shown;

[0324] exist Fig.12 Among them, the one labeled A1 is the first-stage driving circuit, the one labeled A2 is the second-stage driving circuit, the one labeled A3 is the third-stage driving circuit, and the one labeled A4 is the fourth-stage driving circuit;

[0325] The input terminal of A1 is electrically connected to the start voltage terminal STU, and the reset terminal of A1 is electrically connected to CR (7);

[0326] The first cascade output terminal is labeled CR(1), the first first drive output terminal is labeled G1(1), the first second drive output terminal is labeled G2(1), the second first drive output terminal is labeled G1(2), and the second second drive output terminal is labeled G2(2);

[0327] The input terminal of A2 is electrically connected to CR (1);

[0328] The one labeled CR(3) is the third cascade output terminal, the one labeled G1(3) is the third first drive output terminal, the one labeled G2(3) is the third second drive output terminal, the one labeled G1(4) is the fourth first drive output terminal, and the one labeled G2(4) is the fourth second drive output terminal;

[0329] The input terminal of A3 is electrically connected to CR (3);

[0330] The fifth cascade output terminal is labeled CR(5), the fifth first drive output terminal is labeled G1(5), the fifth second drive output terminal is labeled G2(5), the sixth first drive output terminal is labeled G1(6), and the sixth second drive output terminal is labeled G2(6);

[0331] The input terminal of A4 is electrically connected to CR (5);

[0332] The terminal labeled CR(7) is the seventh cascade output terminal, the terminal labeled G1(7) is the seventh first drive output terminal, the terminal labeled G2(7) is the seventh second drive output terminal, the terminal labeled G1(8) is the eighth first drive output terminal, and the terminal labeled G2(8) is the eighth second drive output terminal.

[0333] exist Fig.12 In the figure, the terminal labeled TRST is a frame reset terminal, the terminal labeled VDDA is a first high voltage terminal, and the terminal labeled VDDB is a second high voltage terminal;

[0334] The first output clock signal terminal labeled CLKE1 is the first output clock signal terminal of the first level, the first output clock signal terminal labeled CLKE2 is the first output clock signal terminal of the second level, the first output clock signal terminal labeled CLKE3 is the first output clock signal terminal of the third level, the first output clock signal terminal labeled CLKE4 is the first output clock signal terminal of the fourth level, the first output clock signal terminal labeled CLKE5 is the first output clock signal terminal of the fifth level, the first output clock signal terminal labeled CLKE6 is the first output clock signal terminal of the sixth level, the first output clock signal terminal labeled CLKE7 ​​is the first output clock signal terminal of the seventh level, and the first output clock signal terminal labeled CLKE8 is the first output clock signal terminal of the eighth level;

[0335] The second output clock signal terminal of the first level is labeled CLKF1, the second output clock signal terminal of the second level is labeled CLKF2, the second output clock signal terminal of the second level is labeled CLKF3, the second output clock signal terminal of the third level is labeled CLKF4, the second output clock signal terminal of the fourth level is labeled CLKF5, the second output clock signal terminal of the fifth level is labeled CLKF6, the second output clock signal terminal of the sixth level is labeled CLKF7, and the second output clock signal terminal of the seventh level is labeled CLKF8.

[0336] exist Fig.12Among them, the terminal labeled CLKD1 is the first cascade output clock signal terminal, the terminal labeled CLKD3 is the third cascade output clock signal terminal, the terminal labeled CLKD5 is the fifth cascade output clock signal terminal, and the terminal labeled CLKD7 is the seventh cascade output clock signal terminal.

[0337] Fig.13 yes Fig.12 The working timing diagram of at least one embodiment of the driving module shown.

[0338] exist Fig.13 Among them, the one labeled Td is the display stage, and the one labeled Tb is the blank stage;

[0339] The node labeled Q(1) is the first pull-up node, the node labeled Q(5) is the fifth pull-up node, the node labeled G1(1) is the first first drive output terminal, the node labeled G1(2) is the second first drive output terminal, the node labeled G1(3) is the third first drive output terminal, the node labeled G1(4) is the fourth first drive output terminal, the node labeled G1(5) is the fifth first drive output terminal, and the node labeled G1(6) is the sixth first drive output terminal.

[0340] In at least one embodiment of the present invention, the waveform of CLKFN is the same as the waveform of CLKEN, but the present invention is not limited thereto; wherein N is a positive integer.

[0341] The display device described in the embodiment of the present invention includes the above-mentioned driving circuit.

[0342] The display device provided in the embodiment of the present invention can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

[0343] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A driving circuit, characterized in that: It includes a pull-up node, a first pull-up control node, a second pull-up control node, a first isolation circuit and a second isolation circuit; The first isolation circuit is electrically connected to the first isolation control terminal, the pull-up node and the first pull-up control node respectively, and is used to control the connection or disconnection between the pull-up node and the first pull-up control node under the control of the first isolation control signal provided by the first isolation control terminal; The second isolation circuit is electrically connected to the second isolation control terminal, the pull-up node and the second pull-up control node respectively, and is used to control the connection or disconnection between the pull-up node and the second pull-up control node under the control of the second isolation control signal provided by the second isolation control terminal; The driving circuit also includes a first control node control circuit and a second control node control circuit; The first control node control circuit is electrically connected to the enable terminal, the enable reset terminal and the first control node respectively, and is used to control the connection between the enable reset terminal and the first control node under the control of the enable signal provided by the enable terminal; The second control node control circuit is electrically connected to the first clock signal end, the first control node, the second control node, the pull-up node, the first clock signal end, the second control node, the first pull-up control node and the second pull-up control node, respectively, and is used to control the connection between the first clock signal end and the second control node under the control of the potential of the first control node, and to control the connection between the second control node and the pull-up node under the control of the first clock signal provided by the first clock signal end, control the connection between the second control node and the first pull-up control node under the control of the first clock signal provided by the first clock signal end, and control the connection between the second control node and the second pull-up control node under the control of the first clock signal provided by the first clock signal end.

2. The driving circuit according to claim 1, characterized in that: The first isolation circuit includes a first transistor, and the second isolation circuit includes a second transistor; The gate of the first transistor is electrically connected to the first isolation control terminal, the first electrode of the first transistor is electrically connected to the pull-up node, and the second electrode of the first transistor is electrically connected to the first pull-up control node; The gate of the second transistor is electrically connected to the second isolation control terminal, the first electrode of the second transistor is electrically connected to the pull-up node, and the second electrode of the first transistor is electrically connected to the second pull-up control node.

3. The driving circuit according to claim 1, wherein: comprising an Nth cascade output terminal and a cascade output circuit; The cascade output circuit is electrically connected to the Nth cascade output terminal, the first pull-up control node, the pull-down node, the cascade output clock signal terminal, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the Nth cascade output terminal and the cascade output clock signal terminal under the control of the potential of the first pull-up control node, and control the connection or disconnection between the Nth cascade output terminal and the first voltage terminal under the control of the potential of the pull-down node; N is a positive integer; The driving circuit includes a pull-down node; or, the pull-down node includes a first pull-down node and a second pull-down node.

4. The driving circuit according to claim 2, characterized in that: The first isolation control terminal and the second isolation control terminal are reset terminals; or, the first isolation control terminal and the second isolation control terminal are second voltage terminals.

5. The driving circuit according to claim 1, characterized in that: Also included is a first node control circuit and a second node control circuit; The first node control circuit is electrically connected to the input terminal and the first pull-up control node respectively, and is used to control the potential of the first pull-up control node according to an input signal provided by the input terminal; The second node control circuit is electrically connected to the input terminal and the second pull-up control node respectively, and is used to control the potential of the second pull-up control node according to an input signal provided by the input terminal.

6. The driving circuit according to claim 5, characterized in that: The first node control circuit is also electrically connected to the frame reset terminal and the first voltage terminal, and is used to control the first pull-up control node to be connected to the first voltage terminal under the control of a frame reset signal provided by the frame reset terminal; The second node control circuit is also electrically connected to the frame reset terminal and the first voltage terminal, and is used to control the connection between the second pull-up control node and the first voltage terminal under the control of a frame reset signal provided by the frame reset terminal.

7. The driving circuit according to claim 5, characterized in that: The first node control circuit includes a third transistor, and the second node control circuit includes a fourth transistor; The gate of the third transistor and the first electrode of the third transistor are both electrically connected to the input terminal, and the second electrode of the third transistor is electrically connected to the first pull-up control node; The gate of the fourth transistor and the first electrode of the fourth transistor are both electrically connected to the input terminal, and the second electrode of the fourth transistor is electrically connected to the second pull-up control node.

8. The driving circuit according to claim 6, characterized in that: The first node control circuit includes a fifth transistor and a sixth transistor; The gate of the fifth transistor is electrically connected to the frame reset terminal, the first electrode of the fifth transistor is electrically connected to the first pull-up control node, and the second electrode of the fifth transistor is electrically connected to the first voltage terminal; A gate of the sixth transistor is electrically connected to the frame reset terminal, a first electrode of the sixth transistor is electrically connected to the second pull-up control node, and a second electrode of the sixth transistor is electrically connected to the first voltage terminal.

9. The driving circuit according to any one of claims 2 to 8, characterized in that: The first control node control circuit includes a seventh transistor, and the second control node control circuit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a first capacitor; The gate of the seventh transistor is electrically connected to the enable terminal, the first electrode of the seventh transistor is electrically connected to the enable reset terminal, and the second electrode of the seventh transistor is electrically connected to the first control node; The gate of the eighth transistor is electrically connected to the first control node, the first electrode of the eighth transistor is electrically connected to the first clock signal terminal, and the second electrode of the eighth transistor is electrically connected to the second control node; The gate of the ninth transistor is electrically connected to the first clock signal terminal, the first electrode of the ninth transistor is electrically connected to the second control node, and the second electrode of the ninth transistor is electrically connected to the pull-up node; The gate of the tenth transistor is electrically connected to the first clock signal terminal, the first electrode of the tenth transistor is electrically connected to the second control node, and the second electrode of the tenth transistor is electrically connected to the first pull-up control node; The gate of the eleventh transistor is electrically connected to the first clock signal terminal, the first electrode of the eleventh transistor is electrically connected to the second control node, and the second electrode of the eleventh transistor is electrically connected to the second pull-up control node; The first end of the first capacitor is electrically connected to the first control node, and the second end of the first capacitor is electrically connected to the first voltage end.

10. The driving circuit according to any one of claims 1 to 8, characterized in that: Also included is a pull-up node control circuit; The pull-up node control circuit is electrically connected to the input terminal, the reset terminal, the frame reset terminal, the pull-down node, the pull-up node and the first voltage terminal, respectively, and is used to control the potential of the pull-up node under the control of the input signal provided by the input terminal, control the connection or disconnection between the pull-up node and the first voltage terminal under the control of the reset signal provided by the reset terminal, control the connection or disconnection between the pull-up node and the first voltage terminal under the control of the potential of the pull-down node, and control the connection or disconnection between the pull-up node and the first voltage terminal under the control of the potential of the frame reset signal provided by the frame reset terminal; The driving circuit includes a pull-down node; or, the pull-down node includes a first pull-down node and a second pull-down node.

11. The driving circuit according to any one of claims 1 to 8, characterized in that: Also included is a pull-down node control circuit; The pull-down node control circuit is electrically connected to the second voltage terminal, the pull-down node, the pull-up node, the reset terminal and the first voltage terminal, respectively, and is used to control the connection between the pull-down node and the second voltage terminal under the control of the second voltage signal provided by the second voltage terminal, control the connection between the pull-down node and the first voltage terminal under the control of the potential of the pull-up node, and control the connection between the pull-down node and the first voltage terminal under the control of the reset signal provided by the reset terminal.

12. The driving circuit according to claim 3, characterized in that: When the pull-down node includes a first pull-down node and a second pull-down node, The cascade output circuit includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor and a second capacitor; The gate of the twelfth transistor is electrically connected to the first pull-up control node, the first electrode of the twelfth transistor is electrically connected to the cascade output clock signal terminal, and the second electrode of the twelfth transistor is electrically connected to the Nth cascade output terminal; The gate of the thirteenth transistor is electrically connected to the first pull-down node, the first electrode of the thirteenth transistor is electrically connected to the Nth cascade output terminal, and the second electrode of the thirteenth transistor is electrically connected to the first voltage terminal; The gate of the fourteenth transistor is electrically connected to the second pull-down node, the first electrode of the fourteenth transistor is electrically connected to the Nth cascade output terminal, and the second electrode of the fourteenth transistor is electrically connected to the first voltage terminal; A first end of the second capacitor is electrically connected to the first pull-up control node, and a second end of the second capacitor is electrically connected to the cascade output end.

13. The driving circuit according to claim 3, characterized in that: Also includes an Nth first drive output terminal, an Nth second drive output terminal, a first drive output circuit and a second drive output circuit; The first driver output circuit is electrically connected to the first pull-up control node, the pull-down node, the first first output clock signal terminal, the Nth first driver output terminal and the third voltage terminal respectively, and is used to control the connection or disconnection between the Nth first driver output terminal and the first first output clock signal terminal under the control of the potential of the first pull-up control node, and control the connection or disconnection between the Nth first driver output terminal and the third voltage terminal under the control of the potential of the pull-down node; The second driver output circuit is electrically connected to the first pull-up control node, the pull-down node, the first second output clock signal terminal, the Nth second driver output terminal and the third voltage terminal, respectively, and is used to control the connection or disconnection between the Nth second driver output terminal and the first second output clock signal terminal under the control of the potential of the first pull-up control node, and to control the connection or disconnection between the Nth second driver output terminal and the third voltage terminal under the control of the potential of the pull-down node.

14. The driving circuit according to claim 3, characterized in that: Also includes an N+1th first drive output terminal, an N+1th second drive output terminal, a third drive output circuit and a fourth drive output circuit; The third driver output circuit is electrically connected to the second pull-up control node, the pull-down node, the second first output clock signal terminal, the N+1th first driver output terminal and the third voltage terminal respectively, and is used to control the connection or disconnection between the N+1th first driver output terminal and the second first output clock signal terminal under the control of the potential of the second pull-up control node, and control the connection or disconnection between the N+1th first driver output terminal and the third voltage terminal under the control of the potential of the pull-down node; The fourth driver output circuit is electrically connected to the second pull-up control node, the pull-down node, the second second output clock signal terminal, the N+1th second driver output terminal and the third voltage terminal, respectively, and is used to control the connection or disconnection between the N+1th second driver output terminal and the second second output clock signal terminal under the control of the potential of the second pull-up control node, and to control the connection or disconnection between the N+1th second driver output terminal and the third voltage terminal under the control of the potential of the pull-down node.

15. The driving circuit according to claim 13, characterized in that: When the pull-down node includes a first pull-down node and a second pull-down node, The first drive output circuit includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor and a third capacitor; The gate of the fifteenth transistor is electrically connected to the first pull-up control node, the first electrode of the fifteenth transistor is electrically connected to the first first output clock signal terminal, and the second electrode of the fifteenth transistor is electrically connected to the Nth first driving output terminal; The gate of the sixteenth transistor is electrically connected to the first pull-down node, the first electrode of the sixteenth transistor is electrically connected to the Nth first driving output terminal, and the second electrode of the sixteenth transistor is electrically connected to the third voltage terminal; The gate of the seventeenth transistor is electrically connected to the second pull-down node, the first electrode of the seventeenth transistor is electrically connected to the Nth first driving output terminal, and the second electrode of the seventeenth transistor is electrically connected to the third voltage terminal; A first end of the third capacitor is electrically connected to the first pull-up control node, and a second end of the third capacitor is electrically connected to the Nth first driving output terminal; The second driving output circuit includes an eighteenth transistor, a nineteenth transistor, a twentieth transistor and a fourth capacitor; The gate of the eighteenth transistor is electrically connected to the first pull-up control node, the first electrode of the eighteenth transistor is electrically connected to the first second output clock signal terminal, and the second electrode of the eighteenth transistor is electrically connected to the Nth second driving output terminal; The gate of the nineteenth transistor is electrically connected to the first pull-down node, the first electrode of the nineteenth transistor is electrically connected to the Nth second driving output terminal, and the second electrode of the nineteenth transistor is electrically connected to the third voltage terminal; The gate of the 20th transistor is electrically connected to the second pull-down node, the first electrode of the 20th transistor is electrically connected to the Nth second driving output terminal, and the second electrode of the 20th transistor is electrically connected to the third voltage terminal; A first end of the fourth capacitor is electrically connected to the first pull-up control node, and a second end of the fourth capacitor is electrically connected to the Nth second driving output terminal.

16. The driving circuit according to claim 14, characterized in that: When the pull-down node includes a first pull-down node and a second pull-down node, The third driving output circuit includes a twenty-first transistor, a twenty-second transistor, a twenty-third transistor and a fifth capacitor; The gate of the 21st transistor is electrically connected to the second pull-up control node, the first electrode of the 21st transistor is electrically connected to the second first output clock signal terminal, and the second electrode of the 21st transistor is electrically connected to the N+1th first driving output terminal; The gate of the 22nd transistor is electrically connected to the first pull-down node, the first electrode of the 22nd transistor is electrically connected to the N+1th first driving output terminal, and the second electrode of the 22nd transistor is electrically connected to the third voltage terminal; A gate of the twenty-third transistor is electrically connected to the second pull-down node, a first electrode of the twenty-third transistor is electrically connected to the N+1th first driving output terminal, and a second electrode of the twenty-third transistor is electrically connected to the third voltage terminal; The first end of the fifth capacitor is electrically connected to the second pull-up control node, and the second end of the fifth capacitor is electrically connected to the N+1th first driving output terminal; The fourth driving output circuit includes a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor and a sixth capacitor; The gate of the 24th transistor is electrically connected to the second pull-up control node, the first electrode of the 24th transistor is electrically connected to the second second output clock signal terminal, and the second electrode of the 24th transistor is electrically connected to the N+1th second driving output terminal; The gate of the 25th transistor is electrically connected to the first pull-down node, the first electrode of the 25th transistor is electrically connected to the N+1th second driving output terminal, and the second electrode of the 25th transistor is electrically connected to the third voltage terminal; The gate of the 26th transistor is electrically connected to the second pull-down node, the first electrode of the 26th transistor is electrically connected to the N+1th second driving output terminal, and the second electrode of the 26th transistor is electrically connected to the third voltage terminal; A first end of the sixth capacitor is electrically connected to the second pull-up control node, and a second end of the sixth capacitor is electrically connected to the N+1th second driving output terminal.

17. The driving circuit according to claim 10, characterized in that: When the pull-down node includes a first pull-down node and a second pull-down node, the pull-up node control circuit includes a twenty-seventh transistor, a twenty-eighth transistor, a twenty-ninth transistor, a thirtieth transistor, and a thirty-first transistor; The gate electrode of the twenty-seventh transistor and the first electrode of the twenty-seventh transistor are both electrically connected to the input terminal, and the second electrode of the twenty-seventh transistor is electrically connected to the pull-up node; The gate of the 28th transistor is electrically connected to the frame reset terminal, the first electrode of the 28th transistor is electrically connected to the pull-up node, and the second electrode of the 28th transistor is electrically connected to the first voltage terminal; The gate of the 29th transistor is electrically connected to the reset terminal, the first electrode of the 29th transistor is electrically connected to the pull-up node, and the second electrode of the 29th transistor is electrically connected to the first voltage terminal; The gate of the 30th transistor is electrically connected to the first pull-down node, the first electrode of the 30th transistor is electrically connected to the pull-up node, and the second electrode of the 30th transistor is electrically connected to the first voltage terminal; A gate of the thirty-first transistor is electrically connected to the second pull-down node, a first electrode of the thirty-first transistor is electrically connected to the pull-up node, and a second electrode of the thirty-first transistor is electrically connected to the first voltage terminal.

18. The driving circuit according to claim 11, characterized in that: The pull-down node control circuit includes a thirty-second transistor, a thirty-third transistor, and a thirty-fourth transistor; The gate electrode of the thirty-second transistor and the first electrode of the thirty-second transistor are both electrically connected to the second voltage terminal, and the second electrode of the thirty-second transistor is electrically connected to the pull-down node; The gate of the thirty-third transistor is electrically connected to the pull-up node, the first electrode of the thirty-third transistor is electrically connected to the pull-down node, and the second electrode of the thirty-third transistor is electrically connected to the first voltage terminal; A gate of the thirty-fourth transistor is electrically connected to the reset terminal, a first electrode of the thirty-fourth transistor is electrically connected to the pull-down node, and a second electrode of the thirty-fourth transistor is electrically connected to the first voltage terminal.

19. The driving circuit according to claim 11, characterized in that: The pull-down node includes a first pull-down node and a second pull-down node; the second voltage terminal includes a first control voltage terminal and a second control voltage terminal; The pull-down node control circuit includes a thirty-second transistor, a thirty-third transistor, a thirty-fourth transistor, a thirty-fifth transistor, a thirty-sixth transistor, and a thirty-seventh transistor; The gate electrode of the thirty-second transistor and the first electrode of the thirty-second transistor are both electrically connected to the first control voltage terminal, and the second electrode of the thirty-second transistor is electrically connected to the first pull-down node; The gate of the thirty-third transistor is electrically connected to the pull-up node, the first electrode of the thirty-third transistor is electrically connected to the first pull-down node, and the second electrode of the thirty-third transistor is electrically connected to the first voltage terminal; The gate of the thirty-fourth transistor is electrically connected to the reset terminal, the first electrode of the thirty-fourth transistor is electrically connected to the first pull-down node, and the second electrode of the thirty-fourth transistor is electrically connected to the first voltage terminal; The gate electrode of the thirty-fifth transistor and the first electrode of the thirty-fifth transistor are both electrically connected to the second control voltage terminal, and the second electrode of the thirty-fifth transistor is electrically connected to the second pull-down node; The gate of the thirty-sixth transistor is electrically connected to the pull-up node, the first electrode of the thirty-sixth transistor is electrically connected to the second pull-down node, and the second electrode of the thirty-sixth transistor is electrically connected to the first voltage terminal; A gate of the thirty-seventh transistor is electrically connected to the reset terminal, a first electrode of the thirty-seventh transistor is electrically connected to the second pull-down node, and a second electrode of the thirty-seventh transistor is electrically connected to the first voltage terminal.

20. A display device, characterized in that: The method comprises a driving circuit as claimed in any one of claims 1 to 19.

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