Semiconductor three-dimensional package structure with vapor chamber

Abstract

This invention provides a semiconductor three-dimensional packaging structure with a vapor chamber. A cover and a base plate form a vapor chamber, within which a three-dimensional structure consisting of multiple stacked interposers housing semiconductor wafers is encapsulated. A set of capillary structures is formed inside the cover, and a mesh is attached to the inside of the cover and shields the capillary structures. Each interposer has a set of protrusions around its periphery, with a recess between each protrusion. All interposers contact the mesh with their protrusions, and the recess from the upper interposer to the lower interposer forms a flow channel connecting to the vapor chamber. A suitable amount of cooling fluid is added to the vapor chamber, and the cooling fluid undergoes a liquid-to-gas thermal cycle from the flow channel to the capillary structures, achieving heat dissipation for the semiconductor wafers. Each interposer also has capillary structures on its top and bottom surfaces, guiding the high-temperature gas from the two interposers through the flow channel to the vapor chamber, becoming part of the thermal cycle.

Description

Technical Field

[0001] This invention relates to semiconductor packaging technology, and more particularly to a three-dimensional packaging structure that utilizes a vapor chamber or temperature equalization structure to generate a heat dissipation effect for the semiconductor wafer. Background Technology

[0002] A three-dimensional packaging structure is used to gather more semiconductor chips together, achieving the requirements of small size and high functionality. When powered on, this semiconductor chip generates high heat, which can delay computing efficiency and even shorten its lifespan. Therefore, heat dissipation becomes a pressing issue that needs to be addressed for semiconductor chips.

[0003] In U.S. Patent No. 20200105644, a heat dissipation device is attached to a semiconductor three-dimensional package structure, using a coolant that is continuously replenished to a channel to remove heat from the package structure. While this water-cooling design can improve heat dissipation efficiency, the force driving the coolant flow in this heat dissipation device comes from a pump, and the bulky device is clearly unable to keep up with the advanced technology of miniaturizing package structures.

[0004] Taiwanese Patent No. 202121618 proposes a stacking structure that combines the heat dissipation structure of Taiwanese Patent No. 202002201. It adds a heat conduction structure inside the three-dimensional package to improve heat dissipation. Specifically, a heat dissipation layer is added to each layer of the semiconductor wafer stack. This heat dissipation layer is a thermally conductive interface material, and the heat conduction effect of the semiconductor wafer is achieved through electrical connection structures such as silicon vias or copper pillars. The drawback is that the heat conduction effect is limited. In particular, with multi-layer stacking, the heat dissipation of the lower semiconductor wafers is insufficient, and the effect is significantly reduced.

[0005] Currently, the best solution to the heat dissipation problem is a vapor chamber structure, also known as a homogenizing structure. This vapor chamber structure utilizes the thermal circulation between the gas and liquid phases of the cooling fluid to achieve rapid heat dissipation. Therefore, the application of this vapor chamber in semiconductor 3D packaging technology can improve the heat dissipation efficiency of multiple high-performance chips.

[0006] For example, Japanese Patent No. 5554444 (Publication No. 2015050323) and Taiwan Patent No. 202002031 both mention a cover that is used in the three-dimensional packaging structure of semiconductors to achieve the heat dissipation effect of the vapor chamber.

[0007] Furthermore, Taiwan Patent No. I672775 (Application No. 106119235) designs a three-dimensional packaging structure with at least one cooling channel surrounding a stacked semiconductor wafer. The fluid undergoing a phase change in the cooling channel carries away the heat from the semiconductor wafer, thus achieving a heat dissipation effect; therefore, the cooling channel functions similarly to a vapor chamber.

[0008] Another semiconductor packaging and assembly structure involves setting up a vapor chamber between the semiconductor wafer and the packaging substrate. This vapor chamber removes heat from the semiconductor wafer. Patent applications have been filed in multiple countries, such as U.S. Patent No. 20200111728 and China Patent No. 111009493.

[0009] In the aforementioned vapor chamber patents, a thermal interface material or encapsulating colloid is used as a medium to indirectly integrate the vapor chamber structure with the semiconductor package structure. Therefore, the thermal conductivity of this medium significantly affects the heat dissipation effect of the vapor chamber structure.

[0010] In addition, the disclosure of U.S. Patent No. 20190393193 reveals a semiconductor package with a vapor chamber function, primarily located within an electrical connection structure, where the vapor chamber is situated between multiple integrated circuits. However, the flow space of this vapor chamber is limited to the narrow space between the integrated circuits, resulting in poor overall heat dissipation efficiency of the semiconductor package.

[0011] Another type of semiconductor package includes an interposer attached to the semiconductor, as disclosed in U.S. Patent No. 7,002,247. In this package, the interposer has two plates containing core structures such as grooves. The internal sealed volume of the interposer directly contacts the back side of the semiconductor, thereby forming a vapor chamber to reduce the heat of the semiconductor wafer and achieve a temperature uniformity effect. Unfortunately, this semiconductor package relies solely on the surface attachment structure of the wafer, making it susceptible to damage to the semiconductor wafer and relatively weakening the overall support structure. Summary of the Invention

[0012] In view of this, the inventors of this case provide a new generation of three-dimensional packaging structure, the main purpose of which is to encapsulate the semiconductor wafer and cooling fluid in a vapor chamber structure, so that the cooling fluid can directly remove the heat from the semiconductor wafer, thus the heat dissipation effect is more efficient than the prior art.

[0013] To achieve the above objectives, the present invention provides a semiconductor three-dimensional packaging structure with a vapor chamber, characterized in that it comprises:

[0014] A base plate;

[0015] Multiple semiconductor wafers are stacked on the substrate through multiple interposers. Each interposer has a top capillary structure and a bottom capillary structure. The periphery of the interposer has a set of protrusions, with a recess between two protrusions.

[0016] An inner layer of the cover contains a set of capillary structures and a mesh, which shields the capillary structures. When the cover, combined with the base plate, forms a vapor chamber, the cover covers the entire semiconductor wafer. All the interposers contact the mesh with protrusions, and the recess from the upper interposer to the lower interposer forms a flow channel connecting to the vapor chamber.

[0017] An appropriate amount of cooling fluid is added to the vapor chamber, and a liquid-to-gas thermal cycle is carried out between the capillary structure, the flow channel, the top capillary structure, and the bottom capillary structure to achieve the heat dissipation effect of the semiconductor wafer.

[0018] The semiconductor three-dimensional package structure with a vapor chamber, wherein the recesses of the upper interposer layer and the lower interposer layer are staggered to maintain an inclined flow channel, such that the protrusions of the upper interposer layer and the lower interposer layer are arranged in a stepped state.

[0019] The semiconductor three-dimensional package structure with a vapor chamber, wherein the lid is made of copper, a copper alloy, or one of other thermally conductive metals.

[0020] The semiconductor three-dimensional package structure with a vapor chamber, wherein copper, a copper alloy, or one of other thermally conductive metals is coated on the surface of the cap.

[0021] The semiconductor three-dimensional package structure with a vapor chamber, wherein the set of capillary structures are staggered gaps, formed on the surface of the cap by one of the means of etching, laser engraving, stamping and die casting.

[0022] The semiconductor three-dimensional packaging structure with a vapor chamber, wherein the cooling fluid is selected from one of ultrapure water, ethanol, butane and mixtures thereof.

[0023] The semiconductor three-dimensional package structure with a vapor chamber, wherein the interlayer is selected from one of a ceramic substrate, an aluminum nitride ceramic substrate, an alumina ceramic substrate, a silicon oxide ceramic substrate, and a silicon nitride ceramic substrate.

[0024] The semiconductor three-dimensional package structure with a vapor chamber has an array of thermally conductive pillars that pass through all stacked interposer layers.

[0025] The semiconductor three-dimensional package structure with a vapor chamber, wherein a set of heat dissipation fins are combined on the outside of the cover.

[0026] Thus, the cover and base plate of this invention form a vapor chamber, encapsulating the semiconductor wafer and cooling fluid within the vapor chamber, together forming a three-dimensional packaging structure. The cooling fluid undergoes a thermal cycle in the vapor chamber, changing from a liquid to a gaseous state, directly carrying away the heat from the semiconductor wafer, resulting in a more efficient heat dissipation effect than existing technologies.

[0027] To make the objectives, features and advantages of the present invention readily apparent, one or more preferred embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0028] Figure 1 This is a top view of the first embodiment of the packaging structure of the present invention.

[0029] Figure 2 yes Figure 1 Bottom view of the embodiment.

[0030] Figure 3 This is a schematic diagram showing the internal structure of the package structure from above, with the top of the cover cut off.

[0031] Figure 4 This is a schematic diagram showing the internal structure of the package through the cover.

[0032] Figure 5 It is along Figure 3 A sectional view cut along line AA.

[0033] Figure 6 It is a detailed description Figure 5 A magnified schematic diagram of the flow channel section.

[0034] Figure 7 This is a schematic diagram showing the bottom surface of a single intermediate layer viewed from a downward angle.

[0035] Figure 8 This is a schematic diagram showing the stacked interposer layer and semiconductor wafer.

[0036] Figure 9 This is a schematic diagram showing the internal structure of the packaged product after it has been cut open.

[0037] Figure 10 It is a schematic diagram showing the steam chamber becoming part of the heat cycle through the mesh and capillary structure.

[0038] Figure 11 , Figure 12 This is a schematic diagram of a second embodiment of the packaging structure of the present invention viewed from different angles.

[0039] Figure 13 yes Figure 3 A magnified view of a portion of the image.

[0040] Explanation of reference numerals in the attached drawings: Encapsulation structure 10; Cover 11; Hole 12; Vapor chamber 13; Mesh 14; Capillary structure 15; Base plate 20; Electrical pin 21; Pad 22; Leak-proof structure 23; Upper interlayer 30; Top capillary structure 31; Middle interlayer 32; Lower interlayer 33; Flow channel 34; Bottom capillary structure 35; Protrusion 36; Recess 37; Working area 40; Sealing area 41; Conductive pillar 42; Thermal pillar 43; Semiconductor wafer 44; Arrow 50; Fastener 51; Heat sink fins 52. Detailed Implementation

[0041] Next, embodiments of this case will be described with reference to the accompanying drawings. In the drawings, the same reference numerals denote the same or similar structures or units. It is to be understood that the described embodiments are only some examples of this case, and not all embodiments. Other embodiments can be deduced based on the described examples, or constructions can be modified or varied as needed, all of which fall within the scope of protection of this case.

[0042] In the following description, directional terms such as "up," "down," "left," "right," "front," "back," "inside," "outside," and "side" are used only for reference to the directions in the accompanying drawings. The use of directional terms is for the purpose of better and clearer description and understanding of this application, and does not imply that the described device or element must have a specific orientation, structure, or operation, and therefore should not be construed as a limitation on the technical content of this application.

[0043] Unless specifically and explicitly stated otherwise, in the following description, "installed," "connected," "attached," or "on" should be interpreted broadly, including, for example, fixed connection, detachable connection, integral connection, mechanical connection, direct connection, indirect connection, or connection between two components. Those skilled in the art will understand the meaning of these terms in various embodiments, and even in the specific context, based on ordinary knowledge or experience.

[0044] Unless otherwise stated, in the following description, "multiple" means two or more.

[0045] Figure 1 This is a top view showing a first embodiment of the packaging structure 10 of the present invention. The packaging structure 10 has a cover 11 on top, and the cover 11 is a cube with a hole 12 at each of its four corners.

[0046] In this embodiment, the lid 11 is made of copper, a copper alloy, or one of other thermally conductive metals. In some embodiments, the lid 11 is formed by coating copper, a copper alloy, or one of other thermally conductive metals with a polymer material, which also provides thermal conductivity.

[0047] Figure 2 This is a bottom view. Below the encapsulation structure 10 is a base plate 20 with the same shape as the cover 11. A set of electrical contacts 21 is arrayed in the center of the base plate 20, and the set of electrical contacts 21 is arranged in a square ring. Four pads 22 are formed at the four corners of the base plate 20.

[0048] like Figure 4 , Figure 10As shown, the encapsulation structure 10 is divided into two parts. From the perspective view, the inner side of the lid 11 has five surfaces enclosing an internal space. The base plate 20 seals the opening of the lid 11, and the two together form a sealed vapor chamber 13. A leak-proof structure 23 is located between the base plate 20 and the lid 11 to prevent leakage from the vapor chamber 13.

[0049] In this embodiment, a set of capillary structures 15 is etched on the inner side of the cover 11. There are five capillary structures 15, formed on five surfaces of the inner side of the cover 11. Each capillary structure 15 consists of multiple staggered slits distributed on a corresponding surface of the cover 11. In some embodiments, the set of capillary structures 15 is formed on the surface of the cover 11 by means of laser engraving, stamping, or die casting.

[0050] Additionally, a set of five metal meshes 14 are attached to the inner side of the cover 11. These meshes 14 extend to the five sides of the inner side of the cover 11. Each mesh 14 is fixed to its corresponding side of the cover 11 by welding or adhesive without damaging or blocking the capillary structure 15. Thus, the meshes 14 shield the capillary structure 15.

[0051] like Figure 3 , Figure 5 As shown, a semiconductor wafer stack structure and a suitable amount of cooling fluid are encapsulated in the vapor chamber 13 of the encapsulation structure 10.

[0052] The term "semiconductor wafer stacking structure" as used herein refers to a three-dimensional structure consisting of multiple semiconductor wafers stacked through multiple interposers on a substrate 20. These interposers are stacked in a three-layer structure, defined from bottom to top as a lower interposer 33, a middle interposer 32, and an upper interposer 30, which aids in structural description and avoids confusion. In this embodiment, the interposer is selected from one of a ceramic substrate, an aluminum nitride ceramic substrate, an alumina ceramic substrate, a silicon oxide ceramic substrate, and a silicon nitride ceramic substrate.

[0053] Taking the upper intermediate layer 30 as an example, the center of its top surface is a working area 40, which is a square area. A set of heat-conducting pillars 43 are arrayed around the square area. By means of etching, laser engraving, stamping and die casting, a top surface capillary structure 31 is formed on the top surface of the upper intermediate layer 30. The top surface capillary structure 31 consists of multiple gaps with alternating rows and columns, avoiding the set of heat-conducting pillars 43.

[0054] Then I saw Figure 7The upper interposer layer 30 also has a working area 40 on its bottom surface, which consists of a seating area 41 and a set of conductive pillars 42. The set of conductive pillars 42 surrounds the square seating area 41, and the set of heat-conducting pillars 43 surrounds the set of conductive pillars 42. A bottom capillary structure 35 is formed on the bottom surface of the upper interposer layer 30 by means of etching, laser engraving, stamping, or die casting. The bottom capillary structure 35 is also a series of interlaced slits that avoid the set of conductive pillars 42 and the set of heat-conducting pillars 43. In addition, the upper interposer layer 30 has a set of protrusions 36 around its periphery, with a recess 37 between two protrusions 36, so there is a set of recesses 37 around the upper interposer layer 30.

[0055] from Figure 5 , Figure 6 , Figure 10 , Figure 13 The structure of the middle intermediary layer 32 is roughly the same as that of the upper intermediary layer 30. The difference is that the protrusion 36 of the middle intermediary layer 32 is offset from the protrusion 36 of the upper intermediary layer 30, so that the concave portions 37 of the middle and upper intermediary layers are offset from each other.

[0056] The lower intermediate layer 33 has a structure that is roughly the same as the middle intermediate layer 32, except that the protrusions 36 and concave parts 37 of the lower and middle intermediate layers are also designed with a staggered arrangement.

[0057] When the cover 11 covers the semiconductor wafer stack structure, the upper, middle, and lower interposer layers 30, 32, and 33 contact the network 14 with protrusions 36, which are arranged in a stepped manner from top to bottom. Simultaneously, the recesses 37 staggered from the upper interposer layer 30 to the lower interposer layer 33 form a flow channel 34, which maintains an inclined angle and connects to the vapor chamber 13. Thus, a set of flow channels 34 exists around the periphery of the semiconductor wafer stack structure.

[0058] like Figure 8 , Figure 9 As shown, the group of heat-conducting pillars 43 extends from the upper interposer layer 30 through the middle interposer layer 32 to the lower interposer layer 33. Each heat-conducting pillar 43 is a copper pillar with excellent thermal conductivity, and a tin spot (not shown) is attached to its end, which can be fused to the corresponding electrical contact 21 on the base plate 20. In the semiconductor wafer stack structure, the heat-conducting pillar 43 is non-conductive, but it has a thermal conduction function with the electrical contact 21.

[0059] The semiconductor wafer 44 is located in the mounting area 41. Each interposer layer contains electronic circuitry (not shown) that inputs (or outputs) power (or a signal) between the semiconductor wafer 44 and the set of conductive posts 42. The conductive posts 42 of the upper interposer layer 30 are connected to the electrical contacts 21 of the base plate 20 via the conductive posts 42 of the middle and lower interposer layers 32 and 33; the conductive posts 42 of the middle interposer layer 32 are connected to the electrical contacts 21 of the base plate 20 via the conductive posts 42 of the lower interposer layer 33; and the conductive posts 42 of the lower interposer layer 33 are directly connected to the electrical contacts 21 of the base plate 20. Therefore, the package structure 10 possesses conductive properties.

[0060] like Figure 5 , Figure 6 , Figure 10 , Figure 13 As shown, in this embodiment, the cooling fluid is ultrapure water. This ultrapure water has a thermal conductivity that allows for liquid-to-gas phase conversion within the fixed-volume vapor chamber 13; therefore, adding an appropriate amount of ultrapure water to the vapor chamber 13 is sufficient. In some embodiments, the cooling fluid is selected from ethanol, butane, and mixtures thereof.

[0061] Assume that ultrapure water lies beneath the vapor chamber 13. Due to capillary action, this ultrapure water flows against gravity along the capillary structure 15 surrounding the cover 11 to the top surface inside the cover 11. The mesh 14 contacts each protrusion 36 with a gap, allowing the ultrapure water to rise through the gaps from the lower intermediate layer 33, through the middle intermediate layer 32, to the upper intermediate layer 30, thereby diffusing to the top capillary structure 31 and bottom capillary structure 35 of each intermediate layer 30, 32, 33.

[0062] exist Figure 8 , Figure 9 In the process of electrical conduction, the semiconductor wafers 44 in each layer perform logical operations and generate high temperatures. The lower interposer layer 33, located at the bottom of the semiconductor wafer stack structure, accumulates more heat than other interposers. Therefore, heat is conducted from the bottom semiconductor wafer 44 to the lower interposer layer 33. The ultrapure water in the lower interposer layer 33 is heated, changing from a liquid to a gaseous state, and diffuses to the surrounding area along the top capillary structure 31 and the bottom capillary structure 35. Due to the characteristic of high-temperature to low-temperature transfer, the vapor flows from the channel 34 along arrow 50 (see...). Figure 6 The heat flows in the direction of the liquid to the top surface inside the cover 11, carrying away the heat from the underlying semiconductor chip 44.

[0063] Simultaneously, the semiconductor wafer 44 in the middle of the semiconductor wafer stack structure conducts heat to the intermediate layer 32, causing the ultrapure water in the top capillary structure 31 and the bottom capillary structure 35 to change from a liquid state to high-temperature steam. This steam flows through the channel 34 along arrow 50 (see...). Figure 6 The heat flows in the direction of the liquid to the top surface inside the cover 11, carrying away the heat from the semiconductor chip 44 in the middle.

[0064] Furthermore, the top semiconductor wafer 44, separated by a mesh 14, indirectly contacts the top surface of the inner side of the cover 11, while its other side touches the upper interposer layer 30. Therefore, a portion of the heat from the top semiconductor wafer 44 is conducted to the mesh 14 and then dissipated to the outside by the cover 11, while the remaining heat is conducted to the upper interposer layer 30. This causes the ultrapure water in the top capillary structure 31 and the bottom capillary structure 35 to transform from a liquid state into high-temperature vapor, which mixes with the gases from the middle and lower interposer layers 32 and 33 and passes through the mesh, resulting in heat convection of the ultrapure water in the capillary structure 15 of the cover 11. This ultrapure water undergoes heat exchange to become high-temperature gas, which can be conducted to the wall of the capillary structure 15 and dissipated to the outside by the cover 11 for cooling.

[0065] like Figure 10 , Figure 13 As shown, the cooled steam condenses into ultrapure water. A portion of the ultrapure water continues to undergo thermal convection with the high-temperature gas in the capillary structure 15 of the cover 11. For the mesh 14, this ultrapure water is a wetting liquid, meaning the remaining ultrapure water can adhere to the mesh 14 on the inner top surface of the cover 11. Under gravity, the ultrapure water falls as droplets. Falling onto the top surface of the upper interposer layer 30, the ultrapure water heats the upper interposer layer 30, evaporating from a liquid state into high-temperature gas and rising again. Falling onto the portion of the protrusion 36 that contacts the mesh 14, it diffuses through the capillary action of the gaps to the top capillary structure 31 and bottom capillary structure 35 of the upper interposer layer 30, again carrying away heat from the top or middle layer semiconductor wafer 44.

[0066] Some ultrapure water drips through the flow channel 34 onto the protrusions 36 of the middle interposer 32 or the lower interposer 33. It can usually diffuse to the top capillary structure 31 of the middle and lower interposers 32 and 33, or diffuse to the bottom capillary structure 35 of the middle and lower interposers 32 and 33 through the gaps in the contact mesh 14 of the protrusions 36, and can also carry away the heat of the middle or lower semiconductor wafer 44.

[0067] Thus, the ultrapure water undergoes a liquid-to-gas thermal cycle between the capillary structure 15, the flow channel 34, the top capillary structure 31, and the bottom capillary structure 35, achieving a heat dissipation effect for the semiconductor wafer.

[0068] like Figure 11 , Figure 12 As shown, the second embodiment of the encapsulation structure 10 of the present invention is constructed in a manner similar to the first embodiment, except that a set of fasteners 51 attaches a set of heat dissipation fins 52 to the outside of the cover 11, thereby improving the heat dissipation effect of the encapsulation structure 10.

[0069] The above description is illustrative only and not restrictive of the present invention. Those skilled in the art will understand that many modifications, variations or equivalents can be made without departing from the spirit and scope defined by the claims, and all such modifications, variations or equivalents will fall within the protection scope of the present invention.

Claims

1. A semiconductor three-dimensional packaging structure with a vapor chamber, characterized in that, include: A base plate; Multiple semiconductor wafers are stacked on the substrate through multiple interposers. Each interposer has a top capillary structure and a bottom capillary structure. The periphery of the interposer has a set of protrusions, with a recess between two protrusions. An inner layer of the cover contains a set of capillary structures and a mesh, which shields the capillary structures. When the cover, combined with the base plate, forms a vapor chamber, the cover covers the entire semiconductor wafer. All the interposers contact the mesh with protrusions, and the recess from the upper interposer to the lower interposer forms a flow channel connecting to the vapor chamber. An appropriate amount of cooling fluid is added to the vapor chamber, and a liquid-to-gas thermal cycle is carried out between the capillary structure, the flow channel, the top capillary structure, and the bottom capillary structure to achieve the heat dissipation effect of the semiconductor wafer.

2. The semiconductor three-dimensional packaging structure with a vapor chamber as described in claim 1, characterized in that, The recesses of the upper and lower intermediate layers are staggered to maintain an inclined flow channel, so that the protrusions of the upper and lower intermediate layers are arranged in a stepped state.

3. The semiconductor three-dimensional packaging structure with a vapor chamber as described in claim 1, characterized in that, The lid is made of copper, copper alloy, or one of other thermally conductive metals.

4. The semiconductor three-dimensional packaging structure with a vapor chamber as described in claim 1, characterized in that, The surface of the lid is coated with copper, copper alloys, or one of other thermally conductive metals.

5. The semiconductor three-dimensional packaging structure with a vapor chamber as described in claim 1, characterized in that, The capillary structure consists of interlaced gaps and is formed on the surface of the lid by means of etching, laser engraving, stamping, or die casting.

6. The semiconductor three-dimensional packaging structure with a vapor chamber as described in claim 1, characterized in that, The cooling fluid is selected from one of ultrapure water, ethanol, butane, and mixtures thereof.

7. The semiconductor three-dimensional packaging structure with a vapor chamber as described in claim 1, characterized in that, The interlayer is a ceramic substrate.

8. The semiconductor three-dimensional packaging structure with a vapor chamber as described in claim 1, characterized in that, A set of heat-conducting pillars are arranged in an array and pass through all the stacked intermediate layers.

9. The semiconductor three-dimensional packaging structure with a vapor chamber as described in claim 1, characterized in that, The cover is fitted with a set of heat dissipation fins.

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