A grid-connected T-type inverter fault real-time detection method and device
By calculating the Hausdorff distance and fundamental frequency value of the three-phase current signals, the complexity and robustness of open-circuit fault diagnosis in T-type inverters are solved, achieving low-cost and accurate fault detection and location.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUAZHONG UNIV OF SCI & TECH
- Filing Date
- 2022-11-17
- Publication Date
- 2026-04-17
AI Technical Summary
In existing technologies, open-circuit fault diagnosis methods for T-type inverters suffer from problems such as complex models, excessive signals or parameters, and weak robustness, resulting in poor diagnostic capabilities and difficulty in achieving real-time and accurate fault detection and location.
Fault detection is performed using three-phase current signals. By setting the sampling frequency and sliding window length, the Hausdorff distance and fundamental frequency value are calculated. Combined with the current reference value and fault threshold, real-time detection and location of inverter power tube faults are achieved.
It achieves low-cost, low-complexity fault detection and location, has high robustness, can accurately identify faults under inverter transient conditions, and requires no additional hardware sensors, thus consuming few computing resources.
Smart Images
Figure CN115825620B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of power grid fault detection technology, and more specifically, relates to a method and device for real-time fault detection of grid-connected T-type inverters. Background Technology
[0002] Since the Industrial Revolution, with the overexploitation and gradual consumption of fossil fuels, the energy crisis and environmental degradation have become increasingly severe. The utilization of new energy sources, achieving zero carbon emissions, is the trend for future energy development. Grid-connected T-type inverters, as a crucial power conversion device in new energy power generation, have reliability that significantly impacts energy conversion efficiency and quality, and is a major factor affecting electricity safety. Among the components of inverters, power transistors suffer from a high proportion of device faults and difficulties in diagnosing open-circuit faults. Real-time detection and precise location technologies can promptly identify faults, provide guidance for fault-tolerant control and operation and maintenance strategies, prevent catastrophic secondary failures, and ensure the reliability and safety of the equipment.
[0003] Most published literature on real-time open-circuit fault diagnosis methods for T-type inverters is model-based. These methods utilize a large number of system signals or parameters to construct accurate circuit or signal flow models, calculating signal residuals to achieve fault detection and diagnosis. However, this approach suffers from limitations such as the excessive use of signals or parameters and the complexity of model construction, leading to poor applicability. Other signal-based methods also suffer from issues such as excessive threshold selection and weak robustness. To improve the applicability and robustness of diagnostic methods, a robust diagnostic method designed with a small number of system signals or parameters is needed. Summary of the Invention
[0004] In view of the above-mentioned defects or improvement needs of the existing technology, the present invention provides a method and device for real-time fault detection of grid-connected T-type inverters, the purpose of which is to achieve fault detection through a small number of system signals and diagnostic thresholds.
[0005] To achieve the above objectives, according to one aspect of the present invention, a real-time fault detection method for a grid-connected T-type inverter is provided, which samples the three-phase current i at a set sampling frequency. x x = a, b, c, the ratio of the three-phase current sampling frequency to the grid frequency is taken as the number of samples L of a sliding window, and the sliding window is shifted 2L times from the start of the cycle as a detection cycle. In each detection cycle, the fault is detected based on the selected three-phase current.
[0006] The fault detection process, based on selected three-phase currents, is performed within each detection cycle, including:
[0007] For each phase current i xPerform three-phase normalization processing separately to obtain the three-phase normalized current.
[0008] Calculate the normalized mean current or a proportional value of the mean current for each phase state x within each sliding window w as the current reference value I. xw ;
[0009] For each phase state x, select the maximum current reference value within the current detection cycle. and minimum current reference value Obtain the point set for each phase
[0010] Calculate the Hausdorff distance H between the a-phase point set and the b-phase point set, respectively. ab The Hausdorff distance H between the set of phase points b and the set of phase points c bc And the Hausdorff distance H between the set of c phase points and the set of a phase points. ca And select H ab H bc and H ca The median is used as the fault detection information H;
[0011] Determine if the fault detection information H is greater than the fault threshold. If yes, determine if the inverter has a power transistor fault; otherwise, determine if the inverter has not a power transistor fault.
[0012] In one embodiment, the method for locating the faulty phase includes:
[0013] When determining that a power transistor fault has occurred in the inverter, the phase state corresponding to the minimum fundamental frequency value among the fundamental frequency values of each phase determined based on the last sliding window of the current detection cycle is taken as the fault phase y of the current fault.
[0014] One method for determining the phase state corresponding to the minimum fundamental frequency value within a sliding window includes: calculating the fundamental frequency values of each phase within the corresponding sliding window. Compare F a F b F c The phase state corresponding to the minimum fundamental frequency value is obtained, where i xj Let be the j-th x-phase current within the current sliding window.
[0015] In one embodiment, the method further includes locating the faulty power transistor, wherein the method for locating the faulty power transistor includes using the intersection power transistor of a first group of fault prediction power transistors determined based on the last slide window of the current detection cycle and a second group of fault prediction power transistors determined based on the last L slide windows of the current detection cycle as the faulty power transistor of the current fault.
[0016] The method for determining the first group of fault prediction power transistors includes:
[0017] Compare the reference current I of the faulty phase y within the sliding window w. yw The magnitude of I and 0: If I yw If the value is greater than 0, then the first group of fault prediction power transistors is determined to be S. y2 or S y4 ;if I yw If <0, then the first group of fault prediction power transistors is determined to be S. y1 or S y3 ;
[0018] The methods for determining the second group of fault prediction power transistors include:
[0019] Determine the maximum fundamental frequency value among the three-phase fundamental frequency values within the sliding window, and determine the maximum value F among the L maximum fundamental frequency values calculated by the L sliding windows. max ;
[0020] Determine the minimum value F of the fundamental frequency of the faulty phase y in L sliding windows. min ;
[0021] Compare F min and F max / 2: If F min >F max / 2, then the second group of fault prediction power transistors is determined to be S. y2 or S y3 If F min <F max / 2, then the second group of fault prediction power transistors is determined to be S. y1 or S y4 ;
[0022] Wherein: S y1 For the faulty phase upper arm power transistor of the T-type inverter, S y4 For the power transistor of the lower arm of the faulty phase in a T-type inverter, S y2 S is the power transistor in the bridge arm of the faulty phase connected to the center point of the bus in a T-type inverter. y3 This refers to the power transistor in the faulty phase of a T-type inverter, which is connected to the center point of the upper and lower bridge arms.
[0023] In one embodiment, the three-phase normalized current is calculated. The formula is:
[0024]
[0025] In one embodiment, Hausdorff is far from H ab H bc and H ca The calculation formulas are as follows:
[0026]
[0027]
[0028]
[0029] In one embodiment, the fault threshold th can be set as follows:
[0030]
[0031] 0.2≤q≤0.3.
[0032] In one embodiment, if no fault is detected when the current sampling point is used as the starting point of the current detection cycle, the detection continues from the next adjacent sampling point as the starting point of the next detection cycle.
[0033] According to another aspect of the present invention, a real-time fault detection device for a grid-connected T-type inverter is provided, comprising:
[0034] The normalization module is used to process the current i of each phase. x Perform three-phase normalization processing separately to obtain the three-phase normalized current.
[0035] The current reference value calculation module calculates the normalized mean current or a proportional value of the mean current for each phase state x within each sliding window w as the current reference value I. xw In this case, the number of samples L for each sliding window is the rounded ratio of the three-phase current sampling frequency to the grid frequency.
[0036] The point set selection module is used to select the maximum current reference value within the current detection cycle for each phase state x. and minimum current reference value Obtain the point set for each phase Each detection cycle consists of sliding windows that move 2L backwards from the start of the cycle.
[0037] The Hausdorff distance calculation module is used to calculate the Hausdorff distance H between the set of a-phase points and the set of b-phase points within the current detection period. ab The Hausdorff distance H between the set of phase points b and the set of phase points c bc And the Hausdorff distance H between the set of c phase points and the set of a phase points. ca And select H ab H bc and H ca The median is used as the fault detection information H;
[0038] The fault determination module determines whether the fault detection information H is greater than the fault threshold. If yes, it determines that the inverter has a power transistor fault; otherwise, it determines that the inverter has not a power transistor fault.
[0039] In one embodiment, it further includes:
[0040] The fundamental frequency calculation module is used to calculate the fundamental frequency F of each phase within the sliding window. x
[0041]
[0042] Among them, i xj Let x be the current of the j-th phase x within the current sliding window;
[0043] The fault phase location module is used to identify the phase state corresponding to the minimum fundamental frequency value among the fundamental frequency values of each phase determined based on the last sliding window of the current detection cycle as the fault phase y of the current fault.
[0044] In one embodiment, it further includes;
[0045] The first group of fault power transistor prediction modules is used to compare the current reference value I of the faulty phase y within the sliding window w. yw The magnitude of I and 0: If I yw If the value is greater than 0, then the first group of fault prediction power transistors is determined to be S. y2 or S y4 ;if I yw If <0, then the first group of fault prediction power transistors is determined to be S. y1 or S y3 ;
[0046] The second group of fault power transistor prediction modules is used to compare F min and F max / 2: If F min >F max / 2, then the second group of fault prediction power transistors is determined to be S. y2 or S y3 If F min <F max / 2, then the second group of fault prediction power transistors is determined to be S. y1 or S y4 Among them, F max To determine the maximum fundamental frequency value among the three-phase fundamental frequency values within the sliding window w Then, the maximum value is selected from the L maximum fundamental frequency values calculated by L sliding windows, F. min The minimum fundamental frequency value of the faulty phase y in the L sliding windows;
[0047] The fault power transistor location module is used to identify the current fault power transistor by taking the intersection power transistor of the first group of fault prediction power transistors determined based on the last sliding window of the current detection cycle and the second group of fault prediction power transistors determined based on the last L sliding windows of the current detection cycle.
[0048] Wherein: S y1 For the faulty phase upper arm power transistor of the T-type inverter, S y4 For the power transistor of the lower arm of the faulty phase in a T-type inverter, S y2 S is the power transistor in the bridge arm of the faulty phase connected to the center point of the bus in a T-type inverter. y3 This refers to the power transistor in the faulty phase of a T-type inverter, which is connected to the center point of the upper and lower bridge arms.
[0049] In summary, compared with the prior art, the above-described technical solutions conceived by this invention can achieve the following beneficial effects:
[0050] (1) Low cost: This invention only uses three-phase current signals for fault detection and location, and does not require any hardware sensors other than those necessary for the normal control system. It is highly portable.
[0051] (2) Fewer diagnostic thresholds: This invention only requires one diagnostic threshold and does not require complex manual adjustment, making it highly usable;
[0052] (3) Good robustness. This invention can cope with inverter transient conditions and grid transient conditions, such as grid faults and sensor faults. This invention will not cause false alarms.
[0053] (4) Simple to implement. This invention is implemented in software, which consumes less CPU resources and has low computational complexity. Attached Figure Description
[0054] Figure 1 This is a T-type three-phase four-wire rectifier topology in one embodiment;
[0055] Figure 2 This is a flowchart of the steps of a real-time fault detection method for a grid-connected T-type inverter in one embodiment;
[0056] Figure 3 This is a flowchart of the steps in a real-time fault detection method for grid-connected T-type inverters with added fault phase location in one embodiment.
[0057] Figure 4 This is a flowchart of the steps in a real-time fault detection method for a grid-connected T-type inverter with added fault power transistor location in one embodiment.
[0058] Figure 5This is a flowchart of the steps of a faulty power transistor location method in one embodiment;
[0059] Figure 6 This is a structural block diagram of a grid-connected T-type inverter fault real-time detection device in one embodiment;
[0060] Figure 7 This is a diagram showing the physical experimental results of fault detection using the present invention in one embodiment, where (a) represents the original sampled three-phase current i x (b) represents the normalized three-phase current after normalization. (c) represents the reference current value for the three phases, (d) represents the fault detection information H and the fault threshold th, and (e) represents the fundamental frequency value F of the three phases. a F b F c (f) represents the F of the faulty phase. min and F max / 2. Detailed Implementation
[0061] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.
[0062] like Figure 1 The diagram shows a T-type three-phase four-wire rectifier topology in one embodiment. The system consists of power transistors (S... a1 S a2 S a3 S a4 S b1 S b2 S b3 S b4 S c1 S c2 S c3 S c4 ) Corresponding diode (D a1 D a2 D a3 D a4 D b1 D b2 D b3 D b4 D c1 D c2 D c3 D c4 It consists of busbar energy storage capacitors (C1, C2), Uc1 U c2 These are the voltages of the two capacitors, and E is the DC bus voltage source, where S... x1 For the power transistors of the upper arm of the x-phase bridge of a T-type inverter, S x4 For the lower arm power transistor of the x-phase of a T-type inverter, S x2 S is the power transistor in the x-phase bridge arm of a T-type inverter connected to the center point of the bus. x3 i is the power transistor in phase x of a T-type inverter, connected to the center point of the upper and lower bridge arms. a i b i c For three-phase current, i is used in fault detection according to this invention. a i b i c For variables that need to be collected in real time, based on the collected i a i b i c By performing analysis, fault detection can be achieved.
[0063] In this invention, faults can be periodically detected. A detection cycle start point is set, and data collected within one detection cycle is used for fault analysis. If no fault is identified, the detection process continues in the next detection cycle until a fault is identified. Specifically, each sampling point can be used as the start point of a new detection cycle, with each subsequent detection cycle shifting one sampling point backward relative to the previous one. That is, after the first detection cycle, a periodic fault detection is performed for each additional set of three-phase sampling currents. Alternatively, after the previous cycle of fault detection is completed, a certain time interval can be set before triggering the next cycle of fault detection. The specific triggering method for fault detection can be flexibly set as needed.
[0064] In this invention, the sampling span of a detection cycle is related to the sampling frequency and the power grid frequency. Specifically, the ratio of the three-phase current sampling frequency to the power grid frequency is rounded down to form a sampling number L of a sliding window, and the sliding window is shifted 2L times from the start of the cycle to form a detection cycle.
[0065] Let the current sampling rate be f c The power grid frequency is f g The formula for calculating the length L of the sliding window is:
[0066]
[0067] If L is a decimal, then the integer part of the result can be taken.
[0068] In this invention, starting from the period start point, the sliding window is moved 2L times to form a detection period. For example, L=3, one sliding window spans 3 sampling points, requiring 2L=6 sliding window movements to form a period span. Selecting sampling point t1 as the period start point and setting the sliding window movement compensation to 1, the sampling point set of the first sliding window is t1~t3, the sampling point set of the second sliding window is t2~t4, the sampling point set of the third sliding window is t3~t5, the sampling point set of the fourth sliding window is t4~t6, the sampling point set of the fifth sliding window is t5~t7, and the sampling point set of the sixth sliding window is t6~t8. That is, the detection period starting from t1 spans 8 sets of sampling data (t1~t8), with each adjacent 3 sets forming a single sliding window, resulting in 6 sets of sliding window data. Assuming that fault detection is performed for each new sampling point, after obtaining the sampling point t9, the next detection cycle will start from t2 and use t2 to t9 as the next detection cycle for fault detection.
[0069] In each detection cycle, fault analysis is performed based on the three-phase current collected in the current detection cycle, such as... Figure 2 As shown, fault detection mainly includes the following steps:
[0070] Step S110: For each phase current i x Perform three-phase normalization processing separately to obtain the three-phase normalized current.
[0071] During current sampling, the three-phase current i is sampled at each sampling point. a i b i c The three-phase current at each sampling point is normalized using the following formula:
[0072]
[0073] Where x equals a, b, and c.
[0074] Step S120: Calculate the normalized mean current or the proportional value of the mean current for each phase state x within each sliding window w as the current reference value I. xw .
[0075] The formula for calculating the normalized mean current of each phase state x is:
[0076]
[0077] in, This represents the j-th sampling point of phase state x within the current sliding window.
[0078] The above average value can be used directly as the current reference value, or several other average values can be used as the current reference value I.xw Thus, the current reference value I for each phase of each sliding window w is obtained. aw I bw I cw .
[0079] Step S130: For each phase state x, select the maximum current reference value within the current detection cycle. and minimum current reference value Obtain the point set for each phase
[0080] There are 2L sliding window sets within one detection cycle, and each sliding window set has a current reference value I for the three-phase current. aw I bw I cw Select the maximum current reference value within the current detection cycle. and minimum current reference value in,
[0081]
[0082] Step S140: Calculate the Hausdorff distance H between the a-phase point set and the b-phase point set respectively. ab The Hausdorff distance H between the set of phase points b and the set of phase points c bc And the Hausdorff distance H between the set of c phase points and the set of a phase points. ca And select H ab H bc and H ca The median is used as the fault detection information H.
[0083] Specifically, the formula for calculating the Hausdorff distance of each set of points is as follows:
[0084]
[0085]
[0086]
[0087] H = mid(H) ab H bc H ca )
[0088] The median refers to H ab H bc and H ca The value in the middle is the median value.
[0089] Step S150: Determine whether the fault detection information H is greater than the fault threshold. If yes, determine that the inverter has a power transistor fault; otherwise, determine that the inverter has not a power transistor fault.
[0090] The fault threshold is the maximum H value obtained using the above method when no power transistor fault occurs. It can be determined directly through simulation or by fitting simulation results to obtain a corresponding formula. In this embodiment, the fault threshold th is calculated using the following formula:
[0091]
[0092] 0.2≤q≤0.3.
[0093] Where q is the volatility coefficient.
[0094] The rules for power transistor fault detection are as follows:
[0095]
[0096] By following steps S110 to S150, it can be determined whether a power transistor fault has occurred in the current cycle. If no power transistor fault has occurred, the detection continues in the next fault cycle. Understandably, if the parameters used for fault determination in subsequent cycles have already been calculated during the initial determination period, they do not need to be recalculated and can be directly used.
[0097] In this embodiment, while determining that a power transistor fault has occurred, the faulty phase is also located. Therefore, as... Figure 3 As shown, the above method also includes:
[0098] Step S200: Take the phase state corresponding to the smallest fundamental frequency value among the fundamental frequency values of each phase determined based on the last sliding window of the current detection cycle as the fault phase y of the current fault.
[0099] In other words, the phase state determined by the data collected in the 2Lth sliding window of the current detection cycle is taken as the fault phase y of the current fault.
[0100] Specifically, the fundamental frequency value F of each phase of each sliding window is calculated based on the sampled data in each sliding window. x The calculation formula is:
[0101]
[0102] in, and To calculate intermediate quantities.
[0103] The fault phase within the corresponding sliding window is located by the relative magnitude of the fundamental frequency value:
[0104] min(Fa F b F c ) = F y The Y phase has malfunctioned.
[0105] Specifically, a fault phase analysis can be performed every time a sliding window is moved. Each sliding window will output a fault phase. Only when sliding window 2L is moved and a fault is determined to have occurred is the final output fault phase valid; otherwise, it is an invalid fault phase and no action is taken. Alternatively, only the fault phase of the last sliding window in the current detection cycle can be calculated, and when a fault is determined to have occurred, that fault phase can be output.
[0106] In one embodiment, after locating the faulty phase, the specific faulty power transistor is further located; therefore, as... Figure 4 As shown, it also includes:
[0107] Step S300: The intersection power transistor of the first group of fault prediction power transistors determined based on the last sliding window of the current detection cycle and the second group of fault prediction power transistors determined based on the last L sliding windows of the current detection cycle is taken as the fault power transistor of the current fault.
[0108] In other words, locating a faulty power transistor requires dividing the process into two groups: Figure 5 As shown, step S300 includes:
[0109] The method for locating faulty power transistors and determining the first group of fault prediction power transistors by using the relative magnitude of the fundamental frequency value includes:
[0110] Step S310: Compare the current reference value I of the faulty phase y within the sliding window w. yw Size of 0:
[0111] I yw >0, S y2 / S y4 Fault pre-positioned
[0112] I yw <0, S y1 / S y3 Fault pre-positioned
[0113] The method for locating faulty power transistors and determining the second group of fault prediction power transistors by utilizing the fundamental frequency symmetry of three-phase currents includes:
[0114] Step S321: Determine the maximum fundamental frequency value among the three-phase fundamental frequency values within the sliding window w.
[0115]
[0116] Step S322: Determine the maximum value F among the L maximum fundamental frequency values calculated by the L sliding windows. max ;
[0117]
[0118] Step S323: Determine the minimum fundamental frequency value F of the faulty phase y in the L sliding windows. min ;
[0119] F min =min(F y1 F y2 F yL )
[0120] Among them, F yw y is the fundamental frequency value of the faulty phase y in the sliding window w.
[0121] Step S324: Compare F min and F max / 2:
[0122]
[0123] Step S330: Use the power transistor at the intersection of the first group of fault prediction power transistors and the second group of fault prediction power transistors as the fault power transistor for the current fault.
[0124] Specifically, the fault power transistor can be determined during the fault determination process, or it can be determined after the fault has been detected. Only the fault power transistor output when the fault has been detected is valid.
[0125] Accordingly, the present invention also relates to a real-time fault detection device for grid-connected T-type inverters, such as... Figure 6 As shown, the detection device includes a normalization processing module, a current reference value calculation module, a point set selection module, a Hausdorff distance calculation module, and a fault determination module. These modules can determine whether the power transistor has malfunctioned.
[0126] The normalization module is used to process the current i of each phase. x Perform three-phase normalization processing separately to obtain the three-phase normalized current.
[0127] The current reference value calculation module is used to calculate the normalized mean current or a proportional value of the mean current for each phase state x within each sliding window w, as the current reference value I. xw In this case, the number of samples L for each sliding window is the rounded ratio of the three-phase current sampling frequency to the grid frequency.
[0128] The point set selection module is used to select the maximum current reference value within the current detection cycle for each phase state x. and minimum current reference value Obtain the point set for each phase Each detection cycle consists of sliding windows that move 2L backwards from the start of the cycle.
[0129] The Hausdorff distance calculation module is used to calculate the Hausdorff distance H between the set of a-phase points and the set of b-phase points within the current detection period. ab The Hausdorff distance H between the set of phase points b and the set of phase points c bc And the Hausdorff distance H between the set of c phase points and the set of a phase points. ca And select H ab H bc and H ca The median is used as the fault detection information H;
[0130] The fault determination module is used to determine whether the fault detection information H is greater than the fault threshold. If it is, the inverter is determined to have a power transistor fault; otherwise, the inverter is determined not to have a power transistor fault.
[0131] Furthermore, the detection device also includes a fundamental frequency value calculation module and a fault phase location module for locating the fault phase. Among these,
[0132] The fundamental frequency calculation module is used to calculate the fundamental frequency F of each phase within the sliding window. x
[0133]
[0134] Among them, i xj Let x be the current of the j-th phase x within the current sliding window;
[0135] The fault phase location module is used to identify the phase state corresponding to the minimum fundamental frequency value among the fundamental frequency values of each phase determined based on the last sliding window of the current detection cycle as the fault phase y of the current fault.
[0136] Furthermore, the detection device also includes a first set of fault power transistor prediction modules, a second set of fault power transistor prediction modules, and a fault power transistor location module, used to locate the faulty power transistor. Among these,
[0137] The first set of fault power transistor prediction modules is used to compare the current reference value I of the faulty phase y within the sliding window w. yw The magnitude of I and 0: If I yw If the value is greater than 0, then the first group of fault prediction power transistors is determined to be S. y2 or S y4 ;if I yw If <0, then the first group of fault prediction power transistors is determined to be S. y1 or S y3 ;
[0138] The second set of fault power transistor prediction modules is used to compare F min and F max / 2: If F min >F max / 2, then the second group of fault prediction power transistors is determined to be S. y2 or S y3 If F min <F max / 2, then the second group of fault prediction power transistors is determined to be S. y1 or S y4 Among them, F max To determine the maximum fundamental frequency value among the three-phase fundamental frequency values within the sliding window w Then, the maximum value is selected from the L maximum fundamental frequency values calculated by L sliding windows, F. min The minimum fundamental frequency value of the faulty phase y in the L sliding windows;
[0139] The fault power transistor location module is used to identify the current fault power transistor as the intersection power transistor of the first group of fault prediction power transistors determined based on the last sliding window of the current detection cycle and the second group of fault prediction power transistors determined based on the last L sliding windows of the current detection cycle.
[0140] like Figure 7 The diagram shows the physical experimental results of fault detection according to the present invention. The first vertical dashed line represents the actual fault point, and the second dashed line represents the fault point determined by the present invention. A brief delay occurs due to the time required for calculation. Specifically, (a) represents the original sampled three-phase current i. x (b) represents the normalized three-phase current after normalization. (d) shows the comparison result between the fault detection information H and the fault threshold th, from which it can be seen that the fault was identified at the position of the second vertical dashed line. (e) shows the result of comparing F. a F b F c The faulty phase is located, specifically phase b. (c) and (f) show the locations of the two sets of power transistors respectively. (c) represents a comparison of the faulty phase current reference values, from which the first set of power transistors, S, is located. b1 / S b3 (f) represents the F of the faulty phase. min and F max By comparing / 2, the second group of power transistors is located as S. b1 / S b4 The faulty power transistor was ultimately located as S. b1 The faults matched the actual fault settings perfectly, indicating that the present invention can perform accurate fault diagnosis.
[0141] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A method for real-time fault detection in a grid-connected T-type inverter, characterized in that, The three-phase currents are sampled at the set sampling frequency. , The ratio of the three-phase current sampling frequency to the grid frequency is rounded down to form a sliding window sampling number. 2 from the start of the cycle The secondary sliding window serves as a detection cycle, during which faults are detected based on the selected three-phase current. The fault detection process, based on selected three-phase currents, is performed within each detection cycle, including: For each phase current Perform three-phase normalization processing separately to obtain the three-phase normalized current. ; Calculate each sliding window Internal phases The normalized mean current or a proportional value of the mean current is used as the current reference value. ; For each phase state Select the maximum current reference value within the current detection cycle. and minimum current reference value This yields the point set for each phase. ; Calculate the Hausdorff distance between phase point set a and phase point set b, respectively. Hausdorff distance between the set of phase points b and the set of phase points c And the Hausdorff distance between the set of phase points c and the set of phase points a. And select , and The median is used as fault detection information. ; Determine fault detection information If the value exceeds the fault threshold, the inverter is determined to have a power transistor fault; otherwise, the inverter is determined not to have a power transistor fault. The method further includes locating the faulty power transistor, wherein the method for locating the faulty power transistor includes taking the intersection power transistor of a first group of fault prediction power transistors determined based on the last sliding window of the current detection cycle and a second group of fault prediction power transistors determined based on the last L sliding windows of the current detection cycle as the faulty power transistor of the current fault. The method for determining the first group of fault prediction power transistors includes: Comparison of sliding windows Internal fault phase Current reference value The size of 0: If Then the first group of fault prediction power transistors is determined to be... or ;like Then the first group of fault prediction power transistors is determined to be... or ; The methods for determining the second group of fault prediction power transistors include: Determine the maximum fundamental frequency value among the three-phase fundamental frequency values within the sliding window, and determine the maximum value among the L maximum fundamental frequency values calculated by the L sliding windows. ; Determine the faulty phase The minimum value of the fundamental frequency among L sliding windows ; Compare and :like Then the second group of fault prediction power transistors is determined to be... or ;like Then the second group of fault prediction power transistors is determined to be... or ; in: For the faulty phase upper arm power transistor of the T-type inverter, For the power transistor of the lower arm of the faulty phase in a T-type inverter, For the faulty phase arm power transistor in a T-type inverter connected to the center point of the bus, This refers to the power transistor in the faulty phase of a T-type inverter, which is connected to the center point of the upper and lower bridge arms.
2. The real-time fault detection method for grid-connected T-type inverters as described in claim 1, characterized in that, It also includes locating the faulty phase, the method for locating the faulty phase comprising: When determining that a power transistor fault has occurred in the inverter, the phase state corresponding to the minimum fundamental frequency value among the fundamental frequency values of each phase determined based on the last sliding window of the current detection cycle is taken as the faulty phase. ; One method for determining the phase state corresponding to the minimum fundamental frequency value within a sliding window includes: calculating the fundamental frequency values of each phase within the corresponding sliding window. ,Compare , , The phase state corresponding to the minimum fundamental frequency value is obtained, where, For the first in the current sliding window indivual Phase current.
3. The real-time fault detection method for grid-connected T-type inverters as described in claim 1, characterized in that, Calculate the normalized three-phase current The formula is: 。 4. The real-time fault detection method for grid-connected T-type inverters as described in claim 1, characterized in that, Hausdorf Distance , and The calculation formulas are as follows: ； ； 。 5. The real-time fault detection method for grid-connected T-type inverters as described in claim 1, characterized in that, Fault threshold It can be set as follows: ； 。 6. The real-time fault detection method for grid-connected T-type inverters as described in any one of claims 1 to 5, characterized in that, If no fault is detected when the current sampling point is used as the starting point of the current detection cycle, the detection continues from the next adjacent sampling point as the starting point of the next detection cycle.
7. A real-time fault detection device for a grid-connected T-type inverter, characterized in that, include: The normalization module is used to process the current of each phase. Perform three-phase normalization processing separately to obtain the three-phase normalized current. ; The current reference value calculation module calculates the current for each sliding window. Internal phases The normalized mean current or a proportional value of the mean current is used as the current reference value. The number of samples for each sliding window The ratio of the three-phase current sampling frequency to the grid frequency is rounded down. The point set selection module is used to select each phase state separately. Select the maximum current reference value within the current detection cycle. and minimum current reference value This yields the point set for each phase. Each detection cycle is 2 seconds after the start of the cycle. Secondary sliding window; The Hausdorff distance calculation module is used to calculate the Hausdorff distance between the set of a-phase points and the set of b-phase points within the current detection period. Hausdorff distance between the set of phase points b and the set of phase points c And the Hausdorff distance between the set of phase points c and the set of phase points a. And select , and The median is used as fault detection information. ; The fault determination module determines the fault detection information. If the value exceeds the fault threshold, the inverter is determined to have a power transistor fault; otherwise, the inverter is determined not to have a power transistor fault. The first group of faulty power transistor prediction modules is used for comparison sliding windows. Internal fault phase Current reference value The size of 0: If Then the first group of fault prediction power transistors is determined to be... or ;like Then the first group of fault prediction power transistors is determined to be... or ; The second group of fault power transistor prediction modules is used for comparison. and :like Then the second group of fault prediction power transistors is determined to be... or ;like Then the second group of fault prediction power transistors is determined to be... or ;in, To determine the sliding window The maximum fundamental frequency value among the three internal fundamental frequency values The maximum value is then selected from the L maximum fundamental frequency values calculated using L sliding windows. For the fault phase The minimum fundamental frequency value among L sliding windows; The fault power transistor location module is used to identify the current fault power transistor by taking the intersection power transistor of the first group of fault prediction power transistors determined based on the last sliding window of the current detection cycle and the second group of fault prediction power transistors determined based on the last L sliding windows of the current detection cycle. in: For the faulty phase upper arm power transistor of the T-type inverter, For the power transistor of the lower arm of the faulty phase in a T-type inverter, For the faulty phase arm power transistor in a T-type inverter connected to the center point of the bus, This refers to the power transistor in the faulty phase of a T-type inverter, which is connected to the center point of the upper and lower bridge arms.
8. The real-time fault detection device for grid-connected T-type inverters as described in claim 7, characterized in that, Also includes: The fundamental frequency calculation module is used to calculate the fundamental frequency value of each phase within the sliding window. : ； in, For the first in the current sliding window indivual Phase current; The fault phase location module is used to identify the phase state corresponding to the minimum fundamental frequency value among the fundamental frequency values of each phase determined based on the last sliding window of the current detection cycle as the fault phase of the current fault. .