Shift register unit, gate drive circuit and driving method thereof, and display device

Abstract

The present invention provides a shift register unit, a gate drive circuit and a driving method thereof, and a display device, which relate to the field of display technology and are intended to solve the problem of abnormal output of a display device caused by abnormality of some shift register units in a gate drive circuit. In the shift register unit, a first output subcircuit is used to control whether a first clock signal input terminal is connected to a first output terminal under the control of a pull-up node; a second output subcircuit is used to control whether a second clock signal input terminal is connected to a gate drive signal output terminal under the control of a pull-up node; and a third output subcircuit is used to control whether a second clock signal input terminal is connected to a second output terminal under the control of a pull-up node.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a shift register unit, a gate drive circuit and a drive method thereof, and a display device. Background Art

[0002] The gate drive circuit included in the display device often cannot detect related defects in the front-end detection due to the characteristics of its circuit structure, and can only be detected when the array substrate is detected. Due to the complex wiring relationship of the gate drive circuit, it is difficult to repair even if a defect is detected. When a shift register unit in the gate drive circuit is abnormal, the other shift register units carried and reset by the shift register unit will all have abnormal outputs, causing the display device to display abnormally. Summary of the invention

[0003] The object of the present invention is to provide a shift register unit, a gate driving circuit and a driving method thereof, and a display device, which are used to solve the problem of abnormal output of the display device caused by abnormality of some shift register units in the gate driving circuit.

[0004] In order to achieve the above object, the present invention provides the following technical solutions:

[0005] A first aspect of the present invention provides a shift register unit, comprising:

[0006] A first output subcircuit is coupled to the pull-up node, the first clock signal input terminal and the first output terminal respectively; and is used to control whether the first clock signal input terminal and the first output terminal are connected under the control of the pull-up node;

[0007] A second output subcircuit is coupled to the pull-up node, the second clock signal input terminal and the gate drive signal output terminal respectively; and is used to control whether the second clock signal input terminal and the gate drive signal output terminal are connected under the control of the pull-up node;

[0008] The third output sub-circuit is coupled to the pull-up node, the second clock signal input terminal and the second output terminal respectively; and is used to control whether the second clock signal input terminal and the second output terminal are connected under the control of the pull-up node.

[0009] Optionally, the shift register unit further includes:

[0010] An input subcircuit, coupled to the input signal terminal and the pull-up node respectively, for controlling whether the input signal terminal and the pull-up node are connected under the control of the input signal terminal;

[0011] A first reset subcircuit is coupled to the pull-up node, the reset control terminal and the first level signal input terminal respectively, and is used to control whether the pull-up node is connected to the first level signal input terminal under the control of the reset control terminal;

[0012] A storage sub-circuit, wherein a first terminal of the storage sub-circuit is coupled to the pull-up node, and a second terminal of the storage sub-circuit is coupled to the gate drive signal output terminal.

[0013] Optionally, the shift register unit further includes:

[0014] The second reset subcircuit is coupled to the pull-up node, the frame start signal input terminal and the first level signal input terminal respectively, and is used to control whether the pull-up node and the first level signal input terminal are connected under the control of the frame start signal input terminal.

[0015] Optionally, the shift register unit further includes:

[0016] The first pull-down control subcircuit is coupled to the first level signal input terminal, the second level signal input terminal, the fourth level signal input terminal, the first pull-down node, the pull-up node, the gate drive signal output terminal and the second output terminal respectively; and is used to control whether the second level signal input terminal is connected to the first pull-down node under the control of the second level signal input terminal and the pull-up node; and is also used to control whether the first pull-down node is connected to the first level signal input terminal under the control of the pull-up node; and is also used to control whether the pull-up node is connected to the first level signal input terminal, whether the gate drive signal output terminal is connected to the fourth level signal input terminal, and whether the second output terminal is connected to the first level signal input terminal under the control of the first pull-down node.

[0017] Optionally, the shift register unit further includes:

[0018] The second pull-down control subcircuit is coupled to the first level signal input terminal, the third level signal input terminal, the fourth level signal input terminal, the second pull-down node, the pull-up node, the gate drive signal output terminal and the second output terminal respectively; and is used to control whether the third level signal input terminal is connected to the second pull-down node under the control of the third level signal input terminal and the pull-up node; and is also used to control whether the second pull-down node is connected to the first level signal input terminal under the control of the pull-up node; and is also used to control whether the pull-up node is connected to the first level signal input terminal, whether the gate drive signal output terminal is connected to the fourth level signal input terminal, and whether the second output terminal is connected to the first level signal input terminal under the control of the second pull-down node.

[0019] Optionally, the input subcircuit includes a first transistor, a gate and a first electrode of the first transistor are coupled to the input signal terminal, and a second electrode of the first transistor is coupled to the pull-up node;

[0020] The first reset sub-circuit comprises a second transistor, a gate of the second transistor is coupled to the reset control terminal, a first electrode of the second transistor is coupled to the first level signal input terminal, and a second electrode of the first transistor is coupled to the pull-up node;

[0021] The storage subcircuit comprises a storage capacitor, a first end of the storage capacitor is coupled to the pull-up node, and a second end of the storage capacitor is coupled to the gate drive signal output terminal;

[0022] The second reset subcircuit includes a seventh transistor, a gate of the seventh transistor is coupled to the frame start signal input terminal, a first electrode of the seventh transistor is coupled to the pull-up node, and a second electrode of the seventh transistor is coupled to the first level signal input terminal.

[0023] Optionally, the first pull-down control subcircuit includes a fifth transistor, a sixth transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor;

[0024] A first electrode of the fifth transistor is coupled to the second level signal input terminal, and a second electrode of the fifth transistor is coupled to the first pull-down node;

[0025] The gate of the sixth transistor is coupled to the pull-up node, the first electrode of the sixth transistor is coupled to the first pull-down node, and the second electrode of the sixth transistor is coupled to the first level signal input terminal;

[0026] The gate of the eighth transistor is coupled to the pull-up node, the first electrode of the eighth transistor is coupled to the gate of the fifth transistor, and the second electrode of the eighth transistor is coupled to the first level signal input terminal;

[0027] The gate and the first electrode of the ninth transistor are coupled to the second level signal input terminal, and the second electrode of the ninth transistor is coupled to the gate of the fifth transistor;

[0028] The gate of the tenth transistor is coupled to the first pull-down node, the first electrode of the tenth transistor is coupled to the pull-up node, and the second electrode of the tenth transistor is coupled to the first level signal input terminal;

[0029] The gate of the eleventh transistor is coupled to the first pull-down node, the first electrode of the eleventh transistor is coupled to the gate drive signal output terminal, and the second electrode of the eleventh transistor is coupled to the fourth level signal input terminal;

[0030] A gate of the twelfth transistor is coupled to the first pull-down node, a first electrode of the twelfth transistor is coupled to the second output terminal, and a second electrode of the twelfth transistor is coupled to the first level signal input terminal.

[0031] Optionally, the second pull-down control subcircuit includes a fourth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor and a twentieth transistor;

[0032] A first electrode of the fourth transistor is coupled to the third level signal input terminal, and a second electrode of the fourth transistor is coupled to the second pull-down node;

[0033] The gate of the sixteenth transistor is coupled to the pull-up node, the first electrode of the sixteenth transistor is coupled to the second pull-down node, and the second electrode of the sixteenth transistor is coupled to the first level signal input terminal;

[0034] The gate of the seventeenth transistor is coupled to the pull-up node, the first electrode of the seventeenth transistor is coupled to the gate of the fourth transistor, and the second electrode of the seventeenth transistor is coupled to the first level signal input terminal;

[0035] The gate and the first electrode of the fifteenth transistor are coupled to the third level signal input terminal, and the second electrode of the fifteenth transistor is coupled to the gate of the fourth transistor;

[0036] The gate of the eighteenth transistor is coupled to the second pull-down node, the first electrode of the eighteenth transistor is coupled to the pull-up node, and the second electrode of the eighteenth transistor is coupled to the first level signal input terminal;

[0037] The gate of the nineteenth transistor is coupled to the second pull-down node, the first electrode of the nineteenth transistor is coupled to the gate drive signal output terminal, and the second electrode of the nineteenth transistor is coupled to the fourth level signal input terminal;

[0038] A gate of the twentieth transistor is coupled to the second pull-down node, a first electrode of the twentieth transistor is coupled to the second output terminal, and a second electrode of the twentieth transistor is coupled to the first level signal input terminal.

[0039] Optionally, the first pull-down control subcircuit further includes a twenty-first transistor, a gate of the twenty-first transistor is coupled to the first pull-down node, a first electrode of the twenty-first transistor is coupled to the first output terminal, and a second electrode of the twenty-first transistor is coupled to the first level signal input terminal;

[0040] The second pull-down control subcircuit also includes a twenty-second transistor, a gate of the twenty-second transistor is coupled to the second pull-down node, a first electrode of the twenty-second transistor is coupled to the first output terminal, and a second electrode of the twenty-second transistor is coupled to the first level signal input terminal.

[0041] Optionally, the first output sub-circuit includes: a fourteenth transistor, a gate of the fourteenth transistor is coupled to the pull-up node, a first electrode of the fourteenth transistor is coupled to the first clock signal input terminal, and a second electrode of the fourteenth transistor is coupled to the first output terminal;

[0042] The second output sub-circuit comprises a third transistor, a gate of the third transistor is coupled to the pull-up node, a first electrode of the third transistor is coupled to the second clock signal input terminal, and a second electrode of the third transistor is coupled to the gate drive signal output terminal;

[0043] The third output sub-circuit includes a thirteenth transistor, a gate of the thirteenth transistor is coupled to the pull-up node, a first electrode of the thirteenth transistor is coupled to the second clock signal input terminal, and a second electrode of the thirteenth transistor is coupled to the second output terminal.

[0044] Based on the technical solution of the above-mentioned shift register unit, the second aspect of the present invention provides a gate drive circuit, comprising n cascaded shift register units according to any one of claims 1 to 10, n being a positive integer; further comprising a first clock signal line to an X-th clock signal line, X being a positive integer; the first clock signal rising edges of the first clock signal line to the X-th clock signal line are sequentially staggered by a unit time length H;

[0045] The effective level duration of one signal cycle of each clock signal line is a*H, and the invalid level duration is b*H, a+b=X;

[0046] The second output terminal of the i-th shift register unit is coupled to the input signal terminal of the i+a-th shift register unit; the first output terminal of the i-th shift register unit is coupled to the input signal terminal of the i+a-1-th shift register unit; i≤n;

[0047] The second output end of the i-th shift register unit is coupled to the reset control end of the ib-1-th shift register unit; the first output end of the i-th shift register unit is coupled to the reset control end of the ib-2-th shift register unit.

[0048] Optionally, the n shift register units are divided into a plurality of unit groups, each unit group includes X shift register units, and the second clock signal input terminals of the X shift register units are coupled to the first clock signal line to the Xth clock signal line in a one-to-one correspondence;

[0049] The first clock signal input terminal of the i-th shift register unit is coupled to the second clock signal input terminal of the i-1-th shift register unit; when i=1, the first clock signal input terminal of the i-th shift register unit is coupled to the second clock signal input terminal of the n-th shift register unit;

[0050] The first output terminal of the i-th shift register unit is coupled to the input signal terminal of the i+X / 2-1-th shift register unit;

[0051] The second output terminal of the i-th shift register unit is coupled to the input signal terminal of the i+X / 2-th shift register unit.

[0052] Optionally, the first output terminal of the i-th shift register unit is also coupled to the reset control terminal of the iX / 2-2-th shift register unit;

[0053] The second output terminal of the i-th shift register unit is also coupled to the reset control terminal of the iX / 2-1-th shift register unit.

[0054] Based on the technical solution of the above shift register unit, a third aspect of the present invention provides a driving method of a gate driving circuit, which is used to drive the above gate driving circuit. The driving method includes:

[0055] The first output terminal of the i-th shift register unit simultaneously outputs a first control signal to the input signal terminal of the i+a-1-th shift register unit and the reset control terminal of the ib-2-th shift register unit;

[0056] The second output end of the i-th shift register unit simultaneously outputs a second control signal to the input signal end of the i+a-th shift register unit and the reset control end of the ib-1-th shift register unit.

[0057] Based on the technical solution of the above-mentioned gate driving circuit, a fourth aspect of the present invention provides a display device, comprising two of the above-mentioned gate driving circuits, and the display device further comprises:

[0058] A display area and a peripheral area surrounding the display area, the two gate driving circuits are located in the peripheral area, and the display area is located between the two gate driving circuits;

[0059] A plurality of scan lines extend from the display area to the peripheral area and are respectively coupled to the two gate driving circuits.

[0060] When the shift register unit provided by the present invention is applied to a gate drive circuit, the first output terminal and the second output terminal of each shift register unit can respectively reset and carry different shift register units, thereby realizing control of each shift register unit to receive the reset and carry of two different shift register units. In this way, when a shift register unit used for carry and reset is abnormal, the signal output by the abnormal shift register unit can be cut off to avoid the signal output by the abnormal shift register unit affecting the reset and carry shift register unit. At the same time, since each shift register unit can receive the reset and carry of two different shift register units, after cutting off the carry and reset of an abnormal shift register unit, there is still another normal shift register unit to ensure the normal reset and carry, thereby ensuring the normal operation of the gate drive circuit.

[0061] In addition, when the shift register unit is applied to a double-sided driven display device, even if the shift register unit on one side is cut off, the shift register unit on the other side can still provide a scanning signal for the corresponding scanning line, and in the case of only single-sided driving, the voltage difference between the near end and the far end of the display device is less than two gray levels at the L127 gray level, which meets the optical evaluation. Therefore, when the shift register unit is applied to a double-sided driven display device, it is beneficial to improve the yield of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0063] Figure 1 A circuit structure diagram of a shift register unit provided in an embodiment of the present invention;

[0064] Figure 2 A schematic diagram of the cascade relationship of a gate drive circuit provided by an embodiment of the present invention;

[0065] Figure 3 A schematic diagram of a first control signal outputted by a first output terminal of an i-4th GOA to an i+6th GOA provided in an embodiment of the present invention;

[0066] Figure 4 A signal timing diagram of each port in GOA1 to GOA6 provided in an embodiment of the present invention;

[0067] Figure 5 A schematic diagram of the layout of a gate drive circuit provided by an embodiment of the present invention;

[0068] Figure 6 A basic structural diagram of a shift register unit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0069] In order to further illustrate the shift register unit, the gate driving circuit and the driving method thereof, and the display device provided in the embodiments of the present invention, a detailed description is given below in conjunction with the accompanying drawings.

[0070] See also Figure 1 , Figure 5 and Figure 6 , an embodiment of the present invention provides a shift register unit, comprising:

[0071] The first output sub-circuit (including the fourteenth transistor M14) is coupled to the pull-up node PU, the first clock signal input terminal CLK-1 and the first output terminal OUTR respectively; and is used to control whether the first clock signal input terminal CLK-1 and the first output terminal OUTR are connected under the control of the pull-up node PU;

[0072] The second output sub-circuit (including the third transistor M3) is coupled to the pull-up node PU, the second clock signal input terminal CLK and the gate drive signal output terminal GOUT respectively; and is used to control whether the second clock signal input terminal CLK and the gate drive signal output terminal GOUT are connected under the control of the pull-up node PU;

[0073] The third output sub-circuit (including the thirteenth transistor M13) is coupled to the pull-up node PU, the second clock signal input terminal CLK and the second output terminal OUTC respectively; and is used to control whether the second clock signal input terminal CLK and the second output terminal OUTC are connected under the control of the pull-up node PU.

[0074] Exemplarily, when the shift register unit is applied to a gate driving circuit included in a display device, the gate driving circuit includes a plurality of cascaded shift register units, wherein a first clock signal input terminal CLK-1 of one shift register unit is written with the same clock signal as a second clock signal input terminal CLK of an adjacent previous shift register unit.

[0075] Exemplarily, when the potential of the pull-up node PU is at a valid potential (such as a high potential): the first output sub-circuit controls the connection between the first clock signal input terminal CLK-1 and the first output terminal OUTR; the second output sub-circuit controls the connection between the second clock signal input terminal CLK and the gate drive signal output terminal GOUT; the third output sub-circuit controls the connection between the second clock signal input terminal CLK and the second output terminal OUTC.

[0076] Exemplarily, the gate drive signal output terminal GOUT is coupled to a corresponding scan line in a display device, and is used to provide a gate drive signal for the corresponding scan line. The first control signal output by the first output terminal OUTR is used to reset and carry other shift register units. The second control signal output by the second output terminal OUTC is used to reset and carry other shift register units. The first output terminal OUTR and the second output terminal OUTC control different shift register units for carry. The first output terminal OUTR and the second output terminal OUTC control different shift register units for reset.

[0077] According to the specific structure of the above-mentioned shift register unit, when the shift register unit provided by the embodiment of the present invention is applied to the gate drive circuit, the first output terminal OUTR and the second output terminal OUTC of each shift register unit can respectively reset and carry different shift register units, thereby realizing the control of each shift register unit to receive the reset and carry of two different shift register units. In this way, when a shift register unit used for carry and reset is abnormal, the signal output by the abnormal shift register unit can be cut off to avoid the signal output by the abnormal shift register unit affecting the reset and carry shift register unit. At the same time, since each shift register unit can receive the reset and carry of two different shift register units, after cutting off the carry and reset of an abnormal shift register unit, there is still another normal shift register unit to ensure the normal reset and carry, thereby ensuring the normal operation of the gate drive circuit.

[0078] In addition, when the shift register unit is applied to a double-sided driven display device, even if the shift register unit on one side is cut off, the shift register unit on the other side can still provide a scanning signal for the corresponding scanning line, and in the case of only single-sided driving, the voltage difference between the near end and the far end of the display device is less than two gray levels at the L127 gray level, which meets the optical evaluation. Therefore, when the shift register unit is applied to a double-sided driven display device, it is beneficial to improve the yield of the display device.

[0079] like Figure 1 , Figure 5 and Figure 6 As shown, in some embodiments, the shift register unit further includes:

[0080] An input sub-circuit (including a first transistor M1), coupled to the input signal terminal INPUT and the pull-up node PU, respectively, for controlling whether the input signal terminal INPUT and the pull-up node PU are connected under the control of the input signal terminal INPUT;

[0081] A first reset sub-circuit (including a second transistor M2), coupled to the pull-up node PU, the reset control terminal RST and the first level signal input terminal LVGL, respectively, for controlling whether the pull-up node PU is connected to the first level signal input terminal LVGL under the control of the reset control terminal RST;

[0082] A storage sub-circuit (including a storage capacitor C), a first end of the storage sub-circuit is coupled to the pull-up node PU, and a second end of the storage sub-circuit is coupled to the gate drive signal output terminal GOUT.

[0083] Exemplarily, the first level signal input terminal LVGL inputs a low level signal.

[0084] Exemplarily, when the input signal terminal INPUT is at a valid level, the input sub-circuit controls the input signal terminal INPUT to be connected to the pull-up node PU, transmits the input signal written into the input signal terminal INPUT to the pull-up node PU, pulls up the potential of the pull-up node PU, and the potential of the pull-up node PU is further increased under the bootstrap action of the storage sub-circuit, thereby controlling the first output sub-circuit, the second output sub-circuit and the third output sub-circuit to realize the output function.

[0085] Exemplarily, the input signal terminal INPUT can receive a first control signal and a second control signal provided by other shift register units to implement a carry function.

[0086] Exemplarily, the reset control terminal RST can receive the first control signal and the second control signal provided by other shift register units to implement the reset function. When the reset control terminal RST is at an effective level, the pull-up node PU is controlled to be connected to the first level signal input terminal LVGL.

[0087] like Figure 1 , Figure 5 and Figure 6 As shown, in some embodiments, the shift register unit further includes:

[0088] The second reset sub-circuit (including the seventh transistor M7) is coupled to the pull-up node PU, the frame start signal input terminal STV and the first level signal input terminal LVGL respectively, and is used to control whether the pull-up node PU and the first level signal input terminal LVGL are connected under the control of the frame start signal input terminal STV.

[0089] Exemplarily, at the end of each frame, the second reset subcircuit is controlled by the frame start signal input terminal STV, so that the second reset subcircuit controls the connection between the pull-up node PU and the first level signal input terminal LVGL to achieve the reset of the pull-up node PU.

[0090] The shift register unit is configured as described above and further includes a second reset subcircuit, which can reset the pull-up node PU of each shift register unit after each frame ends, thereby better improving the working stability of the shift register unit.

[0091] like Figure 1 , Figure 5 and Figure 6 As shown, in some embodiments, the shift register unit further includes:

[0092] The first pull-down control subcircuit (including a fifth transistor M5, a sixth transistor M6, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11 and a twelfth transistor M12) is respectively coupled to the first level signal input terminal LVGL, the second level signal input terminal VDD1, the fourth level signal input terminal VGL, the first pull-down node PD1, the pull-up node PU, the gate drive signal output terminal GOUT and the second output terminal OUTC; and is used to control whether the second level signal input terminal VDD1 is connected to the first pull-down node PD1 under the control of the second level signal input terminal VDD1 and the pull-up node PU; and is also used to control whether the first pull-down node PD1 is connected to the first level signal input terminal LVGL under the control of the pull-up node PU; and is also used to control whether the pull-up node PU is connected to the first level signal input terminal LVGL, whether the gate drive signal output terminal GOUT is connected to the fourth level signal input terminal VGL, and whether the second output terminal OUTC is connected to the first level signal input terminal LVGL under the control of the first pull-down node PD1.

[0093] Exemplarily, the first level signal input terminal LVGL and the fourth level signal input terminal VGL both input low level signals, and the low level signal input to the first level signal input terminal LVGL has a different potential from the low level signal input to the fourth level signal input terminal VGL.

[0094] Exemplarily, the second level signal input terminal VDD1 inputs a high level signal.

[0095] Exemplarily, the second level signal input terminal VDD1 and the pull-up node PU can jointly control whether the second level signal input terminal VDD1 is connected to the first pull-down node PD1. When the pull-up node PU and the second level signal input terminal VDD1 are both at high levels, M5 / M9 / M6 / M8 are all in the on state. Under the joint action of these four transistors, M10 / M11 / M12 are all in the off state, and the pull-up node PU, the gate drive signal output terminal GOUT and the second output terminal OUTC cannot be noise-reduced. It should be noted that at this time, the second level signal input terminal VDD1 is also connected to the first pull-down node PD1, but the voltage of the first pull-down node PD1 is low and does not meet the conditions for turning on M10 / M11 / M12.

[0096] Exemplarily, when the first pull-down node PD1 is at a high level, the pull-up node PU is controlled to be connected to the first level signal input terminal LVGL, the gate drive signal output terminal GOUT is controlled to be connected to the fourth level signal input terminal VGL, and the second output terminal OUTC is controlled to be connected to the first level signal input terminal LVGL.

[0097] The shift register unit is configured to include a first pull-down control subcircuit, so as to achieve noise reduction of the pull-up node PU, the gate drive signal output terminal GOUT and the second output terminal OUTC.

[0098] like Figure 1 , Figure 5 and Figure 6 As shown, in some embodiments, the shift register unit further includes:

[0099] The second pull-down control sub-circuit (including a fourth transistor M4, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19 and a twentieth transistor M20) is respectively coupled to the first level signal input terminal LVGL, the third level signal input terminal VDD2, the fourth level signal input terminal VGL, the second pull-down node PD2, the pull-up node PU, the gate drive signal output terminal GOUT and the second output terminal OUTC; and is used for controlling the gate drive signal output terminal GOUT under the control of the third level signal input terminal VDD2 and the pull-up node PU. Whether the three-level signal input terminal VDD2 is connected to the second pull-down node PD2; it is also used to control whether the second pull-down node PD2 is connected to the first level signal input terminal LVGL under the control of the pull-up node PU; it is also used to control whether the pull-up node PU is connected to the first level signal input terminal LVGL, control whether the gate drive signal output terminal GOUT is connected to the fourth level signal input terminal VGL, and control whether the second output terminal OUTC is connected to the first level signal input terminal LVGL under the control of the second pull-down node PD2.

[0100] Exemplarily, the third level signal input terminal VDD2 inputs a high level signal.

[0101] Exemplarily, the third level signal input terminal VDD2 and the pull-up node PU can jointly control whether the third level signal input terminal VDD2 is connected to the second pull-down node PD2. When the pull-up node PU and the third level signal input terminal VDD2 are both at high levels, M4 / M15 / M16 / M17 are all in the on state. Under the joint action of these four transistors, M18 / M19 / M20 are all in the off state, and the pull-up node PU, the gate drive signal output terminal GOUT and the second output terminal OUTC cannot be noise-reduced. It should be noted that at this time, the third level signal input terminal VDD2 is also connected to the second pull-down node PD2, but the voltage of the second pull-down node PD2 is low, which does not meet the conditions for turning on M18 / M19 / M20 and the like.

[0102] Exemplarily, when the second pull-down node PD2 is at a high level, the pull-up node PU is controlled to be connected to the first level signal input terminal LVGL, the gate drive signal output terminal GOUT is controlled to be connected to the fourth level signal input terminal VGL, and the second output terminal OUTC is controlled to be connected to the first level signal input terminal LVGL.

[0103] The shift register unit is configured to include a second pull-down control subcircuit, so as to achieve noise reduction of the pull-up node PU, the gate drive signal output terminal GOUT and the second output terminal OUTC.

[0104] The shift register unit is configured to include both the first pull-down control subcircuit and the second pull-down control subcircuit, so that the first pull-down control subcircuit and the second pull-down control subcircuit can be controlled to work alternately, which is beneficial to improving the working life of the first pull-down control subcircuit and the second pull-down control subcircuit, and can also reduce the threshold voltage drift of the transistors in the first pull-down control subcircuit and the second pull-down control subcircuit.

[0105] like Figure 1 , Figure 5 and Figure 6 As shown, in some embodiments, the input sub-circuit includes a first transistor M1, a gate and a first electrode of the first transistor M1 are coupled to the input signal terminal INPUT, and a second electrode of the first transistor M1 is coupled to the pull-up node PU;

[0106] The first reset sub-circuit includes a second transistor M2, a gate of the second transistor M2 is coupled to the reset control terminal RST, a first electrode of the second transistor M2 is coupled to the first level signal input terminal LVGL, and a second electrode of the first transistor M1 is coupled to the pull-up node PU;

[0107] The storage sub-circuit includes a storage capacitor, a first end of the storage capacitor is coupled to the pull-up node PU, and a second end of the storage capacitor is coupled to the gate drive signal output terminal GOUT.

[0108] Exemplarily, when the input signal terminal INPUT is at a valid level, the first transistor M1 is turned on, controlling the input signal terminal INPUT to be connected to the pull-up node PU, transmitting the input signal written into the input signal terminal INPUT to the pull-up node PU, raising the potential of the pull-up node PU, and further increasing the potential of the pull-up node PU under the bootstrap effect of the storage capacitor, thereby controlling the first output sub-circuit, the second output sub-circuit and the third output sub-circuit to realize the output function.

[0109] Exemplarily, the input signal terminal INPUT can receive a first control signal and a second control signal provided by other shift register units to implement a carry function.

[0110] Exemplarily, the reset control terminal RST can receive the first control signal and the second control signal provided by other shift register units to realize the reset function. When the reset control terminal RST is at an effective level, the second transistor M2 is turned on to control the connection between the pull-up node PU and the first level signal input terminal LVGL.

[0111] like Figure 1 As shown, in some embodiments, the second reset sub-circuit includes a seventh transistor M7, a gate of the seventh transistor M7 is coupled to the frame start signal input terminal STV, a first electrode of the seventh transistor M7 is coupled to the pull-up node PU, and a second electrode of the seventh transistor M7 is coupled to the first level signal input terminal LVGL.

[0112] Exemplarily, at the end of each frame, the seventh transistor M7 is controlled to be turned on through the frame start signal input terminal STV, so that the seventh transistor M7 controls the connection between the pull-up node PU and the first level signal input terminal LVGL to achieve resetting of the pull-up node PU.

[0113] Need to explain, Figure 2 The second frame start line STV2 in is coupled to the frame start signal input terminal STV.

[0114] like Figure 1 , Figure 5 and Figure 6 As shown, in some embodiments, the first pull-down control subcircuit includes a fifth transistor M5, a sixth transistor M6, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11 and a twelfth transistor M12;

[0115] A first electrode of the fifth transistor M5 is coupled to the second level signal input terminal VDD1, and a second electrode of the fifth transistor M5 is coupled to the first pull-down node PD1;

[0116] The gate of the sixth transistor M6 is coupled to the pull-up node PU, the first electrode of the sixth transistor M6 is coupled to the first pull-down node PD1, and the second electrode of the sixth transistor M6 is coupled to the first level signal input terminal LVGL;

[0117] The gate of the eighth transistor M8 is coupled to the pull-up node PU, the first electrode of the eighth transistor M8 is coupled to the gate of the fifth transistor M5, and the second electrode of the eighth transistor M8 is coupled to the first level signal input terminal LVGL;

[0118] The gate and the first electrode of the ninth transistor M9 are coupled to the second level signal input terminal VDD1, and the second electrode of the ninth transistor M9 is coupled to the gate of the fifth transistor M5;

[0119] The gate of the tenth transistor M10 is coupled to the first pull-down node PD1, the first electrode of the tenth transistor M10 is coupled to the pull-up node PU, and the second electrode of the tenth transistor M10 is coupled to the first level signal input terminal LVGL;

[0120] The gate of the eleventh transistor M11 is coupled to the first pull-down node PD1, the first electrode of the eleventh transistor M11 is coupled to the gate drive signal output terminal GOUT, and the second electrode of the eleventh transistor M11 is coupled to the fourth level signal input terminal VGL;

[0121] A gate of the twelfth transistor M12 is coupled to the first pull-down node PD1 , a first electrode of the twelfth transistor M12 is coupled to the second output terminal OUTC, and a second electrode of the twelfth transistor M12 is coupled to the first level signal input terminal LVGL.

[0122] Exemplarily, the second level signal input terminal VDD1 controls whether the ninth transistor M9 is turned on. When the ninth transistor M9 is turned on, the second level signal input from the second level signal input terminal VDD1 is transmitted to the gate of the fifth transistor M5.

[0123] When the pull-up node PU and the second level signal input terminal VDD1 are both at a high level, M9 / M5 / M6 / M8 are all in the on state, but M8 turning on will pull down the gate potential of M5, and M6 turning on will pull down the first pull-down node PD1, but M5 is still turned on. The combined action of these four transistors makes the first pull-down node PD1 a low potential.

[0124] When the first pull-down node PD1 is at a high potential, the tenth transistor M10, the eleventh transistor M11 and the twelfth transistor M12 can be controlled to be turned on, thereby resetting the pull-up node PU, reducing the noise of the gate drive signal output terminal GOUT, and reducing the noise of the second output terminal OUTC.

[0125] like Figure 1 , Figure 5 and Figure 6 As shown, in some embodiments, the second pull-down control subcircuit includes a fourth transistor M4, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19 and a twentieth transistor M20;

[0126] A first electrode of the fourth transistor M4 is coupled to the third level signal input terminal VDD2, and a second electrode of the fourth transistor M4 is coupled to the second pull-down node PD2;

[0127] The gate of the sixteenth transistor M16 is coupled to the pull-up node PU, the first electrode of the sixteenth transistor M16 is coupled to the second pull-down node PD2, and the second electrode of the sixteenth transistor M16 is coupled to the first level signal input terminal LVGL;

[0128] A gate of the seventeenth transistor M17 is coupled to the pull-up node PU, a first electrode of the seventeenth transistor M17 is coupled to the gate of the fourth transistor M4, and a second electrode of the seventeenth transistor M17 is coupled to the first level signal input terminal LVGL;

[0129] The gate and the first electrode of the fifteenth transistor M15 are coupled to the third level signal input terminal VDD2, and the second electrode of the fifteenth transistor M15 is coupled to the gate of the fourth transistor M4;

[0130] The gate of the eighteenth transistor M18 is coupled to the second pull-down node PD2, the first electrode of the eighteenth transistor M18 is coupled to the pull-up node PU, and the second electrode of the eighteenth transistor M18 is coupled to the first level signal input terminal LVGL;

[0131] The gate of the nineteenth transistor M19 is coupled to the second pull-down node PD2, the first electrode of the nineteenth transistor M19 is coupled to the gate drive signal output terminal GOUT, and the second electrode of the nineteenth transistor M19 is coupled to the fourth level signal input terminal VGL;

[0132] A gate of the twentieth transistor M20 is coupled to the second pull-down node PD2 , a first electrode of the twentieth transistor M20 is coupled to the second output terminal OUTC, and a second electrode of the twentieth transistor M20 is coupled to the first level signal input terminal LVGL.

[0133] Exemplarily, the third level signal input terminal VDD2 controls whether the fifteenth transistor M15 is turned on. When the fifteenth transistor M15 is turned on, the third level signal input from the third level signal input terminal VDD2 is transmitted to the gate of the fourth transistor M4.

[0134] When the pull-up node PU and the third level signal input terminal VDD2 are both at a high level, M4 / M15 / M16 / M17 are all in the on state, but M17 turning on will pull down the gate potential of M4, and M16 turning on will pull down the second pull-down node PD2, but M4 is still turned on. The combined action of these four transistors makes the second pull-down node PD2 at a low potential.

[0135] When the second pull-down node PD2 is at a high potential, the eighteenth transistor M18, the nineteenth transistor M19 and the twentieth transistor M20 can be controlled to be turned on, thereby resetting the pull-up node PU, reducing the noise of the gate drive signal output terminal GOUT, and reducing the noise of the second output terminal OUTC.

[0136] like Figure 1 As shown, in some embodiments, the first pull-down control sub-circuit further includes a twenty-first transistor M21, a gate of the twenty-first transistor M21 is coupled to the first pull-down node PD1, a first electrode of the twenty-first transistor M21 is coupled to the first output terminal OUTR, and a second electrode of the twenty-first transistor M21 is coupled to the first level signal input terminal LVGL;

[0137] The second pull-down control subcircuit also includes a twenty-second transistor M22, a gate of the twenty-second transistor M22 is coupled to the second pull-down node PD2, a first electrode of the twenty-second transistor M22 is coupled to the first output terminal OUTR, and a second electrode of the twenty-second transistor M22 is coupled to the first level signal input terminal LVGL.

[0138] Exemplarily, when the first pull-down node PD1 is at a high potential, the 21st transistor M21 is controlled to be turned on to reduce noise at the first output terminal OUTR. When the second pull-down node PD2 is at a high potential, the 22nd transistor M22 is controlled to be turned on to reduce noise at the first output terminal OUTR.

[0139] The above-mentioned setting of the first pull-down control subcircuit including the twenty-first transistor M21 and the setting of the second pull-down control subcircuit including the twenty-second transistor M22 can achieve noise reduction for the first output terminal OUTR and well ensure the working stability of the shift register unit.

[0140] like Figure 1 and Figure 5 As shown, in some embodiments, the first output sub-circuit includes: a fourteenth transistor M14, a gate of the fourteenth transistor M14 is coupled to the pull-up node PU, a first electrode of the fourteenth transistor M14 is coupled to the first clock signal input terminal CLK-1, and a second electrode of the fourteenth transistor M14 is coupled to the first output terminal OUTR;

[0141] The second output sub-circuit comprises a third transistor M3, a gate of the third transistor M3 is coupled to the pull-up node PU, a first electrode of the third transistor M3 is coupled to the second clock signal input terminal CLK, and a second electrode of the third transistor M3 is coupled to the gate drive signal output terminal GOUT;

[0142] The third output sub-circuit includes a thirteenth transistor M13, a gate of the thirteenth transistor M13 is coupled to the pull-up node PU, a first electrode of the thirteenth transistor M13 is coupled to the second clock signal input terminal CLK, and a second electrode of the thirteenth transistor M13 is coupled to the second output terminal OUTC.

[0143] Exemplarily, when the pull-up node PU is at a high level, the fourteenth transistor M14 is controlled, and the third transistor M3 and the thirteenth transistor M13 are both turned on, thereby controlling the first output terminal OUTR, the gate drive signal output terminal OUTR and the second output terminal OUTC to output corresponding signals. When the pull-up node PU is at a low level, the fourteenth transistor M14 is controlled, and the third transistor M3 and the thirteenth transistor M13 are both turned off, thereby controlling the first output terminal OUTR, and the drive signal output terminal and the second output terminal OUTC stop outputting.

[0144] Since the clock signal is a continuous pulse signal, the voltage at the drain and source of the third transistor M3 always switches between the high level and the low level of the clock signal, and it is very easy to generate spike pulses, that is, noise, through coupling. This noise may cause abnormal opening of the scan line. Similarly, the voltage of the pull-up node PU is mainly pulled up due to the capacitive coupling effect, so it is also very easy to generate noise at the pull-up node PU. When the noise is serious, it can even cause the third transistor M3 to be abnormally turned on, resulting in an abnormal output signal. In the shift register unit provided in the above embodiment, by setting the first pull-down control subcircuit and the second pull-down control subcircuit, before and after each shift register unit works, the pull-up node PU, the first output terminal OUTR and the second output terminal OUTC are discharged to weaken the noise pulse signal in the output signal.

[0145] Need to explain, Figure 5 The 23rd transistor M23 and the 24th transistor M24 are also illustrated, the gate of the 23rd transistor M23 is coupled to the input signal terminal INPUT, the first electrode of the 23rd transistor M23 is coupled to the first pull-down node PD1, and the second electrode of the 23rd transistor M23 is coupled to the first level signal input terminal LVGL. The gate of the 24th transistor M24 is coupled to the input signal terminal INPUT, the first electrode of the 24th transistor M24 is coupled to the second pull-down node PD2, and the second electrode of the 24th transistor M24 is coupled to the first level signal input terminal LVGL. The pull-down speed of the first pull-down stage PD1 and the second pull-down node PD2 is optimized.

[0146] The embodiment of the present invention further provides a gate driving circuit, comprising n cascaded shift register units provided in the above embodiment, where n is a positive integer; and further comprising a first clock signal line to an X-th clock signal line; the first clock signal rising edges of the first clock signal line to the X-th clock signal line are sequentially staggered by a unit time length H;

[0147] The effective level duration of one signal cycle of each clock signal line is a*H, and the invalid level duration is b*H, a+b=X;

[0148] The second output terminal OUTC of the i-th shift register unit is coupled to the input signal terminal INPUT of the i+a-th shift register unit; the first output terminal OUTR of the i-th shift register unit is coupled to the input signal terminal INPUT of the i+a-1-th shift register unit; i≤n;

[0149] The second output terminal OUTC of the i-th shift register unit is coupled to the reset control terminal RST of the ib-1-th shift register unit; the first output terminal OUTR of the i-th shift register unit is coupled to the reset control terminal RST of the ib-2-th shift register unit.

[0150] Exemplarily, the unit time length H is the charging time of a row of sub-pixels.

[0151] In some embodiments, the n shift register units are divided into a plurality of unit groups, each unit group includes X shift register units, and the second clock signal input terminals CLK in the X shift register units are coupled to the first clock signal line to the Xth clock signal line in a one-to-one correspondence;

[0152] The first clock signal input terminal CLK-1 of the i-th shift register unit is coupled to the second clock signal input terminal CLK of the i-1-th shift register unit; i≤n; when i=1, the first clock signal input terminal CLK-1 of the i-th shift register unit is coupled to the second clock signal input terminal CLK of the n-th shift register unit;

[0153] The first output terminal OUTR of the i-th shift register unit is coupled to the input signal terminal INPUT of the i+X / 2-1-th shift register unit;

[0154] The second output terminal OUTC of the i-th shift register unit is coupled to the input signal terminal INPUT of the i+X / 2-th shift register unit.

[0155] In some embodiments, the first output terminal OUTR of the i-th shift register unit is also coupled to the reset control terminal RST of the iX / 2-2-th shift register unit;

[0156] The second output terminal OUTC of the i-th shift register unit is also coupled to the reset control terminal RST of the iX / 2-1-th shift register unit.

[0157] In more detail, taking the gate driving circuit including 6 clock signal lines, a=3, b=3 as an example, the shift register unit is defined as a GOA unit.

[0158] In the case where the GOA unit is set up without including the first output sub-circuit:

[0159] When the i-th GOA unit has an abnormality and has no output, the i-th GOA unit cannot carry the i+3-th GOA unit normally, resulting in the i+3-th GOA unit being unable to reset the i-1-th GOA unit; and the i+3-th GOA unit has an abnormal output and cannot carry the i+6-th GOA unit, resulting in the i+6-th GOA unit being unable to reset the i+2-th GOA unit; the i+6-th GOA unit has an abnormal output and cannot carry the i+9-th GOA unit, resulting in the i+9-th GOA unit being unable to reset the i+5-th GOA unit, and so on, thereby causing the display device to display abnormally.

[0160] In the case where the GOA unit is configured to include a first output subcircuit:

[0161] The first output subcircuit includes a fourteenth transistor M14, whose gate is coupled to the pull-up node PU, whose drain is coupled to the second clock signal input terminal CLK of the adjacent previous GOA unit, and whose source is coupled to the first output terminal OUTR, and can replace the reset function of the adjacent previous GOA unit.

[0162] The i-th GOA unit resets the i-4th GOA unit and carries the i+3th GOA unit; it also resets the i-5th GOA unit and carries the i+2th GOA unit. In this way, each GOA unit is carried and reset by two GOA units. When one of the GOA units is abnormal and causes no output or continuous output, the signal of the GOA unit can be cut off, which will not affect the carry and reset of other GOA units. Figure 3 As shown, it is ensured that each row of sub-pixels can be displayed normally.

[0163] like Figure 2 As shown, OUTC of GOA1 gives a carry to GOA4, OUTC of GOA5 and OUTR of GOA6 reset GOA1; OUTC of GOA2 gives a carry to GOA5, and OUTR gives a carry to GOA4; OUTC of GOA6 and OUTR of GOA7 reset GOA2, so that each GOA unit has two GOA units for its carry and reset, which greatly improves the fault tolerance of the GOA layout area and can effectively improve the product yield.

[0164] like Figure 2As shown, in the case where the display device adopts bilateral drive, when the i-th GOA unit on one side has no output abnormally, the i-th scan line driven by the i-th GOA unit can be provided with a driving signal by the normal i-th GOA unit on the other side to ensure that the i-th row of sub-pixels corresponding to the i-th scan line can be displayed normally. Since the i-th GOA unit has no output, the i-4th GOA unit cannot be reset, but the OUTR of the i+1th GOA unit can still reset the i-4th GOA unit, so that it can still display normally. Moreover, through simulation, when the driving mode of the i-th row of sub-pixels changes from bilateral drive to unilateral drive, the grayscale difference between the near end and the far end of the display device under the L127 grayscale does not exceed two grayscales, which meets the optical evaluation. It should be noted that GOA is distributed on the left and right sides of the screen. When the GOAs on both sides are normally bilaterally driven, the scan lines are charged from the left and right sides to the middle at the same time. In this case, the middle position of the scan line is the far end, and the left and right ends of the scan line are both near ends. When there is a line scanning with abnormal GOA on the right side, the scanning line is charged from the left to the right, then the far right is the far end and the left is the near end. When there is a line scanning with abnormal GOA on the left side, the scanning line is charged from the right to the left, then the far left is the far end and the right is the near end.

[0165] Need to explain, Figure 2 Schematic diagram of the first scanning line Gate1 to the sixth scanning line Gate6.

[0166] like Figure 2 As shown, the first three GOA units have no carry from the upper cascade GOA unit, and the start signal is uniformly input from the first frame start line STV1. Figure 2 , CLK1 to CLK6 represent the first clock signal line to the sixth clock signal line. GOA1 to GOA6 represent the first shift register unit to the sixth shift register unit. The second clock signal input terminals CLK in GOA1 to GOA6 are connected to CLK1 to CLK6 in a one-to-one correspondence. The first clock signal input terminal CLK-1 in GOA1 is connected to CLK6, and the first clock signal input terminals CLK-1 of GOA2-GOA6 are connected to CLK1 to CLK5 in a one-to-one correspondence.

[0167] like Figure 4 As shown, taking GOA1 as an example, at the 1H moment, STV1 is at a low level, INPUT1 has no input, M1 is closed and has no output, M3 is closed, C is not charged, PU is at a low level, and GOUT1 has no output.

[0168] At the 2H moment, STV is high level, and starts to input signal to INPUT1 of GOA1, M1 is turned on and outputs, PU is high level, M3, M13 and M14 are turned on, C is charged, and at this time CLK1 and CLK6 are both low level, GOUT1, OUTC1, OUTR1 have no output.

[0169] Until the 4th hour, due to the high level of CLK6 signal, M14 is turned on. Due to the coupling effect of the capacitor, the PU point is slightly pulled up, and the OUTR output signal is carried to the GOA3 unit. It should be noted that the first GOA unit, although there is no upper cascade, can still give M14 a signal with the same timing of CLK6, which is 1H higher than CLK1.

[0170] At the 5H moment, the CLK1 signal is high, M13 is turned on, the voltage at the PU point is pulled high, GOUT and OUTC are output at the same time, GOUT is used to turn on the corresponding scan line, and OUTC is used to carry GOA4.

[0171] In the 5H~8H period, because RST is always at a low level, M2 is closed, PU voltage is high, and GOUT is output.

[0172] At the 7th hour, the INPUT1 input ends and M1 is closed. At the 8th hour, after the CLK1 signal is input, it changes from a high level to a low level. Due to the capacitive coupling, the PU point voltage is slightly lowered.

[0173] At the 9th hour, RST1-5 and RST1-6 signals begin to be input (simultaneously input by OUTC5 of GOA5 and OUTR6 of GOA6), and the signal is in a high level state. At this time, M2 is turned on and resets the PU point, the capacitor is discharged, the PU point drops to a low level, M3, M13 and M14 are turned off, and the output of the GOA1 unit ends.

[0174] like Figure 4 As shown, taking GOA4 as an example, in the 1H~4H time period, INPUT4-1 and INPUT4-2 have no input, and RST4-8 and RST4-9 also have no input. At this time, M1, M2, M3, M13, and M14 are all closed; at the 5H moment, INPUT4-1 and INPUT4-2 start input (by the OUTC input signal of GOA1 and the OUTR input signal of GOA2), M1 is turned on, the PU point voltage is high, M3, M13, and M14 are all turned on, but OUTR4, OUTC4, and GOUT4 have no output.

[0175] At the 7H moment, CLK3 inputs a high level, M14 is turned on, and OUTR4 outputs a signal as INPUT6-4 of GOA6.

[0176] At the 8H moment, CLK4 inputs a high level, M13 is turned on, GOUT4, GOUT4 and OUTC4 output signals, and OUTC4 gives a carry to GOA7;

[0177] At the 12th hour, RST4-8 and RST4-9 input high voltage (input by OUTR of GOA8 and OUTC of GOA9), M2 is turned on and resets the PU point.

[0178] It can be seen from the above two examples that each GOA unit has two GOA units in the upper cascade carried and two GOA units in the lower cascade reset.

[0179] Exemplarily, it is taken that the gate driving circuit includes 8 clock signal lines, a=4, b=4 as an example.

[0180] The second output terminal OUTC of the i-th shift register unit is coupled to the input signal terminal INPUT of the i+4-th shift register unit; the first output terminal OUTR of the i-th shift register unit is coupled to the input signal terminal INPUT of the i+3-th shift register unit. The second output terminal OUTC of the i-th shift register unit is coupled to the reset control terminal RST of the i-5-th shift register unit; the first output terminal OUTR of the i-th shift register unit is coupled to the reset control terminal RST of the i-6-th shift register unit.

[0181] The i-th shift register unit carries the i+4-th shift register unit; the i-th shift register unit carries the i+3-th shift register unit. The i-th shift register unit resets the i-5-th shift register unit; the i-th shift register unit resets the i-6-th shift register unit.

[0182] Exemplarily, it is taken that the gate driving circuit includes 12 clock signal lines, a=6, b=6.

[0183] The second output terminal OUTC of the i-th shift register unit is coupled to the input signal terminal INPUT of the i+6-th shift register unit; the first output terminal OUTR of the i-th shift register unit is coupled to the input signal terminal INPUT of the i+5-th shift register unit. The second output terminal OUTC of the i-th shift register unit is coupled to the reset control terminal RST of the i-7-th shift register unit; the first output terminal OUTR of the i-th shift register unit is coupled to the reset control terminal RST of the i-8-th shift register unit.

[0184] The i-th shift register unit carries the i+6-th shift register unit; the i-th shift register unit carries the i+5-th shift register unit. The i-th shift register unit resets the i-7-th shift register unit; the i-th shift register unit resets the i-8-th shift register unit.

[0185] An embodiment of the present invention further provides a driving method of a gate driving circuit, which is used to drive the gate driving circuit provided by the above embodiment, and the driving method includes:

[0186] The first output terminal OUTR of the i-th stage shift register unit simultaneously outputs a first control signal to the input signal terminal INPUT of the i+a-1-th stage shift register unit and the reset control terminal RST of the ib-2-th stage shift register unit;

[0187] The second output terminal OUTC of the i-th stage shift register unit simultaneously outputs a second control signal to the input signal terminal INPUT of the i+a-th stage shift register unit and the reset control terminal RST of the ib-1-th stage shift register unit.

[0188] When the driving method provided in the embodiment of the present invention is used to drive the gate driving circuit provided in the above embodiment, the problem of abnormal output of the display device caused by abnormality of some shift register units in the gate driving circuit is solved.

[0189] An embodiment of the present invention further provides a display device, comprising the gate driving circuit provided by the above embodiment, and the display device further comprises:

[0190] A display area and a peripheral area surrounding the display area, the two gate driving circuits are located in the peripheral area, and the display area is located between the two gate driving circuits;

[0191] A plurality of scan lines extend from the display area to the peripheral area and are respectively coupled to the two gate driving circuits.

[0192] Exemplarily, the first gate driving circuit of the two gate driving circuits is located on the left side of the display area, that is, the left border area of ​​the display device, and the second gate driving circuit of the two gate driving circuits is located on the right side of the display area, that is, the right border area of ​​the display device.

[0193] Exemplarily, the first gate driving circuit is coupled to the first ends of the plurality of scan lines, and a gate driving signal is input from the first ends of the plurality of scan lines. The second gate driving circuit is coupled to the second ends of the plurality of scan lines, and a gate driving signal is input from the second ends of the plurality of scan lines. Each scan line can receive the same gate driving signal from the first end and the second end, respectively, to achieve bilateral driving.

[0194] When an abnormality occurs in a shift register unit in the first gate drive circuit, the output signal of the abnormal shift register unit can be cut off by laser, that is, the abnormal shift register unit is controlled not to provide a signal to the scan line, nor to reset and carry other shift register units.

[0195] In the display device provided by the embodiment of the present invention, when the gate driving circuit provided by the above embodiment is included, the first output terminal OUTR and the second output terminal OUTC of each shift register unit in the gate driving circuit can respectively reset and carry different shift register units, thereby realizing the control of each shift register unit to receive the reset and carry of two different shift register units. In this way, when a shift register unit used for carry and reset is abnormal, the signal output by the abnormal shift register unit can be cut off to avoid the signal output by the abnormal shift register unit affecting the reset and carry shift register unit. At the same time, since each shift register unit can receive the reset and carry of two different shift register units, after cutting off the carry and reset of an abnormal shift register unit, there is still another normal shift register unit to ensure the normal reset and carry. Therefore, the display device provided by the embodiment of the present invention solves the problem of abnormal output of the display device caused by the abnormality of some shift register units in the gate driving circuit.

[0196] In addition, the display device provided in the embodiment of the present invention is bilaterally driven. Even if the shift register unit on one side is cut off, the shift register unit on the other side can still provide a scanning signal for the corresponding scanning line. Moreover, in the case of only single-sided driving, the voltage difference between the near end and the far end of the display device is less than two gray levels under the L127 gray scale, which meets the optical evaluation.

[0197] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane, etc.

[0198] In some embodiments, the gate driving circuit includes an abnormal shift register unit, and the abnormal shift register unit is independent of the scan line and other shift register units.

[0199] When an abnormal shift register unit appears in the gate drive circuit, the output signal of the abnormal shift register unit can be cut off by laser to avoid affecting other shift register units and ensure the normal operation of other shift register units.

[0200] It should be noted that the "same layer" in the embodiment of the present invention may refer to a film layer on the same structural layer. Or, for example, a film layer on the same layer may be a film layer for forming a specific pattern formed by the same film forming process, and then the film layer is patterned by the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0201] In the various method embodiments of the present invention, the serial numbers of the steps cannot be used to limit the sequence of the steps. For ordinary technicians in this field, without paying creative work, changes to the sequence of the steps are also within the protection scope of the present invention.

[0202] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the product embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the product embodiment.

[0203] Unless otherwise defined, the technical terms or scientific terms used in this disclosure should be understood by people with ordinary skills in the field to which the present invention belongs. "First", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect", "couple" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0204] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0205] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0206] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A shift register unit, characterized in that: include: A first output subcircuit is coupled to the pull-up node, the first clock signal input terminal and the first output terminal respectively; Used to control whether the first clock signal input terminal and the first output terminal are connected under the control of the pull-up node; A second output subcircuit is coupled to the pull-up node, the second clock signal input terminal and the gate drive signal output terminal respectively; and is used to control whether the second clock signal input terminal and the gate drive signal output terminal are connected under the control of the pull-up node; A third output subcircuit is coupled to the pull-up node, the second clock signal input terminal and the second output terminal respectively; and is used to control whether the second clock signal input terminal and the second output terminal are connected under the control of the pull-up node; The gate drive signal output terminal is coupled to the corresponding scan line in the display device, and is used to provide a gate drive signal for the corresponding scan line; the first control signal output by the first output terminal is used to reset and carry other shift register units; the second control signal output by the second output terminal is used to reset and carry other shift register units; the first output terminal and the second output terminal control the carry of different shift register units; the first output terminal and the second output terminal control the reset of different shift register units.

2. The shift register unit according to claim 1, characterized in that: The shift register unit also includes: An input subcircuit, coupled to the input signal terminal and the pull-up node respectively, for controlling whether the input signal terminal and the pull-up node are connected under the control of the input signal terminal; A first reset subcircuit is coupled to the pull-up node, the reset control terminal and the first level signal input terminal respectively, and is used to control whether the pull-up node is connected to the first level signal input terminal under the control of the reset control terminal; A storage sub-circuit, wherein a first terminal of the storage sub-circuit is coupled to the pull-up node, and a second terminal of the storage sub-circuit is coupled to the gate drive signal output terminal.

3. The shift register unit according to claim 2, characterized in that: The shift register unit also includes: The second reset subcircuit is coupled to the pull-up node, the frame start signal input terminal and the first level signal input terminal respectively, and is used to control whether the pull-up node and the first level signal input terminal are connected under the control of the frame start signal input terminal.

4. The shift register unit according to claim 1, characterized in that: The shift register unit also includes: The first pull-down control subcircuit is coupled to the first level signal input terminal, the second level signal input terminal, the fourth level signal input terminal, the first pull-down node, the pull-up node, the gate drive signal output terminal and the second output terminal respectively; and is used to control whether the second level signal input terminal is connected to the first pull-down node under the control of the second level signal input terminal and the pull-up node; and is also used to control whether the first pull-down node is connected to the first level signal input terminal under the control of the pull-up node; and is also used to control whether the pull-up node is connected to the first level signal input terminal, whether the gate drive signal output terminal is connected to the fourth level signal input terminal, and whether the second output terminal is connected to the first level signal input terminal under the control of the first pull-down node.

5. The shift register unit according to claim 4, characterized in that: The shift register unit also includes: The second pull-down control subcircuit is coupled to the first level signal input terminal, the third level signal input terminal, the fourth level signal input terminal, the second pull-down node, the pull-up node, the gate drive signal output terminal and the second output terminal respectively; and is used to control whether the third level signal input terminal is connected to the second pull-down node under the control of the third level signal input terminal and the pull-up node; and is also used to control whether the second pull-down node is connected to the first level signal input terminal under the control of the pull-up node; and is also used to control whether the pull-up node is connected to the first level signal input terminal, whether the gate drive signal output terminal is connected to the fourth level signal input terminal, and whether the second output terminal is connected to the first level signal input terminal under the control of the second pull-down node.

6. The shift register unit according to claim 3, characterized in that: The input subcircuit comprises a first transistor, a gate and a first electrode of the first transistor are coupled to the input signal terminal, and a second electrode of the first transistor is coupled to the pull-up node; The first reset sub-circuit comprises a second transistor, a gate of the second transistor is coupled to the reset control terminal, a first electrode of the second transistor is coupled to the first level signal input terminal, and a second electrode of the first transistor is coupled to the pull-up node; The storage subcircuit comprises a storage capacitor, a first end of the storage capacitor is coupled to the pull-up node, and a second end of the storage capacitor is coupled to the gate drive signal output terminal; The second reset subcircuit includes a seventh transistor, a gate of the seventh transistor is coupled to the frame start signal input terminal, a first electrode of the seventh transistor is coupled to the pull-up node, and a second electrode of the seventh transistor is coupled to the first level signal input terminal.

7. The shift register unit according to claim 4, characterized in that: The first pull-down control subcircuit includes a fifth transistor, a sixth transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor; A first electrode of the fifth transistor is coupled to the second level signal input terminal, and a second electrode of the fifth transistor is coupled to the first pull-down node; The gate of the sixth transistor is coupled to the pull-up node, the first electrode of the sixth transistor is coupled to the first pull-down node, and the second electrode of the sixth transistor is coupled to the first level signal input terminal; The gate of the eighth transistor is coupled to the pull-up node, the first electrode of the eighth transistor is coupled to the gate of the fifth transistor, and the second electrode of the eighth transistor is coupled to the first level signal input terminal; The gate and the first electrode of the ninth transistor are coupled to the second level signal input terminal, and the second electrode of the ninth transistor is coupled to the gate of the fifth transistor; The gate of the tenth transistor is coupled to the first pull-down node, the first electrode of the tenth transistor is coupled to the pull-up node, and the second electrode of the tenth transistor is coupled to the first level signal input terminal; The gate of the eleventh transistor is coupled to the first pull-down node, the first electrode of the eleventh transistor is coupled to the gate drive signal output terminal, and the second electrode of the eleventh transistor is coupled to the fourth level signal input terminal; A gate of the twelfth transistor is coupled to the first pull-down node, a first electrode of the twelfth transistor is coupled to the second output terminal, and a second electrode of the twelfth transistor is coupled to the first level signal input terminal.

8. The shift register unit according to claim 5, characterized in that: The second pull-down control subcircuit includes a fourth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, and a twentieth transistor; A first electrode of the fourth transistor is coupled to the third level signal input terminal, and a second electrode of the fourth transistor is coupled to the second pull-down node; The gate of the sixteenth transistor is coupled to the pull-up node, the first electrode of the sixteenth transistor is coupled to the second pull-down node, and the second electrode of the sixteenth transistor is coupled to the first level signal input terminal; The gate of the seventeenth transistor is coupled to the pull-up node, the first electrode of the seventeenth transistor is coupled to the gate of the fourth transistor, and the second electrode of the seventeenth transistor is coupled to the first level signal input terminal; The gate and the first electrode of the fifteenth transistor are coupled to the third level signal input terminal, and the second electrode of the fifteenth transistor is coupled to the gate of the fourth transistor; The gate of the eighteenth transistor is coupled to the second pull-down node, the first electrode of the eighteenth transistor is coupled to the pull-up node, and the second electrode of the eighteenth transistor is coupled to the first level signal input terminal; The gate of the nineteenth transistor is coupled to the second pull-down node, the first electrode of the nineteenth transistor is coupled to the gate drive signal output terminal, and the second electrode of the nineteenth transistor is coupled to the fourth level signal input terminal; A gate of the twentieth transistor is coupled to the second pull-down node, a first electrode of the twentieth transistor is coupled to the second output terminal, and a second electrode of the twentieth transistor is coupled to the first level signal input terminal.

9. The shift register unit according to claim 5, characterized in that: The first pull-down control subcircuit further includes a twenty-first transistor, a gate of the twenty-first transistor is coupled to the first pull-down node, a first electrode of the twenty-first transistor is coupled to the first output terminal, and a second electrode of the twenty-first transistor is coupled to the first level signal input terminal; The second pull-down control subcircuit also includes a twenty-second transistor, a gate of the twenty-second transistor is coupled to the second pull-down node, a first electrode of the twenty-second transistor is coupled to the first output terminal, and a second electrode of the twenty-second transistor is coupled to the first level signal input terminal.

10. The shift register unit according to claim 1, characterized in that: The first output sub-circuit comprises: a fourteenth transistor, a gate of the fourteenth transistor is coupled to the pull-up node, a first electrode of the fourteenth transistor is coupled to the first clock signal input terminal, and a second electrode of the fourteenth transistor is coupled to the first output terminal; The second output sub-circuit comprises a third transistor, a gate of the third transistor is coupled to the pull-up node, a first electrode of the third transistor is coupled to the second clock signal input terminal, and a second electrode of the third transistor is coupled to the gate drive signal output terminal; The third output sub-circuit includes a thirteenth transistor, a gate of the thirteenth transistor is coupled to the pull-up node, a first electrode of the thirteenth transistor is coupled to the second clock signal input terminal, and a second electrode of the thirteenth transistor is coupled to the second output terminal.

11. A gate drive circuit, characterized in that: The invention comprises n cascaded shift register units according to any one of claims 1 to 10, wherein n is a positive integer; and further comprises a first clock signal line to an X-th clock signal line, wherein X is a positive integer; and the rising edges of the first clock signals of the first clock signal line to the X-th clock signal line are sequentially staggered by a unit time length of H; The effective level duration of one signal cycle of each clock signal line is a*H, and the invalid level duration is b*H, a+b=X; The second output terminal of the i-th shift register unit is coupled to the input signal terminal of the i+a-th shift register unit; the first output terminal of the i-th shift register unit is coupled to the input signal terminal of the i+a-1-th shift register unit; i≤n; The second output end of the i-th shift register unit is coupled to the reset control end of the ib-1-th shift register unit; the first output end of the i-th shift register unit is coupled to the reset control end of the ib-2-th shift register unit.

12. The gate driving circuit according to claim 11, characterized in that: The n shift register units are divided into a plurality of unit groups, each unit group includes X shift register units, and the second clock signal input terminals of the X shift register units are coupled to the first clock signal line to the Xth clock signal line in a one-to-one correspondence; The first clock signal input terminal of the i-th shift register unit is coupled to the second clock signal input terminal of the i-1-th shift register unit; When i=1, the first clock signal input terminal of the i-th shift register unit is coupled to the second clock signal input terminal of the n-th shift register unit; The first output terminal of the i-th shift register unit is coupled to the input signal terminal of the i+X / 2-1-th shift register unit; The second output terminal of the i-th shift register unit is coupled to the input signal terminal of the i+X / 2-th shift register unit.

13. The gate driving circuit according to claim 12, characterized in that: The first output terminal of the i-th shift register unit is also coupled to the reset control terminal of the iX / 2-2-th shift register unit; The second output terminal of the i-th shift register unit is also coupled to the reset control terminal of the iX / 2-1-th shift register unit.

14. A driving method for a gate driving circuit, characterized in that: Used to drive the gate driving circuit as claimed in claim 11, the driving method comprising: The first output terminal of the i-th shift register unit simultaneously outputs a first control signal to the input signal terminal of the i+a-1-th shift register unit and the reset control terminal of the ib-2-th shift register unit; The second output end of the i-th shift register unit simultaneously outputs a second control signal to the input signal end of the i+a-th shift register unit and the reset control end of the ib-1-th shift register unit.

15. A display device, characterized in that: The display device comprises two gate drive circuits as claimed in any one of claims 11 to 13, and further comprises: A display area and a peripheral area surrounding the display area, the two gate driving circuits are located in the peripheral area, and the display area is located between the two gate driving circuits; A plurality of scan lines extend from the display area to the peripheral area and are respectively coupled to the two gate driving circuits.

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