A superconducting quantum chip testing method, device and medium

Abstract

The present application relates to the field of superconducting quantum chip testing, and discloses a superconducting quantum chip testing method, device, and medium, which obtains the measurement and control circuit configuration and related parameters set by the user; confirms the optimized iterative cycle algorithm and test process of each measurement and control circuit configuration; applies the corresponding control waveform according to each measurement and control circuit configuration; sends instructions to the measurement and control system to perform testing and obtain test data. With this technical solution, the user only needs to select the measurement and control circuit configuration for the superconducting quantum chip and set relevant parameters for it, confirm the optimized iterative cycle algorithm and test process, and after applying the control waveform, the measurement and control system can start testing, thereby realizing the testing of the superconducting quantum chip. In this technical solution, the user can freely combine the test process sequence, cycle content, optimization method, etc., and support multiple testing requirements based on the stored optimized iterative algorithm, reducing the waste of human resources and improving testing efficiency.

Description

Technical Field

[0001] The present application relates to the field of superconducting quantum chip testing, and in particular to a superconducting quantum chip testing method, device and medium. Background Art

[0002] After completing basic process testing at room temperature, superconducting quantum chips need to obtain signal parameters that resonate with quantum bits in a low-temperature environment, and combine appropriate control technology to achieve quantum logic gates with higher fidelity, so as to use these quantum logic gates to form quantum circuits and complete quantum algorithms. Common characterization methods of obtaining signal parameters that resonate with quantum bits and using these parameters to implement quantum logic gates are collectively referred to as superconducting quantum chip testing.

[0003] In current technology, manual testing is usually required, but in practice, since it involves testing and calibration of multiple signals, the testing process contains a large number of data parameters. The entire process takes a lot of time and the computational complexity increases exponentially with the increase in the number of quantum bits.

[0004] It can be seen that how to provide a more convenient superconducting quantum chip testing method is an urgent problem to be solved by technicians in this field. Summary of the invention

[0005] The purpose of this application is to provide a superconducting quantum chip testing method, device and medium, which are used to reduce the waste of human resources and improve testing efficiency when performing superconducting quantum chip testing.

[0006] In order to solve the above technical problems, the present application provides a superconducting quantum chip testing method, comprising:

[0007] Obtain the measurement and control circuit configuration and corresponding related parameters set by the user;

[0008] Applying corresponding control waveforms according to the configuration of each measurement and control circuit;

[0009] Confirming the optimization iterative cycle algorithm and test process of each measurement and control circuit configuration according to user settings;

[0010] Send instructions to the measurement and control system to perform tests and obtain test data.

[0011] Preferably, after acquiring the test data, the method further includes:

[0012] The standard data in the database is called to calibrate the test data.

[0013] Preferably, it also includes:

[0014] The test results of each test process and the time taken for each test process are displayed according to the test data.

[0015] Preferably, it also includes:

[0016] Indicates that each of the measurement and control circuit configurations has uncalibrated related parameters.

[0017] Preferably, it also includes: displaying the current test process position during the test.

[0018] Preferably, it also includes: displaying whether the control waveform configured in each of the measurement and control circuits has been calibrated.

[0019] Preferably, the corresponding control waveform applied according to each of the measurement and control circuit configurations is:

[0020] The experimental sequence template is called to apply corresponding control waveforms to each of the measurement and control circuit configurations.

[0021] In order to solve the above technical problems, the present application also provides a superconducting quantum chip testing device, comprising:

[0022] The acquisition module is used to obtain the measurement and control circuit configuration and corresponding related parameters set by the user;

[0023] An application module, used for applying corresponding control waveforms according to the configuration of each measurement and control circuit;

[0024] A confirmation module, used to confirm the optimization iterative cycle algorithm and test process of each measurement and control circuit configuration according to user settings;

[0025] The sending module is used to send instructions to the measurement and control system to perform tests and obtain test data.

[0026] In order to solve the above technical problems, the present application also provides another superconducting quantum chip testing device, including a memory for storing a computer program;

[0027] A processor is used to implement the steps of the superconducting quantum chip testing method as described above when executing the computer program.

[0028] In order to solve the above technical problems, the present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the superconducting quantum chip testing method as described above are implemented.

[0029] The superconducting quantum chip testing method provided in this application obtains the measurement and control circuit configuration and related parameters set by the user; confirms the optimization iterative cycle algorithm and test process of each measurement and control circuit configuration according to the user setting; applies the corresponding control waveform according to each measurement and control circuit configuration; sends instructions to the measurement and control system to test and obtain test data. Compared with the current technology, manual superconducting quantum chip testing requires complex calculations and multiple operation steps, which wastes a lot of time and human resources. With this technical solution, the user only needs to select the measurement and control circuit configuration for the superconducting quantum chip and set relevant parameters for it, confirm the optimization iterative cycle algorithm and test process, and after applying the control waveform, send instructions to the measurement and control system to start testing, and receive the test data fed back by the measurement and control system, so as to realize the test of the superconducting quantum chip. In this technical solution, the user can freely combine the test process sequence, cycle content, optimization method, etc., and support multiple test requirements according to the stored optimization iterative algorithm, reduce the waste of human resources, and improve the test efficiency.

[0030] In addition, the superconducting quantum chip testing device and medium provided in this application correspond to the above-mentioned superconducting quantum chip testing method, and the effect is the same as above. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 A flow chart of a superconducting quantum chip testing method provided in an embodiment of the present application;

[0033] Figure 2 A schematic diagram illustrating a superconducting quantum chip testing method provided in an embodiment of the present application;

[0034] Figure 3 A schematic diagram of an automated process definition interactive interface provided in an embodiment of the present application;

[0035] Figure 4 A structural diagram of a superconducting quantum chip testing device provided in an embodiment of the present application;

[0036] Figure 5 A structural diagram of another superconducting quantum chip testing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0038] After completing basic process testing at room temperature, superconducting quantum chips need to obtain signal parameters that resonate with quantum bits in a low-temperature environment, and combine appropriate control technology to achieve quantum logic gates with high fidelity, so as to use these quantum logic gates to form quantum circuits and complete quantum algorithms. Common methods of obtaining signal parameters that resonate with quantum bits and using these parameters to implement quantum logic gates are collectively referred to as superconducting quantum chip testing. In the actual process, since it involves multi-channel signal testing and calibration, the test process is based on the idea of ​​iterative optimization, that is, using known data to obtain rough parameter information, and then supplementing experiments based on this information to optimize and iterate in turn, and finally obtain parameters with higher accuracy.

[0039] In current technology, manual testing is usually required, but in practice, since it involves testing and calibration of multiple signals, the testing process contains a large number of data parameters. The entire process takes a lot of time and the computational complexity increases exponentially with the increase in the number of quantum bits.

[0040] The core of this application is to provide a superconducting quantum chip testing method, device and medium, which are used to reduce the waste of human resources and improve testing efficiency when performing superconducting quantum chip testing.

[0041] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0042] Figure 1 A flow chart of a superconducting quantum chip testing method provided in an embodiment of the present application, such as Figure 1 As shown, the method includes:

[0043] S10: Obtain the measurement and control circuit configuration and corresponding related parameters set by the user;

[0044] S11: applying corresponding control waveforms according to the configuration of each measurement and control circuit;

[0045] S12: confirming the optimization iteration cycle algorithm and test process of each measurement and control circuit configuration according to user settings;

[0046] S13: Send instructions to the measurement and control system to perform testing and obtain test data.

[0047] First of all, it should be explained that the executor of the superconducting quantum chip testing method provided in the embodiment of the present application can be a superconducting quantum chip testing device or a host computer and other equipment, which is connected to the measurement and control system. After the user sets the relevant information in the superconducting quantum chip testing device or the host computer, the superconducting quantum chip testing device or the host computer can send instructions to the measurement and control system to thereby implement the test of the superconducting quantum chip.

[0048] In this embodiment, the optimized iterative loop algorithm is pre-stored in the database, and when testing, the user only needs to call the corresponding optimized iterative loop algorithm according to the user setting to perform the test. In addition, the user can also add a new algorithm for testing later.

[0049] The so-called quantum chip is to integrate quantum circuits on a substrate, thereby carrying the function of quantum information processing. In this embodiment, the user can freely combine the test items according to the needs. In order to facilitate the user to set the configuration data required in this method, a custom operation interface can usually be set on the operation interface. Figure 2 This is a diagram illustrating the framework of a superconducting quantum chip testing method provided in the embodiment of the present application. For ease of understanding, the framework is mainly divided into five modules, namely: basic parameter setting module, automated process definition interactive interface, optimization and direction module, calibration module, and line module. Among them, the line module can be divided into three small modules, namely: drive circuit, control circuit, and read circuit.

[0050] For the basic parameter setting module: This module collects the measurement and control line configuration and basic related parameter ranges provided by the user, and initializes the automation process.

[0051] For the interactive interface of automated process definition: This interface allows experimenters to customize experimental processes and experimental objectives, select optimization methods and experimental processes, and supports modular dragging, which is convenient for experimenters to conduct quick experiments.

[0052] For the optimization and direction module: This module provides the experimental process sequence and parameter docking, and also provides various optimization iterative cycle algorithms. By setting the optimization cycle goals, the parameter acquisition requirements are completed.

[0053] For the line module: This module is mainly used to complete the combined experimental waveform sequence by applying control waveforms on three lines and setting the timing. Among them, in order to facilitate the experiment, a variety of common experimental sequence templates can also be provided to facilitate rapid experiments. For the relevant waveforms and delay settings used in the experiment, parameters can be set separately, and the auxiliary function can provide relevant parameter suggestions. For waveform data with large data, you can choose to call it directly from the database.

[0054] For the calibration module: This module has built-in multiple benchmark test experiments. This module requires that after the relevant door operation calibration is completed, the database must contain the corresponding door data, and supports multiple calibration schemes. After obtaining the test data, it is used to call the standard data in the database to calibrate the test data.

[0055] It can be seen from the framework illustration that in this embodiment, the user can use the above five modules to perform the configuration required for the test. After selecting the measurement and control circuit configuration and setting relevant parameters for it, the superconducting quantum chip testing device or the host computer can notify the measurement and control system to start the test and receive the data fed back by the measurement and control system, which can be displayed in the automated process definition interactive interface.

[0056] In order to better illustrate the application of the above method, Figure 3 A schematic diagram of an automated process definition interactive interface provided in an embodiment of the present application. In the automated process definition interactive interface, the experimenter can drag and select a custom experimental process and experimental goal, select an optimization method and experimental process, such as Figure 3 As shown, when the experimenter conducts the experiment, he can select the corresponding module in the "Module Selection and Function Bar" in the automated process definition interactive interface, drag the corresponding module and optimization scheme in the "Module Combination and Experiment Customization Bar", and build the test process by combining. The corresponding parameters can be modified in the "Parameter Configuration Bar" and "Waveform Selection Bar" on the left for customization. In the specific implementation, the method provided by the technical solution can be used to test a variety of superconducting quantum chips according to the settings of the experimenter, and the tests for the same type of superconducting quantum chips are also the same, or only some of the control waveforms are different. Therefore, in order to facilitate the operation of the experimenter, the experimental sequence template can be pre-configured and stored, and the experimental sequence template can be called when the test is performed to configure the corresponding control waveform for each measurement and control circuit, thereby reducing the amount of operation of the experimenter. After the construction is completed, click "Run" in the "Module Selection and Function Bar" to test. In addition, the experimental process and auxiliary information prompt bar are also provided in the automated process definition interactive interface to display the current test process position during the test. The constructed test process structure is displayed in the "Experimental Process and Auxiliary Information Prompt Bar", and it is displayed whether the control waveform configured for each measurement and control circuit has been calibrated. In the specific implementation, after obtaining the test data set by the user, the standard data in the database can also be called to calibrate the test data. In order to facilitate the experimenter to control the data, the experimental process and auxiliary information prompt bar can also indicate the relevant parameters of each measurement and control circuit configuration that have not been calibrated. Finally, the experimenter can obtain the test data from the "Experimental Results and Operation Information Bar" and display the test results and time of each test process based on the obtained test data.

[0057] The following is an actual example to illustrate the process: if you need to adjust the fast-adjusting signal for a single bit, click the "Experiment" button in the "Module Selection and Function Bar", select the "Single-bit Test" module in the drop-down bar, and drag it into the "Module Combination and Experiment Customization Bar"; select the "Two-bit Gate" module and drag it into the "Module Combination and Experiment Customization Bar". Click the "Sequence" button in the "Module Selection and Function Bar", select the "Single Process" module in the drop-down bar, drag it into the "Module Combination and Experiment Customization Bar", and connect the "Single-bit Test" module and the "Two-bit Gate" module. Double-click to expand the "Two-bit Gate" and select to delete the part after "Fast-adjusting Signal Adjustment". In addition to obtaining the bit fast-adjusting information, you need to obtain the relationship between the bit fast-adjusting information and the read information. Select the "Single-bit Test" module again and drag it to the back of the "Two-bit Gate" module. Double-click to expand the "Single-bit Test" module and keep only the "Read Optimization" part. Click the "Sequence" button in the "Module Selection and Function Bar", select the "Single Trigger Cycle" module in the drop-down bar, drag it into the "Module Combination and Experiment Customization Bar", and connect the fast-adjust signal adjustment and reading optimization in the "Two-bit Gate" module. In the auxiliary information prompt, select "Single Trigger Cycle" with the highest priority, and the experiment settings are completed, and you can conduct the experiment.

[0058] The superconducting quantum chip testing method provided in the embodiment of the present application obtains the measurement and control circuit configuration and related parameters set by the user, confirms the optimization iterative cycle algorithm and test process of each measurement and control circuit configuration; applies the corresponding control waveform according to each measurement and control circuit configuration; sends instructions to the measurement and control system to test and obtain test data. Compared with the current technology, manual superconducting quantum chip testing requires complex calculations and multiple operation steps, which wastes a lot of time and human resources. With this technical solution, the user only needs to select the measurement and control circuit configuration for the superconducting quantum chip and set relevant parameters for it, confirm the optimization iterative cycle algorithm and test process, and after applying the control waveform, send instructions to the measurement and control system to start testing, and receive the test data fed back by the measurement and control system, so as to realize the test of the superconducting quantum chip. In this technical solution, the user can freely combine the test process sequence, cycle content, optimization method, etc., and support multiple test requirements according to the stored optimization iterative algorithm, reduce the waste of human resources, and improve the test efficiency.

[0059] In a specific implementation, in order to accurately obtain the test results of the superconducting quantum chip and make an accurate analysis of the test, in this embodiment, after obtaining the test data, it also includes:

[0060] The test results of each test process and the time used for each test process are displayed according to the test data.

[0061] During the testing process, it also includes: displaying the current test process position.

[0062] By locating the test process, the experimenter can accurately know the current test items and test time. When the test time exceeds the normal range, the experimenter can handle it in time to avoid delays in the test process.

[0063] In addition, based on the above embodiment, in this embodiment, the superconducting quantum chip testing method further includes:

[0064] Indicates that the relevant parameters of each measurement and control circuit configuration have not been calibrated.

[0065] Displays whether the control waveform configured in each measurement and control circuit has been calibrated.

[0066] In this embodiment, by calibrating and confirming the relevant parameters and the control waveform, inaccuracy of the test items due to the negligence of the experimenter can be avoided, thereby improving the accuracy of the test.

[0067] In the above embodiments, the superconducting quantum chip testing method is described in detail, and the present application also provides an embodiment corresponding to the superconducting quantum chip testing device. It should be noted that the present application describes the embodiments of the device part from two perspectives, one is based on the functional module perspective, and the other is based on the hardware perspective.

[0068] Figure 4 A structural diagram of a superconducting quantum chip testing device provided in an embodiment of the present application, such as Figure 4 As shown, the device comprises:

[0069] The acquisition module 10 is used to obtain the measurement and control circuit configuration and corresponding related parameters set by the user;

[0070] An application module 11 is used to apply corresponding control waveforms according to the configuration of each measurement and control circuit;

[0071] Confirmation module 12, used to confirm the optimization iterative cycle algorithm and test process of each measurement and control circuit configuration according to user settings;

[0072] The sending module 13 is used to send instructions to the measurement and control system to perform testing and obtain test data.

[0073] Since the embodiments of the apparatus part correspond to the embodiments of the method part, please refer to the description of the embodiments of the method part for the embodiments of the apparatus part, which will not be repeated here.

[0074] The superconducting quantum chip testing device provided in the embodiment of the present application obtains the measurement and control circuit configuration and related parameters set by the user; confirms the optimization iterative cycle algorithm and test process of each measurement and control circuit configuration; applies the corresponding control waveform according to each measurement and control circuit configuration; sends instructions to the measurement and control system to test and obtain test data. Compared with the current technology, manual superconducting quantum chip testing requires complex calculations and multiple operation steps, which wastes a lot of time and human resources. With this technical solution, the user only needs to select the measurement and control circuit configuration for the superconducting quantum chip and set relevant parameters for it, confirm the optimization iterative cycle algorithm and test process, and after applying the control waveform, send instructions to the measurement and control system to start testing, and receive the test data fed back by the measurement and control system, so as to realize the test of the superconducting quantum chip. In this technical solution, the user can freely combine the test process sequence, cycle content, optimization method, etc., and support multiple test requirements according to the stored optimization iterative algorithm, reducing the waste of human resources and improving the test efficiency.

[0075] Figure 5 A structural diagram of another superconducting quantum chip testing device provided in an embodiment of the present application, such as Figure 5 As shown, the device comprises: a memory 20 for storing a computer program;

[0076] The processor 21 is used to implement the steps of the superconducting quantum chip testing method in the above embodiment when executing the computer program.

[0077] The superconducting quantum chip testing device provided in this embodiment may include but is not limited to a smart phone, a tablet computer, a laptop computer or a desktop computer.

[0078] Among them, the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 can be implemented in at least one hardware form of a digital signal processor (DSP), a field-programmable gate array (FPGA), and a programmable logic array (PLA). The processor 21 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 21 may be integrated with a graphics processing unit (GPU), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 21 may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

[0079] The memory 20 may include one or more computer-readable storage media, which may be non-transitory. The memory 20 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 20 is at least used to store the following computer program 201, wherein the computer program is loaded and executed by the processor 21, and the relevant steps of the superconducting quantum chip testing method disclosed in any of the aforementioned embodiments can be implemented. In addition, the resources stored in the memory 20 may also include an operating system 202 and data 203, etc., and the storage method may be short-term storage or permanent storage. Among them, the operating system 202 may include Windows, Unix, Linux, etc. Data 203 may include, but is not limited to, relevant parameters, optimization iterative loop algorithms, etc.

[0080] In some embodiments, the superconducting quantum chip testing device may further include a display screen 22 , an input / output interface 23 , a communication interface 24 , a power supply 25 , and a communication bus 26 .

[0081] Those skilled in the art will understand that Figure 5 The structure shown in the figure does not constitute a limitation on the superconducting quantum chip testing device, and may include more or fewer components than those shown in the figure.

[0082] The superconducting quantum chip testing device provided in the embodiment of the present application includes a memory and a processor. When the processor executes the program stored in the memory, it can implement the following method: obtain the measurement and control circuit configuration and corresponding related parameters set by the user; apply the corresponding control waveform according to each measurement and control circuit configuration; confirm the optimization iterative cycle algorithm and test process of each measurement and control circuit configuration; send instructions to the measurement and control system to perform testing and obtain test data.

[0083] The superconducting quantum chip testing device provided in the embodiment of the present application obtains the measurement and control circuit configuration and related parameters set by the user; confirms the optimization iterative cycle algorithm and test process of each measurement and control circuit configuration; applies the corresponding control waveform according to each measurement and control circuit configuration; sends instructions to the measurement and control system to test and obtain test data. Compared with the current technology, manual superconducting quantum chip testing requires complex calculations and multiple operation steps, which wastes a lot of time and human resources. With this technical solution, the user only needs to select the measurement and control circuit configuration for the superconducting quantum chip and set relevant parameters for it, confirm the optimization iterative cycle algorithm and test process, and after applying the control waveform, send instructions to the measurement and control system to start testing, and receive the test data fed back by the measurement and control system, so as to realize the test of the superconducting quantum chip. In this technical solution, the user can freely combine the test process sequence, cycle content, optimization method, etc., and support multiple test requirements according to the stored optimization iterative algorithm, reducing the waste of human resources and improving the test efficiency.

[0084] Finally, the present application also provides an embodiment corresponding to a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps recorded in the above method embodiment are implemented.

[0085] It is understandable that if the method in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0086] The computer-readable storage medium provided in the embodiment of the present application obtains the measurement and control circuit configuration and related parameters set by the user; confirms the optimization iterative cycle algorithm and test process of each measurement and control circuit configuration; applies the corresponding control waveform according to each measurement and control circuit configuration; sends instructions to the measurement and control system to test and obtain test data. Compared with the current technology, manual superconducting quantum chip testing requires complex calculations and multiple operation steps, which wastes a lot of time and human resources. With this technical solution, the user only needs to select the measurement and control circuit configuration for the superconducting quantum chip and set relevant parameters for it, confirm the optimization iterative cycle algorithm and test process, and after applying the control waveform, send instructions to the measurement and control system to start testing, and receive the test data fed back by the measurement and control system, so as to realize the test of the superconducting quantum chip. In this technical solution, the user can freely combine the test process sequence, cycle content, optimization method, etc., and support multiple test requirements according to the stored optimization iterative algorithm, reduce the waste of human resources, and improve the test efficiency.

[0087] The superconducting quantum chip testing method, device and medium provided by the present application are introduced in detail above. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

[0088] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

Claims

1. A superconducting quantum chip testing method, characterized in that: include: Obtain the measurement and control circuit configuration and corresponding related parameters set by the user; Applying corresponding control waveforms according to the configuration of each measurement and control circuit; Confirming the optimization iterative cycle algorithm and test process of each measurement and control circuit configuration according to user settings; Send instructions to the measurement and control system to perform tests and obtain test data; Applying corresponding control waveforms according to the configuration of each of the measurement and control circuits includes: Determine the selected type as experiment or sequence according to the module selection in the automated process definition interactive interface and the experiment button or sequence button pressed in the function bar, the experiment includes an experiment connecting a single-bit test and a two-bit gate, and the sequence includes a single process; Determine corresponding parameters according to the parameter configuration bar and waveform selection bar in the automation process definition interactive interface; Send instructions to the measurement and control system to perform tests and obtain test data, including: The module selection in the automation process definition interactive interface and the run button in the function bar are pressed, and the selected type is determined to be runtime, and a command is sent to the measurement and control system; Controlling the experimental process and auxiliary information prompt bar in the automated process definition interactive interface to display the constructed test process structure and whether the control waveforms configured for each measurement and control circuit have been calibrated; The experimental result and operation information column in the automated process definition interactive interface is controlled to display the test data, and the test results of each test process and the time used for each test process are displayed according to the obtained test data.

2. The superconducting quantum chip testing method according to claim 1, characterized in that: After obtaining the test data, the method further includes: The standard data in the database is called to calibrate the test data.

3. The superconducting quantum chip testing method according to claim 1, characterized in that: Also includes: Indicates that each of the measurement and control circuit configurations has uncalibrated related parameters.

4. The superconducting quantum chip testing method according to claim 1, characterized in that: Also includes: Display the current test process position during the test.

5. The superconducting quantum chip testing method according to claim 1, characterized in that: The corresponding control waveform applied according to each of the measurement and control circuit configurations is: The experimental sequence template is called to apply corresponding control waveforms to each of the measurement and control circuit configurations.

6. A superconducting quantum chip testing device, characterized in that: include: The acquisition module is used to obtain the measurement and control circuit configuration and corresponding related parameters set by the user; An application module, used for applying corresponding control waveforms according to the configuration of each measurement and control circuit; A confirmation module, used to confirm the optimization iterative cycle algorithm and test process of each measurement and control circuit configuration according to user settings; A sending module is used to send instructions to the measurement and control system to perform tests and obtain test data; The application module is specifically used to determine the selected type as an experiment or a sequence according to the module selection in the automated process definition interactive interface and the experiment button or sequence button pressed in the function bar, the experiment includes an experiment of connecting a single-bit test and a two-bit gate, and the sequence includes a single process; Determine corresponding parameters according to the parameter configuration bar and waveform selection bar in the automation process definition interactive interface; The sending module is specifically used to send instructions to the measurement and control system when the module selection and the run button in the function bar in the automation process definition interactive interface are pressed and the selected type is determined to be run time; Controlling the experimental process and auxiliary information prompt bar in the automated process definition interactive interface to display the constructed test process structure and whether the control waveforms configured for each measurement and control circuit have been calibrated; The experimental result and operation information column in the automated process definition interactive interface is controlled to display the test data, and the test results of each test process and the time used for each test process are displayed according to the obtained test data.

7. A superconducting quantum chip testing device, characterized in that: comprising a memory for storing a computer program; A processor, configured to implement the steps of the superconducting quantum chip testing method according to any one of claims 1 to 5 when executing the computer program.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by the processor, the steps of the superconducting quantum chip testing method according to any one of claims 1 to 5 are implemented.

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