Wafer Acceptance Test Methodology

Abstract

The present invention provides a wafer acceptance test method, including: placing a pin card on all PADs; connecting the pogo pin of a parallel test device to the pin card; using pogo pins to set a proximal shielding layer on all signal end sides; connecting a mounting resistor between a first target PAD, a second target PAD, a first adjacent PAD, and a second adjacent PAD; defining a signal end to be measured and a non-measured signal end; grounding the proximal shielding layer on the non-measured signal end side; applying a bias voltage between the first target PAD and the second target PAD to obtain the current between the signal ends to be measured. The present application sets a proximal shielding layer on all signal end sides and grounds the proximal shielding layer on the non-measured signal end side, so that the noise formed by the non-measured signal end after contacting the wafer can be promptly guided to the internal ground end of the parallel test device, thereby avoiding the generation of loop noise and improving the stability of test data in a small current test.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor device testing, and in particular to a wafer acceptance testing method. Background Art

[0002] The WAT test (Wafer Acceptance Test) monitors the process stability by applying a current or voltage signal after probing the wafer. Traditionally, electrical test equipment (WAT Tester) generally uses the method of physically draining the interference noise during the test process through the shell of the test equipment to the external remote ground to suppress the noise.

[0003] However, this method cannot completely suppress interference and eliminate noise in some test applications. It is mainly manifested in that the small current test is easily affected by noise, resulting in test data deviation and large StdDev (standard deviation). In terms of test machine models, the leakage measured by the serial tester is stable at the pA level, while the data measured by the parallel tester fluctuates around the ~e-11A level, with poor stability and noise interference. At this time, the traditional external remote grounding method is not enough to completely shield the noise interference on the parallel tester. Summary of the invention

[0004] The present application provides a wafer acceptance test method, which can solve at least one of the following problems in the small current test of WAT test, namely, parallel test is interfered by noise, noise signal interference cannot be completely shielded, resulting in poor stability of test data, etc.

[0005] On the one hand, an embodiment of the present application provides a wafer acceptance test method, wherein the wafer to be tested includes: a plurality of identical chips and a plurality of PADs, each of the chips has at least two signal terminals, and each of the signal terminals is electrically connected to each of the PADs correspondingly, and the wafer acceptance test method includes:

[0006] Contact all PADs with a pin card, which is used to perform electrical testing;

[0007] Connecting a pogo pin of a parallel test device to the pin card, wherein the parallel test device is provided with a remote shielding cover;

[0008] Use the pogo pins of the parallel test device to set the near-end shield layer on all signal end sides;

[0009] A plurality of mounting resistors on the same chip are connected in series using a first target PAD, a second target PAD, a first adjacent PAD, and a second adjacent PAD, wherein the first adjacent PAD is located on the side of the first target PAD, and the second adjacent PAD is located on the side of the second target PAD;

[0010] Define a signal end electrically connected to the first target PAD and the second target PAD as a signal end to be measured, and define a signal end electrically connected to the remaining PADs except the first target PAD and the second target PAD as a non-measurement signal end;

[0011] Grounding the proximal shielding layer on the non-measurement signal end side;

[0012] A bias voltage is applied between the first target PAD and the second target PAD to obtain a current between the signal terminals to be measured.

[0013] Optionally, in the wafer acceptance test method, the step of connecting a plurality of mounting resistors on the same chip in series using the first target PAD, the second target PAD, the first adjacent PAD, and the second adjacent PAD includes:

[0014] Connecting a first mounting resistor in series between the first adjacent PAD and the first target PAD;

[0015] Connecting a second mounting resistor in series between the first adjacent PAD and the second target PAD;

[0016] A third mounting resistor is connected in series between the first adjacent PAD and the second adjacent PAD.

[0017] Optionally, in the wafer acceptance test method, the resistance value of the first mounting resistor is smaller than the resistance value of the second mounting resistor, and the resistance value of the second mounting resistor is smaller than the resistance value of the third mounting resistor.

[0018] Optionally, in the wafer acceptance test method, after connecting the pogo pin of the parallel test device to the pin card and before grounding the proximal shielding layer of the signal end side of the remaining PADs electrically connected except the first target PAD and the second target PAD, the wafer acceptance test method further includes:

[0019] The remote shield is grounded.

[0020] Optionally, in the wafer acceptance test method, all of the proximal shielding layers are independent of each other.

[0021] Optionally, in the wafer acceptance test method, the first target PAD and the second target PAD are any two PADs among all PADs.

[0022] Optionally, in the wafer acceptance test method, after applying a bias voltage between the first target PAD and the second target PAD to obtain the current between the signal terminals to be measured, the wafer acceptance test method further includes:

[0023] The connection between the proximal shielding layer on the non-measurement signal end side and the ground end is cut off.

[0024] The technical solution of this application has at least the following advantages:

[0025] The present application uses pogo pins to set a proximal shielding layer on all signal end sides; then connects mounting resistors between the first target PAD, the second target PAD and the first adjacent PAD and the second adjacent PAD; then grounds the proximal shielding layer on the non-measurement signal end side, and finally applies a bias voltage between the first target PAD and the second target PAD to obtain the current between the signal ends to be measured. In this way, the noise generated by all non-measurement signal ends after contacting the wafer can be promptly led to the ground end inside the parallel test device, thereby avoiding the generation of loop noise, eliminating the noise interference caused by the non-measurement signal ends, improving the stability of the test data (small current) of the signal end to be measured in the small current test, and being able to timely monitor whether the device has a leakage risk.

[0026] Furthermore, the present application uses pogo pin to set a proximal shielding layer on all signal end sides, and grounds the proximal shielding layer on the non-measurement signal end side, and also grounds the distal shielding cover on the parallel test device. This can achieve a double shielding effect on interference noise, further improving the stability of the test data (small current) at the signal end to be measured in the small current test. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 is a flow chart of a wafer acceptance test method according to an embodiment of the present invention;

[0029] Figure 2 is a schematic diagram of a proximal shielding layer suppressing interference sources according to an embodiment of the present invention;

[0030] The reference numerals are described as follows:

[0031] 11-first target PAD, 12-second target PAD, 13-first adjacent PAD, 14-second adjacent PAD, 21-proximal shielding layer. DETAILED DESCRIPTION

[0032] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0033] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0034] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0035] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0036] The inventors have found that a parallel test device will conduct parallel testing on devices with the same test structure during testing. However, this will result in influence between adjacent PADs during small current testing. As a result, a noise loop is easily formed between other non-measurement pins (non-measurement signal terminals) and the signal terminal to be measured when the wafer is tested, thereby affecting the test.

[0037] The present application embodiment provides a wafer acceptance test method, referring to Figure 1 , Figure 1 is a flowchart of a wafer acceptance test method according to an embodiment of the present invention, referring to Figure 2 , Figure 2It is a schematic diagram of suppressing interference sources by a proximal shielding layer according to an embodiment of the present invention.

[0038] In this embodiment, the wafer to be tested includes: a plurality of identical chips and a plurality of PADs, each of the chips has at least two signal terminals, and each of the signal terminals is electrically connected to each of the PADs correspondingly.

[0039] The wafer acceptance test method comprises:

[0040] Step S10: All PADs are contacted with a pin card, and the pin card is used for electrical testing.

[0041] Step S20: Connect the pogo pin of the parallel test device to the pin card, wherein the parallel test device is provided with a remote shielding cover. In this embodiment, the remote shielding cover may be a housing of the parallel test device.

[0042] Step S30: Using the pogo pin of the parallel test device to set a proximal shielding layer 21 on all signal terminals. Specifically, the proximal shielding layer 21 is set on both sides of each signal terminal, and each proximal shielding layer 21 may include: two parallel metal shielding layers.

[0043] Preferably, all the proximal shielding layers 21 are independent of each other and do not contact each other.

[0044] Step S40: using the first target PAD11, the second target PAD12, the first adjacent PAD13, and the second adjacent PAD14 to connect in series a plurality of mounting resistors on the same chip, wherein the first adjacent PAD13 is located at the first target PAD11 side, and the second adjacent PAD14 is located at the second target PAD12 side.

[0045] In this embodiment, the first target PAD 11 and the second target PAD 12 are selected according to a signal end that actually needs to be measured, and the first target PAD 11 and the second target PAD 12 are any two PADs among all PADs.

[0046] Specifically, the step of connecting a plurality of mounting resistors on the same chip in series by using the first target PAD11, the second target PAD12, the first adjacent PAD13, and the second adjacent PAD14 may include:

[0047] A first mounting resistor R1 is connected in series between the first neighboring PAD13 and the first target PAD11;

[0048] A second mounting resistor R2 is connected in series between the first adjacent PAD13 and the second target PAD12;

[0049] A third mounting resistor R3 is connected in series between the first adjacent PAD13 and the second adjacent PAD14.

[0050] Further, the resistance value of the first mounting resistor R1 is smaller than the resistance value of the second mounting resistor R2 , and the resistance value of the second mounting resistor R2 is smaller than the resistance value of the third mounting resistor R3 .

[0051] The first target PAD 11 , the second target PAD 12 , the first adjacent PAD 13 , and the second adjacent PAD 14 are generally used as a group of test PADs, and a group of test PADs can be used for one chip on a wafer.

[0052] In another embodiment, the step of connecting a plurality of mounting resistors on the same chip in series using the first target PAD11, the second target PAD12, the first neighbor PAD13, and the second neighbor PAD14 includes:

[0053] A mounting resistor is connected in series between the first adjacent PAD13 and the first target PAD11;

[0054] A mounting resistor is connected in series between the first target PAD11 and the second target PAD12;

[0055] A mounting resistor is connected in series between the second target PAD 12 and the second adjacent PAD 14 .

[0056] Step S50: Define the signal end to which the first target PAD11 and the second target PAD12 are electrically connected as the signal end to be measured, and define the signal end to which the remaining PADs except the first target PAD11 and the second target PAD12 are electrically connected as the non-measurement signal end, so the first adjacent PAD13 and the second adjacent PAD14 are also defined as the non-measurement signal end.

[0057] Step S60: grounding the proximal shielding layer 21 on the non-measurement signal end side.

[0058] In this embodiment, whether the proximal shielding layer 21 on the non-measurement signal end side is grounded can be controlled by controlling a control algorithm of the parallel test device.

[0059] Preferably, after connecting the pogo pin of the parallel test device to the pin card (step S20), and before grounding the proximal shielding layer on the signal end side of the remaining PADs electrically connected except the first target PAD and the second target PAD (step S60), the wafer acceptance test method may also include: grounding the distal shielding cover.

[0060] Specifically, the step of grounding the remote shielding cover may be performed between any two adjacent steps between step S20 and step S60.

[0061] In this embodiment, grounding the remote shielding cover may be: grounding a housing of the parallel testing device.

[0062] Step S70: Apply a bias voltage between the first target PAD11 and the second target PAD12 to obtain the current between the signal ends to be measured. Specifically, the current between the signal ends to be measured can be obtained based on the bias voltage applied between the first target PAD11 and the second target PAD12 and the resistance value of the mounting resistor between the first target PAD11 and the second target PAD12.

[0063] In the present application, a proximal shielding layer is set on all signal end sides by using pogo pins; then a mounting resistor is connected between the first target PAD11, the second target PAD12, the first adjacent PAD13, and the second adjacent PAD14; then the distal shielding cover on the parallel test device is grounded, and the proximal shielding layer on the non-measured signal end side is grounded, and finally a bias voltage is applied between the first target PAD11 and the second target PAD12 to obtain the current between the signal ends to be measured, so that the noise generated by all non-measured signal ends after contacting the wafer can be promptly led to the ground end inside the parallel test device (see the attached figure for details). Figure 2 The device can detect the destination of noise in the test signal, thereby avoiding loop noise and eliminating noise interference caused by non-measurement signal ends. It improves the stability of test data (small current) at the signal end to be measured in small current tests, improves the standard deviation of test data, and can timely monitor whether there is leakage risk in the device, thereby improving the overall anti-interference ability of the parallel test device model.

[0064] Furthermore, the present application grounds the far-end shielding cover on the parallel test device and grounds the proximal shielding layer on the non-measurement signal end side, which can achieve a double shielding effect on interference noise and further improve the stability of the test data (small current) at the signal end to be measured in the small current test.

[0065] Furthermore, after applying a bias voltage between the first target PAD11 and the second target PAD12 to obtain the current between the signal terminals to be measured, the wafer acceptance test method may further include: step S80: disconnecting the proximal shielding layer on the non-measurement signal terminal side from the ground terminal. Specifically, the proximal shielding layer 21 on the non-measurement signal terminal side may be disconnected from the ground terminal by controlling a control algorithm of the parallel test device.

[0066] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A wafer acceptance test method, wherein the wafer to be tested comprises: A plurality of identical chips and a plurality of PADs, each of the chips having at least two signal terminals, each of the signal terminals being electrically connected to each of the PADs correspondingly, wherein the wafer acceptance test method comprises: Contact all PADs with a pin card, which is used to perform electrical testing; Connecting a pogo pin of a parallel test device to the pin card, wherein the parallel test device is provided with a remote shielding cover; Use the pogo pins of the parallel test device to set the near-end shield layer on all signal end sides; A plurality of mounting resistors on the same chip are connected in series using a first target PAD, a second target PAD, a first adjacent PAD, and a second adjacent PAD, wherein the first adjacent PAD is located on the side of the first target PAD, and the second adjacent PAD is located on the side of the second target PAD; Define a signal end electrically connected to the first target PAD and the second target PAD as a signal end to be measured, and define a signal end electrically connected to the remaining PADs except the first target PAD and the second target PAD as a non-measurement signal end; Grounding the proximal shielding layer on the non-measurement signal end side; A bias voltage is applied between the first target PAD and the second target PAD to obtain a current between the signal terminals to be measured.

2. The wafer acceptance test method according to claim 1, characterized in that: The step of connecting a plurality of mounting resistors on the same chip in series by using the first target PAD, the second target PAD, the first adjacent PAD, and the second adjacent PAD comprises: Connecting a first mounting resistor in series between the first adjacent PAD and the first target PAD; Connecting a second mounting resistor in series between the first adjacent PAD and the second target PAD; A third mounting resistor is connected in series between the first adjacent PAD and the second adjacent PAD.

3. The wafer acceptance test method according to claim 2, characterized in that: The resistance value of the first mounting resistor is smaller than the resistance value of the second mounting resistor, and the resistance value of the second mounting resistor is smaller than the resistance value of the third mounting resistor.

4. The wafer acceptance test method according to claim 1, characterized in that: After connecting the pogo pin of the parallel test device to the pin card and before grounding the proximal shielding layer of the signal end side of the remaining PADs electrically connected except the first target PAD and the second target PAD, the wafer acceptance test method further includes: The remote shield is grounded.

5. The wafer acceptance test method according to claim 1, characterized in that: All of the proximal shielding layers are independent of each other.

6. The wafer acceptance test method according to claim 1, characterized in that: The first target PAD and the second target PAD are any two PADs among all PADs.

7. The wafer acceptance test method according to claim 1, characterized in that: After applying a bias voltage between the first target PAD and the second target PAD to obtain the current between the signal terminals to be measured, the wafer acceptance test method further includes: The connection between the proximal shielding layer on the non-measurement signal end side and the ground end is cut off.

Images