Instruction execution method, device, chip and computer equipment

Abstract

The embodiments of the present invention provide an instruction execution method, device, chip and computer equipment. The instruction execution method includes: receiving a first instruction, when the first instruction depends on a second instruction, sending the first instruction to a first pipeline, and sending a second signal to a second pipeline, the second instruction is an instruction received earlier than the first instruction and has not yet been executed; wherein the first pipeline includes a first dependent pipeline stage, the second pipeline includes a second dependent pipeline stage, the processing of the first instruction in the first dependent pipeline stage depends on the processing of the second instruction in the second dependent pipeline stage; if the second signal has entered the second dependent pipeline stage before the first instruction enters the first dependent pipeline stage for processing, the first instruction is sent to enter the first dependent pipeline stage. The instruction execution method, device, chip and computer equipment provided by the embodiments of the present application can save circuit area and reduce chip power consumption while improving efficiency in order-preserving execution.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of processor technology, and specifically to an instruction execution method, apparatus, chip and computer equipment. Background Art

[0002] Computer processors read instructions from memory or cache and then execute them. The execution methods are divided into sequential execution and out-of-order execution. Sequential execution will process the instructions in the order in which the processor reads them, while out-of-order execution will put the instructions that cannot be executed due to lack of execution conditions into a waiting state and execute the instructions that meet the execution conditions in the later order, thereby reducing the waiting time of the subsequent circuits and improving the efficiency of the processor in processing data.

[0003] However, some instructions have dependencies, that is, the execution of subsequent instructions requires hardware resources or processed data released after the execution of the previous instructions. Therefore, even if the previous instructions are placed in a waiting state and the conditions for the subsequent instructions to be executed are met, the subsequent instructions will usually wait for the previous instructions to be executed before they are executed. The dependence of subsequent instructions on previous instructions leads to order restrictions in out-of-order execution, which is called order-preserving execution. Order-preserving execution increases the waiting time of subsequent circuits and reduces the efficiency of the processor in processing data.

[0004] Therefore, how to improve the efficiency of processors in processing data during order-preserving execution has become a technical problem that technical personnel in this field need to solve urgently. Summary of the invention

[0005] In view of this, embodiments of the present invention provide an instruction execution method, apparatus, chip and computer device to improve efficiency in order-preserving execution while saving circuit area and reducing chip power consumption.

[0006] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0007] In a first aspect, in order to solve the above problem, an embodiment of the present invention provides an instruction execution method, including:

[0008] receiving a first instruction, and determining whether the first instruction depends on a second instruction, where the second instruction is an instruction received earlier than the first instruction and has not yet been executed;

[0009] When the first instruction depends on the second instruction, the first instruction is sent to a first pipeline, and a second signal is sent to a second pipeline; the second pipeline is a route for sending the second instruction, wherein the first pipeline includes a first dependent pipeline stage, the second pipeline includes a second dependent pipeline stage, and processing of the first instruction at the first dependent pipeline stage depends on processing of the second instruction at the second dependent pipeline stage;

[0010] Before the first instruction enters the first dependent pipeline stage, it is determined whether the second signal has entered the second dependent pipeline stage; if the second signal has entered the second dependent pipeline stage, the first instruction is sent to enter the first dependent pipeline stage.

[0011] In a second aspect, an embodiment of the present application further provides an instruction execution device, including:

[0012] a first instruction receiving unit, adapted to receive a first instruction, and determine whether the first instruction depends on a second instruction, the second instruction being an instruction received earlier than the first instruction and not yet executed;

[0013] A first instruction and second signal sending unit, adapted to send the first instruction to a first pipeline and send a second signal to a second pipeline when the first instruction depends on the second instruction; the second pipeline is a route for sending the second instruction, wherein the first pipeline includes a first dependent pipeline stage, the second pipeline includes a second dependent pipeline stage, and processing of the first instruction at the first dependent pipeline stage depends on processing of the second instruction at the second dependent pipeline stage;

[0014] The first dependent pipeline stage gate unit is suitable for judging whether the second signal enters the second dependent pipeline stage before the first instruction enters the first dependent pipeline stage for processing, and sending the first instruction to enter the first dependent pipeline stage if the second signal has entered the second dependent pipeline stage.

[0015] In a third aspect, an embodiment of the present application further provides a chip, comprising the instruction execution device as described in the second aspect.

[0016] In a fourth aspect, an embodiment of the present application further provides a computer device, comprising the chip as described in the third aspect.

[0017] The instruction execution method provided in the embodiment of the present application includes receiving a first instruction, determining whether the first instruction depends on a second instruction, the second instruction being an instruction received earlier than the first instruction and not yet executed; when the first instruction depends on the second instruction, sending the first instruction to a first pipeline, and sending a second signal to a second pipeline; the second pipeline is the route sent by the second instruction, wherein the first pipeline includes a first dependent pipeline stage, the second pipeline includes a second dependent pipeline stage, and the processing of the first instruction at the first dependent pipeline stage depends on the processing of the second instruction at the second dependent pipeline stage; before the first instruction enters the first dependent pipeline stage for processing, determining whether the second signal enters the second dependent pipeline stage, and if the second signal has entered the second dependent pipeline stage, sending the first instruction to enter the first dependent pipeline stage.

[0018] In this way, after determining that the first instruction and the second instruction have a dependency relationship and need to be executed in order (i.e., processing the first instruction depends on the completion of processing the second instruction), the embodiment of the present application does not immediately block the execution of the first instruction, but allows the first instruction to continue to be executed to the first dependent pipeline stage, thereby avoiding congestion of the first instruction, thereby improving the efficiency of the processor in processing data during order-preserving execution; after determining that the first instruction depends on the second instruction, a second signal is sent to the first pipeline instead of sending the address of the second instruction, thereby saving the number of wirings between each stage of the pipeline, thereby saving circuit area and reducing chip power consumption.

[0019] It can be seen that the instruction execution method provided in the embodiment of the present application can improve the efficiency in order-preserving execution while saving circuit area and reducing chip power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0021] Figure 1 A schematic diagram of an order-preserving execution;

[0022] Figure 2 A flowchart of the instruction execution method provided in the embodiment of the present application;

[0023] Figure 3 A pipeline diagram of the instruction execution method provided in an embodiment of the present application;

[0024] Figure 4Another flowchart of the instruction execution method provided in the embodiment of the present application;

[0025] Figure 5 A schematic diagram of an instruction execution device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] There are usually multiple pipelines in a processor. After the instruction is fetched, it can be decoded. The decoded instructions can be distributed to different pipelines according to the type of instruction to achieve concurrent execution of instructions. The execution order of instructions in the same pipeline can be sequential, and the execution order of instructions in different pipelines can be out of order (also known as out-of-order execution).

[0028] However, instructions between different pipelines may still have dependencies, where the execution of one pipeline requires the completion of the execution of another pipeline. For ease of understanding, let's take read instructions and write instructions as an example: read instructions will be distributed to the pipeline responsible for executing read instructions, and write instructions will be distributed to the pipeline responsible for executing write instructions. However, due to the requirements of write first and then read and read first and then write, the subsequent instructions in the two depend on the previous instructions, so read instructions and write instructions need to be executed strictly in order, that is, order-preserving execution.

[0029] To achieve order-preserving execution of instructions with dependencies, please refer to Figure 1 , Figure 1 A schematic diagram of order-preserving execution.

[0030] like Figure 1 As shown, before an instruction enters path 1 or path 2, a dependency check needs to be performed in the dependency check module, that is, before the instruction is distributed and executed, it is first determined whether the current instruction has a dependency relationship with the previous instruction.

[0031] The judgment method may be to judge the execution status of each recorded request. Specifically, before distributing each instruction, the execution status of each request is recorded. The execution status may be the register required for instruction execution and the usage status of the register; and after each instruction enters execution, the status update information returned by each instruction is received, and the execution status of the instruction is updated according to the information; for example, the register required for the instruction is updated. In this way, before distributing an instruction, the record of the execution status of the preceding instruction is read to determine whether the instruction to be distributed is dependent on a preceding instruction, for example, the current instruction and the preceding instruction need to use the same register (as shown in the figure, the dependency-related process of path 1 and the dependency-related process of path 2 can indicate that instruction 1 and instruction 2 use the same register in the related process).

[0032] If the dependency check module detects a dependency, it stops the pipeline at the detection point until the dependency is eliminated, for example, the previous instruction updates the status to show that the register is no longer needed.

[0033] Specifically, the above processing process can be implemented in hardware through the circuit in the processor.

[0034] In this way, since the pipeline is executed sequentially, it will affect the distribution of all subsequent instructions to the pipeline stage, reducing the processing efficiency of the circuit.

[0035] Therefore, how to improve the efficiency of processors in processing data during order-preserving execution has become a technical problem that technical personnel in this field need to solve urgently.

[0036] To solve the above technical problems, the present application provides an instruction execution method, please refer to Figure 2 ,

[0037] Figure 2 A flowchart of an instruction execution method provided in an embodiment of the present application.

[0038] As shown in the figure, the instruction execution method provided in the embodiment of the present application includes:

[0039] In step S11, a first instruction is received.

[0040] The first instruction may be any instruction waiting to be distributed to the pipeline for execution. In some embodiments, the first instruction may specifically be a read instruction or a write instruction.

[0041] It is worth noting that the pipeline referred to in this application refers to the pipelines to which instructions are distributed after fetching and decoding. Different pipelines are responsible for the execution of different types of instructions, thereby realizing the parallel execution of different types of instructions. The pipeline subdivides the instruction execution process into multiple execution steps, each execution step is responsible for a pipeline stage, and different pipeline stages of the same pipeline can execute different instructions, so multiple instructions can be executed simultaneously in the same pipeline (such as different pipeline stages of the same pipeline).

[0042] However, it is worth noting that different pipeline stages can only execute one instruction at the same time (or the same clock cycle), and each instruction in the same pipeline enters each pipeline stage in sequence, so each instruction in the pipeline has an execution order.

[0043] The subject receiving the first instruction may be an instruction distribution module responsible for distributing instructions to each pipeline for execution. In some embodiments, the instruction distribution module may be a circuit; in other embodiments, the instruction distribution module may also be program software. There is no restriction on the receiving subject, as long as the subject is responsible for distributing instructions to each pipeline for execution; there is no restriction on whether the subject implements the technical solution provided in this application in the form of hardware or software after receiving the first instruction.

[0044] In step S12, it is determined whether the first instruction depends on a second instruction, where the second instruction is an instruction received earlier than the first instruction and has not yet been executed; if the determination is yes, step S13 is executed; if the determination is no, step S17 is executed.

[0045] The second instruction may be any instruction that has been sent to the pipeline and is being executed. Therefore, in some embodiments, it is possible to determine whether there is a second instruction that is dependent on the first instruction by traversing and checking all instructions being executed.

[0046] The dependency means that the execution of the first instruction in a certain pipeline stage in a pipeline must be completed later than the execution of the second instruction in a certain pipeline stage in another pipeline due to some reason. The embodiment of the present application does not limit the specific reasons for such sequence restriction.

[0047] In order to determine the dependency, in a specific implementation, a first instruction state of the first instruction is recorded, the first instruction state including registers required to execute the first instruction, and based on the first instruction state and a pre-recorded second instruction state, it is determined whether the first instruction depends on the second instruction.

[0048] It is worth noting that the reason why the second instruction is required to be an instruction received earlier than the first instruction and not yet executed is that only the second instruction being executed can actually affect the execution of the first instruction. Although theoretically dependent on the first instruction, an instruction that has actually been executed when the first instruction makes a dependency judgment will not affect the execution of the first instruction. Therefore, it is necessary to exclude this part of instructions and limit the second instruction to instructions received earlier than the first instruction and not yet executed.

[0049] In step S13, the first instruction is sent to the first pipeline, and the second signal is sent to the second pipeline; the second pipeline is the route for the second instruction to be sent, wherein the first pipeline includes a first dependent pipeline stage, the second pipeline includes a second dependent pipeline stage, and the processing of the first instruction at the first dependent pipeline stage depends on the processing of the second instruction at the second dependent pipeline stage.

[0050] After determining that there is a second instruction that is dependent on the first instruction, a second signal is sent to a second pipeline that executes the second instruction, and the first instruction and the first signal are sent to the first pipeline.

[0051] The second pipeline refers to a pipeline that executes a second instruction, and the first pipeline refers to a pipeline that can execute a first instruction. Specifically, when the second instruction is a write instruction and the first instruction is a read instruction, the second pipeline is a write operation pipeline, responsible for executing all write instructions; the first pipeline is a read operation pipeline, responsible for executing all read instructions.

[0052] It is worth noting that the processing of data in the pipeline is usually based on a clock cycle as a time unit, that is, in each clock cycle, each pipeline stage in the pipeline will send data to the next stage, receive data from the previous stage, and complete the processing of the received data. Therefore, data will only be transmitted once in the pipeline in each clock cycle. Therefore, if a pipeline stage wants to transmit 22 bits of data (including all data such as control information and address) to the next pipeline stage, there must be at least 22 physical connections between the pipeline stage and the next pipeline stage for transmitting data, where each physical connection transmits one bit (0 or 1). Since there are many pipelines in the processor and different pipelines have many pipeline stages, reducing the bits occupied by the pipeline control information can greatly reduce the demand for physical connections in the integrated circuit, thereby reducing the space occupied by the connection and saving space in the integrated circuit. In addition, since the size of the data that needs to be transmitted each time the data is transmitted between pipeline stages is saved, the power consumption of the integrated circuit during operation is also reduced, which is more power-saving and environmentally friendly.

[0053] Therefore, the second signal of the embodiment of the present application can be implemented with fewer bits. In some embodiments, the second signal can occupy only 1 bit and only requires one physical connection, thereby reducing the space occupied by the integrated circuit.

[0054] It is worth noting that the first dependent pipeline stage and the second dependent pipeline stage are pipeline stages where dependency actually occurs, that is, the execution of the first instruction in the first dependent pipeline stage must be based on the premise that the second instruction is executed in the second dependent pipeline stage. For example: when the first instruction is a read instruction and the second instruction is a write instruction, the second dependent pipeline stage can be used for the write instruction to implement the step of writing data into the memory, and the first dependent pipeline stage can be used for the read instruction to implement the step of obtaining data from the memory. Before the second dependent pipeline stage, there can be a pipeline stage for obtaining the data to be written from the register, and before the first dependent pipeline stage, there can be a pipeline stage for obtaining the address where the data to be read is located from the register. It is worth noting that the out-of-order execution between the steps in the above different pipelines will not cause data processing errors, but it must be ensured that the second instruction in the second dependent pipeline stage is executed first (writing data into the memory), and then the first instruction in the first dependent pipeline stage reads data from the memory. Therefore, there may be many pipeline stages in the pipeline, but the number of pipeline stages that can be used as the first dependent pipeline stage or the second dependent pipeline stage is relatively small, and usually there is only one pipeline.

[0055] To facilitate understanding of the process of sending the second signal, an example is given for specific explanation: assuming that the second instruction is a write instruction, bits 0-9 of the instruction are address bits, used to indicate a register, which stores a memory address, and the memory space indicated by the memory address is the memory space for writing the data to be written; bits 10-19 of the instruction are data bits, used to indicate another register, which stores the data to be written. Then there can be 21 physical connections in the second pipeline, of which physical connections 0-19 are used to transmit address bits and data bits, and physical connection No. 20 is used to transmit the second signal. When the bit transmitted by physical connection No. 20 is "0", the second pipeline performs data write operations according to bits 0-19; and when the bit transmitted by physical connection No. 20 is "1", each pipeline stage in the second pipeline does not perform any operation on bits 0-20, and only passes them to the next pipeline stage in the next cycle until they are passed to the second dependent pipeline stage. For example, when sending the second instruction, 000110011001110110011 may be sent to the second pipeline, and when sending the second signal, 0000000000000000000 may be sent to the second pipeline.

[0056] In step S14, before the first instruction enters the first dependent pipeline stage for processing, it is determined whether the second signal has entered the second dependent pipeline stage; if it is determined to be yes, step S15 is executed; if it is determined to be no, step S16 is executed.

[0057] Since the processing of instructions in the second pipeline is performed in sequence, and the second signal is sent to the second pipeline later than the second instruction, when the second signal enters the second dependent pipeline stage, the second instruction must have been executed in the second pipeline stage and entered the next pipeline stage. Of course, it is not necessary to know how long ago the second instruction was executed in the second pipeline stage.

[0058] Therefore, when the second signal enters the second dependent pipeline stage, it indicates that the first instruction can enter the first dependent pipeline stage for execution.

[0059] In a specific implementation, an embodiment of the present application provides a method for determining whether the second signal enters a second dependent pipeline stage in an instruction execution method, the method comprising:

[0060] Before the first instruction enters the first dependent pipeline stage, checking the number of the second signal entering the second dependent pipeline stage;

[0061] Whether the second signal enters the second dependent pipeline stage is determined based on the pre-recorded number of the second signals of the second dependent pipeline stage and the number of the second signals checked before the first instruction enters the first pipeline stage.

[0062] It is worth noting that computers usually process instructions continuously, so they may process multiple groups of first instructions and corresponding second instructions one after another in time. When processing each group of first instructions, a second signal will be sent in the second dependent pipeline stage. By recording the total number of second signals that reach the second dependent pipeline stage, it is possible to know the number of second signals that have entered the second dependent pipeline stage before processing the current first instruction. Therefore, before the current instruction enters the first pipeline stage, it is possible to check whether the recorded number is increased by one. If it is not increased by one, it means that the second signal has not yet reached the second dependent pipeline stage, otherwise it has arrived.

[0063] Since the computer operation process is the process of continuously executing instructions, and each instruction may be dependent on other instructions, the second pipeline stage may have received multiple second signals.

[0064] In order to facilitate recording the number of the second signal, in a specific implementation, please refer to Figure 3 , Figure 3A pipeline diagram of the instruction execution method provided in the embodiment of the present application. As shown in the figure, the instruction execution method provided in the embodiment of the present application can increase the value of the counter associated with the second dependent pipeline stage by one when the second signal enters the second dependent pipeline stage, and the initial value of the counter is zero.

[0065] As shown in the figure, in the device for executing the instruction execution method provided by the embodiment of the present application, a counter for counting the number of second signals can be set. The plus signal input terminal of the counter is connected to the second dependent pipeline stage. In this way, when the second signal enters the second dependent pipeline stage, the second dependent pipeline stage can send an plus signal to the counter to add one to the value in the counter, thereby realizing the recording of the number of the second signals entering the second dependent pipeline stage.

[0066] It is worth noting that, as described above, not every pipeline stage is dependent, and the number of second dependent pipeline stages in the second pipeline is limited, usually only one, so usually only one counter needs to be set.

[0067] In this way, by setting a counter associated with the second dependent pipeline stage, the entry into the second dependent pipeline stage can be recorded conveniently and quickly in a hardware manner.

[0068] In this way, by recording the total number of the second signals entering the second dependent pipeline stage and the number of the second signals entering the second dependent pipeline stage before the first instruction enters the first dependent pipeline stage, it is possible to compare the two to determine whether the sent second signal reaches the second dependent pipeline stage. In some embodiments, it is possible to determine whether the second signal has reached the second dependent pipeline stage by determining whether the number of recorded second signals has increased.

[0069] In step S15, the first instruction is sent to the first dependent pipeline stage.

[0070] The first instruction is sent to the first dependent pipeline stage, and the steps of the first instruction that the first dependent pipeline stage is responsible for are executed in the first dependent pipeline stage.

[0071] In step S16, the execution of the first pipeline is stopped.

[0072] While stopping the execution of the first pipeline stage, step S14 is re-executed until the result of the determination in step S14 is yes.

[0073] In step S17, end.

[0074] When it is determined that there is no second instruction, or after it is determined that there is a second instruction, the above steps S13-S15 have been implemented, and the execution of the first instruction has been achieved, then the process can be ended. Of course, the end of the process does not mean that the first instruction will not be executed, but it means that the subsequent operations on the first instruction will continue, and the above steps S11-S15 will no longer be considered.

[0075] In this way, after determining that the first instruction and the second instruction have a dependency relationship and need to be executed in order (i.e., the second instruction must be executed before the first instruction), the execution of the first instruction is not immediately blocked, but allowed to continue to the first dependent pipeline stage, avoiding the blockage of the first instruction, thereby improving the efficiency of the processor in processing data during order-preserving execution; after determining that the first instruction depends on the second instruction, a second signal of only 1 bit is sent to the first pipeline instead of sending the address of the second instruction of several bits, thereby saving the number of wirings between each stage of the pipeline, thereby saving circuit area and reducing chip power consumption.

[0076] The present application also provides a method for executing an instruction. Figure 4 , Figure 4 Another flowchart of the instruction execution method provided in an embodiment of the present application.

[0077] As shown in the figure, the instruction execution method provided in the embodiment of the present application includes:

[0078] In step S21, a first instruction is received.

[0079] In step S22, it is determined whether the first instruction depends on a second instruction, where the second instruction is an instruction received earlier than the first instruction and has not yet been executed; if the determination is yes, step S23 is executed; if the determination is no, step S28 is executed.

[0080] For the related description of step S21-step S22, please refer to the description of step S11-step S12, which will not be repeated here.

[0081] In step S23, the first signal is sent to the first pipeline, the first signal occupies 1 bit; the first instruction is sent to the first pipeline, and the second signal is sent to the second pipeline; the second pipeline is the route for the second instruction to be sent, wherein the first pipeline includes a first dependent pipeline stage, the second pipeline includes a second dependent pipeline stage, and the processing of the first instruction at the first dependent pipeline stage depends on the processing of the second instruction at the second dependent pipeline stage.

[0082] For the relevant description of step S23, please refer to the description of step S13, which will not be repeated here.

[0083] However, what is different from step S13 is that in step S23, the first signal is also sent to the first pipeline, and the first signal occupies 1 bit.

[0084] It is worth noting that the first signal and the first instruction are sent to the first pipeline in the same cycle, while the second signal and the second instruction are sent to the second pipeline in different cycles. This is because the second signal is sent when the first instruction is distributed, and the second instruction is sent before the first instruction.

[0085] For ease of understanding, here are some examples:

[0086] Assume that the first instruction is a read instruction, bits 0-9 of the instruction are address bits, used to indicate a register, which stores a memory address, and the memory space indicated by the memory address is the memory space for reading the data to be read; bits 10-19 of the instruction are address bits, used to indicate another register, which is used to store the data to be read. Then there can be 21 physical connections in the second pipeline, of which physical connections 0-19 are used to transmit address bits, and physical connection No. 20 is used to transmit the first signal. When the transmission bit of physical connection No. 20 is "0", the second pipeline performs data reading operations according to bits 0-19; and when the transmission bit of physical connection No. 20 is "1", step S25 is executed.

[0087] For example, when sending the first instruction and the first signal, 100110011001110110011 can be sent to the first pipeline.

[0088] In step S24, before the first instruction enters the first dependent pipeline stage, it is determined whether a first signal is received when the first instruction is received; if the determination is yes, step S25 is executed, and if the determination is no, step S28 is executed.

[0089] It is worth noting that when determining whether the first instruction is dependent on the second instruction in step S22, if the determination is no, step S28 will be executed and the process will end. The end of step S28 does not mean that the first instruction will not be executed, but that steps S23-S27 will no longer be executed on the first instruction. Therefore, the first instruction that is determined to have no dependency may also be sent to the first dependency pipeline stage, that is, in addition to the first instruction that has a dependency relationship, the first dependency pipeline stage also has the first instruction that is determined to have no dependency relationship in step S22.

[0090] Therefore, the above-mentioned different first instructions can be distinguished in the first pipeline, so that for the first instruction judged to be yes in step S22, subsequent steps S24-step S28 are executed (step S23 is executed before being sent to the first pipeline, and is not executed in the first pipeline), and it can be determined whether the first signal is received at the same time as the first instruction is received. Specifically, before the first instruction enters the first dependent pipeline stage, when checking whether the first signal is received, if it is checked that the first signal is received, it means that the instruction accompanying the first signal is a first instruction that depends on the second instruction; when the first signal is not received and sent at the same time as the first instruction, it can be determined that the first instruction is an instruction that is judged to have no dependency relationship in step S22, so that step S28 is executed, and steps S24-step S27 are not executed for the first instruction.

[0091] In some embodiments, a pipeline stage may be set before the first dependent pipeline stage to be responsible for determining whether the first signal is received. Specifically, it may be set at a stage immediately before the first dependent pipeline stage, such as Figure 3 The dependency count checking pipeline stage shown may specifically be a circuit responsible for dependency count checking, such as a dependency count checking module.

[0092] In step S25, before the first instruction enters the first dependent pipeline stage, determine whether the number of the second signals entering the second dependent pipeline stage is greater than the number of records of the first signals entering the first dependent pipeline stage; if so, execute step S26; if not, execute step S27.

[0093] In some embodiments, by pre-recording the number of first signal records of the first signal entering the first dependent pipeline stage and recording the number of second signal records of the second signal entering the second dependent pipeline stage, the number of first signal records and the number of second signal records can be checked before the first instruction enters the first dependent pipeline stage, and the number of records of the first signal entering the first dependent pipeline stage can be determined by judging the size of the number of first signal records and the number of second signal records.

[0094] In order to more quickly determine whether the first instruction is executed at the first dependent pipeline stage when the computer frequently processes instructions, in a specific implementation, please continue to refer to Figure 3 .

[0095] As shown in the figure, the instruction execution method provided in the embodiment of the present application, based on the illustrated structure, may include: checking the count value in the counter to determine whether the count value is greater than zero; the counter is associated with the first dependent pipeline stage and the second dependent pipeline stage, and is suitable for reducing the count value by one when the first signal enters the first dependent pipeline stage, and increasing the count value by one when the second signal enters the second dependent pipeline stage.

[0096] Specifically, the counter may be connected to the first dependent pipeline stage via a subtraction signal terminal, and connected to the second dependent pipeline stage via a addition signal terminal.

[0097] In this way, when the first signal enters the first dependent pipeline stage, the first dependent pipeline stage will send it to the counter, and the counter will receive the first signal and the count value will decrease by one; when the second signal enters the second dependent pipeline stage, it will be sent to the counter, and the counter will receive the second signal and the count value will increase by one. In this way, after a group of dependent and dependent first instructions and second instructions are executed, the counter is reset to 0. Based on whether the counter is 0, it can be determined whether the first instruction has been executed in the first dependent pipeline stage, so that when the computer frequently processes instructions, the subsequent instructions can be judged in the same steps.

[0098] For ease of understanding, let's take an example from the starting state:

[0099] First, in the initial state after the computer is started, since there is no first signal and no second signal, the counter is 0.

[0100] Afterwards, the computer obtains the write instruction, and uses the write instruction as the first instruction to search for dependencies before distributing the pipeline. It does not find the second instruction that the write instruction depends on, so it is directly sent to the second pipeline (write operation pipeline).

[0101] Afterwards, the computer obtains the read instruction, and uses the read instruction as the first instruction to search for dependencies before distributing the pipeline. After checking, it is found that it depends on the above-mentioned write instruction, that is, the above-mentioned write instruction is the second instruction. For the convenience of description, in this example, the following description will refer to the write instruction as the second instruction and the read instruction as the first instruction.

[0102] Therefore, when the computer sends the first instruction to the first pipeline stage (read operation pipeline stage), it also sends the first signal to the first pipeline stage and the second signal to the second pipeline stage.

[0103] When the first instruction is executed through the levels and completes the execution of the previous pipeline stage of the first dependent pipeline stage, the computer needs to determine whether it can enter the first dependent pipeline stage, that is, to determine whether the second instruction has been executed in the second dependent pipeline stage of the second pipeline. Therefore, the computer checks the counters associated with the first dependent pipeline stage and the second dependent pipeline stage at the same time. The plus signal end of the counter is associated with the second dependent pipeline stage, and the minus signal end is associated with the first dependent pipeline stage. When the first dependent pipeline stage receives the first signal, the counter will be reduced by one, and when the second dependent pipeline stage receives the second signal, the counter will be increased by one.

[0104] If the count value of the counter is 0, it means that the second signal has not entered the second dependent pipeline stage (because the second signal will add one to the counter when entering the second dependent pipeline stage). At this time, it is assumed that the second signal has not been executed in the second dependent pipeline stage, so the first instruction waits until the value of the counter is not 0; if the value of the counter is not 0, it means that the second signal has entered the second dependent pipeline stage. The second signal enters the second path later than the second instruction, so it must be slower than the second instruction. Therefore, when the second signal enters the second dependent pipeline stage, it means that the second instruction must have been executed in the second dependent pipeline stage and sent from the second dependent pipeline stage to the next pipeline stage, so the first instruction can enter the first dependent pipeline stage.

[0105] When the first instruction enters the first dependent pipeline stage, the first signal also enters the first dependent pipeline stage at the same time. After the first signal enters the first dependent pipeline stage, the count value in the counter is reduced by one, so the counter becomes 0 again.

[0106] It can be seen that, through the above counter method, each time a group of first instructions and second instructions are executed, the counter can be reset to 0, so that when subsequent instructions have dependencies again, the same steps can be used to implement the judgment. Therefore, when the computer frequently processes instructions, it can be more quickly determined whether the first instruction is executed in the first dependent pipeline stage.

[0107] In step S26, the first instruction is sent to the first dependent pipeline stage.

[0108] In step S27, the execution of the first pipeline is stopped.

[0109] In step S28, end.

[0110] For the related description of steps S26 to S28, please refer to the description of steps S15 to S17, which will not be repeated here.

[0111] In a specific embodiment, the first pipeline includes multiple first dependent pipeline stages, the second pipeline includes multiple second dependent pipeline stages, the first dependent pipeline stages and the second dependent pipeline stages correspond to each other in pairs to form a group of pipeline stages, and multiple counters are set, and each group of pipeline stages is associated with a counter in a one-to-one correspondence.

[0112] Of course, it is not ruled out that there may be multiple second dependent pipeline stages in the second pipeline. In this case, there also needs to be multiple counters, and each counter is only connected to one second pipeline stage, thereby only recording the number of second signals entering one second pipeline stage.

[0113] Of course, the first signals received by different first dependent pipeline stages are different. Specifically, by adding physical connections, the first signals transmitted by different physical lines correspond to different first dependent pipeline stages. For example, when the first pipeline has three first dependent pipeline stages, the three physical lines correspond to the three dependent pipeline stages respectively. In this way, through the three changes of 001, 010 and 100, it can be clearly distinguished which first dependent pipeline stage the first signal belongs to. The processing of the second signal and the second pipeline stage is similar.

[0114] In this way, each group of first dependent pipeline stages and second dependent pipeline stages can implement the technical solution provided in the embodiment of the present application without affecting each other.

[0115] It is worth noting that each pipeline may be the first pipeline or the second pipeline, or it may be the first pipeline and the second pipeline at the same time. For example, there are three pipelines a, b, and c. In the group ab, a is the first pipeline and b is the second pipeline; in the group ac, a is the second pipeline and c is the first pipeline; in the group bc, b is the first pipeline and c is the second pipeline. The same is true for other pipeline stages.

[0116] Of course, when a pipeline can be both the first pipeline and the second pipeline, the pipeline needs to have at least two physical connections at the same time, respectively transmitting the first signal and the second signal.

[0117] To solve the above problems, the present application also provides an instruction execution device, please refer to Figure 5 , Figure 5 A schematic diagram of an instruction execution device provided in an embodiment of the present application.

[0118] As shown in the figure, the instruction execution device provided in the embodiment of the present application includes:

[0119] A first instruction receiving unit 1, adapted to receive a first instruction, and determine whether the first instruction depends on a second instruction, the second instruction being an instruction received earlier than the first instruction and not yet executed;

[0120] A first instruction and second signal sending unit 2, adapted to send the first instruction to a first pipeline and send a second signal to a second pipeline when the first instruction depends on the second instruction; the second pipeline is a route sent by the second instruction, wherein the first pipeline includes a first dependent pipeline stage, the second pipeline includes a second dependent pipeline stage, and the processing of the first instruction at the first dependent pipeline stage depends on the processing of the second instruction at the second dependent pipeline stage;

[0121] The first dependent pipeline stage gate unit 3 is suitable for judging whether the second signal enters the second dependent pipeline stage before the first instruction enters the first dependent pipeline stage for processing, and sending the first instruction to enter the first dependent pipeline stage if the second signal has entered the second dependent pipeline stage.

[0122] It can be seen that the instruction execution device provided in the embodiment of the present application can improve the efficiency in order-preserving execution while saving circuit area and reducing chip power consumption.

[0123] In a specific implementation manner, in the instruction execution device provided in the embodiment of the present application, the first dependent pipeline stage gate unit 3 is adapted to determine whether the second signal enters the second dependent pipeline stage before the first instruction enters the first dependent pipeline stage for processing, including:

[0124] Before the first instruction enters the first dependent pipeline stage, checking the number of second signals entering the second dependent pipeline stage;

[0125] Whether the second signal enters the second dependent pipeline stage is determined based on the pre-recorded number of second signals of the second dependent pipeline stage and the checked number of second signals.

[0126] In a specific implementation, the instruction execution device provided in the embodiment of the present application further includes:

[0127] A first signal sending unit 4, adapted to send a first signal to the first pipeline when the first instruction depends on the second instruction, the first signal occupying 1 bit;

[0128] The first dependency pipeline stage gate unit 3 is adapted to determine whether the second signal has entered the second dependency pipeline stage before the first instruction enters the first dependency pipeline stage for execution, and if the second signal has entered the second dependency pipeline stage, send the first instruction to enter the first dependency pipeline stage, including:

[0129] Before the first instruction enters the first dependent pipeline stage for processing, determining whether the number of second signals that have entered the second dependent pipeline stage is greater than the number of first signals that have entered the first dependent pipeline stage;

[0130] When the number of the second signals that have entered the second dependent pipeline stage is greater than the number of the first signals that have entered the first dependent pipeline stage, the first instruction is sent to enter the first dependent pipeline stage.

[0131] In a specific embodiment, the instruction execution device provided by the embodiment of the present application, the first dependent pipeline stage gate unit 3 is adapted to determine whether the number of second signals that have entered the second dependent pipeline stage is greater than the number of first signals that have entered the first dependent pipeline stage before the first instruction enters the first dependent pipeline stage for processing, including:

[0132] Checking the count value in the counter to determine whether the count value is greater than zero;

[0133] The counter is associated with the first dependent pipeline stage and the second dependent pipeline stage, and is adapted to decrease a count value by one when the first signal enters the first dependent pipeline stage, and increase a count value by one when the second signal enters the second dependent pipeline stage.

[0134] In a specific embodiment, the instruction execution device provided in the embodiment of the present application, the first dependent pipeline stage gate unit 3 is also suitable for checking whether a first signal is received before the step of checking the count value in the counter, and if the first signal is received, triggering the execution of the step of checking the count value in the counter.

[0135] In a specific embodiment, the instruction execution device provided in the embodiment of the present application, the first instruction receiving unit 1, the first instruction and second signal sending unit 2 and the first signal sending unit 4 are arranged in the dependency checking module (shown in Figure 3 ), the first dependent pipeline stage gate unit 3 is arranged in the dependent count checking module.

[0136] To solve the aforementioned problem, an embodiment of the present application further provides a chip, comprising the instruction execution device as described above.

[0137] An embodiment of the present invention further provides a computer device, comprising the chip as described above.

[0138] It can be seen that the chip and electronic device provided in the embodiments of the present application can improve efficiency in order-preserving execution while saving circuit area and reducing chip power consumption.

[0139] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0140] The above describes multiple implementation schemes provided by the embodiments of the present invention. The various optional methods introduced in each implementation scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present invention.

[0141] Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for executing an instruction, characterized in that: include: receiving a first instruction, and determining whether the first instruction depends on a second instruction, where the second instruction is an instruction received earlier than the first instruction and has not yet been executed; When the first instruction depends on the second instruction, the first instruction is sent to a first pipeline, and a second signal is sent to a second pipeline; the first pipeline is a pipeline for executing the first instruction, and the second pipeline is a route for sending the second instruction, wherein the first pipeline includes a first dependent pipeline stage, the second pipeline includes a second dependent pipeline stage, and the processing of the first instruction at the first dependent pipeline stage depends on the processing of the second instruction at the second dependent pipeline stage; Before the first instruction enters the first dependent pipeline stage for processing, it is determined whether the second signal has entered the second dependent pipeline stage; if the second signal has entered the second dependent pipeline stage, the first instruction is sent to enter the first dependent pipeline stage.

2. The instruction execution method according to claim 1, characterized in that: Before the first instruction enters the first dependent pipeline stage for processing, determining whether the second signal enters the second dependent pipeline stage includes: Before the first instruction enters the first dependent pipeline stage, checking the number of second signals entering the second dependent pipeline stage; Whether the second signal enters the second dependent pipeline stage is determined based on the pre-recorded number of second signals of the second dependent pipeline stage and the checked number of second signals.

3. The instruction execution method according to claim 2, characterized in that: The checking the number of second signals entering the second dependent pipeline stage includes: When the second signal enters the second dependent pipeline stage, the value of the counter associated with the second dependent pipeline stage is increased by one, and the initial value of the counter is zero.

4. The instruction execution method according to any one of claims 1 to 3, characterized in that: The second signal occupies 1 bit.

5. The instruction execution method according to claim 1, characterized in that: Also includes: When the first instruction depends on the second instruction, sending a first signal to the first pipeline, where the first signal occupies 1 bit; Before the first instruction enters the first dependent pipeline stage for execution, determining whether the second signal enters the second dependent pipeline stage, and if the second signal has entered the second dependent pipeline stage, sending the first instruction to enter the first dependent pipeline stage, comprises: Before the first instruction enters the first dependent pipeline stage for processing, determining whether the number of second signals that have entered the second dependent pipeline stage is greater than the number of first signals that have entered the first dependent pipeline stage; When the number of the second signals that have entered the second dependent pipeline stage is greater than the number of the first signals that have entered the first dependent pipeline stage, the first instruction is sent to enter the first dependent pipeline stage.

6. The instruction execution method according to claim 5, characterized in that: The determining, before the first instruction enters the first dependent pipeline stage for processing, whether the number of second signals that have entered the second dependent pipeline stage is greater than the number of first signals that have entered the first dependent pipeline stage comprises: Checking the count value in the counter to determine whether the count value is greater than zero; The counter is associated with the first dependent pipeline stage and the second dependent pipeline stage, and is adapted to decrease a count value by one when the first signal enters the first dependent pipeline stage, and increase a count value by one when the second signal enters the second dependent pipeline stage.

7. The instruction execution method according to claim 6, characterized in that: Before the step of checking the count value in the counter, the method further comprises: Check whether the first signal is received, and if the first signal is received, trigger the step of checking the count value in the counter.

8. The instruction execution method according to claim 6, characterized in that: The first pipeline includes a plurality of first dependent pipeline stages, the second pipeline includes a plurality of second dependent pipeline stages, and the first dependent pipeline stages and the second dependent pipeline stages correspond to each other one by one to form a group of pipeline stages; Each group of pipeline stages is associated with a counter in a one-to-one correspondence.

9. The instruction execution method according to claim 1, characterized in that: The determining whether the first instruction depends on the second instruction includes: Record a first instruction state of the first instruction, where the first instruction state includes registers required to execute the first instruction; and determine whether the first instruction depends on the second instruction based on the first instruction state and a pre-recorded second instruction state.

10. The instruction execution method according to claim 1, characterized in that: The first instruction is a read instruction, and the second instruction is a write instruction.

11. An instruction execution device, characterized in that: include: a first instruction receiving unit, adapted to receive a first instruction, and determine whether the first instruction depends on a second instruction, the second instruction being an instruction received earlier than the first instruction and not yet executed; A first instruction and second signal sending unit, adapted to send the first instruction to a first pipeline and send a second signal to a second pipeline when the first instruction depends on the second instruction; the first pipeline is a pipeline for executing the first instruction, and the second pipeline is a route for sending the second instruction, wherein the first pipeline includes a first dependent pipeline stage, the second pipeline includes a second dependent pipeline stage, and the processing of the first instruction at the first dependent pipeline stage depends on the processing of the second instruction at the second dependent pipeline stage; The first dependent pipeline stage gate unit is suitable for judging whether the second signal enters the second dependent pipeline stage before the first instruction enters the first dependent pipeline stage for processing, and sending the first instruction to enter the first dependent pipeline stage if the second signal has entered the second dependent pipeline stage.

12. The instruction execution device according to claim 11, characterized in that: The first dependent pipeline stage gate unit is adapted to determine whether the second signal enters the second dependent pipeline stage before the first instruction enters the first dependent pipeline stage for processing, including: Before the first instruction enters the first dependent pipeline stage, checking the number of second signals entering the second dependent pipeline stage; Whether the second signal enters the second dependent pipeline stage is determined based on the pre-recorded number of second signals of the second dependent pipeline stage and the checked number of second signals.

13. The instruction execution device according to claim 11, characterized in that: Also includes: a first signal sending unit, adapted to send a first signal to the first pipeline when the first instruction depends on the second instruction, the first signal occupying 1 bit; The first dependent pipeline stage gate unit is adapted to determine whether the second signal has entered the second dependent pipeline stage before the first instruction enters the first dependent pipeline stage for execution, and if the second signal has entered the second dependent pipeline stage, send the first instruction to enter the first dependent pipeline stage, including: Before the first instruction enters the first dependent pipeline stage for processing, determining whether the number of second signals that have entered the second dependent pipeline stage is greater than the number of first signals that have entered the first dependent pipeline stage; When the number of the second signals that have entered the second dependent pipeline stage is greater than the number of the first signals that have entered the first dependent pipeline stage, the first instruction is sent to enter the first dependent pipeline stage.

14. The instruction execution device according to claim 13, characterized in that: The first dependent pipeline stage gate unit is adapted to determine whether the number of second signals that have entered the second dependent pipeline stage is greater than the number of first signals that have entered the first dependent pipeline stage before the first instruction enters the first dependent pipeline stage for processing, including: Checking the count value in the counter to determine whether the count value is greater than zero; The counter is associated with the first dependent pipeline stage and the second dependent pipeline stage, and is adapted to decrease a count value by one when the first signal enters the first dependent pipeline stage, and increase a count value by one when the second signal enters the second dependent pipeline stage.

15. The instruction execution device according to claim 14, characterized in that: The first dependent pipeline stage gate unit is further adapted to check whether a first signal is received before the step of checking the count value in the counter, and if the first signal is received, trigger the step of checking the count value in the counter.

16. The instruction execution device according to any one of claims 13 to 15, characterized in that: The first instruction receiving unit, the first instruction and second signal sending unit and the first signal sending unit are arranged in a dependency checking module; and the first dependency pipeline stage gate unit is arranged in a dependency count checking module.

17. A chip, characterized in that: The method comprises an instruction execution device as claimed in any one of claims 11 to 16.

18. A computer device, characterized in that: Comprising the chip as claimed in claim 17.

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