Power circuit and chip

Abstract

The present disclosure provides a power supply circuit and chip. The power supply circuit includes: a power switch, the power switch includes a control end, and the power switch is configured to be controlled to turn on or off the power supply and the load; a drive circuit, the drive circuit is coupled to the control end of the power switch, and the drive circuit is configured to control the potential of the control end of the power switch to control the turning on or off of the power switch; wherein, during the process of the power switch being turned on, the potential establishment rate of the control end of the power switch in the first stage is greater than the potential establishment rate in the second stage, and the first stage is earlier than the second stage. Since the power switch is turned on at a slow rate in the second stage, the peak current when the power switch is turned on is reduced, thereby improving the stability of the power supply circuit. At the same time, since the potential establishment rate of the control end of the power switch is fast in the first stage, the time required for the power switch to be turned on is reduced, thereby improving the reliability of the power supply circuit.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a power supply circuit and a chip. Background Art

[0002] In semiconductor chips, multiple voltage domains are used to supply power to loads to reduce power consumption of the chip. However, when a power circuit in a voltage domain is switched from an idle state to an operating state, there is a problem of low stability. Summary of the invention

[0003] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

[0004] The present disclosure provides a power circuit and a chip.

[0005] According to a first aspect of an embodiment of the present disclosure, there is provided a power supply circuit, the power supply circuit comprising:

[0006] A power switch, the power switch comprising a control terminal, the power switch being configured to be controlled to switch on or off between a power source and a load;

[0007] a driving circuit, the driving circuit being coupled to the control terminal of the power switch, the driving circuit being configured to control the potential of the control terminal of the power switch to control the on or off of the power switch;

[0008] Wherein, during the conduction of the power switch, the potential establishment rate of the control end of the power switch in the first stage is greater than the potential establishment rate in the second stage, and the first stage is earlier than the second stage.

[0009] According to some embodiments of the present disclosure, the power switch includes a first P-type transistor, and the driving circuit includes:

[0010] A first inverter group, a second inverter group, a first gating circuit and a second gating circuit, wherein the first inverter group includes a plurality of first inverters connected in series, the second inverter group includes a plurality of second inverters connected in series, the first inverter and the first gating circuit are coupled in series between a first node and a gate of the first P-type transistor, the second inverter and the second gating circuit are coupled in series between the first node and the gate of the first P-type transistor, the first node receives an enable signal, the first gating circuit is switched on or off according to a first control signal and an inverted signal of the first control signal, and the second gating circuit is switched on or off according to a second control signal and an inverted signal of the second control signal;

[0011] The channel width-to-length ratio of the first N-type transistor in the first inverter closest to the first P-type transistor in the first inverter group is greater than the channel width-to-length ratio of the second N-type transistor in the second inverter closest to the first P-type transistor in the second inverter group.

[0012] According to some embodiments of the present disclosure, during the process of turning on the first P-type transistor, the first gating circuit is enabled before the second gating circuit and the gating times of the first gating circuit and the second gating circuit are staggered.

[0013] According to some embodiments of the present disclosure, the number of the first inverters and the number of the second inverters are both odd numbers.

[0014] According to some embodiments of the present disclosure, the first gating circuit includes a first transmission gate, the first transmission gate and the first inverter are coupled in series between the first node and the gate of the first P-type transistor;

[0015] The second gating circuit includes a second transmission gate, and the second transmission gate and the second inverter are coupled in series between the first node and the gate of the first P-type transistor.

[0016] According to some embodiments of the present disclosure, the first transmission gate and the second transmission gate each include a first control end and a second control end, the first control end of the first transmission gate receives the first control signal, the second control end of the first transmission gate receives an inverted signal of the first control signal, the first control end of the second transmission gate receives the second control signal, and the second control end of the second transmission gate receives an inverted signal of the second control signal.

[0017] According to some embodiments of the present disclosure, the first control signal and the second control signal are in anti-phase.

[0018] According to some embodiments of the present disclosure, the power supply includes a first power supply, a first end of the first P-type transistor is coupled to the first power supply, and a second end of the first P-type transistor is coupled to the load.

[0019] According to some embodiments of the present disclosure, the power switch includes a third N-type transistor, and the driving circuit includes:

[0020] A third inverter group, a fourth inverter group, a third gating circuit and a fourth gating circuit, wherein the third inverter group includes a plurality of third inverters connected in series, the fourth inverter group includes a plurality of fourth inverters connected in series, the third inverter and the third gating circuit are coupled in series between a first node and a gate of the third N-type transistor, the fourth inverter and the fourth gating circuit are coupled in series between the first node and the gate of the third N-type transistor, the first node receives an enable signal, the third gating circuit is switched on or off according to a first control signal and an inverted signal of the first control signal, and the fourth gating circuit is switched on or off according to a second control signal and an inverted signal of the second control signal;

[0021] The channel width-to-length ratio of the second P-type transistor in the third inverter closest to the third N-type transistor in the third inverter group is greater than the channel width-to-length ratio of the third P-type transistor in the fourth inverter closest to the third N-type transistor in the fourth inverter group.

[0022] According to some embodiments of the present disclosure, during the process of turning on the third N-type transistor, the third gating circuit is enabled before the fourth gating circuit and the gating times of the third gating circuit and the fourth gating circuit are staggered.

[0023] According to some embodiments of the present disclosure, the number of the third inverters and the number of the fourth inverters are both even numbers.

[0024] According to some embodiments of the present disclosure, the third gating circuit includes a third transmission gate, wherein the third transmission gate and the third inverter are coupled in series between the first node and the gate of the third N-type transistor;

[0025] The fourth gating circuit includes a fourth transmission gate, and the fourth transmission gate and the fourth inverter are coupled in series between the first node and the gate of the third N-type transistor.

[0026] According to some embodiments of the present disclosure, the third transmission gate and the fourth transmission gate each include a first control end and a second control end, the first control end of the third transmission gate receives the first control signal, the second control end of the third transmission gate receives an inverted signal of the first control signal, the first control end of the fourth transmission gate receives the second control signal, and the second control end of the fourth transmission gate receives an inverted signal of the second control signal.

[0027] According to some embodiments of the present disclosure, the power supply includes a second power supply, a first terminal of the third N-type transistor is coupled to the load, and a second terminal of the third N-type transistor is coupled to the second power supply.

[0028] According to some embodiments of the present disclosure, the power supply circuit further includes:

[0029] A control signal generating circuit is used to generate the first control signal and the second control signal according to the enable signal, and the first control signal and the second control signal are inverted signals to each other.

[0030] According to some embodiments of the present disclosure, the control signal generating circuit includes:

[0031] A delay circuit, wherein an input end of the delay circuit receives the enable signal and is used to delay the enable signal for a preset time;

[0032] A logic gate circuit is configured to perform a logic operation on the enable signal and the output signal of the delay circuit to generate the first control signal, wherein a pulse width of the first control signal is the same as the preset time.

[0033] According to some embodiments of the present disclosure, the control signal generating circuit further includes:

[0034] a fifth inverter, wherein an input terminal of the fifth inverter receives the first control signal, and an output terminal of the fifth inverter outputs an inverted signal of the first control signal;

[0035] a sixth inverter, wherein an input terminal of the sixth inverter receives an inverted signal of the first control signal, and an output terminal of the sixth inverter outputs an inverted signal of the second control signal;

[0036] A seventh inverter, wherein an input terminal of the seventh inverter receives an inverted signal of the second control signal, and an output terminal of the seventh inverter outputs the second control signal.

[0037] A second aspect of the present disclosure provides a chip, wherein the chip includes the power supply circuit as described above.

[0038] In the power supply circuit and chip provided in the embodiments of the present disclosure, the power supply circuit includes a power switch and a drive circuit, and the power switch is coupled to the drive circuit. The potential of the control end of the power switch is controlled by the drive circuit to control the power switch to be turned on or off, so that the power supply supplies power to the load or stops supplying power. When the power supply circuit is converted from an idle state to a working state, the drive circuit establishes the potential of the control end of the power switch at a rate that is first fast and then slow, and slowly turns on the power switch in the second stage. Since the power switch is turned on at a slow rate, the peak current when the power switch is turned on is reduced, thereby improving the stability of the power supply circuit. At the same time, since the potential establishment rate of the control end of the power switch is fast in the first stage, the time required for the power switch to be turned on is reduced, thereby improving the reliability of the power supply circuit.

[0039] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings incorporated into the specification and constituting a part of the specification illustrate embodiments of the present disclosure and are used together with the description to explain the principles of the embodiments of the present disclosure. In these drawings, similar reference numerals are used to represent similar elements. The drawings described below are some embodiments of the present disclosure, rather than all embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1 is a structural schematic diagram of a power supply circuit according to an example;

[0042] Figure 2 is a structural schematic diagram of a power supply circuit according to an exemplary embodiment;

[0043] Figure 3 is a structural schematic diagram of a power supply circuit according to an exemplary embodiment;

[0044] Figure 4 is a structural schematic diagram of a power supply circuit according to an exemplary embodiment;

[0045] Figure 5 is a structural schematic diagram of a power supply circuit according to an exemplary embodiment;

[0046] Figure 6 is a structural schematic diagram of a power supply circuit according to an exemplary embodiment;

[0047] Figure 7 is a timing diagram showing a working process of a power supply circuit according to an exemplary embodiment.

[0048] In the figure: 1, power switch; 2, driving circuit; 3, power supply; 4, load; 5, control signal generating circuit; 21, first inverter group; 22, second inverter group; 23, first gating circuit; 24, second gating circuit; 25, third inverter group; 26, fourth inverter group; 27, third gating circuit; 28, fourth gating circuit; 51, fifth inverter; 52, sixth inverter; 53, seventh inverter; 211, first inverter; 221, second inverter; 251, third inverter; 261, fourth inverter; TG1, first transmission gate; TG2, second transmission gate; TG3, third transmission gate; TG4, fourth transmission gate; Q1, first P-type transistor; Q2, third N-type transistor; VCC, first power supply; VSS, second power supply; Td, delay circuit; XNOR, logic gate circuit; En, enable signal; N1, first node. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure. It should be noted that the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other without conflict.

[0050] In semiconductor chips, multiple voltage domains are used for multi-voltage power supply to reduce the power consumption of the chip. In order to improve the power supply capacity of the power circuit in the voltage domain, the size of the power switch in the power circuit (or the channel width-to-length ratio) is often larger. When the power circuit is converted from an idle state to a working state, directly turning on the power switch will cause a large peak current in the power switch, affecting the stability of the power circuit and even causing damage to the power circuit.

[0051] For example, Figure 1As shown, in the related art, the power supply circuit includes a power switch 1. The power switch 1 includes a first P-type transistor Q1 and a third N-type transistor Q2. The first end of the first P-type transistor Q1 is coupled to the first power supply VCC, the second end is coupled to the load 4, and the gate receives the inverted signal of the enable signal En. The first end of the third N-type transistor Q2 is coupled to the load 4, the second end is coupled to the second power supply VSS, and the gate receives the enable signal En. When the power supply circuit is not needed to be powered, the enable signal En is at a low level, the first P-type transistor Q1 and the third N-type transistor Q2 are disconnected, and the first power supply VCC and the second power supply VSS stop supplying power to the load 4. When the power supply circuit is needed to be powered, the enable signal En is at a high level, the first P-type transistor Q1 and the third N-type transistor Q2 are turned on, and the first power supply VCC and the second power supply VSS supply power to the load 4.

[0052] However, in the above power supply circuit, the size of the power switch is large. When the power switch is turned on, the peak current in the power switch is large. The large peak current will reduce the stability of the power supply circuit on the one hand, and may damage the power supply circuit on the other hand.

[0053] Based on this, the present disclosure provides a power supply circuit. When the power supply circuit is converted from an idle state to a working state, the driving circuit establishes the potential of the control end of the power switch at different rates at different stages of the conduction process. Since the potential establishment rate of the control end of the power switch is slow in the second stage, the peak current when the power switch is turned on is reduced, thereby improving the stability of the power supply circuit and avoiding damage to the power supply circuit. At the same time, since the potential establishment rate of the control end of the power switch is fast in the first stage, the time required for the conduction process of the power switch is reduced, thereby improving the reliability of the power supply circuit.

[0054] In an exemplary embodiment of the present disclosure, a power supply circuit is provided, such as Figure 2As shown, the power supply circuit includes a power switch 1 and a drive circuit 2. The power switch 1 includes a control terminal, the power switch 1 is coupled to the power supply 3 and the load 4, and is configured to be controlled to turn on or off the power supply 3 and the load 4. The drive circuit 2 is coupled to the control terminal of the power switch 1, and is configured to control the potential of the control terminal of the power switch 1 to control the turning on or off of the power switch 1. In the process of turning on the power switch 1, the potential of the control terminal of the power switch 1 is established in a multi-stage manner, and the potential establishment rate of each stage is gradually reduced. For example, the potential establishment process of the control terminal of the power switch 1 is divided into a first stage and a second stage. In the first stage, the potential of the control terminal of the power switch 1 is established at a higher rate, and the power switch 1 is not turned on (that is, the voltage of the control terminal of the power switch 1 is close to the threshold voltage of the power switch 1 without crossing the threshold voltage). In the second stage, the potential of the control terminal of the power switch 1 is established at a lower rate, and the power switch 1 is turned on. That is, the potential establishment rate of the control terminal of the power switch 1 in the first stage is greater than the potential establishment rate in the second stage, and the first stage is earlier than the second stage.

[0055] In this embodiment, the power supply circuit includes a power switch and a drive circuit, and the power switch is coupled to the drive circuit. The potential of the control end of the power switch is controlled by the drive circuit to control the power switch to be turned on or off, so that the power supply supplies power to the load or stops supplying power. When the power supply circuit is converted from an idle state to a working state, the drive circuit establishes the potential of the control end of the power switch at a rate that is first fast and then slow, and slowly turns on the power switch in the second stage. Since the power switch is turned on at a slow rate, the peak current when the power switch is turned on is reduced, thereby improving the stability of the power supply circuit. At the same time, since the potential establishment rate of the control end of the power switch is fast in the first stage, the time required for the power switch to be turned on is reduced, thereby improving the reliability of the power supply circuit.

[0056] In some exemplary embodiments provided in the present disclosure, Figure 3As shown, the power switch 1 includes a first P-type transistor Q1, and the control end of the power switch 1 is the gate of the first P-type transistor Q1. The driving circuit 2 includes a first inverter group 21, a second inverter group 22, a first gating circuit 23 and a second gating circuit 24. The first inverter group 21 includes a plurality of first inverters 211 connected in series. The second inverter group 22 includes a plurality of second inverters 221 connected in series. The first inverter 211 and the first gating circuit 23 are coupled in series between the first node N1 and the gate of the first P-type transistor Q1. The second inverter 221 and the second gating circuit 24 are coupled in series between the first node N1 and the gate of the first P-type transistor Q1. The first node N1 receives an enable signal En, and the enable signal En is used to turn the power switch 1 on or off. The first gating circuit 23 is turned on or off according to the first control signal E1 and the inverted signal of the first control signal E1. The second gating circuit 24 is turned on or off according to the second control signal E2 and the inverted signal of the second control signal E2. The channel width-to-length ratio of the first N-type transistor in the first inverter 211 closest to the first P-type transistor Q1 in the first inverter group 21 is greater than the channel width-to-length ratio of the second N-type transistor in the second inverter 221 closest to the first P-type transistor Q1 in the second inverter group 22. The first inverter 211 closest to the first P-type transistor Q1 in the first inverter group 21 refers to the first inverter 211 at the last stage in the first inverter group 21 in terms of the cascade relationship. The second inverter 221 closest to the first P-type transistor Q1 in the second inverter group 22 refers to the second inverter 221 at the last stage in the second inverter group 22 in terms of the cascade relationship.

[0057] In this embodiment, by setting the channel width-to-length ratio of the first N-type transistor in the first inverter group and the second N-type transistor in the second inverter group, the falling edge time of the signal output by the first inverter closest to the first P-type transistor in the first inverter group is shorter than the falling edge time of the signal output by the second inverter closest to the first P-type transistor in the second inverter group, thereby making the potential establishment rate of the gate of the first P-type transistor different, which serves as the basis for controlling the potential establishment rate of the gate of the first P-type transistor. The first inverter group or the second inverter group is gated in different stages of the conduction process by the first gating circuit and the second gating circuit to control the gate of the first P-type transistor to establish a potential at different rates in different stages. The first P-type transistor is turned on at a slower rate by the second inverter group, which reduces the peak current when the first P-type transistor is turned on, thereby improving the stability of the power supply circuit. At the same time, the first P-type transistor is set up at a faster rate by the first inverter group, which reduces the time required for the conduction process of the first P-type transistor, thereby improving the reliability of the power supply circuit.

[0058] In some exemplary embodiments provided by the present disclosure, the channel width-to-length ratio of the first N-type transistor is greater than a first preset value, and the channel width-to-length ratio of the second N-type transistor is less than the first preset value, wherein the first preset value is the channel width-to-length ratio corresponding to a threshold voltage of 0.7V of the N-type transistor.

[0059] In this embodiment, the channel width-to-length ratio of the first N-type transistor is set to be greater than the first preset value to improve the driving capability of the first inverter group, thereby accelerating the rate at which the potential of the gate of the first P-type transistor is established. The channel width-to-length ratio of the first N-type transistor is set to be less than the first preset value to reduce the driving capability of the second inverter group, thereby slowing down the rate at which the potential of the gate of the first P-type transistor is established. The channel width-to-length ratio of the first N-type transistor and the second N-type transistor is set based on the first preset value to reduce the peak current when the first P-type transistor is turned on while reducing the time required for the conduction process of the first P-type transistor.

[0060] In some exemplary embodiments provided in the present disclosure, during the conduction of the first P-type transistor Q1 , the first gating circuit 23 is enabled before the second gating circuit 24 , and the gating times of the first gating circuit 23 and the second gating circuit 24 are staggered.

[0061] In this embodiment, since the driving capability of the first inverter group is strong and the driving capability of the second inverter group is weak, in the first stage, the first P-type transistor needs to be driven by the first inverter group, and the first inverter group is gated by the first gating circuit to reduce the time required for the first P-type transistor to be turned on. In the second stage, the first P-type transistor needs to be driven by the second inverter group, and the second inverter group is gated by the second gating circuit to reduce the peak current when the first P-type transistor is turned on. Since only one inverter group is needed to drive the first P-type transistor at the same time, the gating time of the first gating circuit and the second gating circuit is staggered, thereby reducing the peak current when the first P-type transistor is turned on and reducing the time required for the first P-type transistor to be turned on.

[0062] In some exemplary embodiments provided in the present disclosure, the number of the first inverters 211 and the number of the second inverters 221 are both odd numbers. For example, the number of the first inverters 211 and the number of the second inverters 221 are both three.

[0063] In this embodiment, since the enable signal needs to turn off the first P-type transistor when it is at a low level and turn on the first P-type transistor when it is at a high level, the number of the first inverter and the second inverter needs to be an odd number to invert the enable signal. By setting the number of the first inverter and the second inverter, the enable signal is controlled to turn on or off the power switch through the drive circuit, so that the power supply supplies power to the load or stops supplying power.

[0064] In some exemplary embodiments provided by the present disclosure, the first gating circuit 23 includes a first transmission gate TG1. The first transmission gate TG1 and the first inverter 211 are coupled in series between the first node N1 and the gate of the first P-type transistor Q1. The second gating circuit 24 includes a second transmission gate TG2. The second transmission gate TG2 and the second inverter 221 are coupled in series between the first node N1 and the gate of the first P-type transistor Q1.

[0065] In this embodiment, the first gating circuit is formed by the first transmission gate, and the second gating circuit is formed by the second transmission gate. The first gating circuit and the second gating circuit have simple structures. By gating the first inverter group through the first transmission gate and gating the second inverter group through the second transmission gate, the potential of the first P-type transistor can be established at different rates at different stages, so as to reduce the peak current when the first P-type transistor is turned on and reduce the time required for the first P-type transistor to turn on.

[0066] In some exemplary embodiments provided by the present disclosure, the first transmission gate TG1 and the second transmission gate TG2 each include a first control terminal and a second control terminal. The first control terminal of the first transmission gate TG1 receives a first control signal E1, and the second control terminal receives an inverted signal of the first control signal E1. The first control terminal of the second transmission gate TG2 receives a second control signal E2, and the second control terminal receives an inverted signal of the second control signal E2.

[0067] In this embodiment, since the first transmission gate and the second transmission gate both require two inverted signals to control staggered conduction during operation, the first transmission gate is controlled by the first control signal and its inverted signal, and the second transmission gate is controlled by the second control signal and its inverted signal. The first transmission gate and the second transmission gate are controlled separately by two different control signals, thereby improving the ability to drive the first transmission gate and the second transmission gate, thereby improving the reliability of the power supply circuit.

[0068] In some exemplary embodiments provided in the present disclosure, the first control signal E1 and the second control signal E2 are in opposite phases.

[0069] In this embodiment, since the gating time of the first transmission gate and the second transmission gate is staggered, the signal at the same control end of the first transmission gate and the second transmission gate is an inverted signal, and the first control signal and the second control signal are inverted. By setting the first control signal and the second control signal to be inverted, only one transmission gate is turned on at the same time, thereby avoiding unexpected changes in the potential of the gate of the first P-type transistor, thereby improving the stability of the power supply circuit.

[0070] In some exemplary embodiments provided by the present disclosure, the power source 3 includes a first power source VCC. A first terminal of the first P-type transistor Q1 is coupled to the first power source VCC, and a second terminal thereof is coupled to the load 4.

[0071] In this embodiment, the first P-type transistor is coupled between the first power source and the load, and can connect or disconnect the first power source and the load under the action of an enable signal, thereby enabling the first power source to supply power to the load or stop supplying power.

[0072] In some exemplary embodiments provided in the present disclosure, Figure 4 As shown, the power switch 1 includes a third N-type transistor Q2, and the control end of the power switch 1 is the gate of the third N-type transistor Q2. The driving circuit 2 includes a third inverter group 25, a fourth inverter group 26, a third gating circuit 27 and a fourth gating circuit 28. The third inverter group 25 includes a plurality of third inverters 251 connected in series. The fourth inverter group 26 includes a plurality of fourth inverters 261 connected in series. The third inverter 251 and the third gating circuit 27 are coupled in series between the first node N1 and the gate of the third N-type transistor Q2. The fourth inverter 261 and the fourth gating circuit 28 are coupled in series between the first node N1 and the gate of the third N-type transistor Q2. The first node N1 receives the enable signal En. The third gating circuit 27 is turned on or off according to the first control signal E1 and the inverted signal of the first control signal E1. The fourth gating circuit 28 is turned on or off according to the second control signal E2 and the inverted signal of the second control signal E2. The channel width-to-length ratio of the second P-type transistor in the third inverter 251 closest to the third N-type transistor Q2 in the third inverter group 25 is greater than the channel width-to-length ratio of the third P-type transistor in the fourth inverter 261 closest to the third N-type transistor Q2 in the fourth inverter group 26. The third inverter 251 closest to the third N-type transistor Q2 in the third inverter group 25 refers to the third inverter 251 at the last stage in the third inverter group 25 in terms of the cascade relationship. The fourth inverter 261 closest to the third N-type transistor Q2 in the fourth inverter group 26 refers to the fourth inverter 261 at the last stage in the fourth inverter group 26 in terms of the cascade relationship.

[0073] In this embodiment, by setting the channel width-to-length ratio of the second P-type transistor in the third inverter group and the third P-type transistor in the fourth inverter group, the rising edge time of the signal output by the third inverter closest to the third N-type transistor in the third inverter group is shorter than the rising edge time of the signal output by the fourth inverter closest to the third N-type transistor in the fourth inverter group, thereby making the potential establishment rate of the gate of the third N-type transistor different, which serves as the basis for controlling the potential establishment rate of the gate of the third N-type transistor. The third inverter group or the fourth inverter group is gated in different stages of the conduction process by the third gating circuit and the fourth gating circuit to control the gate of the third N-type transistor to establish a potential at different rates in different stages. The third N-type transistor is turned on at a slower rate by the fourth inverter group, which reduces the peak current when the third N-type transistor is turned on, thereby improving the stability of the power supply circuit. At the same time, the third N-type transistor is set up at a faster rate by the third inverter group, which reduces the time required for the conduction process of the third N-type transistor, thereby improving the reliability of the power supply circuit.

[0074] In some exemplary embodiments provided by the present disclosure, the channel width-to-length ratio of the second P-type transistor is greater than a second preset value, and the channel width-to-length ratio of the third P-type transistor is less than the second preset value, wherein the second preset value is the channel width-to-length ratio corresponding to a threshold voltage of 0.8V of the P-type transistor.

[0075] In this embodiment, the channel width-to-length ratio of the second P-type transistor is set to be greater than the second preset value to improve the driving capability of the third inverter group, thereby accelerating the rate at which the potential of the gate of the third N-type transistor is established. The channel width-to-length ratio of the third P-type transistor is set to be less than the second preset value to reduce the driving capability of the fourth inverter group, thereby slowing down the rate at which the potential of the gate of the third N-type transistor is established. The channel width-to-length ratios of the second P-type transistor and the third P-type transistor are set based on the second preset value to reduce the peak current when the third N-type transistor is turned on while reducing the time required for the conduction process of the third N-type transistor.

[0076] In some exemplary embodiments provided in the present disclosure, when the third N-type transistor is turned on, the third gating circuit 27 is enabled before the fourth gating circuit 28 and the gating times of the third gating circuit 27 and the fourth gating circuit 28 are staggered.

[0077] In this embodiment, since the driving capability of the third inverter group is strong and the driving capability of the fourth inverter group is weak, the third N-type transistor needs to be driven by the third inverter group in the first stage, and the third inverter group is gated by the third gating circuit to reduce the time required for the conduction process of the third N-type transistor. In the second stage, the third N-type transistor needs to be driven by the fourth inverter group, and the second inverter group is gated by the second gating circuit to reduce the peak current when the third N-type transistor is turned on. Since only one inverter group is needed to drive the third N-type transistor at the same time, the gate times of the third gating circuit and the fourth gating circuit are staggered, thereby reducing the peak current when the third N-type transistor is turned on and reducing the time required for the conduction process of the third N-type transistor.

[0078] In some exemplary embodiments provided by the present disclosure, the number of the third inverters 251 and the number of the fourth inverters 261 are both even numbers. For example, the number of the third inverters 251 and the number of the fourth inverters 261 are both four.

[0079] In this embodiment, since the enable signal needs to turn off the third N-type transistor when it is at a low level and turn on the third N-type transistor when it is at a high level, the number of the third inverter and the fourth inverter needs to be an even number to maintain the enable signal. By setting the number of the third inverter and the fourth inverter, the enable signal is used to control the on or off of the power switch through the drive circuit, so that the power supply supplies power to the load or stops supplying power.

[0080] In some exemplary embodiments provided by the present disclosure, the third gating circuit 27 includes a third transmission gate TG3. The third transmission gate TG3 and the third inverter 251 are coupled in series between the first node N1 and the gate of the third N-type transistor Q2. The fourth gating circuit 28 includes a fourth transmission gate TG4. The fourth transmission gate TG4 and the fourth inverter 261 are coupled in series between the first node N1 and the gate of the third N-type transistor Q2.

[0081] In this embodiment, the third gating circuit is formed by the third transmission gate, and the fourth gating circuit is formed by the fourth transmission gate. The third gating circuit and the fourth gating circuit have simple structures. The third inverter group is gated by the third transmission gate and the fourth inverter group is gated by the fourth transmission gate, so that the potential of the third N-type transistor can be established at different rates at different stages, so as to reduce the peak current when the third N-type transistor is turned on and reduce the time required for the conduction process of the third N-type transistor.

[0082] In some exemplary embodiments provided by the present disclosure, the third transmission gate TG3 and the fourth transmission gate TG4 each include a first control terminal and a second control terminal. The first control terminal of the third transmission gate TG3 receives the first control signal E1, and the second control terminal receives the inverted signal of the first control signal E1. The first control terminal of the fourth transmission gate TG4 receives the second control signal E2, and the second control terminal receives the inverted signal of the second control signal E2.

[0083] In this embodiment, since the third transmission gate and the fourth transmission gate both require two inverted signals for control during operation, the third transmission gate is controlled by the first control signal and its inverted signal, and the fourth transmission gate is controlled by the second control signal and its inverted signal. The third transmission gate and the fourth transmission gate are respectively controlled by two different control signals, thereby improving the ability to drive the third transmission gate and the fourth transmission gate, thereby improving the reliability of the power supply circuit.

[0084] In some exemplary embodiments provided in the present disclosure, the power supply 3 includes a second power supply VSS. The first end of the third N-type transistor Q2 is coupled to the load 4, and the second end is coupled to the second power supply VSS. The first power supply VCC is a high level, and the second power supply VSS is a low level. Exemplarily, the first power supply VCC is 1.5V, 1.8V or 3.3V, etc. The second power supply VSS is 0V, 0.1V, etc.

[0085] In this embodiment, the third N-type transistor is coupled between the second power supply and the load, and can connect or disconnect the second power supply and the load under the action of the enable signal, thereby enabling the second power supply to supply power or stop supplying power to the load.

[0086] In some exemplary embodiments provided in the present disclosure, a threshold voltage of the first P-type transistor Q1 is greater than 0.8V, and a threshold voltage of the third N-type transistor Q2 is greater than 0.7V.

[0087] In this embodiment, by increasing the threshold voltage of the power switch, the leakage current of the power switch can be reduced while preventing the third inverter group and the fourth inverter group from erroneously turning on the power switch, thereby improving the reliability of the power circuit.

[0088] In some exemplary embodiments provided in the present disclosure, the duration of the first stage is a preset time. The preset time is related to the threshold voltage of the power switch 1. If the threshold voltage of the first P-type transistor Q1 is low and the threshold voltage of the third N-type transistor Q2 is high, the preset time is longer. If the threshold voltage of the first P-type transistor Q1 is high and the threshold voltage of the third N-type transistor Q2 is low, the preset time is shorter. Exemplarily, the preset time is in the nanosecond level or microsecond level, for example, it can be 5ns, 100ns or 10μs, etc.

[0089] In this embodiment, the preset time is selected according to the threshold voltages of the first P-type transistor and the third N-type transistor, thereby determining the time when the third inverter group and the fourth inverter group are turned on. By adjusting the preset time according to the threshold voltage, the problem of erroneous turning on of the power switch due to a long turn-on time or slow turning on of the power switch due to a short turn-on time is avoided, thereby improving the reliability of the power circuit.

[0090] In some exemplary embodiments provided in the present disclosure, Figure 5 and Figure 6 As shown, the power supply circuit also includes a control signal generating circuit 5. The control signal generating circuit 5 is coupled to the driving circuit 2, specifically to the first node N1, the first gating circuit 23, the second gating circuit 24, the third gating circuit 27 and the fourth gating circuit 28. The control signal generating circuit 5 is used to generate a first control signal E1, an inverted signal of the first control signal E1, a second control signal E2 and an inverted signal of the second control signal E2 according to the enable signal En. Among them, the first control signal E1 and the second control signal E2 are inverted signals to each other. It can be understood that the inverted signal of the first control signal E1 in the embodiment of the present disclosure can be used as the second control signal E2.

[0091] In this embodiment, the power supply circuit also includes a control signal generating circuit, which automatically generates a first control signal and a second control signal according to an enable signal to control each gating circuit in the driving circuit. Under the first control signal and the second control signal generated by the control signal generating circuit, the first gating circuit and the third gating circuit can enable the first inverter group and the third inverter group to quickly establish a potential at the control end of the power switch in the first stage, and the second gating circuit and the fourth gating circuit can enable the second inverter group and the fourth inverter group to slowly establish a potential at the control end of the power switch in the second stage. Since the first control signal and the second control signal can be generated according to the enable signal, the potential establishment rate of the control end of the power switch is automatically adjusted, thereby reducing the complexity of the power supply circuit control.

[0092] It is understandable that, in addition to using the control signal generating circuit 5 to generate the first control signal E1 and the second control signal E2, a controller inside the chip may also be used to generate them.

[0093] In some exemplary embodiments provided in the present disclosure, Figure 6As shown, the control signal generating circuit 5 includes a delay circuit Td and a logic gate circuit XNOR. The input end of the delay circuit Td is coupled to the first node N1, and receives the enable signal En, which is used to delay the enable signal En for a preset time. The first input end of the logic gate circuit XNOR is coupled to the output end of the delay circuit Td, and the second input end is coupled to the first node N1, and is configured to perform a logical operation on the enable signal En and the output signal of the delay circuit Td to generate a first control signal E1, and the pulse width of the first control signal E1 is the same as the preset time. Exemplarily, the logic gate circuit XNOR is an XNOR gate or other circuit capable of implementing XNOR logic. Exemplarily, after the enable signal En passes through the delay circuit Td, the delay circuit Td outputs the enable signal En after the preset time delay. When the enable signal En changes from a low level to a high level, within the preset time, one input end of the logic gate circuit XNOR is a low level and one input end is a high level. At this time, the output of the logic gate circuit XNOR changes from a high level to a low level. After the preset time, both input terminals of the logic gate circuit XNOR are high level. At this time, the output of the logic gate circuit XNOR changes from low level to high level. Therefore, the logic gate circuit XNOR forms a first control signal E1 which is low level within the preset time and high level outside the preset time.

[0094] In this embodiment, the enable signal is delayed by a delay circuit to determine the preset time required for the first stage. The enable signal before and after the delay is operated by a logic gate circuit to automatically generate a first control signal with a pulse width of the preset time, thereby reducing the complexity of the power circuit control.

[0095] In some exemplary embodiments provided by the present disclosure, the control signal generating circuit 5 further includes a fifth inverter 51, a sixth inverter 52 and a seventh inverter 53. The input end of the fifth inverter 51 is coupled to the output end of the logic gate circuit XNOR, receives the first control signal E1, and the output end outputs the inverted signal of the first control signal E1. The input end of the sixth inverter 52 is coupled to the output end of the fifth inverter 51, receives the inverted signal of the first control signal E1, and the output end outputs the inverted signal of the second control signal E2. The input end of the seventh inverter 53 is coupled to the output end of the sixth inverter 52, receives the inverted signal of the second control signal E2, and the output end outputs the second control signal E2.

[0096] In this embodiment, the first control signal output by the control signal generating circuit is inverted by the fifth inverter, and together with the first control signal, a group of control signals for driving the first transmission gate and the third transmission gate are formed to be switched on or off. The inverted signal of the first control signal is inverted by the sixth inverter, and the inverted signal of the second control signal is inverted by the seventh inverter to drive the second transmission gate and the fourth transmission gate, thereby improving the driving capability of the second transmission gate and the fourth transmission gate and thus improving the reliability of the power supply circuit.

[0097] Combination Figure 6 and Figure 7 As shown, the working principle of the power supply circuit provided by the present disclosure is described. The power switch 1 includes a first P-type transistor Q1 and a third N-type transistor Q2. The driving circuit 2 includes a first inverter group 21, a second inverter group 22, a third inverter group 25, a fourth inverter group 26, a first gating circuit 23, a second gating circuit 24, a third gating circuit 27 and a fourth gating circuit 28. The first inverter group 21 includes a plurality of first inverters 211 connected in series. The second inverter group 22 includes a plurality of second inverters 221 connected in series. The third inverter group 25 includes a plurality of third inverters 251 connected in series. The fourth inverter group 26 includes a plurality of fourth inverters 261 connected in series. The first gating circuit 23 includes a first transmission gate TG1. The second gating circuit 24 includes a second transmission gate TG2. The third gating circuit 27 includes a third transmission gate TG3. The fourth gating circuit 28 includes a fourth transmission gate TG4. The power supply 3 includes a first power supply VCC and a second power supply VSS. The control signal generating circuit 5 includes a delay circuit Td, a logic gate circuit XNOR, a fifth inverter 51, a sixth inverter 52 and a seventh inverter 53. The first node N1 receives an enable signal En.

[0098] When the power supply circuit is not required to supply power, the enable signal En is at a low level. When the power supply circuit is required to supply power, the enable signal En changes from a low level to a high level. The enable signal En and the enable signal En delayed by the delay circuit Td are input to the logic gate circuit XNOR, and the logic gate circuit XNOR outputs a first control signal E1 with a pulse width of a preset time. The first control signal E1 is inverted by the fifth inverter 51 to generate an inverted signal of the first control signal E1. The inverted signal of the first control signal E1 is passed through the sixth inverter 52 to generate an inverted signal of the second control signal E2. The inverted signal of the second control signal E2 is passed through the seventh inverter 53 to generate a second control signal E2. The first control signal E1 is input into the first control end of the first transmission gate TG1 and the third transmission gate TG3, the inverted signal of the first control signal E1 is input into the second control end of the first transmission gate TG1 and the third transmission gate TG3, the second control signal E2 is input into the first control end of the second transmission gate TG2 and the fourth transmission gate TG4, and the inverted signal of the second control signal E2 is input into the second control end of the second transmission gate TG2 and the fourth transmission gate TG4.

[0099] The first transmission gate TG1 and the third transmission gate TG3 are turned on for a preset time, the first inverter group 21 quickly discharges the gate of the first P-type transistor Q1 to a voltage slightly higher than its threshold voltage, and the third inverter group 25 quickly charges the gate of the third N-type transistor Q2 to a voltage slightly lower than its threshold voltage. After the preset time is reached, the first transmission gate TG1 and the third transmission gate TG3 are turned off, and the second transmission gate TG2 and the fourth transmission gate TG4 are turned on. The second inverter group 22 slowly turns on the first P-type transistor Q1, and the fourth inverter group 26 slowly turns on the third N-type transistor Q2 so that the first power supply VCC and the second power supply VSS supply power to the load 4. The conduction rates of the first P-type transistor Q1 and the third N-type transistor Q2 are controlled by two inverter groups respectively, which reduces the peak current when the power switch is turned on, thereby improving the stability of the power supply circuit. Among them, V En is the voltage of the enable signal En, V E1 is the voltage of the first control signal E1, V E2 is the voltage of the second control signal E2, V Q1G is the gate voltage of the first P-type transistor Q1, I Q1 is the current of the first P-type transistor Q1, V VCC is the voltage of the first power supply VCC, V Q2G is the gate voltage of the third N-type transistor Q2, I Q2 is the current of the third N-type transistor Q2, V VSS is the voltage of the second power supply VSS.

[0100] The embodiment of the present disclosure further provides a chip, the chip including the power supply circuit as in any of the above embodiments. The chip may be, for example, a random access memory (RAM) or a read-only memory (ROM).

[0101] The present disclosure is described with reference to flowcharts and / or block diagrams of methods, apparatuses (devices) and computer program products according to embodiments of the present disclosure. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0102] These computer program instructions may also be stored in a computer readable chip that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable chip produce an article of manufacture including an instruction device that implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0103] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0104] In the present disclosure, the terms "comprises", "comprising" or any other variations thereof are intended to cover non-exclusive inclusion, so that an article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such article or device. In the absence of more restrictions, the elements defined by the sentence "comprising..." do not exclude the presence of other identical elements in the article or device comprising the elements.

[0105] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0106] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the intent of the present disclosure also includes these modifications and variations.

Claims

1. A power supply circuit, characterized in that: The power supply circuit comprises: A power switch, the power switch comprising a control terminal, the power switch being configured to be controlled to switch on or off between a power source and a load; a driving circuit, the driving circuit being coupled to the control terminal of the power switch, the driving circuit being configured to control the potential of the control terminal of the power switch to control the on or off state of the power switch; Wherein, during the conduction of the power switch, the potential establishment rate of the control end of the power switch in the first stage is greater than the potential establishment rate in the second stage, and the first stage is earlier than the second stage; Wherein, in the first stage, the voltage at the control terminal of the power switch is close to the threshold voltage of the power switch but does not cross the threshold voltage, and the power switch is not turned on; in the second stage, the power switch is turned on; Wherein, the power switch includes a first P-type transistor, and the driving circuit includes: A first inverter group, a second inverter group, a first gating circuit and a second gating circuit, wherein the first inverter group includes a plurality of first inverters connected in series, the second inverter group includes a plurality of second inverters connected in series, the first inverter and the first gating circuit are coupled in series between a first node and a gate of the first P-type transistor, the second inverter and the second gating circuit are coupled in series between the first node and the gate of the first P-type transistor, the first node receives an enable signal, the first gating circuit is switched on or off according to a first control signal and an inverted signal of the first control signal, and the second gating circuit is switched on or off according to a second control signal and an inverted signal of the second control signal; The channel width-to-length ratio of the first N-type transistor in the first inverter closest to the first P-type transistor in the first inverter group is greater than the channel width-to-length ratio of the second N-type transistor in the second inverter closest to the first P-type transistor in the second inverter group.

2. The power supply circuit according to claim 1, characterized in that: When the first P-type transistor is turned on, the first gating circuit is turned on before the second gating circuit, and the gating times of the first gating circuit and the second gating circuit are staggered.

3. The power supply circuit according to claim 1, characterized in that: The number of the first inverters and the number of the second inverters are both odd numbers.

4. The power supply circuit according to claim 1, characterized in that: The first gating circuit includes a first transmission gate, wherein the first transmission gate and the first inverter are coupled in series between the first node and the gate of the first P-type transistor; The second gating circuit includes a second transmission gate, and the second transmission gate and the second inverter are coupled in series between the first node and the gate of the first P-type transistor.

5. The power supply circuit according to claim 4, characterized in that: The first transmission gate and the second transmission gate each include a first control end and a second control end, the first control end of the first transmission gate receives the first control signal, the second control end of the first transmission gate receives an inverted signal of the first control signal, the first control end of the second transmission gate receives the second control signal, and the second control end of the second transmission gate receives an inverted signal of the second control signal.

6. The power supply circuit according to claim 5, characterized in that: The first control signal and the second control signal are in antiphase.

7. The power supply circuit according to claim 1, characterized in that: The power supply includes a first power supply, a first terminal of the first P-type transistor is coupled to the first power supply, and a second terminal of the first P-type transistor is coupled to the load.

8. A power supply circuit, characterized in that: The power supply circuit comprises: A power switch, the power switch comprising a control terminal, the power switch being configured to be controlled to switch on or off between a power source and a load; a driving circuit, the driving circuit being coupled to the control terminal of the power switch, the driving circuit being configured to control the potential of the control terminal of the power switch to control the on or off state of the power switch; Wherein, during the conduction of the power switch, the potential establishment rate of the control end of the power switch in the first stage is greater than the potential establishment rate in the second stage, and the first stage is earlier than the second stage; Wherein, in the first stage, the voltage at the control terminal of the power switch is close to the threshold voltage of the power switch but does not cross the threshold voltage, and the power switch is not turned on; in the second stage, the power switch is turned on; Wherein, the power switch includes a third N-type transistor, and the driving circuit includes: A third inverter group, a fourth inverter group, a third gating circuit and a fourth gating circuit, wherein the third inverter group includes a plurality of third inverters connected in series, the fourth inverter group includes a plurality of fourth inverters connected in series, the third inverter and the third gating circuit are coupled in series between a first node and a gate of the third N-type transistor, the fourth inverter and the fourth gating circuit are coupled in series between the first node and the gate of the third N-type transistor, the first node receives an enable signal, the third gating circuit is switched on or off according to a first control signal and an inverted signal of the first control signal, and the fourth gating circuit is switched on or off according to a second control signal and an inverted signal of the second control signal; The channel width-to-length ratio of the second P-type transistor in the third inverter closest to the third N-type transistor in the third inverter group is greater than the channel width-to-length ratio of the third P-type transistor in the fourth inverter closest to the third N-type transistor in the fourth inverter group.

9. The power supply circuit according to claim 8, characterized in that: In the process of turning on the third N-type transistor, the third gating circuit is enabled before the fourth gating circuit, and the gating times of the third gating circuit and the fourth gating circuit are staggered.

10. The power supply circuit according to claim 8, characterized in that: The number of the third inverters and the number of the fourth inverters are both even numbers.

11. The power supply circuit according to claim 8, characterized in that: The third gating circuit includes a third transmission gate, wherein the third transmission gate and the third inverter are coupled in series between the first node and the gate of the third N-type transistor; The fourth gating circuit includes a fourth transmission gate, and the fourth transmission gate and the fourth inverter are coupled in series between the first node and the gate of the third N-type transistor.

12. The power supply circuit according to claim 11, characterized in that: The third transmission gate and the fourth transmission gate each include a first control end and a second control end, the first control end of the third transmission gate receives the first control signal, the second control end of the third transmission gate receives an inverted signal of the first control signal, the first control end of the fourth transmission gate receives the second control signal, and the second control end of the fourth transmission gate receives an inverted signal of the second control signal.

13. The power supply circuit according to claim 8, characterized in that: The power supply includes a second power supply, a first terminal of the third N-type transistor is coupled to the load, and a second terminal of the third N-type transistor is coupled to the second power supply.

14. The power supply circuit according to any one of claims 8 to 13, characterized in that: The power supply circuit also includes: A control signal generating circuit is used to generate the first control signal and the second control signal according to the enable signal, and the first control signal and the second control signal are inverted signals to each other.

15. The power supply circuit according to claim 14, characterized in that: The control signal generating circuit comprises: A delay circuit, wherein an input end of the delay circuit receives the enable signal and is used to delay the enable signal for a preset time; A logic gate circuit is configured to perform a logic operation on the enable signal and the output signal of the delay circuit to generate the first control signal, wherein a pulse width of the first control signal is the same as the preset time.

16. The power supply circuit according to claim 15, characterized in that: The control signal generating circuit further includes: a fifth inverter, wherein an input terminal of the fifth inverter receives the first control signal, and an output terminal of the fifth inverter outputs an inverted signal of the first control signal; a sixth inverter, wherein an input terminal of the sixth inverter receives an inverted signal of the first control signal, and an output terminal of the sixth inverter outputs an inverted signal of the second control signal; A seventh inverter, wherein an input terminal of the seventh inverter receives an inverted signal of the second control signal, and an output terminal of the seventh inverter outputs the second control signal.

17. A chip, characterized in that: The chip comprises the power supply circuit according to any one of claims 1 to 16.

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