A precise irradiation assessment method for complex IP cores of SRAM-based FPGAs

Abstract

The present invention provides a method for accurately evaluating the irradiation of complex IP cores of SRAM-type FPGAs, comprising: (1) performing Geant4 Monte Carlo simulation on heavy ions; (2) performing device unit-level TCAD simulation on the FPGA to be tested, which includes the physical characteristics of heavy ions; (3) converting simulation parameters into a spice netlist and performing Pspice simulation; (4) performing a high-precision laser test on the sensitive area obtained by the simulation; (5) performing heavy ion effect correction on the laser test results and fitting a heavy ion evaluation curve. The method performs accurate irradiation testing on complex IP cores in FPGAs through software simulation, laser refinement, and equivalent correction, thereby realizing accurate evaluation of the irradiation effect of complex IP cores embedded in FPGAs.

Description

Technical Field

[0001] The present application relates to the technical field of FPGA radiation evaluation, and in particular to a method for accurate radiation evaluation of a complex IP core of an SRAM-type FPGA. Background Art

[0002] Static random-access memory (SRAM) field programmable gate array (FPGA) has the advantages of low cost, abundant resources, and strong dynamic reconfiguration capability, and is widely used in various aerospace models at home and abroad. However, spacecraft are exposed to cosmic rays, earth radiation belt particles, and high-energy particles such as protons and neutrons in outer space. After being exposed to radiation, FPGAs are prone to single-particle effects. With the gradual reduction of semiconductor device process size, FPGAs are becoming more and more sensitive to single-particle radiation effects. Therefore, in order to ensure the reliability of aerospace models, it is particularly important to evaluate the ground radiation effects of FPGAs before they carry out actual space missions. IP cores are the most complex and most advanced modules in FPGAs at present, and aerospace models have an increasingly urgent demand for them. Different from general FPGA resources, due to the complex circuit structure, small area share, and fast data transmission speed, the evaluation of intellectual property core (IP) radiation has become a major challenge in the current evaluation of ground radiation effects.

[0003] The main means of ground evaluation is to use a heavy ion accelerator to conduct single-particle simulation tests. Since the IP core area is too small, taking the high-speed interface IP as an example, the current smallest single-particle beam spot area is still dozens of times its area. Therefore, the particle injection injected into the IP core is too small compared with expectations. The results of multiple evaluations vary greatly and the accuracy is too low. It cannot be used as a basis for evaluating the irradiation effect of the IP core, which in turn affects the reliability of FPGA space applications.

[0004] Laser simulation of single-particle experiments is low-cost, the laser frequency is precisely adjustable, and single pulse irradiation experiments can be realized. The laser source can be accurately moved using a precise three-dimensional mobile carrier, and precise irradiation can be performed on specific areas. However, the laser spot size is too small, and a full-area test of the FPGA requires nearly 610,000 scans. At the same time, due to the difference in ionization mechanisms between lasers and heavy ions, the laser test results cannot be equivalent to the heavy ion test results, and the reliability of large-area tests cannot be guaranteed.

[0005] In summary, FPGA, as the core control chip of aerospace models, is a device sensitive to radiation effects. The radiation assessment of existing IP cores is unreliable, which will have a significant impact on the operation of aerospace models. Therefore, it is very important to study a method for accurate radiation assessment of complex IP cores. Summary of the invention

[0006] The present application provides a method for accurate irradiation assessment of complex IP cores in SRAM-type FPGAs. The method performs accurate irradiation testing on complex IP cores in FPGAs through software simulation, laser refinement, and equivalent correction, thereby achieving accurate assessment of the irradiation effects of complex IP cores embedded in FPGAs.

[0007] In a first aspect, a method for evaluating an IP core applied to an SRAM-type FPGA is provided, comprising:

[0008] (1-1) Simulate heavy ions and FPGA devices to determine the preliminary prediction results of the IP core radiation sensitive area;

[0009] (1-2) Use laser to perform scanning test on the preliminary prediction results of the sensitive area determined in (1-1) to determine the accurate prediction results of the sensitive area;

[0010] (1-3) Perform single particle effect correction on the accurate prediction results of the sensitive area obtained in (1-2) to determine the IP core evaluation results.

[0011] In conjunction with the first aspect, in certain implementations of the first aspect, the specific steps of simulating in step (1-1) include:

[0012] (2-1) Use Geant4 software to simulate the heavy ions to be tested and extract physical characteristic parameters;

[0013] (2-2) Combined with the heavy ion physical properties obtained in (2-1), the device-level TCAD simulation of the corresponding process of the SRAM type FPGA to be tested is performed to obtain the device-level radiation effect simulation results;

[0014] (2-3) Convert the TCAD simulation results obtained in (2-2) into a spice netlist, use Hspice to perform circuit simulation including radiation effects, and determine the preliminary prediction results of the IP core radiation sensitive area.

[0015] In conjunction with the first aspect, in some implementations of the first aspect, step (2-1) specifically includes:

[0016] Design device geometry and irradiation environment model, determine the response of cover material structure and material sensitive components, and establish Geant4 geometry model;

[0017] Setting the particle trajectory and angle of ions passing through the electromagnetic region of the material to be tested can be set by coding in the Geant4 software;

[0018] Select the ion transport model related to heavy ion simulation, simulate the physical process of ion reaction, and analyze and extract the physical characteristic parameters.

[0019] In conjunction with the first aspect, in some implementations of the first aspect, step (2-2) specifically includes:

[0020] Convert the Geant4 geometry model in step (2-1) into a TCAD model;

[0021] Pisces is used to calculate the electrical behavior based on the device structure obtained from process simulation, and Slivaco's SPICE model parameter extraction tool Utmost IV is used to extract device parameters that meet the BSIM standard and generate a SPICE netlist.

[0022] In conjunction with the first aspect, in certain implementations of the first aspect, the specific steps of the scanning test in step (1-2) include:

[0023] (3-1) Based on the preliminary prediction results of the IP core radiation sensitive area, cut the back of the area to expose the FPGA substrate;

[0024] (3-2) Install the FPGA to be tested on an FPGA test board, which provides power supply signals, clock signals and data communication functions for the FPGA chip to be tested;

[0025] (3-3) Power on the FPGA chip, aim the laser at the sensitive area of ​​the opening, and perform a scanning test;

[0026] (3-4) Monitor the working current, voltage, and data transmission bit error rate. When any electrical parameter changes, or the value is too high or too low, it is considered that the FPGA area to be tested has a fault.

[0027] In combination with the first aspect, in certain implementations of the first aspect, the opening accuracy is controlled at 0.8 mm. 2 .

[0028] In combination with the first aspect, in some implementations of the first aspect, the FPGA test board is used to evaluate the FPGA chip to be tested, and the FPGA test board includes: an FPGA master chip, a configuration module, a DDR module, a reset module, a clock module, a power supply system, and a communication module; wherein,

[0029] The power supply system is used to realize power supply;

[0030] The DDR module is used to store FPGA test vectors. After power-on, the test vectors will be burned into the FPGA to be tested by configuring the FLASH module. After the FPGA chip to be tested is powered on, the test vectors in the DDR module will be read and run.

[0031] Configuration module, configure the functional test program stored in DDR after power-on;

[0032] The FPGA master chip cooperates with the functional test of the FPGA chip to be tested, and sends the functional test results obtained after the test program is run to the monitoring and control equipment;

[0033] The reset module is connected to the communication module and the FPGA to be tested, and controls the FPGA to be tested to reset by monitoring and controlling the operation of the device;

[0034] The clock circuit connects the main control and the FPGA chip to be tested through the circuit board line, and provides a clock signal when the main control and the FPGA chip to be tested implement the test function;

[0035] The communication module transmits the test data of the FPGA to the monitoring and control device through the USB port, and controls the power supply and reset of the FPGA by the monitoring and control device.

[0036] In conjunction with the first aspect, in certain implementations of the first aspect, the specific steps of performing test data correction in step (1-3) are as follows:

[0037] (4-1) Analyze the differences in the ionization principles of the laser light source and the heavy ions to be simulated, and derive the energy level difference formula.

[0038] (4-2) Determine various parameters according to the irradiation environment and derive the energy level equivalent compensation formula.

[0039] (4-3) Perform equivalent compensation correction on the test results.

[0040] (4-4) The correction result is fitted by the least square method to generate the Bezier curve.

[0041] In a second aspect, an FPGA test board is provided, the FPGA test board is used to evaluate the FPGA chip to be tested, the FPGA test board includes an FPGA main control chip, and is used to monitor the working current, voltage, and data transmission bit error rate of the FPGA chip to be tested during the irradiation test, cooperate with the functional test of the FPGA chip to be tested, and send the functional test results obtained after the test program is run to the monitoring and control device;

[0042] The FPGA test board also includes: a configuration module, a DDR module, a reset module, a clock module, a power supply system, and a communication module; wherein,

[0043] The power supply system is used to realize power supply;

[0044] The DDR module is used to store FPGA test vectors. After power-on, the test vectors will be burned into the FPGA to be tested by configuring the FLASH module. After the FPGA chip to be tested is powered on, the test vectors in the DDR module will be read and run.

[0045] Configuration module, configure the functional test program stored in DDR after power-on;

[0046] The reset module is connected to the communication module and the FPGA to be tested, and controls the FPGA to be tested to reset by monitoring and controlling the operation of the device;

[0047] The clock circuit connects the main control and the FPGA chip to be tested through the circuit board line, and provides a clock signal when the main control and the FPGA chip to be tested implement the test function;

[0048] The communication module transmits the test data of the FPGA to the monitoring and control device through the USB port, and controls the power supply and reset of the FPGA by the monitoring and control device.

[0049] In combination with the first aspect, in certain implementations of the first aspect, the area of ​​the FPGA chip to be tested where the FPGA substrate is exposed is the sensitive area to be tested, and the sensitive area to be tested is determined by simulating heavy ions and FPGA devices. The irradiation test process includes aiming the laser at the sensitive area to be tested for scanning, while monitoring the operating current, voltage, and data transmission bit error rate.

[0050] The advantages of the present invention compared with the prior art are:

[0051] (1) The present invention innovatively cascades heavy ion simulation, device simulation and circuit simulation into one, obtains circuit simulation results with single particle effect, and accurately locates the radiation sensitive area only by using software.

[0052] (2) The present invention accurately opens a hole for the FPGA to be tested, and the opening area is less than 0.8mm 2 , completely avoid the impact of large-area laser testing on the accuracy of FPGA irradiation evaluation, and improve the precise positioning accuracy of sensitive areas.

[0053] (3) In the case of functional testing of the present invention, classification testing can be performed according to the characteristics of different IP cores, which is flexible and efficient. At the same time, accurate testing can be performed according to the software prediction area to reduce test errors.

[0054] (4) The test board of the present invention uses a dual power supply method of LDO and programmable power supply to meet the power supply requirements of different experimental environments, overcome the problem of large power ripple of the programmable power supply, and solve the problem of low power supply accuracy of LDO.

[0055] (5) The status monitoring and control host computer of the present invention adopts one-key window-type operation and is easy to debug. It can automatically identify the type of IP core to be tested and select the bit stream of different addresses in DDR. It can store the comparison of high-speed data transmission, record the bit error rate, record the current, voltage transient and jump waveform, and provide convenience for subsequent research.

[0056] (6) The present invention sets upper and lower thresholds for current and voltage, and also sets a data transmission bit error rate threshold. When the set threshold is exceeded, automatic recording and warning are issued. In addition, an automatic power-off function is set when the current exceeds the chip's tolerable current to prevent the FPGA from being damaged due to the latch effect.

[0057] (7) The present invention performs energy level equivalent conversion and statistical processing on the test results of the laser irradiation test, which greatly improves the evaluation accuracy compared with the existing inaccurate irradiation evaluation results, and provides a reliable reference for the subsequent FPGA IP partial radiation resistance reinforcement and radiation effect protection scheme during space application. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 The present invention implements a flow chart of a method for accurate irradiation assessment of a complex IP core of an SRAM-type FPGA.

[0059] Figure 2 This is a schematic diagram of the FPGA chip radiation effect detection and positioning test system of the present invention. DETAILED DESCRIPTION

[0060] The present application is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0061] like Figure 1 As shown, in view of the limitations of the prior art in the evaluation of irradiation effects of complex IP cores of FPGAs, the present invention proposes a precise irradiation evaluation method for complex IP cores of SRAM-type FPGAs, including software simulation, precise laser irradiation, and heavy ion equivalent calibration. The specific steps of each stage are as follows.

[0062] 1. Steps of software simulation:

[0063] (1-1) Simulate the physical characteristics of the heavy ions to be tested and extract the physical parameters.

[0064] In some embodiments provided in this application, Geant4 software is used to simulate heavy ions. Geant4 software can provide particles existing in space and corresponding radiation environments in a relatively complete manner, and has advantages in terms of computational efficiency and three-dimensional structure simulation. The final state of the particle can be determined according to the energy range, particle type and material model. Here, high-energy particle Bi ions are selected as simulation particles.

[0065] Heavy ion simulation includes the following parts: designing the device geometry and irradiation environment model, determining the response of the covering material structure and material-sensitive components, and establishing the Geant4 geometry model; setting the particle trajectory and angle of ions passing through the electromagnetic region of the material to be tested, which can be set by coding in the Geant4 software; selecting the ion transport model related to heavy ion simulation to simulate the physical process of ion reaction; finally, designing other parameters of the software simulation and processing the data port interaction link, analyzing and capturing simulation data at different levels of detail and refinement.

[0066] (1-2) Combine heavy ion physical parameters to simulate FPGA device units.

[0067] The TCAD (technology computer aided design) semiconductor process simulation and device simulation tool is used to perform device-level simulation on FPGA, and the Geant4 geometric model in step (1-1) needs to be converted into a TCAD model. The present invention uses a geometric description markup language GDML to convert the Geant4 geometric model into a TCAD model. First, the definition, material, entity, structure and other information of the Geant4 geometric model file are saved in a data structure, a basic body described by a boundary representation method is created, and the basic body processed by Boolean operation is rotated and translated to obtain a TCAD model corresponding to the Geant4 geometric model.

[0068] Here, we take the 28nm process as an example. First, we write the process simulation file and the device structure description file to determine the material characteristics under the standard process. This part of the operation includes the ion implantation part. The ion simulation data obtained in (1-1) is implanted to complete the process simulation. Then, pisces is used to calculate the electrical behavior based on the device structure obtained by the process simulation, and Slivaco's SPICE model parameter extraction tool Utmost IV is used to extract the device parameters that meet the BSIM standard. This tool uses a complete SPICE simulation engine to fit the curve, and can use the automatically generated overlay map for visual inspection, and then calculate the curve fitting error for model calibration to ensure that the device characteristics obtained in the simulation are completely matched with the extracted model in the subsequent SPICE simulation stage. After extracting the device parameters, a spice netlist is generated, which also includes the ion implantation parameters.

[0069] (1-3) Perform circuit simulation on the SPICE netlist to locate abnormal areas of electrical parameters.

[0070] The spice netlist obtained in (1-2) is used for circuit-level simulation using Hspice. The 28nm process library is selected, and the basic functional units of the IP core are mapped on it to verify the transient state of the electrical parameters when the function is working, so as to determine the electrical parameter jump and abnormal area, which is preliminarily predicted to be the radiation sensitive area.

[0071] 2. Steps of laser precision test

[0072] (2-1) Perform hole processing on the sensitive area obtained by software simulation of the FPGA chip to expose the FPGA chip substrate.

[0073] According to the preliminary prediction results of step 1, the sensitive area is located at about 0.8mm 2 Since there are many types of IP cores in FPGA, each type of IP core test is performed on each opening of the FPGA chip.

[0074] (2-2) Place the processed FPGA chip on the FPGA irradiation test board. The test board provides the power supply module necessary for the FPGA chip to be tested and the data transmission module for communication with the host computer, so that the FPGA can operate normally according to the test content after power-on.

[0075] (2-3) Configure the FPGA chip code stream burning, make sure the FPGA clock and data transmission functions are normal, and make the FPGA chip run normally after power-on.

[0076] (2-4) Install the laser light source on the 3D scanning work platform, aim it at the FPGA chip processing area, and perform precise scanning and irradiation.

[0077] (2-5) Monitor the three electrical parameters of working current, voltage, and data transmission bit error rate. If there is a parameter jump, or the value is too high or too low, it is considered that the FPGA area to be tested has an irradiation effect, and the test results are recorded.

[0078] The method for judging current and voltage anomalies is as follows: When the FPGA chip is in normal operation, the current and voltage are stable within a small fluctuation range. The set fluctuation threshold is 1.5 times the maximum current or voltage value under non-irradiation conditions. Once exceeded, it is judged as an electrical parameter abnormality.

[0079] Regarding the judgment of the data transmission bit error rate, the IP core's bit error rate is no higher than 1e-12 under non-irradiation conditions. Taking into account the extreme conditions of high and low temperature, vacuum, and high and low air pressure, the maximum bit error rate is 1e-9. During the irradiation test, if the bit error rate is higher than 1e-9, it is judged that the bit error rate is abnormal.

[0080] The above method effectively solves the problem of low efficiency in laser irradiation tests on the entire chip, and also solves the problem of low accuracy in large-area laser irradiation tests. By performing precise laser testing on the area predicted by the software, it is convenient to further refine the irradiation-sensitive area and obtain accurate laser irradiation evaluation results.

[0081] 3. Steps of laser equivalent correction

[0082] (3-1) Analyze the differences in the ionization principles of the laser light source and the heavy ions to be simulated, and derive the energy level difference formula.

[0083] (3-2) Determine various parameters according to the irradiation environment and derive the energy level equivalent compensation formula.

[0084] (3-3) Perform equivalent compensation correction on the test results.

[0085] (3-4) The correction result is fitted by the least square method to generate the Bezier curve.

[0086] In order to ensure smooth progress of radiation evaluation, the present invention also proposes an FPGA chip radiation effect detection and positioning test system.

[0087] like Figure 2 As shown, the FPGA chip radiation effect detection and positioning test system includes a state monitoring control device and an FPGA radiation test board.

[0088] The status monitoring control host computer can remotely control the FPGA irradiation test board through the C# software interface, and can power on, configure, and monitor the electrical parameters of the FPGA test chip with one click, and draw current and voltage curves on the software interface; at the same time, it can interact with the FPGA main control chip, monitor the data transmission status during work in real time, and automatically calculate the bit error rate. At the same time, any data can be saved in the background based on time.

[0089] The FPGA irradiation test board can ensure that the FPGA under test completes the test function and sends the FPGA test status to the status monitoring and control host computer. The FPGA irradiation test board can include the FPGA under test chip, FPGA main control chip, configuration module, DDR module, reset module, clock module, power supply system, and communication module.

[0090] The power supply system supplies power to the core, AUX, IO, and IP of the FPGA through LDO or program-controlled power supply. The DDR module is used to store FPGA test vectors. After power-on, the test vectors will be burned into the FPGA to be tested by configuring the FLASH module. The configuration module configures the functional test program stored in the DDR after power-on. After the FPGA chip to be tested is powered on, the test vector in the DDR module is read and run. The FPGA master chip cooperates with the functional test of the FPGA chip to be tested, and sends the functional test results obtained after the test program is run to the status monitoring and control host computer. The FPGA master chip can be used to monitor the working current, voltage, and data transmission bit error rate of the FPGA chip to be tested. The reset module is connected to the communication module and the FPGA to be tested, and controls the FPGA to be tested to reset through the host computer operation. The clock circuit connects the FPGA master chip and the FPGA chip to be tested through the circuit board line, and provides a clock signal for the FPGA master chip and the FPGA chip to be tested to implement the test function. The communication module realizes the data transmission between the various test data of the FPGA to be tested to the monitoring host computer through the USB port, and at the same time realizes the control of the power supply and reset of the FPGA by the monitoring host computer.

[0091] By applying the above-mentioned FPGA chip radiation effect detection and positioning test system and software simulation, as well as the laser precision test detection method, reliable experimental conditions and mature test processes can greatly improve the radiation evaluation conclusions of FPGA complex IP, improve the reliability of the IP core part of the FPGA chip in space applications, and guide the subsequent improvement of FPGA reinforcement processing or radiation-resistant design of IP core.

[0092] The parts of the present invention that are not described in detail belong to the common knowledge of those skilled in the art. Although the present invention is disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be based on the scope defined by the claims of the present invention.

Claims

1. A method for evaluating an IP core for an SRAM-type FPGA, characterized in that: include: (1-1) Simulate heavy ions and FPGA devices to determine the preliminary prediction results of the IP core radiation sensitive area; (1-2) Use laser to perform scanning test on the preliminary prediction results of the sensitive area determined in (1-1) to determine the accurate prediction results of the sensitive area; (1-3) Perform single-particle effect correction on the accurate prediction results of the sensitive areas obtained in (1-2) to determine the IP core evaluation results; The specific steps of simulation in step (1-1) include: (2-1) Use Geant4 software to simulate the heavy ions to be tested and extract physical characteristic parameters; (2-2) Combined with the heavy ion physical properties obtained in (2-1), the device-level TCAD simulation of the corresponding process of the SRAM type FPGA to be tested is performed to obtain the device-level radiation effect simulation results; (2-3) Convert the TCAD simulation results obtained in (2-2) into a spice netlist, use Hspice to perform circuit simulation including radiation effects, and determine the preliminary prediction results of the IP core radiation sensitive area; The specific steps of the scanning test in step (1-2) include: (3-1) Based on the preliminary prediction results of the IP core radiation sensitive area, cut the back of the area to expose the FPGA substrate; (3-2) Install the FPGA to be tested on an FPGA test board, which provides power supply signals, clock signals and data communication functions for the FPGA chip to be tested; (3-3) Power on the FPGA chip, aim the laser at the sensitive area of ​​the opening, and perform a scanning test; (3-4) Monitor the working current, voltage, and data transmission bit error rate. When any electrical parameter changes, or the value is too high or too low, it is considered that the FPGA area to be tested has a fault.

2. The method according to claim 1, characterized in that Step (2-1) specifically includes: Design device geometry and irradiation environment model, determine the response of cover material structure and material sensitive components, and establish Geant4 geometry model; Setting the particle trajectory and angle of ions passing through the electromagnetic region of the material to be tested can be set by coding in the Geant4 software; Select the ion transport model related to heavy ion simulation, simulate the physical process of ion reaction, and analyze and extract the physical characteristic parameters.

3. The method according to claim 2, characterized in that Step (2-2) specifically includes: Convert the Geant4 geometry model in step (2-1) into a TCAD model; Pisces is used to calculate the electrical behavior based on the device structure obtained from process simulation, and Slivaco's SPICE model parameter extraction tool Utmost IV is used to extract device parameters that meet the BSIM standard and generate a SPICE netlist.

4. The method according to claim 1, characterized in that: The opening accuracy is controlled at 0.8mm 2 .

5. The method according to claim 1 or 4, characterized in that: The FPGA test board is used to evaluate the FPGA chip to be tested. The FPGA test board includes: an FPGA main control chip, a configuration module, a DDR module, a reset module, a clock module, a power supply system, and a communication module; wherein, The power supply system is used to realize power supply; The DDR module is used to store FPGA test vectors. After power-on, the test vectors will be burned into the FPGA to be tested by configuring the FLASH module. After the FPGA chip to be tested is powered on, the test vectors in the DDR module will be read and run. Configuration module, configure the functional test program stored in DDR after power-on; The FPGA master chip cooperates with the functional test of the FPGA chip to be tested, and sends the functional test results obtained after the test program is run to the monitoring and control equipment; The reset module is connected to the communication module and the FPGA to be tested, and controls the FPGA to be tested to reset by monitoring and controlling the operation of the device; The clock circuit connects the main control and the FPGA chip to be tested through the circuit board line, and provides a clock signal when the main control and the FPGA chip to be tested implement the test function; The communication module transmits the test data of the FPGA to the monitoring and control device through the USB port, and controls the power supply and reset of the FPGA by the monitoring and control device.

6. The method according to claim 1, characterized in that The specific steps for correcting the test data in steps (1-3) are as follows: (4-1) Analyze the difference between the ionization principle of the laser light source and the heavy ion to be simulated, and derive the energy level difference formula; (4-2) Determine various parameters according to the irradiation environment and derive the energy level equivalent compensation formula; (4-3) Perform equivalent compensation correction on the test results; (4-4) The correction result is fitted by the least square method to generate the Bezier curve.

7. An FPGA test board, characterized in that: The FPGA test board is used to evaluate the FPGA chip to be tested. The FPGA test board includes an FPGA main control chip, which is used to monitor the working current, voltage, and data transmission bit error rate of the FPGA chip to be tested during the irradiation test, cooperate with the functional test of the FPGA chip to be tested, and send the functional test results obtained after the test program is run to the monitoring and control device; The FPGA test board also includes: a configuration module, a DDR module, a reset module, a clock module, a power supply system, and a communication module; wherein, The power supply system is used to realize power supply; The DDR module is used to store FPGA test vectors. After power-on, the test vectors will be burned into the FPGA to be tested by configuring the FLASH module. After the FPGA chip to be tested is powered on, the test vectors in the DDR module will be read and run. Configuration module, configure the functional test program stored in DDR after power-on; The reset module is connected to the communication module and the FPGA to be tested, and controls the FPGA to be tested to reset by monitoring and controlling the operation of the device; The clock circuit connects the main control and the FPGA chip to be tested through the circuit board line, and provides a clock signal when the main control and the FPGA chip to be tested implement the test function; The communication module transmits the test data of the FPGA to the monitoring and control device through the USB port, and controls the power supply and reset of the FPGA by the monitoring and control device. The area of ​​the FPGA chip to be tested that exposes the FPGA substrate is the sensitive area to be tested, and the sensitive area to be tested is determined by simulating heavy ions and FPGA devices. The irradiation test process includes aiming the laser at the sensitive area to be tested for scanning, while monitoring the working current, voltage, and data transmission bit error rate; The specific steps of the simulation include: (2-1) Use Geant4 software to simulate the heavy ions to be measured and extract physical characteristic parameters; (2-2) Combined with the heavy ion physical properties obtained in (2-1), the device-level TCAD simulation of the corresponding process of the SRAM type FPGA to be tested is performed to obtain the device-level radiation effect simulation results; (2-3) Convert the TCAD simulation results obtained in (2-2) into a spice netlist, use Hspice to perform circuit simulation including radiation effects, and determine the preliminary prediction results of the IP core radiation sensitive area.

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