An efficient core-on-chip network bridge connection circuit

Abstract

The present invention discloses an efficient core-on-chip network bridge connection circuit, including two discrete, support multiple data interface bit widths, support key instruction detection of the first channel and the second channel, the first channel is used for the communication from the core to the on-chip network, the second channel is used for the communication from the on-chip network to the core; the first channel includes a buffer, a translator and a transmitter connected in sequence, the buffer temporarily stores memory requests, the translator re-encodes the requests in the buffer, and the transmitter packages the re-encoded requests of the translator into a network packet format and sends them to the on-chip network in sequence; the second channel includes a receiver and a decoder connected to each other, the receiver is responsible for receiving the network packet and buffering, and assembling it into a msg format after receiving it completely, and the decoder extracts sub-information from the msg format, and encodes it according to the kernel interface and returns it to the kernel. The bridge structure can not only efficiently realize communication on both sides, but also support multiple kernel interfaces, and also support key instruction detection priority transmission.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to an efficient core-on-chip network bridge connection circuit. Background Art

[0002] With the development of integrated circuit technology, simply increasing the clock frequency will make it difficult to control the power consumption of the chip, and multi-core and many-core processors have become a development trend. Multi-core processors bring users more powerful computing performance and can also meet the user's requirements for multi-tasking and multi-tasking computing environments.

[0003] Traditional multi-core communication uses bus technology. However, as the number of cores integrated in the chip continues to increase, the bus-based system-on-chip will gradually find it difficult to meet the growing computing needs due to its poor scalability, low average communication efficiency, and single clock synchronization. Network-on-Chip (NoC) is a new communication method for multi-core systems on a chip. Due to its concurrent and non-blocking exchange characteristics, its performance is significantly better than that of traditional bus-based systems.

[0004] However, there are compatibility issues between the on-chip network and the original kernel interface and protocol. The multi-core processor platform design such as OpenPiton has restrictions on the kernel interface bit width, and high-channel kernels are difficult to embed into the multi-core framework, which limits the scalability and heterogeneity of the on-chip network. At the same time, data packaging, buffering, synchronization and interface increase latency and reduce the communication efficiency of the on-chip network. Summary of the invention

[0005] In order to overcome the compatibility issues between the on-chip network and the original kernel interface and protocol as well as the high latency problem, the present invention provides an efficient kernel-on-chip network bridge connection structure, which can not only efficiently realize communication between the two sides, support multiple kernel interfaces, but also support key instruction detection and priority sending.

[0006] The technical solution adopted by the present invention to solve its technical problem is:

[0007] The present invention firstly provides an efficient core-on-chip network bridge connection structure, which includes two separate first channels and second channels that support multiple data interface bit widths and key instruction detection, wherein the first channel is used for core-to-on-chip network communication, and the second channel is used for on-chip network-to-core communication;

[0008] The first channel comprises a buffer, a translator and a transmitter connected in sequence, the buffer temporarily stores kernel requests, the translator re-encodes the requests in the buffer, and the transmitter packages the requests re-encoded by the translator into a network packet format and sends them to the on-chip network in sequence;

[0009] The second channel includes a receiver and a decoder connected to each other. The receiver is responsible for receiving and buffering network packets. After receiving the complete network packets, the receiver assembles the network packets and sends them to the decoder. The decoder extracts sub-information from the assembled network packet data, encodes it according to the kernel interface, and returns it to the kernel.

[0010] As a preferred solution of the present invention, the buffer of the first channel temporarily stores the request from the kernel, indicates the location of the storage request through a write pointer, indicates the location of the read storage request through a read pointer, and assigns a value to the valid bit of each location to indicate whether the request can be sent;

[0011] The read and write control modules in the buffer control the increase and decrease of the write pointer and the read pointer, as well as when to send a request to the next module; after receiving a new request, the write pointer is incremented by 1, and the valid bit of the position indicated by the write pointer is assigned to 1; after receiving a new reply, that is, the previous request has been successfully sent through the transmitter, the valid bit of the position indicated by the read pointer is assigned to 0, and then the read pointer is incremented by 1.

[0012] Preferably, when the request from the kernel is a cache consistency related instruction, the read pointer is reduced by 1 and written to the location indicated by the read pointer so that the instruction data does not affect other data, ensuring that the instruction data can be sent first when the on-chip network is idle.

[0013] Preferably, when the request from the kernel is a storage (store) instruction of a high-width kernel interface, it is split; assuming that the data interface of the buffer is n bits, if the kernel data interface is m bits, m=n*d, d is an integer, then d times of data are obtained from the kernel in sequence, temporarily stored in the buffer as d sub-instructions, and sent in sequence.

[0014] As a preferred solution of the present invention, when the on-chip network is idle, the transmitter sends fixed-bit-width network packets to the on-chip network in sequence, and the network packet format includes length, type, destination, cache type, and data information.

[0015] As a preferred solution of the present invention, the receiver receives a network packet with a fixed bit width when the kernel is idle, parses the network packet length through the information in the header, cooperates with the index to indicate the buffer storage location, and controls the receiving process until the information is complete.

[0016] As a preferred solution of the present invention, the decoder parses the network packet format into the kernel interface format, and returns the information to the kernel when the kernel is idle.

[0017] Compared with the prior art, the present invention uses two separate parallel channels for data conversion in two directions. The first channel is responsible for receiving the kernel's request, converting it into a network packet format and sending it to the on-chip network. In the first channel, the buffer, translator, and transmitter are connected in sequence. When the kernel issues a memory request, the buffer first temporarily stores the request. When the on-chip network is found to be idle, the request in the buffer is re-encoded by the translator, and the transmitter is packaged into a network packet format and sent to the on-chip network. The second channel is responsible for receiving the on-chip network packet, converting it into a reply message and returning it to the kernel. In the second channel, the receiver and translator are connected in sequence. When the on-chip network returns, the receiver first temporarily stores the complete network packet. When the kernel is idle, the complete data is re-encoded by the translator and returned to the kernel. By setting two separate channels and buffers, it is ensured that the kernel and the on-chip network are not blocked, and efficient connection is achieved. For a high-bit-width kernel interface, the buffer of the first channel can split its data and address and send it multiple times; the receiver of the second channel can splice the low-bit-width network data and return it to the high-bit-width kernel. For cache consistency related instructions, after being detected in the buffer of the first channel, the instructions temporarily stored in its memory can be reordered so that the cache consistency instructions are sent first.

[0018] The present invention adopts two discrete channels, overcoming the problem of low communication efficiency of the single-channel connection structure in the prior art, thereby achieving the effect of efficient communication between the core and the on-chip network.

[0019] The present invention adopts a method of detecting cache consistency instructions and reordering buffer temporarily stored instructions, thereby overcoming the problem in the prior art that key instructions cannot be sent in time, thereby achieving the effect of key instruction detection;

[0020] The present invention adopts a method of splitting and sequentially sending storage read instructions for a high-bit-width kernel interface, thereby overcoming the problem of mismatch between the kernel and on-chip network bit widths in the prior art, thereby achieving the effect of supporting multiple kernel bit widths. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a circuit schematic diagram of the core-on-chip network bridge connection structure of the present invention;

[0022] Figure 2 yes Figure 1 The control flow chart of the transmitter in the figure;

[0023] Figure 3 yes Figure 1 Control flow diagram of the receiver. DETAILED DESCRIPTION

[0024] The present invention is further described and illustrated below in conjunction with specific embodiments. The embodiments are merely exemplary of the present disclosure and do not define the scope of limitation. The technical features of each embodiment of the present invention may be combined accordingly without conflicting with each other.

[0025] like Figure 1 As shown, the connection relationship and control signals of each device of the bridge connection structure of the present invention are shown. The core-on-chip network (NOC) bridge connection structure of the present invention includes two separate first channels and second channels that support multiple data interface bit widths and key instruction detection. The first channel is used for communication from the core to the on-chip network, and the second channel is used for communication from the on-chip network to the core.

[0026] The first channel comprises a buffer, a translator and a transmitter connected in sequence, the buffer temporarily stores kernel requests, the translator re-encodes the requests in the buffer, and the transmitter packages the requests re-encoded by the translator into a network packet format and sends them to the on-chip network in sequence;

[0027] The second channel includes a receiver and a decoder connected to each other. The receiver is responsible for receiving and buffering network packets. After receiving the complete network packets, the receiver assembles the network packets and sends them to the decoder. The decoder extracts sub-information from the assembled network packet data, encodes it according to the kernel interface, and returns it to the kernel.

[0028] The buffer temporarily stores requests from the kernel. The pointer indicates the location of the storage request, the read pointer indicates the location of the read storage request, and the valid bit of each location is assigned a value to indicate whether the request can be sent. The read and write control module controls the increase and decrease of the write pointer and the read pointer, as well as when to send requests to the next level. After receiving a new request, the write pointer is incremented by 1, and the valid bit of the location indicated by the write pointer is assigned to 1. After receiving a new reply, that is, the previous request has been successfully sent through the transmitter, the valid bit of the location indicated by the read pointer is assigned to 0, and then the read pointer is incremented by 1.

[0029] For keyword instructions (such as cache coherence related instructions), the read pointer is reduced by 1 and written to the read pointer position. This ensures that the instruction data does not affect other data and that the instruction data can be sent first when the on-chip network is idle.

[0030] For the store instruction of the high-bit width kernel interface, it can be split in the buffer. The data interface of the buffer is n bits. If the kernel data interface is m bits (m=n*d, d is an integer), then d data are obtained from the kernel in sequence, temporarily stored in the buffer as d sub-instructions, and sent in sequence.

[0031] The translator is responsible for mapping the kernel's request into a message of a specific format. The data size, address, destination and other information can be directly mapped, and the message type, length and cache category need to be classified and processed according to the type of request.

[0032] The sender is responsible for sending messages in network packet format. Each request follows the format of "header-data-...-data" and is sent in sequence with a fixed bit width. The sender includes a sending control module and an encapsulating network packet module. The sending control module controls how many packets each request is sent through. The encapsulating network packet module encapsulates the message into a fixed bit width network packet format, where the header has a special format and all bits of the data packet are data.

[0033] The receiver is responsible for receiving network packets and buffering them. After receiving them completely, they are assembled into messages of a specific format. The length of the network packet is parsed through the information in the header, and the index indicates the receiving storage location to control the complete receiving process.

[0034] The decoder is responsible for extracting sub-information such as address, cache type, return data, etc. from the spliced ​​message, encoding it according to the kernel interface, and returning it to the kernel.

[0035] like Figure 2 As shown, Figure 1 The controller logic of the transmitter in the middle. The transmitter is in the idle state initially. After receiving the signal from the buffer that it can be sent, if the on-chip network is not ready, the transmitter enters the waiting state. If the on-chip network is ready, it enters the sending state and continuously sends fixed-bit-width network packets to the on-chip network. The number of transmissions is determined according to the packet length determined by the translator. After the transmission is completed, the transmitter returns to the idle state.

[0036] like Figure 3 As shown, Figure 1 The controller logic of the receiver is shown in the figure. The receiver is initially in the idle state. If it receives a valid signal from the on-chip network data, it enters the receiving state. It continuously receives fixed-bit-width network packets through the length information in the packet header. After receiving the complete packet, it enters the waiting for response state. After the core receives the return information, the receiver returns to the idle state.

[0037] The above-mentioned embodiments only express several implementation methods of the present invention, and the description is relatively specific and detailed, but it cannot be understood as limiting the scope of the present invention. For ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. An efficient core-on-chip network bridge connection circuit, characterized in that: It includes two separate first channels and second channels that support multiple data interface bit widths and key instruction detection, the first channel is used for communication from the core to the on-chip network, and the second channel is used for communication from the on-chip network to the core; The first channel comprises a buffer, a translator and a transmitter connected in sequence, the buffer temporarily stores kernel requests, the translator re-encodes the requests in the buffer, and the transmitter packages the requests re-encoded by the translator into a network packet format and sends them to the on-chip network in sequence; The buffer temporarily stores requests from the kernel, indicates the location of the storage request through the write pointer, indicates the location of the read request through the read pointer, and assigns a value to the valid bit of each location to indicate whether the request can be sent; the read and write control module in the buffer controls the increase and decrease of the write pointer and the read pointer, and when to send a request to the next module; after receiving a new request, the write pointer is increased by 1, and the valid bit of the location indicated by the write pointer is assigned to 1; after receiving a new reply, that is, the previous request has been successfully sent through the transmitter, the valid bit of the location indicated by the read pointer is assigned to 0, and then the read pointer is increased by 1; for a keyword instruction, the read pointer is reduced by 1, and it is written to the read pointer position; The sender is responsible for sending messages in the network packet format. Each request follows the format of "header-data-...-data" and is sent in sequence with a fixed bit width. The initial sender is in an idle state. After receiving the sendable signal from the buffer, if the on-chip network is not ready, the sender enters a waiting state. If the on-chip network is ready, it enters the sending state and continuously sends fixed-bit-width network packets to the on-chip network. The number of transmissions is determined according to the packet length determined by the translator. After the transmission is completed, the transmitter returns to the idle state. For storage instructions of high-bit width kernel interface, they are split in the buffer; the data interface of the buffer is n bits, if the kernel data interface is m bits, m=n*d, d is an integer, then d times of data are obtained from the kernel in sequence, temporarily stored in the buffer as d sub-instructions, and sent in sequence; The second channel includes a receiver and a decoder connected to each other, the receiver is responsible for receiving network packets and buffering them, and after receiving the complete network packets, assembling the network packets and sending them to the decoder; The decoder extracts sub-information from the assembled network packet data, encodes it according to the kernel interface, and returns it to the kernel; The receiver is responsible for receiving network packets and buffering them. After receiving the complete packets, it assembles them into messages of a specific format. It parses the length of the network packet through the information in the header, and uses the index to indicate the receiving storage location to control the complete receiving process. The initial receiver is in an idle state. If it receives a signal that the on-chip network data is valid, it enters the receiving state. It continuously receives fixed-bit-width network packets through the length information in the packet header. After receiving the complete message, it enters the waiting state for response; after the kernel receives the return information, the receiver returns to the idle state.

2. The core-on-chip network bridge connection circuit according to claim 1, characterized in that: The decoder parses the network packet format into a kernel interface format and returns the information to the kernel when the kernel is idle.

Images