Display panel and display device

Abstract

This application discloses a display panel and display device, relating to the field of display technology. It solves the problem that removing a portion of the organic layer in the non-display area exposes some signal lines in subsequent processing steps, preventing oxidation or corrosion of the exposed signal lines and improving the reliability of the display panel. The display panel includes: a substrate layer comprising a display area and a non-display area; a first metal layer disposed on one side of the substrate layer; a buffer insulating layer disposed on the side of the first metal layer away from the substrate layer; a pixel driving device disposed in the display area, located on the side of the buffer insulating layer away from the first metal layer; and a driving signal line disposed in the non-display area, located on the first metal layer, electrically connected to the pixel driving device. The orthographic projection of the driving signal line on the substrate layer falls into the orthographic projection of the buffer insulating layer on the substrate layer. The driving signal line is used to transmit display driving signals.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] Currently, with the continuous development of display technology, the requirements for the reliability and display effect of display panels are becoming increasingly stringent. Typically, display panels include organic and inorganic layers. The organic layer easily forms channels for external water and oxygen erosion, leading to the corrosion of components or layers within the display area, affecting the reliability and lifespan of the display panel. Therefore, in the non-display areas surrounding the display area, the corresponding organic film layers are removed to cut off the water and oxygen intrusion channels. However, the removal of some organic layers in the non-display areas exposes some signal lines in subsequent processing steps, making them susceptible to oxidation or corrosion, thus affecting the reliability of the signal lines. Summary of the Invention

[0003] This application provides a display panel and display device that can solve the problem that the removal of some organic layers in the non-display area will cause exposure of some signal lines in subsequent process steps. It can avoid the exposure of signal lines being oxidized or corroded, thereby improving the reliability of the display panel.

[0004] A first aspect of this application provides a display panel, including:

[0005] A substrate layer, the substrate layer including a display area and a non-display area;

[0006] A first metal layer is disposed on one side of the substrate layer;

[0007] A buffer insulating layer is disposed on the side of the first metal layer away from the substrate layer;

[0008] A pixel driving device is provided in the display area, and the pixel driving device is located on the side of the buffer insulating layer away from the first metal layer.

[0009] A driving signal line is provided in the non-display area. The driving signal line is disposed on the first metal layer and is electrically connected to the pixel driving device. The orthogonal projection of the driving signal line on the substrate layer falls into the orthogonal projection of the buffer insulating layer on the substrate layer. The driving signal line is used to transmit display driving signals.

[0010] In some embodiments, the display panel further includes:

[0011] A signal lead, wherein the signal lead is disposed in the non-display area, and / or, the signal lead is disposed in the display area, and / or, the signal lead passes through the non-display area and the display area;

[0012] The signal lead is disposed on a conductive layer other than the first metal layer, and the driving signal line is electrically connected to the pixel driving device through the signal lead;

[0013] The buffer insulation layer is provided with a first via, and the drive signal line and the signal lead are electrically connected through the first via.

[0014] In some embodiments, the display panel further includes:

[0015] The driving circuit is electrically connected to the pixel driving device;

[0016] The driving circuit and the driving signal line are electrically connected through the signal lead.

[0017] In some embodiments, the display panel further includes:

[0018] The second metal layer is disposed on the side of the buffer insulating layer away from the first metal layer;

[0019] The pixel driving device includes a thin-film transistor, the gate of which is disposed on the second metal layer;

[0020] The signal lead is disposed on the second metal layer.

[0021] In some embodiments, the display panel further includes:

[0022] A gate insulating layer is disposed between the buffer insulating layer and the second metal layer;

[0023] The gate insulating layer is provided with a second via, which communicates with the first via. The drive signal line and the signal lead are electrically connected through the communicating first via and second via.

[0024] In some embodiments, the display panel further includes:

[0025] A passivation layer is disposed on the side of the thin-film transistor away from the substrate layer;

[0026] An organic layer is disposed on the side of the passivation layer away from the substrate layer;

[0027] The non-display area includes a bridging area and a wiring area, the drive signal line is disposed in the wiring area, and the bridging area covers the orthogonal projection of the second via on the substrate layer;

[0028] The orthographic projection of the organic layer onto the substrate covers the bridging region, and the orthographic projection of the organic layer onto the substrate does not overlap with the wiring region.

[0029] In some embodiments, the minimum distance between the boundary of the organic layer projected onto the substrate and the second via is less than or equal to the line spacing between two adjacent drive signal lines.

[0030] In some embodiments, at least two second vias are provided at a crossover point between the drive signal line and the corresponding electrically connected signal lead, the orthographic projections of the at least two second vias on the substrate layer do not overlap, and each second via corresponds to one first via;

[0031] The minimum distance between the boundary of the organic layer projected onto the substrate and the second via is greater than or equal to the hole spacing between any two second vias corresponding to the same bridging point.

[0032] In some embodiments, the first metal layer comprises a reflective metallic material;

[0033] The display area is also provided with a light-emitting device, which is disposed on the side of the pixel driving device away from the substrate layer, and the light-emitting device is electrically connected to the pixel driving device;

[0034] The orthographic projection of the light-emitting area of ​​the light-emitting device onto the substrate falls on the orthographic projection of the first metal layer onto the substrate; or...

[0035] The orthographic projection of the light-emitting area of ​​the light-emitting device onto the substrate layer does not overlap with the orthographic projection of the first metal layer onto the substrate layer.

[0036] In some embodiments, the passivation layer and the organic layer are obtained by etching the same mask.

[0037] In some embodiments, the passivation layer is provided with a third via, the organic layer is provided with a fourth via, and the third via communicates with the fourth via;

[0038] The display area is also provided with a light-emitting device, which includes a first electrode. The first electrode is electrically connected to the source or drain of the thin-film transistor through the third via and the fourth via.

[0039] The difference between the first slope angle difference and the second slope angle difference is less than or equal to 5°;

[0040] Wherein, the first slope angle difference is the difference between the slope angle of the inner wall of the third through hole and the slope angle of the inner wall of the fourth through hole, and the second slope angle difference is the difference between the slope angle of the passivation layer boundary and the slope angle of the organic layer boundary corresponding to the non-display area.

[0041] In some embodiments, the source and / or drain of the thin-film transistor are disposed on the second metal layer.

[0042] In some embodiments, the first metal layer comprises a light-shielding metal material;

[0043] The orthogonal projection of the channel of the thin-film transistor onto the substrate falls into the orthogonal projection of the first metal layer onto the substrate.

[0044] In some embodiments, the non-display area includes an electrostatic discharge (ESD) protection area, and an ESD protection circuit is provided within the ESD protection area;

[0045] The passivation layer's orthogonal projection onto the substrate covers the electrostatic protection area.

[0046] A second aspect of this application provides a display device, comprising:

[0047] The display panel as described in the first aspect.

[0048] The display panel provided in this application embodiment features a first metal layer disposed between a substrate layer and pixel driving devices. Driving signal lines are disposed on the first metal layer. A buffer insulating layer is also disposed on the side of the first metal layer away from the substrate layer. The orthogonal projection of the driving signal lines onto the substrate layer falls into the orthogonal projection of the buffer insulating layer onto the substrate layer, thus covering the driving signal lines. In subsequent process manufacturing, the buffer insulating layer protects the driving signal lines, solving the problem of exposed driving signal lines being oxidized or corroded, thereby improving the reliability and display effect of the display panel. Furthermore, since the driving signal lines are disposed on the first metal layer and protected by the buffer insulating layer, the display panel provided in this application embodiment is compatible with processes where organic and inorganic layers share a mask, compatible with production solutions that reduce production costs, and compatible with structural solutions that cut off the water-oxygen erosion channels of the organic layer in non-display areas. Therefore, the display panel provided in this application embodiment can achieve a low-cost production solution that uses a shared mask and does not require the use of a halftone mask, as well as a structural solution that cuts off the water and oxygen channels in the inorganic layer. It can also solve the problem of exposed driving signal lines being oxidized or corroded, thereby improving the reliability and display effect of the display panel. Attached Figure Description

[0049] Figure 1 A schematic structural diagram of a display panel provided in an embodiment of this application;

[0050] Figure 2 A partial structural diagram of a display area and a non-display area is provided in an embodiment of this application;

[0051] Figure 3A schematic structural diagram of another display panel provided in an embodiment of this application;

[0052] Figure 4 A schematic structural diagram of another display panel provided in an embodiment of this application;

[0053] Figure 5 This is a partial structural diagram of another display area and non-display area provided in an embodiment of this application;

[0054] Figure 6 A schematic diagram of a cross-sectional structure of a cross-connection is provided in an embodiment of this application;

[0055] Figure 7 A schematic diagram of the connection structure between a drive signal line and a signal lead provided for the implementation of this application;

[0056] Figure 8 This is a partial structural diagram of another display area and non-display area provided in an embodiment of this application;

[0057] Figure 9 This is a schematic diagram of another connection structure between a drive signal line and a signal lead provided in an embodiment of this application;

[0058] Figure 10 This is a partial structural diagram of a display area provided in an embodiment of this application;

[0059] Figure 11 This is a schematic structural diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0060] To better understand the technical solutions provided in the embodiments of this specification, the technical solutions of the embodiments of this specification will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of this specification and the specific features in the embodiments are detailed descriptions of the technical solutions of the embodiments of this specification, rather than limitations on the technical solutions of this specification. In the absence of conflict, the embodiments of this specification and the technical features in the embodiments can be combined with each other.

[0061] In this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The term "two or more" includes two or more cases.

[0062] Currently, with the continuous development of display technology, the requirements for the reliability and display effect of display panels are becoming increasingly stringent. Typically, display panels include organic and inorganic layers. The organic layer easily forms channels for external water and oxygen erosion, leading to the corrosion of components or layers within the display area, affecting the reliability and lifespan of the display panel. Therefore, in the non-display areas surrounding the display area, the corresponding organic film layers are removed to cut off the water and oxygen intrusion channels. However, the removal of some organic layers in the non-display areas exposes some signal lines in subsequent processing steps, making them susceptible to oxidation or corrosion, thus affecting the reliability of the signal lines.

[0063] In view of this, the present application provides a display panel and display device that can solve the problem that the removal of some organic layers in the non-display area will cause exposure of some signal lines in subsequent process steps, and can avoid oxidation or corrosion of exposed signal lines, thereby improving the reliability of the display panel.

[0064] A first aspect of this application provides a display panel. Figure 1 A schematic structural diagram of a display panel provided in an embodiment of this application; Figure 2 This is a partial structural diagram of a display area and a non-display area provided in an embodiment of this application. For example... Figure 1 and Figure 2As shown, the system includes a substrate layer 100, a first metal layer 200, and a buffer insulating layer 300. The substrate layer 100 includes a display area 101 and a non-display area 102. Exemplarily, the substrate layer 100 can be a rigid substrate, such as glass, or a flexible substrate, such as a polyimide substrate. Exemplarily, the non-display area 102 can be disposed around the periphery of the display area 101. The first metal layer 200 is disposed on one side of the substrate layer 100; the buffer insulating layer 300 is disposed on the side of the first metal layer 200 away from the substrate layer 100. Exemplarily, the buffer insulating layer 300 can include at least one of silicon nitride and silicon oxide, and can also include other insulating materials; however, this embodiment does not specifically limit the scope of the invention. A pixel driver device 400 is disposed within the display area 101, and the pixel driver device 400 is located on the side of the buffer insulating layer 300 away from the first metal layer 200. A drive signal line 210 is disposed within the non-display area 102, and the drive signal line 210 is disposed on the first metal layer 200 and electrically connected to the pixel driver device 400. The drive signal line 210 is used to transmit display drive signals, and the orthographic projection of the drive signal line 210 on the substrate layer 100 falls on the orthographic projection of the buffer insulating layer 300 on the substrate layer 100. Exemplarily, the display drive signals transmitted by the drive signal line 210 may include gate signals, data signals, frame start signals, clock signals, reset signals, high-level signals, low-level signals, etc., which are not listed here. Exemplarily, the first metal layer 200 may be used as a light-shielding layer, reflective layer, or other wiring functional film layer of the display panel; this embodiment does not specifically limit its use.

[0065] It should be noted that the display panel provided in this application embodiment may include a liquid crystal display panel, an organic light-emitting display panel, an LED display panel, or a laser display panel, etc., and this application embodiment does not specifically limit it. For example, the pixel driving device 400 can be used to drive the liquid crystal to rotate, thereby controlling the transmittance of the backlight and realizing image display. The pixel driving device 400 can drive the light-emitting device to emit light for image display.

[0066] It should be noted that, Figure 1 The drive signal lines 210 shown are distributed on the bottom, left, and right bezels of the display panel. The distribution of the drive signal lines 210 on the top bezel is not shown. Figure 1 The distribution of the drive signal lines 210 is only illustrative, and the number of drive signal lines 210 is also illustrative. This application does not impose specific limitations on the embodiments.

[0067] It should be noted that, Figure 2 The diagram illustrates a partial structure of the display panel. The number of drive signal lines 210 and the number of pixel drive devices 400 are illustrative and are not intended to limit the specific implementation of this application.

[0068] It should be noted that with the continuous development of display technology, in order to reduce production costs, the same mask is often used to pattern different film layers. For example, inorganic and organic layers can share a mask to set the patterned structure. However, organic layers are prone to forming channels for external water and oxygen erosion, which can lead to the corrosion of components or film layers within the display area, affecting the lifespan of the display panel. Therefore, the corresponding organic film layers are removed in the non-display areas surrounding the display area to cut off the water and oxygen intrusion channels. However, because the mask is shared, the inorganic layer is also removed in the non-display areas where the organic film layers are removed, resulting in exposed signal lines. In subsequent process steps, the exposed signal lines will be oxidized or corroded, affecting the reliability of the signal lines and signal transmission performance, ultimately affecting the reliability and display effect of the display panel.

[0069] It should be noted that in some display panel designs, to balance the issues of shared mask and exposed signal lines, a halftone mask (semi-transparent mask) is usually used for the shared mask, retaining part of the inorganic layer in the non-display area. However, the cost of halftone masks is relatively high, which is still a significant burden on production costs.

[0070] To address the aforementioned issues, the display panel provided in this application embodiment includes a first metal layer 200 disposed between the substrate layer 100 and the pixel driving device 400. A driving signal line 210 is disposed on the first metal layer 200. A buffer insulating layer 300 is also disposed on the side of the first metal layer 200 away from the substrate layer 100. The orthographic projection of the driving signal line 210 onto the substrate layer 100 falls onto the orthographic projection of the buffer insulating layer 300 onto the substrate layer 100, thus the buffer insulating layer 300 covers the driving signal line 210. In subsequent manufacturing processes, the buffer insulating layer 300 can protect the driving signal line 210, solving the problem of the existing exposed driving signal line 210 being oxidized or corroded, thereby improving the reliability and display effect of the display panel. Furthermore, since the drive signal line 210 is disposed on the first metal layer 200 and can be protected by the buffer insulation layer 300, the display panel provided in this embodiment is compatible with the process of sharing a mask between the organic and inorganic layers, compatible with production solutions that reduce production costs, and compatible with structural solutions that cut off the water and oxygen erosion channels of the organic layer in the non-display area. Therefore, the display panel provided in this embodiment can achieve a low-cost production solution that uses a shared mask and does not require the use of a halftone mask, can achieve a structural solution that cuts off the water and oxygen channels of the inorganic layer, and can also solve the problem of the existing drive signal line 210 being exposed and oxidized or corroded, thereby improving the reliability and display effect of the display panel.

[0071] In some embodiments, the display panel provided in this application further includes signal leads, which are disposed on other conductive layers besides the first metal layer 200. The driving signal line 210 is electrically connected to the pixel driving device via the signal leads. A first via is provided in the buffer insulating layer 300, through which the driving signal line 210 and the signal leads are electrically connected. Since the driving signal line 210 and the signal leads are disposed on different layers, the buffer insulating layer 300 can protect the driving signal line 210.

[0072] In some embodiments, the signal lead may be located in the non-display area 102. The signal lead may also be located in the display area 101. The signal lead may also pass through the non-display area 102 and the display area 101, that is, the signal lead may be a line that spans between the display area 101 and the non-display area 102.

[0073] In some embodiments, the display panel may further include a driving circuit electrically connected to pixel driving devices. For example, the driving circuit may be electrically connected to the pixel driving devices via signal leads. The driving circuit is also electrically connected to driving signal lines via signal leads.

[0074] In some implementations, the non-display area includes a bridging area and a wiring area. The drive signal line 210 is disposed in the wiring area, and the bridging point where the drive signal line 210 and the signal lead are electrically connected across layers through the first via can be disposed in the bridging area. It should be noted that the bridging point is not a point, but can be understood as a local area.

[0075] For example, Figure 3 This is a schematic structural diagram of another display panel provided in an embodiment of this application. Figure 3 As shown, the non-display area 102 includes a wiring area 103 and a bridging area 104, with the bridging area 104 typically located close to the display area 101. Figure 3 The distribution of the bridging regions 104 shown is merely illustrative and is not intended to limit the specific implementation of this application.

[0076] For example, Figure 4 This is a schematic structural diagram of another display panel provided in an embodiment of this application. Figure 4As shown, the driving circuit 500 is electrically connected to the driving signal line 210 via signal lead 610, and the pixel driving device 400 is electrically connected to the driving circuit 500 via signal lead 610, and also electrically connected to the driving signal line 210 via signal lead 610. The driving signal line 210 and signal lead 610 are electrically connected via jumper 106. The non-display area 102 also includes a bonding area 105, which can be used to bond the driving chip. Bonding pins can be set within the bonding area 105, and these bonding pins are electrically connected to the driving signal line 210. The bonding pins and the driving signal line 210 are on different layers and can be electrically connected via insulating layer vias. Figure 4 The driving circuit 500 shown is configured as a dual-sided driving mode, but it can also be a single-sided driving mode. This application embodiment does not make specific limitations.

[0077] In some embodiments, the display panel further includes a second metal layer and a gate insulating layer. The second metal layer is disposed on the side of the buffer insulating layer 300 away from the first metal layer 200. The pixel driving device 400 includes a thin-film transistor, the gate of which is disposed on the second metal layer. The signal lead 610 is disposed on the second metal layer. The gate insulating layer is disposed between the buffer insulating layer 300 and the second metal layer. The gate insulating layer has a second via, which communicates with the first via. The driving signal line 210 and the signal lead 610 are electrically connected through the communicating first and second vias.

[0078] For example, Figure 5 This is a schematic diagram of a partial structure of the display area and non-display area provided in an embodiment of this application. (See attached diagram.) Figure 5 As shown, signal lead 610 is disposed on second metal layer 600, buffer insulating layer 300 is provided with first via 301, gate insulating layer GI is provided with second via 601, and signal lead 610 is electrically connected to drive signal line 210 through first via 301 and second via 601. Figure 5 The signal lead 610 shown is spanning the display area 101 and the non-display area 102, and is only schematic.

[0079] In some embodiments, at least two second vias 601 are provided at a bridging point 106 between the drive signal line 210 and the corresponding electrically connected signal lead 610. The orthographic projections of the at least two second vias 601 on the substrate layer 100 do not overlap, and each second via 601 corresponds to a first via 301. The more vias provided on the same bridging point 106, the better the bridging stability. However, considering space constraints, the number of bridging vias needs to be set appropriately.

[0080] For example, Figure 6 This is a schematic diagram of a cross-sectional structure of a cross-connection provided in an embodiment of this application. Figure 6As shown, the two second vias 601 in the same cross-connection 106 are set independently, that is, the two first vias 301 are also set independently. Figure 7 This is a schematic diagram illustrating the connection structure between a drive signal line and a signal lead, provided for the implementation of this application. (See attached diagram.) Figure 7 As shown, each jumper 106 is provided with two second vias 601, and the overlapping area of ​​the drive signal line 210 and the signal lead 610 constitutes the area of ​​the jumper 106.

[0081] In some embodiments, the display panel further includes a passivation layer and an organic layer. The passivation layer is disposed on the side of the thin-film transistor away from the substrate; the organic layer is disposed on the side of the passivation layer away from the substrate; the orthographic projection of the organic layer on the substrate covers the bridging region 104, and the orthographic projection of the organic layer on the substrate does not overlap with the wiring region 103. Both the passivation layer and the organic layer are insulating layers, which can flatten the unevenness of the film structure. Since the organic layer is not suitable for direct contact with the metal layer, a passivation layer is needed for contact with the metal layer before the organic layer is disposed. The passivation layer is usually difficult to make very thick, while the organic layer can be made thicker, resulting in a stronger flattening effect.

[0082] In some implementations, the passivation layer and the organic layer are patterned using the same photomask. Sharing a photomask for both the passivation and organic layers reduces the number of photomasks required and eliminates one exposure and development step, thereby reducing production costs.

[0083] In some embodiments, the display panel further includes a light-emitting device disposed on the side of the pixel driver device 400 away from the substrate layer 100. The light-emitting device is electrically connected to the pixel driver device 400. Specifically, the light-emitting device may include a first electrode and a second electrode, with a light-emitting layer disposed between the first and second electrodes. The first electrode can be electrically connected to the pixel driver device. The first electrode can be connected to the source or drain of the thin-film transistor of the pixel driver device. A passivation layer has a third via, and an organic layer has a fourth via, with the third and fourth vias communicating with each other. The first electrode of the light-emitting device is electrically connected to the source or drain of the thin-film transistor through the communicating third and fourth vias.

[0084] In some implementations, at least one of the source and drain of the thin-film transistor can be disposed on the second metal layer, which can simplify the film structure and reduce production costs.

[0085] In some embodiments, the first metal layer 200 may include a light-shielding metal material; the first metal layer 200 can serve a light-shielding function, for example, the orthographic projection of the thin-film transistor channel on the substrate layer 100 falls on the orthographic projection of the first metal layer 200 on the substrate layer 100. That is, the first metal layer 200 in the display area 101 can block light from outside the substrate layer 100 from entering the channel of the thin-film transistor, preventing light from outside the substrate layer 100 from causing the photoelectric effect in the channel and generating leakage current, thereby preventing external light from affecting the electrical performance of the thin-film transistor. By placing the drive signal line 210 on the first metal layer 200, which serves as a light-shielding functional layer, the problem of exposed drive signal lines can be solved without adding an additional film layer.

[0086] In some embodiments, the first metal layer 200 may include a reflective metal material; the orthographic projection of the light-emitting area of ​​the light-emitting device onto the substrate layer 100 falls onto the orthographic projection of the first metal layer 200 onto the substrate layer 100. That is, the light-emitting area overlaps with the first metal layer 200. In a top-emitting display panel, the first metal layer 200, which includes a reflective metal material, can serve as a reflective layer. Light emitted by the light-emitting device that strikes the first metal layer 200 can be reflected and emitted from the light-emitting side of the light-emitting device, thereby improving the light emission efficiency of the display panel and reducing light waste.

[0087] In some embodiments, the orthographic projection of the light-emitting area of ​​the light-emitting device onto the substrate 100 does not overlap with the orthographic projection of the first metal layer 200 onto the substrate 100. That is, the first metal layer 200 is offset from the light-emitting area. In a bottom-emitting display panel, the light emitted by the light-emitting device needs to be emitted from the substrate 100, so the light transmittance of the first metal layer 200 is relatively poor, requiring a perforated design for light transmission. In a bottom-emitting display panel, the first metal layer 200 can still serve as a light-shielding layer, blocking the channel.

[0088] For example, the first metal layer 200 can be a composite film such as Cu / MoNb or Cu / MoTi, where MoNb or MoTi is a diffusion barrier layer for Cu. After photolithography and wet etching for patterning, the photoresist on the metal surface is stripped to obtain the pattern of the light-shielding layer and the driving signal line 210. The thickness of the first metal layer 200 can be in the range of 50 to 1000 μm and can be set by magnetron sputtering.

[0089] For example, Figure 8 This is a schematic diagram of a partial structure of a display area and a non-display area provided in an embodiment of this application. For example... Figure 8As shown, the thin-film transistor of the pixel driving device 400 includes a gate G, a source S, a drain D, and an active layer ACT. The first metal layer 200 of the display area 101 can serve as a light-shielding layer, blocking the channel region formed by the overlap of the gate G and the active layer ACT. An inter-insulating layer ILD is disposed between the source S and the drain D and the gate G. The signal lead 610 is electrically connected to the drain D and the driving signal line 210, respectively. The passivation layer PVX and the organic layer Resin cover the display area 101 and the bridging area 104, and the passivation layer PVX and the organic layer Resin do not overlap with the wiring area 103. The passivation layer PVX is provided with a third via 701, and the organic layer Resin is provided with a fourth via 702. The first electrode 710 and the source S are electrically connected through the connected third via 701 and fourth via 702.

[0090] It should be noted that the first electrode 710 can be the anode of a light-emitting device, or it can be a pixel electrode in a liquid crystal display panel. The embodiments in this application are merely illustrative and are not intended to limit the specific scope of this application.

[0091] It should be noted that, Figure 8 This is merely a simple illustration of the connection relationship between the drive signal line 210 and the thin-film transistor of the pixel drive device 400. Other connection methods are also possible and are not intended to limit the specific implementation of this application.

[0092] For example, refer to Figure 8 The inner wall of the third via 701 has a first slope angle a1, the inner wall of the fourth via 702 has a second slope angle a2, the boundary of the passivation layer PVX in the non-display area 102 has a third slope angle b1, and the boundary of the organic layer Resin in the non-display area 102 has a fourth slope angle b2. Since the passivation layer PVX and the organic layer Resin share the same mask etching pattern and via, the difference between the first slope angle a1 and the second slope angle a2 will not be too large, and the difference between the third slope angle b1 and the fourth slope angle b2 will not be too large either.

[0093] For example, the difference between the first slope angle difference and the second slope angle difference is less than or equal to 5°; wherein, the first slope angle difference is the difference between the first slope angle a1 and the second slope angle a2, and the second slope angle difference is the difference between the third slope angle b1 and the fourth slope angle b2.

[0094] In some embodiments, the minimum distance between the boundary of the organic layer Resin projected onto the substrate layer 100 and the second via 601 is less than or equal to the line spacing between two adjacent drive signal lines 210.

[0095] In some embodiments, the minimum distance between the boundary of the organic layer Resin projected onto the substrate layer 100 and the second via 601 is greater than or equal to the hole spacing of any two second vias 601 corresponding to the same bridging point 106.

[0096] For example, Figure 9 This is a schematic diagram illustrating another connection structure between a drive signal line and a signal lead provided in an embodiment of this application. (See diagram below.) Figure 9 As shown, the minimum distance between the boundary of the organic layer Resin projected onto the substrate layer 100 and the second via 601 is the first distance L1, the line spacing between two adjacent drive signal lines 210 is the second distance L2, and the hole spacing between any two second vias 601 corresponding to the same bridging point 106 is the third distance L3. The first distance L1 is less than or equal to the second distance L2, and the first distance L1 is greater than or equal to the third distance L3.

[0097] For example, Figure 10 This is a partial structural diagram of a display area provided in an embodiment of this application. Figure 10 As shown, the light-emitting device includes a first electrode 710, a second electrode 720, and a light-emitting layer 730. The first electrode 710 can serve as the anode, and the second electrode 720 can serve as the cathode. The light-emitting layer 730 emits light under the drive of the first electrode 710 and the second electrode 720. The electrical signal of the first electrode 710 comes from the source S of the thin-film transistor. The first electrodes 710 of different light-emitting devices are independent of each other, so the light-emitting layers 730 of light-emitting devices that emit different colors are connected to different thin-film transistors. Pixel-defining structures (PDLs) are spaced between adjacent light-emitting devices to separate the light-emitting layers 730 of different colors. In the fabrication process, the first electrode 710 can be fabricated first, followed by the pixel-defining structure (PDL).

[0098] For example, a buffer insulating layer 300 can be deposited using PECVD (chemical vapor deposition), and the thickness of the buffer insulating layer 300 can range from 150 to 500 nm. The active layer ACT can include amorphous oxides such as IGZO (indium gallium zinc oxide), ZnON (zinc oxynitride), and ITZO (indium tin zinc oxide). The thickness of the second metal layer 600 can range from 200 to 1000 nm, and the second metal layer 600 can include Al, Mo, Cr, Cu, Ti, etc. The passivation layer PVX can include SiO2, and the thickness can range from 2 to 3.5 μm. The organic layer Resin can be exposed and developed first, and then oxygen ashing can be used to remove the organic layer in the corresponding area to obtain the pattern of the organic layer, i.e., the fourth via, and to remove part of the organic layer in the non-display area. The third via on the inorganic layer Resin and the removal of part of the inorganic layer in the non-display area can be achieved by dry etching. The first electrode 710 may include Al, Mo, ITO, etc., with a thickness of 200 to 1000 nm. For top-emitting devices, the first electrode 710 requires a metal with a high work function and reflectivity exceeding 90%. For bottom-emitting devices, the first electrode 710 may be ITO (indium tin oxide). In bottom-emitting devices, the overlap region between the gate and source / drain electrodes in the driving circuit area is ITO connected to either the source or drain. In top-emitting devices, the overlap region between the gate and source / drain electrodes is MoNb / Cu / ITO connected to either the source or drain. After the pixel definition structure (PDL) is patterned, it can be post-baked at 230°C to remove water and organic solvents, resulting in a thickness of 1.8 to 2.0 μm.

[0099] For example, a color filter layer can be disposed on the side of the light-emitting device away from the substrate layer for filtering light, and the filter color can correspond to the color of the light emitted by the light-emitting device. The thickness of the color filter film is 2.0 to 3.5 μm; the bottom-emitting color filter layer is disposed on the side of the light-emitting device closest to the substrate layer, and the top-emitting color filter layer is disposed on the cover glass.

[0100] In some embodiments, the non-display area may include an electrostatic discharge (ESD) protection region, within which an ESD protection circuit is disposed. The ESD protection region may be located near the four corners of the display area, or at the top bezel, etc., and this application does not impose specific limitations on these locations. The orthogonal projection of the passivation layer PVX onto the substrate 100 covers the ESD protection region. The PVX coverage protects the ESD protection circuit from damage by static electricity or other external forces during the film preparation process.

[0101] A second aspect of this application provides a display device. Figure 11 This is a schematic structural diagram of a display device provided in an embodiment of this application. Figure 11 As shown, the display device includes a display panel 1000 as described in the first aspect.

[0102] It should be noted that the display device provided in the embodiments of this application may include smartphones, tablets, laptops, televisions or other displays, and the embodiments of this application do not specifically limit it.

[0103] It should be noted that the descriptions of each embodiment in the above embodiments have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0104] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

[0105] Although preferred embodiments have been described in this specification, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this specification.

[0106] Obviously, those skilled in the art can make various modifications and variations to this specification without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims and their equivalents, this specification is also intended to include such modifications and variations.

Claims

1. A display panel, characterized in that, include: A substrate layer, the substrate layer including a display area and a non-display area; A first metal layer is disposed on one side of the substrate layer; A buffer insulating layer is disposed on the side of the first metal layer away from the substrate layer, and the buffer insulating layer includes at least one of silicon nitride and silicon oxide; A pixel driving device is provided in the display area, and the pixel driving device is located on the side of the buffer insulating layer away from the first metal layer. A driving signal line is provided in the non-display area. The driving signal line is disposed on the first metal layer and is electrically connected to the pixel driving device. The orthographic projection of the driving signal line on the substrate layer falls into the orthographic projection of the buffer insulating layer on the substrate layer. The driving signal line is used to transmit display driving signals. A signal lead, wherein the signal lead is disposed in the non-display area, and / or, the signal lead is disposed in the display area, and / or, the signal lead passes through the non-display area and the display area; The signal lead is disposed on a conductive layer other than the first metal layer, and the driving signal line is electrically connected to the pixel driving device through the signal lead; The buffer insulating layer is provided with a first via, and the drive signal line and the signal lead are electrically connected through the first via; A second metal layer is disposed on the side of the buffer insulating layer away from the first metal layer; the pixel driving device includes a thin-film transistor, the gate of which is disposed on the second metal layer; A passivation layer is disposed on the side of the thin-film transistor away from the substrate layer; An organic layer is disposed on the side of the passivation layer away from the substrate layer; The non-display area includes a bridging area and a wiring area. The bridging area is located close to the display area. The drive signal line is located in the wiring area. The bridging point where the drive signal line and the signal lead are electrically connected across layers through the first via is located in the bridging area. The orthographic projection of the organic layer onto the substrate covers the bridging region, and the orthographic projection of the organic layer onto the substrate does not overlap with the wiring region, nor does the passivation layer overlap with the wiring region.

2. The display panel according to claim 1, characterized in that, Also includes: The driving circuit is electrically connected to the pixel driving device; The driving circuit and the driving signal line are electrically connected through the signal lead.

3. The display panel according to claim 1, characterized in that, Also includes: The signal lead is disposed on the second metal layer.

4. The display panel according to claim 3, characterized in that, Also includes: A gate insulating layer is disposed between the buffer insulating layer and the second metal layer; The gate insulating layer is provided with a second via, which communicates with the first via. The drive signal line and the signal lead are electrically connected through the communicating first via and second via.

5. The display panel according to claim 4, characterized in that, Also includes: The bridging region covers the orthogonal projection of the second via onto the substrate layer.

6. The display panel according to claim 5, characterized in that, The minimum distance between the boundary of the organic layer projected onto the substrate and the second via is less than or equal to the line spacing between two adjacent drive signal lines.

7. The display panel according to claim 5, characterized in that, At least two second vias are provided at a crossover point between the drive signal line and the corresponding electrically connected signal lead. The orthographic projections of the at least two second vias on the substrate layer do not overlap. Each second via corresponds to one first via. The minimum distance between the boundary of the organic layer projected onto the substrate and the second via is greater than or equal to the hole spacing between any two second vias corresponding to the same bridging point.

8. The display panel according to claim 5, characterized in that, The first metal layer includes a reflective metallic material; The display area is also provided with a light-emitting device, which is disposed on the side of the pixel driving device away from the substrate layer, and the light-emitting device is electrically connected to the pixel driving device; The orthographic projection of the light-emitting area of ​​the light-emitting device onto the substrate falls into the orthographic projection of the first metal layer onto the substrate. or, The orthographic projection of the light-emitting area of ​​the light-emitting device onto the substrate layer does not overlap with the orthographic projection of the first metal layer onto the substrate layer.

9. The display panel according to claim 5, characterized in that, The passivation layer and the organic layer are obtained by etching the same mask.

10. The display panel according to claim 6, characterized in that, The passivation layer is provided with a third via, and the organic layer is provided with a fourth via, wherein the third via and the fourth via are connected. The display area is also provided with a light-emitting device, which includes a first electrode. The first electrode is electrically connected to the source or drain of the thin-film transistor through the third via and the fourth via. The difference between the first slope angle difference and the second slope angle difference is less than or equal to 5°; Wherein, the first slope angle difference is the difference between the slope angle of the inner wall of the third through hole and the slope angle of the inner wall of the fourth through hole, and the second slope angle difference is the difference between the slope angle of the passivation layer boundary and the slope angle of the organic layer boundary corresponding to the non-display area.

11. The display panel according to claim 3, characterized in that, The source and / or drain of the thin-film transistor are disposed on the second metal layer.

12. The display panel according to claim 3, characterized in that, The first metal layer includes a light-shielding metal material; The orthogonal projection of the channel of the thin-film transistor onto the substrate falls into the orthogonal projection of the first metal layer onto the substrate.

13. The display panel according to claim 5, characterized in that, The non-display area includes an electrostatic discharge (ESD) protection area, and an ESD protection circuit is provided within the ESD protection area. The passivation layer's orthogonal projection onto the substrate covers the electrostatic protection area.

14. A display device, characterized in that, include: The display panel as described in any one of claims 1-13.

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