A surface emitting laser semiconductor array chip and a method for manufacturing the same

Abstract

The present application relates to the field of laser semiconductor, and especially relates to a surface-emitting laser semiconductor array chip and a manufacturing method thereof. The surface-emitting laser semiconductor array chip comprises a substrate assembly, a first mirror assembly, an active region assembly, a step assembly and a second mirror assembly, the first mirror assembly is arranged on the upper surface of the first substrate assembly, the active region assembly is arranged on the upper surface of the first mirror assembly, the step assembly is arranged on the upper surface of the active region assembly, the second mirror assembly is arranged on each step of the step assembly, a light-emitting unit is arranged on each step of the step assembly, and the light-emitting unit is embedded in the second mirror assembly. By designing different combinations of patterns and wavelengths of array chips, each batch of array chips has a unique ID, and the present application can be used as a signal emission source of a laser radar, so that the problem of mutual influence of signals between different radars can be effectively solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of laser semiconductor, in particular to a surface-emitting laser semiconductor array chip and a manufacturing method thereof. BACKGROUND

[0002] Surface-emitting semiconductor lasers have gradually become a new hotspot in the field of semiconductor lasers due to their vertical light emission, easy integration, low power consumption, and circular light spot. In particular, in recent years, due to the development of face recognition and laser radar intelligent sensing technology, vertical cavity surface-emitting semiconductor laser (VCSEL) array chips have become a hotspot in research and industrial fields.

[0003] Currently, VCSEL array chips used in the field of face recognition, laser radar and other intelligent sensing technologies are mainly based on gallium arsenide (GaAs) material system and rely on oxide aperture 205 to form photoelectric confinement. The VCSEL array chip has multiple light emitting units 110, and the emitted laser generally has a single center wavelength. Commonly used VCSEL array light emitting wavelengths include 850 nm, 910 nm, 940 nm, etc. Different light emitting units 110 of the entire VCSEL array chip are prepared based on the same epitaxial structure and have almost the same oscillation cavity length. Therefore, the light emitting wavelength of the entire array is generally a single wavelength. At present, the laser radar field, especially the vehicle-mounted laser radar technology, is mainly based on the time-of-flight (ToF) principle. That is, by continuously emitting light pulses (usually invisible light) to the measured object, then receiving the light pulses reflected from the object, and detecting the round-trip time of the light pulses to calculate the distance from the camera to the measured object. A key problem faced by this technology in real road conditions is how to distinguish whether the light pulses received by the detector are emitted by itself or by other vehicles' radars. Currently, the laser pulses emitted by the VCSEL array chip laser radar source only contain energy information, and different laser signals emitted by laser radars cannot be distinguished from each other. The existing array chip has a uniform oscillation cavity length, and the laser emitted by the chip has a single center wavelength, so the laser signal does not have uniqueness and different laser signals cannot be distinguished from each other. SUMMARY

[0004] The present application provides a surface-emitting laser semiconductor array chip and a manufacturing method thereof. The surface-emitting laser semiconductor array chip can emit multiple different wavelengths of laser simultaneously in a single array chip, and the wavelength distribution in the laser spot emitted by the array chip has a certain regularity, thereby solving at least one technical problem existing in the prior art.

[0005] One technical solution of the present invention is as follows: a surface-emitting laser semiconductor array chip includes a substrate assembly, a first reflector assembly, an active region assembly, a stepped assembly, and a second reflector assembly. The first reflector assembly is disposed on the upper surface of the substrate assembly, the active region assembly is disposed on the upper surface of the first reflector assembly, the stepped assembly is disposed on the upper surface of the active region assembly, a second reflector assembly is disposed on each step of the stepped assembly, and a light-emitting unit is disposed on each step of the stepped assembly, the light-emitting unit being embedded in the second reflector assembly.

[0006] Furthermore, the substrate assembly includes a first electrode layer and a substrate, wherein the substrate is disposed on the upper surface of the second electrode layer.

[0007] Furthermore, the active region component includes an active layer, a first limiting layer, and a second limiting layer, wherein the active layer is disposed between the first limiting layer and the second limiting layer.

[0008] Furthermore, the stepped assembly includes an oxide layer and a step layer, the step layer being disposed on the surface of the oxide layer, and the step layer comprising multiple steps of different heights.

[0009] Furthermore, the light-emitting unit includes an annular groove, a second electrode layer, and an insulating layer. The annular groove is embedded with a second reflector assembly, an oxide layer, and a step layer. The annular groove and the surrounding oxide layer form an oxide aperture. The oxide layer is disposed on the surface of the annular groove and the upper surface of the second reflector assembly. The second electrode layer is disposed on the surface of the oxide layer. Light-transmitting holes are formed on the second electrode layer and the oxide layer located on the upper surface of the second reflector assembly.

[0010] Furthermore, each step of the stepped layer is rectangular, with the height of each step changing progressively. Each step is parallel to the edge of the surface-emitting laser semiconductor array chip or at a 45° angle to the edge of the surface-emitting laser semiconductor array chip.

[0011] Furthermore, when each step is set at a 45° angle to the edge of the surface-emitting laser semiconductor array chip, the length of the step in the middle position is greater than the length of the steps on both sides, and the length of the outermost step is the shortest.

[0012] Furthermore, the steps of the stepped layer are arranged in a ring and concentrically, and the height of the steps decreases or increases sequentially from the center to the edge.

[0013] Furthermore, the width of the annular step is 20-500 micrometers, and the light emission aperture of the light-emitting unit is 5-200 micrometers.

[0014] Another technical solution of the present invention is as follows: A method for fabricating any of the above-described surface-emitting laser semiconductor array chips, comprising:

[0015] Select a substrate assembly, and use an epitaxial device to sequentially epitaxially grow a first reflector assembly, an active region assembly, and a stepped assembly substrate on the substrate assembly;

[0016] Multiple steps of different heights are etched on the stepped component substrate using photolithography and dry etching processes;

[0017] A second reflector assembly is epitaxially grown on each step, and a light-emitting unit is etched on the second reflector assembly on each step.

[0018] The beneficial effects of the present invention are as follows: The present invention provides an array chip containing patterned wavelength information in the light spot. By designing different combinations of patterns and wavelengths of array chips, each batch of array chips has its own unique ID. Using the VCSEL array chip provided by the present invention as the signal transmission light source of lidar can effectively solve the problem of mutual interference between signals of different lidars. Attached Figure Description

[0019] Figure 1 This is a cross-sectional structural diagram of a surface-emitting laser semiconductor array chip according to the present invention.

[0020] Figure 2 This is a schematic diagram of the epitaxial structure of a surface-emitting laser semiconductor array chip according to the present invention.

[0021] Figure 3 This is a top view of Embodiment 1 of a surface-emitting laser semiconductor array chip according to the present invention.

[0022] Figure 4 This is a top view of Embodiment 2 of a surface-emitting laser semiconductor array chip according to the present invention.

[0023] Figure 5 This is a top view of embodiment 3 of the surface-emitting laser semiconductor array chip of the present invention. Detailed Implementation

[0024] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. The described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0025] In an embodiment of the present invention, Figure 1 andFigure 2 This is a schematic diagram illustrating the specific structure of a surface-emitting laser semiconductor array chip according to the present invention. For example... Figure 1 and Figure 2 As shown, the present invention specifically includes: a substrate assembly, a first reflector assembly 102, an active region assembly, a stepped assembly, and a second reflector assembly 108. The first reflector assembly 102 is disposed on the upper surface of the substrate assembly, the active region assembly is disposed on the upper surface of the first reflector assembly 102, and the stepped assembly is disposed on the upper surface of the active region assembly. A second reflector assembly 108 is disposed on each step of the stepped assembly, and a plurality of light-emitting units 110 are disposed on each step of the stepped assembly. The light-emitting units 110 are embedded in the second reflector assembly 108. Specifically, the bottom of the light-emitting unit 110 is slightly embedded in the top of the stepped assembly.

[0026] like Figure 1 As shown, the substrate assembly includes a first electrode layer 201 and a substrate 101, with the substrate 101 disposed on the upper surface of the first electrode layer 201. The second electrode layer 203101 is an N-type electrode with a thickness between 200 nanometers and 500 nanometers, and is made of an alloy of metallic titanium, platinum, gold, nickel, germanium, etc. The substrate 101102 can be made of N-type GaAs material.

[0027] like Figure 1 As shown, the first reflector assembly 102 can be an N-type distributed Bragg reflector (DBR), specifically a periodically grown indium aluminum gallium arsenide / indium aluminum gallium arsenide (InAlGaAs / InAlGaAs) material. Each layer has an In composition of 0.5~0.6 and an Al composition of 0.05~0.95. The thickness of each layer is the ratio of one-quarter of the emitted light wavelength to the material's refractive index, specifically one-quarter of the emitted light wavelength divided by the material's refractive index. The number of periodic logarithmic pairs ranges from 20 to 40 (including endpoints), and the total thickness ranges from 2 to 5 micrometers (including endpoints). The dopant is Si, with a doping concentration of 1E16~8E18 / cm². 3 .

[0028] like Figure 1 As shown, the active region component includes an active layer 104, a first confinement layer 103, and a second confinement layer 105, with the active layer 104 disposed between the first confinement layer 103 and the second confinement layer 105. Specifically, the active layer 104 is disposed on the upper surface of the first confinement layer 103, and the second confinement layer 105 is disposed on the upper surface of the active layer 104. The first confinement layer 103 can be an N-type confinement layer, which is made of aluminum gallium arsenide (AlGaAs) material with an Al composition of 0.05~0.95, a thickness of 0.1 μm~10 μm, and silicon (Si) as the dopant with a doping concentration of 1E16-8E18 / cm².3 The active layer 104 is non-actively doped, forming a barrier / quantum well / barrier structure. The material is AlGaAs / InAlGaAs / AlGaAs, with an In composition of 0–0.2% and an Al composition of 0–0.5%. The barrier thickness is 1–200 nm, the quantum well thickness is 1–20 nm, and the emission wavelength is 700–1100 nm. The second confinement layer 105 can be a p-type confinement layer, specifically made of AlGaAs material with an Al composition of 0.05–0.95%, a thickness of 0.05–0.5 μm, and C as the dopant with a doping concentration of 1E16–8E18 / cm³. 3 .

[0029] like Figure 2 As shown, the stepped assembly includes an oxide layer 106 and a step layer 107. The step layer 107 is disposed on the surface of the oxide layer 106 and comprises multiple steps of different heights. The oxide layer 106 is made of AlGaAs with an Al composition of 0.95–0.98, a thickness of 0.01–0.05 μm, and is doped with C at a concentration of 1E16–8E18 / cm³. 3 The 107 step layer is p-type and can be made of AlGaAs material with an Al composition of 0.05-0.95 and a thickness of 0.05-10 μm. The dopant is C with a doping concentration of 1E16-8E18 / cm³. 3 .

[0030] The second reflector assembly 108 can be a P-type distributed Bragg reflector (DBR), specifically a periodically grown AlGaAs / AlGaAs material. Each layer has an Al composition of 0.05-0.95, a thickness equal to one-quarter of the emitted light wavelength divided by the material's refractive index, a periodicity ranging from 20 to 40 pairs (including endpoints), and a total thickness ranging from 2 to 5 micrometers (including endpoints). The dopant is C, with a doping concentration of 1E16-8E18 / cm³. 3 A capping layer 109 is applied to the second reflector assembly 108. Specifically, the capping layer 109 is a P-type capping layer made of gallium arsenide (GaAs) material, with a thickness ranging from 0.1 micrometers to 3 micrometers. The dopant is carbon (C), and the doping concentration is 1E18-1E20 / cm². 3 .

[0031] The light-emitting unit 110 specifically includes an annular groove 206, a second electrode layer 203, an insulating layer 202, and an internal second reflector assembly and a stepped assembly. The groove between the light-emitting unit 110 and the external second reflector assembly is an annular groove 206. The annular groove 206 is formed by an etching process. The annular groove 206 is embedded with the second reflector assembly 108, the oxide layer 106, and the stepped layer 107. The annular groove 206 and the surrounding oxide layer 106 form an oxide aperture 205. The second reflector assembly 108 and the stepped assembly inside the light-emitting unit 110 are located above the oxide aperture 205 and within the annular area formed by the annular groove 206. The oxide layer 106 is disposed on the surface of the annular groove 206 and the upper surface of the second reflector assembly 108. The second electrode layer 203 is disposed on the surface of the oxide layer 106. Light-transmitting holes 204 are opened on the second electrode layer 203 and the oxide layer 106 located on the upper surface of the second reflector assembly 108. The second electrode layer 203 is a P-type electrode with a thickness between 200 and 500 nanometers, and is made of an alloy of metallic titanium, platinum, gold, nickel, germanium, etc. The insulating layer 202 is made of SiO2 or Si3N4 and has a thickness of 50 to 1000 nanometers.

[0032] The present invention forms a stepped patterned platform by etching P-type step layers 107 of different heights. Each step includes a different number of light-emitting units 110, forming different patterned designs, which can assign different ID information to each batch of surface-emitting laser semiconductor array chips.

[0033] In Embodiment 1 of the present invention, as Figure 3 As shown in Figure 3, each step of the step layer 107 is rectangular, with the height of each step changing progressively. Each step is parallel to the edge of the surface-emitting laser semiconductor array chip. Specifically, it includes four steps of different heights, all horizontally arranged. The step height can decrease or increase progressively from top to bottom. The height difference between different steps can be designed according to specific requirements, ranging from 0.05 micrometers to 1 micrometer. Furthermore, a different number of light-emitting units 110 are set on each step of each height. In this embodiment, five light-emitting units 110 are set on each step, and the laser wavelengths emitted by the light-emitting units 110 on different steps are different.

[0034] In Embodiment 2 of the present invention, as Figure 4As shown, each step of the staircase is rectangular, with a progressively varying height. Each step forms a 45° angle with the edge of the surface-emitting laser semiconductor array chip. The surface-emitting laser semiconductor array chip has a length ranging from 300 micrometers to 4000 micrometers and a width ranging from 300 micrometers to 4000 micrometers. There are seven steps, with the middle step being longer than the steps on either side, and the outermost step being the shortest. The height of the seven steps can increase or decrease progressively from the lower left corner to the upper right corner of the surface-emitting laser semiconductor array chip. The width of each step ranges from 40 micrometers to 500 micrometers, and the step's inclination angle is 45°. The long wavelength of the step extends to the edge of the surface-emitting laser semiconductor array chip.

[0035] The steps, from the lower left to the upper right, are sequentially designated as Step 1, Step 2, Step 3, Step 4, Step 5, Step 6, and Step 7. Step 1 and Step 7 each contain one light-emitting unit 110, with the platform diameter of the light-emitting unit 110 ranging from 5 micrometers to 300 micrometers. Step 2 and Step 6 each contain three light-emitting units 110, with the platform diameter of the light-emitting unit 110 ranging from 5 micrometers to 300 micrometers. Step 3 and Step 5 each contain six light-emitting units 110, with the platform diameter of the light-emitting unit 110 ranging from 5 micrometers to 300 micrometers. Step 4 contains eight light-emitting units 110, with the platform diameter of the light-emitting unit 110 ranging from 5 micrometers to 300 micrometers.

[0036] In embodiment 3 of the present invention, as Figure 5 As shown, the steps of the step layer 107 are arranged in a ring and concentrically, and the height of the steps decreases or increases from the center to the edge.

[0037] Among them, the length of the surface-emitting laser semiconductor array chip ranges from 300 micrometers to 4000 micrometers, and the width ranges from 300 micrometers to 4000 micrometers.

[0038] Specifically, the surface-emitting laser semiconductor array chip comprises four different steps arranged in a ring. The central circular step, designated Step 1, has the highest height and a diameter ranging from 50 to 500 micrometers. Step 1 contains one large-sized light-emitting unit 110, with a mesa diameter of 30 to 300 micrometers. The adjacent ring step, designated Step 2, has a lower height and a ring width ranging from 20 to 500 micrometers. Step 2 contains four light-emitting units 110 arranged in a ring, with a mesa diameter of 5 to 200 micrometers. The adjacent ring step, designated Step 3, has a lower height and a ring width ranging from 20 to 500 micrometers. Step 3 contains eight light-emitting units 110 arranged in a ring, with a mesa diameter of 5 to 200 micrometers. The annular step adjacent to step 3 is lower in height than step 3 and is referred to as step 4. The annular width of step 4 ranges from 20 micrometers to 500 micrometers. Step 4 contains 8 light-emitting units 110 arranged in a ring. The platform diameter of the light-emitting unit 110 is 5 micrometers to 200 micrometers.

[0039] In another technical solution of the present invention, a method for fabricating any of the above-described surface-emitting laser semiconductor array chips is provided, comprising:

[0040] A substrate assembly is selected, and the first reflector assembly 102, the active region assembly, and the stepped assembly substrate are epitaxially grown sequentially on the substrate assembly using an epitaxial device.

[0041] Specifically, an N-type GaAs substrate 101 is used. An N-type DBR mirror, an N-type confinement layer, an active region, a P-type confinement layer, an oxide layer 106, and a P-type step layer 107 are sequentially grown on the N-type GaAs substrate 101. The growth equipment is a commercially available MOCVD or MBE.

[0042] Multiple steps of varying heights are etched onto the stepped component substrate using photolithography and dry etching processes.

[0043] Specifically, using traditional photolithography and dry etching processes, periodic stepped mesa are etched on the surface of the substrate 101 after the P-type stepped layer 107 has been grown. Each cycle is a surface-emitting laser semiconductor array chip, with a cycle length ranging from 300 micrometers to 5000 micrometers and a cycle width ranging from 300 micrometers to 5000 micrometers. In the surface-emitting laser semiconductor array chip in Example 1, each cycle contains four steps of different heights, with the step length being the same as the cycle length, and the width of each step ranging from 50 micrometers to 1500 micrometers.

[0044] A second reflector assembly 108 is epitaxially grown on each step, and a light-emitting unit 110 is etched onto the second reflector assembly 108 on each step. Specifically, a second epitaxial process is performed on the substrate 101 after etching the patterned mesa, sequentially growing a P-type DBR reflector and a P-type capping layer 109 to obtain an epitaxial substrate 101 with a complete structure. Annular trenches are etched on the four steps of the epitaxial substrate 101 using photolithography and dry etching processes. The trench width is 5-50 micrometers, and the trench etching depth is required to etch the peroxide layer 106. The circular mesa surrounded by the trenches has a direct range of 5-500 micrometers. Oxide apertures 205 are prepared using a conventional wet oxidation process, with an oxide aperture diameter ranging from 3-300 micrometers. A silicon oxide or silicon nitride insulating layer 202 is grown on the surface of the epitaxial substrate 101. Electrode injection windows are etched on the surface of the insulating layer 202 using photolithography and etching processes. A P-type metal electrode is grown, and the light emission port is fabricated using a lift-off process. The back side of substrate 101 is thinned and polished. An N-type metal electrode is grown. Ohmic contacts are formed using an alloying process. A single surface-emitting laser semiconductor array chip is then formed through cleaving.

[0045] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A surface-emitting laser semiconductor array chip, characterized in that, The substrate assembly, the first mirror assembly (102), the active region assembly, the step assembly and the second mirror assembly (108), the first mirror assembly (102) is arranged on the upper surface of the substrate assembly, the active region assembly is arranged on the upper surface of the first mirror assembly (102), the step assembly is arranged on the upper surface of the active region assembly, the second mirror assembly (108) is arranged on each step of the step assembly, the light emitting unit (110) is arranged on each step of the step assembly, and the light emitting unit (110) is embedded in the second mirror assembly (108); The step assembly includes an oxidation layer (106) and a step layer (107), the step layer (107) is arranged on the surface of the oxidation layer (106), and the step layer (107) includes multiple steps with different heights; The light emitting unit (110) includes a ring-shaped groove (206), a second electrode layer (203) and an insulating layer (202), the ring-shaped groove (206) is embedded in the second mirror assembly (108), the oxidation layer (106) and the step layer (107), the ring-shaped groove (206) and the surrounding oxidation layer (106) form an oxidation aperture (205), the oxidation layer (106) is arranged on the surface of the ring-shaped groove (206) and the upper surface of the second mirror assembly (108), the second electrode layer (203) is arranged on the surface of the oxidation layer (106), and a light transmission hole (204) is formed in the second electrode layer (203) and the oxidation layer (106) on the upper surface of the second mirror assembly (108).

2. The array chip of claim 1, wherein the array chip is a vertical cavity surface emitting laser (VCSEL) array chip. The substrate assembly includes a first electrode layer (201) and a substrate (101), and the substrate (101) is arranged on the upper surface of the first electrode layer (201).

3. The array chip of claim 1, wherein the array chip is a vertical cavity surface emitting laser (VCSEL) array chip. The active region assembly includes an active layer (104), a first limiting layer (103) and a second limiting layer (105), and the active layer (104) is arranged between the first limiting layer (103) and the second limiting layer (105).

4. The array chip of claim 1, wherein the array chip is a vertical cavity surface emitting laser (VCSEL) array chip. Each step of the step layer (107) is rectangular, the height of each step changes gradually, and each step is arranged in parallel with the edge of the surface-emitting laser semiconductor array chip or at an angle of 45° with the edge of the surface-emitting laser semiconductor array chip.

5. The array chip of claim 4, wherein the first and second waveguide layers are formed of a material selected from the group consisting of InP, GaAs, and AlGaAs. When each step is arranged at an angle of 45° with the edge of the surface-emitting laser semiconductor array chip, the length of the step in the middle position is greater than the length of the steps on both sides, and the length of the step on the outermost side is the shortest.

6. The array chip of claim 1, wherein the array chip is a vertical cavity surface emitting laser (VCSEL) array chip. The steps of the step layer (107) are annular and arranged in concentric circles, and the height of the steps decreases from the center to the edge or decreases and then increases from the center to the edge.

7. The array chip of claim 6, wherein the first and second waveguide layers are formed of a material selected from the group consisting of InP, GaAs, and AlGaAs. The width of the annular step is 20-500 microns, and the light emitting aperture of the light emitting unit (110) is 5-200 microns.

8. A production method for producing the surface emitting laser semiconductor array chip according to any one of claims 1 to 7, characterized by, The method comprises the following steps: Selecting a substrate assembly, and sequentially epitaxially growing a first mirror assembly (102), an active region assembly and a step assembly base on the substrate assembly by an epitaxial device; Etching multiple steps with different heights on the step assembly base by a photoetching and dry etching process; A second mirror component (108) is grown by epitaxy on each step, and a light emitting unit (110) is etched on the second mirror component (108) on each step.

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