High-side driving semiconductor chip and substrate potential processing method

Abstract

A high-side drive semiconductor chip and a substrate potential processing method, the chip includes a Vbb terminal, an IN terminal and an OUT terminal, and a P-type substrate, a charge pump, and a GATE drive module arranged in the chip; the GATE drive module includes a power MOS tube; a substrate potential bias circuit is added between the IN terminal and the GATE terminal of the GATE drive module; when the power MOS tube control signal inL1 is turned off, the substrate potential bias circuit turns off the power MOS tube and provides an additional pull-down current at the same time, so that the GATE terminal potential is approximately equal to the OUT terminal potential; when the power MOS tube control signal inL1 is turned on, the substrate potential bias circuit turns on the power MOS tube and flows the current flowing into the P-type substrate into the IN terminal, thereby clamping the substrate potential to the IN terminal potential. The present invention adds a substrate potential bias circuit in the high-side drive semiconductor chip, which can prevent the substrate bias diode of the device from being turned on, and avoid the problem of leakage when the parasitic tube is turned on.

Description

Technical Field

[0001] The present invention relates to a power switch chip and a control method, and in particular to a high-side drive semiconductor chip and a substrate potential processing method. Background Art

[0002] The system structure principle of the high-side driver semiconductor chip can be found in Figure 1 When the chip is used on the high side of the circuit, the chip has no pins directly connected to the ground, so it is generally designed using an N-type semiconductor process (ntype). The N-type substrate (nsub) is connected to the highest potential power supply voltage Vbb, and then a P well is made in the N-type substrate. The P well is used as the substrate for other devices to achieve isolation between the functional modules in the chip.

[0003] However, when a P-type semiconductor process (ptype) is used for design, the substrate potential of the P-type substrate (psub) needs to be connected to the lowest potential, otherwise the substrate diode is easily forward-biased, causing the problem of substrate parasitic leakage.

[0004] Figure 2 It is a schematic diagram of the N-type semiconductor process. When Vc is connected to the power supply voltage Vbb, the substrate bias potential Ve can be any voltage without forming a forward biased PN junction, so it will not cause the problem of substrate parasitic leakage.

[0005] See also Figure 3 In the P-type semiconductor process, it is impossible to connect each non-isolated NMOS device to the power supply voltage Vbb to avoid substrate bias. Therefore, it is necessary to consider whether the substrate bias diode from the P-type substrate to the NMOS device is turned on. If the substrate bias diode is turned on, it may cause other parasitic transistors to turn on and leak. For this reason, measures must be taken to ensure that the P-type substrate forms a reverse bias on the substrate bias diode in the functional module inside the chip.

[0006] In addition, Figure 1 In the chip, when the switch Vin is closed, the IN terminal is connected to the ground, and the GATE driver module realizes the output of the charge pump by controlling the on and off of the power MOS tube. When the chip is not working, the GATE pull-down module works and the power MOS tube is turned off; when the chip is working normally, in order to turn on the power MOS tube, the GATE pull-down module needs to be turned off. When the IN terminal is at a low level, the P-type substrate needs to be pulled down to the same potential as the IN terminal, but the pull-down current must be less than the pull-up current of the IN terminal, otherwise the IN terminal cannot be pulled up, and the power MOS tube cannot be turned off accordingly. Summary of the invention

[0007] The purpose of the present invention is to provide a high-side driving semiconductor chip and a substrate potential processing method, which solves the technical problem of parasitic tube conduction leakage in high-side driving semiconductor chips prepared by existing P-type semiconductor processes.

[0008] The technical solution provided by the present invention is:

[0009] The present invention discloses a first substrate potential processing method for a high-side driving semiconductor chip, wherein the high-side driving semiconductor chip comprises a Vbb terminal, an IN terminal and an OUT terminal, and a P-type substrate, a charge pump and a GATE driving module arranged in the chip; the GATE driving module comprises a power MOS tube; the special feature is that when the high-side driving semiconductor chip is prepared by a P-type semiconductor process, a substrate potential bias circuit is added between the IN terminal of the chip and the GATE terminal of the GATE driving module; the substrate potential bias circuit realizes the following functions: when the power MOS tube control signal inL1 is turned off, the substrate potential bias circuit turns off the power MOS tube and provides an additional pull-down current, so that the GATE terminal potential is approximately equal to the OUT terminal potential; when the power MOS tube control signal inL1 is turned on, the substrate potential bias circuit turns on the power MOS tube and flows the current flowing into the P-type substrate into the IN terminal, thereby clamping the substrate potential to the IN terminal potential.

[0010] The substrate potential bias circuit includes a driving switch module, a current mirror module and a GATE pull-down module; the input end of the driving switch module is connected to the output end of the charge pump, and is used to control the on and off of the charge pump output driving current; the current mirror module includes a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5, and a second PMOS tube P2; the source of the fifth NMOS tube N5 is connected to the P-type substrate, the drain thereof is connected to the IN terminal, and the gate thereof is connected to the gate and drain of the fourth NMOS tube N4, the gate of the third NMOS tube N3, and the drain of the second PMOS tube P2; the drain of the fourth NMOS tube N4 and the source of the third NMOS tube N3 are connected to the P-type substrate; the gate of the second PMOS tube P2 is connected to the power MOS tube control signal inL1, and the source thereof is connected to the bias current bias1; the GATE pull-down module includes a second NMOS tube N2, a third resistor R3, a fourth resistor R4, and a pull-down resistor R5; one end of the third resistor R3 is connected to the gate of the second NMOS tube N2; one end of the fourth resistor R4 is connected to the second The drain of the NMOS tube N2; the source of the second NMOS tube N2 and one end of the fifth resistor are connected to the OUT end; the other ends of the third resistor R3, the fourth resistor R4 and the fifth resistor are all connected to the output end of the driving switch module; the drain of the third NMOS tube N3 is connected to the gate of the second NMOS tube N2; when the power MOS tube control signal inL1 is turned off, the second NMOS tube N2 in the GATE pull-down module of the substrate potential bias circuit is turned on, and the power MOS tube is turned off by pulling down the GATE, and there is no output current at the OUT end; when the GATE is pulled down, the pull-down resistor R5 provides additional pull-down current, so that the potential of the GATE end is approximately equal to that of the OUT end; when the power MOS tube control signal inL1 is turned on, the second NMOS tube N2 is turned off, thereby turning off the pull-down current of the GATE end, the power MOS tube is turned on, and the charge pump outputs current from the OUT end; when the power MOS tube is turned on, the current flowing into the P-type substrate flows into the IN end through the substrate bias circuit, and at the same time clamps the substrate potential to the IN end potential.

[0011] When the second NMOS tube N2 is turned on, the fourth resistor R4 limits the pull-down current of the second NMOS tube N2 to control the turn-off speed of the power MOS tube.

[0012] The present invention implements the high-side driving semiconductor chip of the first substrate potential processing method, comprising a Vbb terminal, an IN terminal and an OUT terminal, as well as a P-type substrate, a charge pump and a GATE driving module arranged in the chip; the GATE driving module comprises a power MOS tube; the special feature is that it also comprises a substrate potential bias circuit; the substrate potential bias circuit comprises a driving switch module, a current mirror module and a GATE pull-down module; the input terminal of the driving switch module is connected to the output terminal of the charge pump, and is used to control the on-off of the charge pump output driving current; the current mirror module comprises a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5, and a second PMOS tube P2; the source of the fifth NMOS tube N5 is connected to the P-type substrate, the drain thereof is connected to the IN terminal, and the gate thereof is connected to the gate and drain of the fourth NMOS tube N4, the gate of the third NMOS tube N5, and the drain of the third NMOS tube N5. The gate of the S tube N3 and the drain of the second PMOS tube P2; the drain of the fourth NMOS tube N4 and the source of the third NMOS tube N3 are connected to the P-type substrate; the gate of the second PMOS tube P2 is connected to the power MOS tube control signal inL1, and its source is connected to the bias current bias1; the GATE pull-down module includes the second NMOS tube N2, the third resistor R3, the fourth resistor R4, and the pull-down resistor R5; one end of the third resistor R3 is connected to the gate of the second NMOS tube N2; one end of the fourth resistor R4 is connected to the drain of the second NMOS tube N2; the source of the second NMOS tube N2 and one end of the fifth resistor are connected to the OUT end; the other ends of the third resistor R3, the fourth resistor R4 and the fifth resistor are all connected to the output end of the driving switch module; the drain of the third NMOS tube N3 is connected to the gate of the second NMOS tube N2.

[0013] The above-mentioned driving switch module specifically includes a first PMOS tube P1 and a first resistor R1; the gate of the first PMOS tube P1 is connected to the power MOS tube control signal inL1 through the first resistor R1, its source is connected to the charge pump output end, and its drain is connected to the third resistor R3, the fourth resistor R4 and one end of the fifth resistor R5.

[0014] The driving switch module may further include a first voltage regulator tube D1; the positive electrode of the first voltage regulator tube D1 is connected to the gate of the first PMOS tube P1, and the negative electrode thereof is connected to the source of the first PMOS tube P1.

[0015] The above-mentioned GATE pull-down module may further include a second voltage regulator tube D2; the anode of the second voltage regulator tube D2 is connected to the gate of the second NMOS tube N2, and the cathode of the second voltage regulator tube D2 is connected to the drain of the first PMOS tube P1.

[0016] The second substrate potential processing method of a high-side driving semiconductor chip of the present invention comprises a Vbb terminal, an IN terminal, an OUT terminal and a GND terminal, as well as a P-type substrate, a charge pump and a GATE driving module arranged in the chip; the GATE driving module comprises a power MOS tube; the characteristic is that: when a power switch chip is prepared by a P-type semiconductor process, a substrate potential bias circuit is added between the GND terminal of the high-side driving semiconductor chip and the P-type substrate; the substrate potential bias circuit is used to realize the following functions: when the power MOS tube control signal inL1 is turned off, the substrate potential bias circuit turns off the power MOS tube and provides an additional pull-down current at the same time, so that the GATE terminal potential of the GATE driving module pair is approximately equal to the OUT terminal potential; when the power MOS tube control signal inL1 is turned on, the substrate potential bias circuit turns on the power MOS tube and flows the current flowing into the P-type substrate into the IN terminal, thereby clamping the substrate potential to the IN terminal potential.

[0017] The substrate potential bias circuit is a depletion-type MOS tube or JFET tube connected in parallel between the GND terminal and the P-type substrate.

[0018] The present invention implements the high-side driving semiconductor chip of the second substrate potential processing method, comprising a Vbb terminal, an IN terminal, an OUT terminal and a GND terminal, as well as a P-type substrate, a charge pump and a GATE driving module arranged in the chip; the GATE driving module comprises a power MOS tube; it is characterized in that: it also comprises a substrate potential bias circuit; the substrate potential bias circuit is a depletion MOS tube or a JFET tube connected in parallel between the GND terminal and the P-type substrate.

[0019] Beneficial effects of the present invention:

[0020] The present invention adds a substrate potential bias circuit to a high-side driving semiconductor chip based on a P-type semiconductor process, introduces a bias current into a GATE pull-down module through a current mirror module, so that when the IN end is pulled down, that is, when the power MOS tube is turned on, the current flowing into the P-type substrate flows into the IN end through the substrate bias circuit, and at the same time, the P-type substrate potential is clamped to the IN end potential, and the IN end potential is the lowest at this time, so the substrate bias diode of the device can be prevented from being turned on, avoiding the problem of parasitic tube conduction leakage.

[0021] If the high-side driving semiconductor chip is provided with a GND terminal, the present invention adopts a depletion-type MOS tube or a JFET tube connected in parallel between the GND terminal and the P-type substrate in the substrate potential bias circuit of the high-side driving semiconductor chip, so as to pull the P-type substrate potential and the GND terminal potential to be approximately equal, thereby preventing the parasitic leakage problem caused by the floating P-type substrate potential inside the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a system structure schematic diagram of a high-side driver semiconductor chip;

[0023] Figure 2 It is a schematic diagram of the structure of a high-side driver semiconductor chip based on an N-type semiconductor process;

[0024] Figure 3 It is a schematic diagram of the structure of a high-side driver semiconductor chip based on a P-type semiconductor process;

[0025] Figure 4 It is a schematic diagram of a substrate potential bias circuit of a high-side driving semiconductor chip embodiment 1 based on a P-type semiconductor process of the present invention;

[0026] Figure 5 Schematic diagram of the substrate potential bias circuit of embodiment 2 of the high-side driving semiconductor chip based on the P-type semiconductor process of the present invention. DETAILED DESCRIPTION

[0027] High-side driver semiconductor chip Figure 1 , including a VBB terminal, an IN terminal and an OUT terminal arranged on the chip, and a P-type substrate (psub), a charge pump, a GATE driving module and a substrate potential bias circuit arranged in the chip; the GATE driving module includes a power MOS tube.

[0028] Example 1

[0029] See also Figure 4The substrate potential bias circuit includes a driving switch module, a current mirror module and a GATE pull-down module. The driving switch module includes a first PMOS tube P1, a first resistor R1 and a first voltage regulator D1; the gate of the first PMOS tube P1 is connected to the power MOS tube control signal inL1 through the first resistor R1, its source is connected to the charge pump output terminal charge, and its drain is connected to the third resistor R3, the fourth resistor R4 and one end of the fifth resistor. The positive electrode of the first voltage regulator D1 is connected to the gate of the first PMOS tube P1, and its negative electrode is connected to the source of the first PMOS tube P1; the driving switch module is used to control the on and off of the charge pump output drive current. The current mirror module includes a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5, and a second PMOS tube P2; the source of the fifth NMOS tube N5 is connected to the P-type substrate, the drain thereof is connected to the IN terminal, and the gate thereof is connected to the gate and drain of the fourth NMOS tube N4, the gate of the third NMOS tube N3, and the drain of the second PMOS tube P2; the drain of the fourth NMOS tube N4 is connected to the P-type substrate; the source of the third NMOS tube N3 is connected to the P-type substrate; the gate of the second PMOS tube P2 is connected to the power MOS tube control signal inL1, and the source thereof is connected to the bias current bias1; GA The TE pull-down module includes a second NMOS tube N2, a third resistor R3, a fourth resistor R4, a pull-down resistor R5 and a second voltage regulator tube D2; one end of the third resistor R3 is connected to the gate of the second NMOS tube N2; one end of the fourth resistor R4 is connected to the drain of the second NMOS tube N2; the source of the second NMOS tube N2 and one end of the fifth resistor are connected to the OUT terminal; the other ends of the third resistor R3, the fourth resistor R4 and the fifth resistor are all connected to the output end of the driving switch module; the positive electrode of the second voltage regulator tube D2 is connected to the gate of the second NMOS tube N2, and the negative electrode thereof is connected to the drain of the first PMOS tube P1. The drain of the third NMOS tube N3 is connected to the gate of the second NMOS tube N2.

[0030] Working principle:

[0031] See also Figure 1 When the high-side driving semiconductor chip works normally, the switch Vin is closed, the IN terminal is turned on and becomes low level, and the charge pump outputs current from the OUT terminal after passing through the first PMOS tube P1 and the GATE driving module.

[0032] The control signal inL1 is a control signal required for the power MOS tube to be turned on. When the control signal inL1 is low, the power MOS tube is turned on to drive the OUT terminal to output; at the same time, the first PMOS tube P1 and the second PMOS tube P2 are turned on. Since the third NMOS tube N3 and the fourth NMOS tube N4 form a current mirror, the current flowing through the third NMOS tube N3 is proportional to the bias current bias1 flowing through the third NMOS tube N3. The current of the third NMOS tube N3 pulls down the gate voltage of the second NMOS tube N2, so that the second NMOS tube N2 is turned off, and the pull-down current of the GATE terminal of the GATE driving module is turned off.

[0033] The third resistor R3 provides a gate voltage to the second NMOS transistor N2 when the third NMOS transistor N3 is turned off, so that the second NMOS transistor N2 is turned on and the GATE terminal is pulled down, thereby turning off the power MOS transistor;

[0034] The fourth resistor R4 limits the pull-down current of the second NMOS tube N2 when the second NMOS tube N2 is turned on to control the turn-off speed of the power MOS tube.

[0035] The fifth resistor R5 provides additional pull-down current when the GATE terminal is pulled down, especially when the GATE terminal is pulled down to the threshold voltage Vth of the second NMOS transistor N2, the fifth resistor R5 continues to pull down so that the GATE terminal and the OUT terminal have approximately equal potentials.

[0036] Example 2

[0037] like Figure 5 As shown, the voltage source, overvoltage protection, current limiting, gate voltage protection, voltage sampling, charge pump potential shift rectifier, inductive demagnetization clamp, logic control, current sampling, output voltage detection, temperature sampling, electrostatic protection, current source and other modules inside the high-side driving semiconductor chip are all connected to the P-type substrate, and the high-side driving semiconductor chip has a GND terminal directly grounded, and a depletion-type MOS tube or JFET tube is connected in parallel between the GND terminal and the P-type substrate so that the P-type substrate potential and the GND terminal potential are pulled to be approximately equal, which can prevent parasitic leakage problems caused by the floating P-type substrate potential inside the chip.

Claims

1. A method for processing substrate potential of a high-side driving semiconductor chip, wherein the high-side driving semiconductor chip comprises a Vbb terminal, an IN terminal and an OUT terminal, and a P-type substrate, a charge pump and a GATE driving module arranged in the chip; the GATE driving module comprises a power MOS tube; characterized in that: When a high-side driving semiconductor chip is prepared by using a P-type semiconductor process, a substrate potential bias circuit is added between the IN terminal of the chip and the GATE terminal of the GATE driving module; The substrate potential bias circuit includes a driving switch module, a current mirror module and a GATE pull-down module; the input end of the driving switch module is connected to the output end of the charge pump, and is used to control the on and off of the charge pump output driving current; the current mirror module includes a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5, and a second PMOS tube P2; the source of the fifth NMOS tube N5 is connected to the P-type substrate, the drain thereof is connected to the IN terminal, and the gate thereof is connected to the gate and drain of the fourth NMOS tube N4, the gate of the third NMOS tube N3 and the drain of the second PMOS tube P2; the drain of the fourth NMOS tube N4 and the source of the third NMOS tube N3 are connected to the P-type substrate; The gate of the second PMOS tube P2 is connected to the power MOS tube control signal inL1, and the source thereof is connected to the bias current bias1; the GATE pull-down module includes a second NMOS tube N2, a third resistor R3, a fourth resistor R4, and a pull-down resistor R5; one end of the third resistor R3 is connected to the gate of the second NMOS tube N2; one end of the fourth resistor R4 is connected to the drain of the second NMOS tube N2; the source of the second NMOS tube N2 and one end of the fifth resistor are connected to the OUT end; the other ends of the third resistor R3, the fourth resistor R4 and the fifth resistor are all connected to the output end of the driving switch module; the drain of the third NMOS tube N3 is connected to the gate of the second NMOS tube N2; The substrate potential bias circuit realizes the following functions: When the power MOS tube control signal inL1 is turned off, the substrate potential bias circuit turns off the power MOS tube and provides additional pull-down current, so that the GATE terminal potential is approximately equal to the OUT terminal potential; When the power MOS tube control signal inL1 is turned on, the substrate potential bias circuit turns on the power MOS tube and simultaneously flows the current flowing into the P-type substrate into the IN terminal, thereby clamping the substrate potential to the IN terminal potential.

2. The substrate potential processing method of the high-side driving semiconductor chip according to claim 1, characterized in that ； When the power MOS tube control signal inL1 is turned off, the second NMOS tube N2 in the GATE pull-down module of the substrate potential bias circuit is turned on, and the power MOS tube is turned off by pulling down the GATE, and there is no output current at the OUT end; when the GATE is pulled down, the pull-down resistor R5 provides additional pull-down current, so that the potential of the GATE end is approximately equal to that of the OUT end; When the power MOS tube control signal inL1 is turned on, the second NMOS tube N2 is turned off, thereby turning off the pull-down current at the GATE end, the power MOS tube is turned on, and the charge pump outputs current from the OUT end; when the power MOS tube is turned on, the current flowing into the P-type substrate flows into the IN end through the substrate bias circuit, and at the same time clamps the substrate potential to the IN end potential.

3. The method for processing substrate potential of a high-side driving semiconductor chip according to claim 2, characterized in that: When the second NMOS tube N2 is turned on, the fourth resistor R4 limits the pull-down current of the second NMOS tube N2 to control the turn-off speed of the power MOS tube.

4. A high-side driving semiconductor chip, comprising a Vbb terminal, an IN terminal and an OUT terminal, as well as a P-type substrate, a charge pump, and a GATE driving module arranged in the chip; the GATE driving module comprises a power MOS tube; characterized in that: Also included is a substrate potential bias circuit; The substrate potential bias circuit includes a driving switch module, a current mirror module and a GATE pull-down module; The input end of the driving switch module is connected to the output end of the charge pump, and is used to control the on and off of the charge pump output driving current; the current mirror module includes a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5, and a second PMOS tube P2; the source of the fifth NMOS tube N5 is connected to the P-type substrate, the drain thereof is connected to the IN terminal, and the gate thereof is connected to the gate and drain of the fourth NMOS tube N4, the gate of the third NMOS tube N3, and the drain of the second PMOS tube P2; the drain of the fourth NMOS tube N4 and the source of the third NMOS tube N3 are connected to the P-type substrate; the gate of the second PMOS tube P2 is connected to the power M The OS tube control signal inL1 has a source connected to the bias current bias1; the GATE pull-down module includes a second NMOS tube N2, a third resistor R3, a fourth resistor R4, and a pull-down resistor R5; one end of the third resistor R3 is connected to the gate of the second NMOS tube N2; one end of the fourth resistor R4 is connected to the drain of the second NMOS tube N2; the source of the second NMOS tube N2 and one end of the fifth resistor are connected to the OUT end; the other ends of the third resistor R3, the fourth resistor R4 and the fifth resistor are all connected to the output end of the driving switch module; the drain of the third NMOS tube N3 is connected to the gate of the second NMOS tube N2; The substrate potential bias circuit realizes the following functions: When the power MOS tube control signal inL1 is turned off, the substrate potential bias circuit turns off the power MOS tube and provides additional pull-down current, so that the GATE terminal potential is approximately equal to the OUT terminal potential; When the power MOS tube control signal inL1 is turned on, the substrate potential bias circuit turns on the power MOS tube and simultaneously flows the current flowing into the P-type substrate into the IN terminal, thereby clamping the substrate potential to the IN terminal potential.

5. The high-side driver semiconductor chip according to claim 4, characterized in that: The driving switch module includes a first PMOS tube P1 and a first resistor R1; the gate of the first PMOS tube P1 is connected to the power MOS tube control signal inL1 through the first resistor R1, its source is connected to the charge pump output end, and its drain is connected to the third resistor R3, the fourth resistor R4 and one end of the fifth resistor R5.

6. The high-side driver semiconductor chip according to claim 5, characterized in that: The driving switch module further includes a first voltage regulator tube D1; the positive electrode of the first voltage regulator tube D1 is connected to the gate of the first PMOS tube P1, and the negative electrode thereof is connected to the source of the first PMOS tube P1.

7. The high-side driver semiconductor chip according to claim 4, 5 or 6, characterized in that: The GATE pull-down module further includes a second voltage regulator tube D2; the anode of the second voltage regulator tube D2 is connected to the gate of the second NMOS tube N2, and the cathode of the second voltage regulator tube D2 is connected to the drain of the first PMOS tube P1.

8. A method for processing substrate potential of a high-side driving semiconductor chip, wherein the high-side driving semiconductor chip comprises a Vbb terminal, an IN terminal, an OUT terminal and a GND terminal, and a P-type substrate, a charge pump and a GATE driving module arranged in the chip; the GATE driving module comprises a power MOS tube; characterized in that: When the power switch chip is prepared by using a P-type semiconductor process, a substrate potential bias circuit is added between the GND terminal of the high-side driving semiconductor chip and the P-type substrate; The substrate potential bias circuit is a depletion-type MOS tube or JFET tube connected in parallel between the GND terminal and the P-type substrate; The substrate potential bias circuit is used to realize the following functions: When the power MOS tube control signal inL1 is turned off, the substrate potential bias circuit turns off the power MOS tube and provides additional pull-down current, so that the GATE terminal potential of the GATE driver module pair is approximately equal to the OUT terminal potential; When the power MOS tube control signal inL1 is turned on, the substrate potential bias circuit turns on the power MOS tube and simultaneously flows the current flowing into the P-type substrate into the IN terminal, thereby clamping the substrate potential to the IN terminal potential.

9. A high-side driving semiconductor chip, comprising a Vbb terminal, an IN terminal, an OUT terminal and a GND terminal, as well as a P-type substrate, a charge pump and a GATE driving module arranged in the chip; the GATE driving module comprises a power MOS tube; characterized in that: It also includes a substrate potential bias circuit; the substrate potential bias circuit is a depletion-type MOS tube or JFET tube connected in parallel between the GND terminal and the P-type substrate; The substrate potential bias circuit realizes the following functions: When the power MOS tube control signal inL1 is turned off, the substrate potential bias circuit turns off the power MOS tube and provides additional pull-down current, so that the GATE terminal potential is approximately equal to the OUT terminal potential; When the power MOS tube control signal inL1 is turned on, the substrate potential bias circuit turns on the power MOS tube and simultaneously flows the current flowing into the P-type substrate into the IN terminal, thereby clamping the substrate potential to the IN terminal potential.

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