Storage medium, debugging auxiliary device, debugging auxiliary method and machine learning device

Abstract

The debugging auxiliary program causes the computer to execute the following steps: extracting a first variable assigned to an input to a module program (31) and a second variable assigned to an output from the module program (31) from a module program (31) constituting a sequencing program (30); creating a verification item for verifying the action of the module program (31), the verification item including a first set value set to the first variable and a second set value set to the second variable; verifying the action of the module program (31) based on the verification item; and outputting the result of verifying the action of the module program (31).

Description

Technical Field

[0001] The present invention relates to a storage medium, a debugging assistance device, a debugging assistance method and a machine learning device for assisting the debugging of a sequencer. Background Art

[0002] In factories that implement FA (Factory Automation), control devices represented by programmable logic controllers (PLCs) are used. The control devices control controlled devices by executing sequence programs.

[0003] A sequence program is composed of componentized programs, i.e., multiple modules. Hereinafter, the constituent elements of a sequence program, i.e., modules, are referred to as module programs. Input labels and output labels are recorded in a module program. An input label is a variable assigned to input from the outside of the module program to the module program. An output label is a variable assigned to output from the module program to the outside of the module program. A module program includes input labels and output labels with dependency relationships. A dependency relationship is a relationship in which the value of an input label determines the value of an output label.

[0004] In debugging for verifying the operation of a sequence program, the operation of a module program constituting the sequence program is verified. The module program is executed by inputting values ​​to the module program and the values ​​output from the module program are monitored to verify the operation of the module program.

[0005] Patent Document 1 discloses a simulation support tool that extracts variables for test input from a sequence program, generates test input values ​​for the extracted variables, and supplies input signals to a PLC that executes the sequence program.

[0006] Patent Document 1: Japanese Patent Application Publication No. 2005-44316 Summary of the invention

[0007] According to the prior art disclosed in the above-mentioned Patent Document 1, the input value for verification can be set, but on the other hand, the expected output value corresponding to the set input value is not set. Therefore, according to the prior art, there is a problem that it is difficult to verify the operation of the module program based on the monitored output value and it is difficult to debug the sequence program efficiently.

[0008] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to obtain a debugging assisting program for realizing efficient debugging of a sequence program.

[0009] In order to solve the above-mentioned problems and achieve the purpose, the debugging assistance program of the present invention enables a computer to function as a debugging assistance device that assists in debugging a sequence program executed by a control device. The debugging assistance program enables the computer to execute the following steps: extracting a first variable assigned to an input to the module program and a second variable assigned to an output from the module program from a module program constituting the sequence program; creating a verification item for verifying the action of the module program, the verification item including a first setting value set to the first variable and a second setting value set to the second variable; verifying the action of the module program based on the verification item; and outputting the result of verifying the action of the module program.

[0010] Effects of the Invention

[0011] The debugging assisting program according to the present invention achieves the effect of enabling efficient debugging of a sequence program. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a diagram showing the debugging support device according to the first embodiment.

[0013] Figure 2 This is a diagram showing the functional configuration of the debugging support device according to the first embodiment.

[0014] Figure 3 It is used to illustrate Figure 2 The diagram shows the structure of a verification pattern file used for operation verification of a module program.

[0015] Figure 4 FIG. 1 is a first diagram showing an example of a module program which is a debugging target in the first embodiment.

[0016] Figure 5 FIG. 2 is a second diagram showing an example of a module program which is a debugging target in the first embodiment.

[0017] Figure 6 Yes means Figure 4 and Figure 5 A diagram showing the tag names, data types, and categories of the tags contained in the module program.

[0018] Figure 7 This is a diagram showing a specific example of the verification mode used for debugging the module program in the first embodiment.

[0019] Figure 8 Yes means Figure 2 The flowchart of the operation flow of the input / output label extraction unit shown is shown.

[0020] Fig. 9 Yes means through Figure 2The diagram shown is a display example of the verification pattern obtained by the verification pattern display editing unit.

[0021] Fig.10 Yes means through Figure 2 The illustrated diagram is a diagram of an example of an editing screen of the verification mode implemented by the verification mode display editing unit.

[0022] Fig.11 Yes means through Figure 2 The illustrated diagram is a diagram of an example of a verification item editing screen implemented by the verification item display editing unit.

[0023] Fig.12 This is a first flow chart showing the flow of operations of the debug control unit constituting the debug support device according to the first embodiment.

[0024] Fig.13 This is a second flow chart showing the flow of operations of the debug control unit constituting the debug support device according to the first embodiment.

[0025] Fig.14 Yes means through Figure 2 FIG. 2 is a diagram showing an example of a verification result display screen implemented by the verification result display unit shown.

[0026] Fig.15 This is a diagram showing a machine learning device according to Implementation Example 2.

[0027] Fig.16 This is a diagram showing a structural example of a neural network used for learning in a machine learning device involved in Implementation Example 2.

[0028] Fig.17 This is a diagram showing a configuration example of hardware for realizing the debugging support device according to the first embodiment.

[0029] Fig.18 This is a diagram showing a configuration example of hardware for realizing a machine learning device according to Implementation Example 2. DETAILED DESCRIPTION

[0030] Hereinafter, the debugging assistance program, the debugging assistance device, the debugging assistance method, and the machine learning device involved in the implementation manner will be described in detail based on the accompanying drawings.

[0031] Implementation Method 1

[0032] Figure 11 is a diagram showing a debugging assistance device according to Embodiment 1. The debugging assistance device is a computer 10 having a debugging assistance program, namely a debugging assistance tool 11, installed therein. The computer 10 is a personal computer or a general-purpose computer. The debugging assistance device assists in debugging a sequence program executed by a control device, namely a PLC 12. The debugging assistance tool 11 is a program for assisting in debugging a sequence program.

[0033] When debugging the sequence program, the computer 10 is connected to the PLC 12. During debugging, the PLC 12 connected to the computer 10 is in a state where only the power supply unit and the CPU (Central Processing Unit) unit are connected to the base unit. The computer 10 writes the module program to the PLC 12 and causes the PLC 12 to execute the module program, thereby verifying the operation of the module program.

[0034] In the operation verification of the sequence program, the simulator 13 may be used instead of the PLC 12. The simulator 13 is an application that simulates the PLC 12 on the computer 10. The simulator 13 is installed in the computer 10. The computer 10 uses one of the PLC 12 and the simulator 13 to verify the operation of the module program, that is, debug. Figure 1 2 shows both a PLC 12 connected to a computer 10 and a simulator 13 installed in the computer 10 .

[0035] The computer 10 and the PLC 12 are connected to each other via a control network 15. The simulator 13 installed in the computer 10 is connected to the debugging support tool 11 via a virtual control network 14. The virtual control network 14 is a network based on the premise that the debugging support tool 11 and the simulator 13 are installed in the same computer 10. In addition, the debugging support tool 11 may be installed as a functional module in a tool other than the debugging support tool 11.

[0036] The debugging support tool 11 sets the values ​​of input labels and output labels included in the module program in advance, and verifies whether the set values ​​are obtained when the module program is executed.

[0037] like Figure 1 As shown in FIG. 1 , when the computer 10 is connected to the PLC 12, the module program to be debugged is written into the PLC 12 through the debugging auxiliary tool 11. Alternatively, Figure 1 As shown, in a state where the simulator 13 is installed in the computer 10 , the module program to be verified in operation is written into the simulator 13 via the debugging support tool 11 .

[0038] The debugging assistance tool 11 rewrites the value of the input label in the module program to the value set in the debugging assistance tool 11, and causes the PLC 12 or the simulator 13 to execute the module program. The value of the output label in the module program changes by the execution of the module program. The debugging assistance tool 11 monitors the changed value and compares the monitored value with the value pre-set by the debugging assistance tool 11. The debugging assistance tool 11 determines whether the monitored value is consistent with the pre-set value or whether the monitored value is inconsistent with the pre-set value. The debugging assistance tool 11 verifies the operation of the module program through this judgment. The debugging assistance tool 11 outputs the verification result. By outputting the verification result from the debugging assistance tool 11, the operator who has performed the debugging can easily confirm the result of the debugging.

[0039] Figure 2 1 is a diagram showing a functional configuration of the debug support device according to Embodiment 1. The functional configuration of the debug support device is implemented when a computer 10 executes a debug support tool 11 .

[0040] The debugging support tool 11 includes an input / output label extraction unit 20 , a verification item display editing unit 21 , a verification mode display editing unit 22 , a verification mode input / output unit 23 , a debugging control unit 24 , a verification result display unit 25 , a PLC transceiver unit 26 , a simulator transceiver unit 27 , and an internal storage unit 28 .

[0041] The input / output label extraction unit 20 is an extraction unit that extracts the first variable, that is, the input label, and the second variable, that is, the output label, from the module program 31 included in the sequencer 30. The input label is a label assigned to the input to the module program 31. A value is input to the input label from the outside of the module program 31. The output label is a label assigned to the output from the module program 31. The value of the output label is output to the outside of the module program 31. The input / output label extraction unit 20 classifies the extracted labels into input labels and output labels.

[0042] The verification item display editing unit 21 is a verification item creation unit that creates verification items for verifying the actions of the module program 31. The verification item includes a set of a first setting value set to an input tag and a second setting value set to an output tag. The verification item display editing unit 21 sets the first setting value and the second setting value. The verification item display editing unit 21 includes a set of a first setting value and a second setting value for an input tag and an output tag that have a dependency relationship with each other. The dependency relationship is a relationship in which the value of the second variable is determined by the value of the first variable. In addition, the verification item display editing unit 21 displays the verification items.

[0043] The verification pattern display editor 22 is a verification pattern creation unit that creates a verification pattern that groups a plurality of verification items for verifying the operation of the module program 31. The verification pattern display editor 22 manages the verification pattern. In addition, the verification pattern display editor 22 displays the verification pattern.

[0044] The verification pattern file 32 that collects a plurality of verification patterns is stored in the internal storage unit 28 or the external storage unit 29. The internal storage unit 28 is a storage unit inside the debug support device, and the external storage unit 29 is a storage unit outside the debug support device.

[0045] The verification mode input / output unit 23 outputs the verification mode file 32 to the internal storage unit 28 or the external storage unit 29. Also, the verification mode file 32 is input to the verification mode input / output unit 23 from the internal storage unit 28 or the external storage unit 29.

[0046] The PLC transceiver 26 transmits information to the PLC 12 and receives information from the PLC 12. The PLC transceiver 26 writes the verification mode and the module program 31 to the PLC 12 and causes the PLC 12 to execute the module program 31. When causing the PLC 12 to execute the module program 31, the PLC transceiver 26 obtains the output value of the module program 31.

[0047] The simulator transceiver 27 sends information to the simulator 13 and receives information from the simulator 13. The simulator transceiver 27 writes the verification mode and the module program 31 to the simulator 13 and causes the simulator 13 to execute the module program 31. When causing the simulator 13 to execute the module program 31, the simulator transceiver 27 obtains the output value of the module program 31.

[0048] The debug control unit 24 controls the writing of the module program 31 and the input value set to the verification mode to the PLC 12 or the simulator 13, and the monitoring of the output value of the module program 31. In addition, the debug control unit 24 performs the action verification of the module program 31 by comparing the monitored output value with the output value set to the verification mode. The verification result display unit 25 displays the result of the action verification. The verification result display unit 25 is a verification result output unit that outputs the verification result of the action of the module program 31.

[0049] Next, the structure of the verification pattern file 32 will be described. Figure 3 It is used to illustrate Figure 2 FIG. 2 is a diagram showing the structure of a verification pattern file 32 used for operation verification of a module program 31. FIG.

[0050] The verification mode file 32 is a file in which a plurality of verification modes 33 are grouped and filed. The verification mode file 32 is data for performing operation verification of the module program 31. Figure 3 As shown, one verification pattern file 32 is created for one module program 31 .

[0051] The verification pattern 33 is data obtained by grouping a plurality of verification items 35. The verification pattern 33 is assigned a verification category 34, which is information indicating the category of the action verification performed by the verification pattern 33. The verification category 34 is also referred to as an attribute of the verification pattern 33. The action verification is classified into the first verification, which is verification of normal action, the second verification, which is verification of abnormal action, and the third verification other than the first and second verifications. The third verification includes phenomena that cannot be clearly classified as normal or abnormal. The phenomenon includes quasi-normal values ​​that are different from normal but can be regarded as normal. The verification pattern 33 is assigned a verification category 34 indicating any one of the first verification, the second verification, and the third verification. The debug control unit 24 performs action verification according to the verification category 34 assigned to the verification pattern 33.

[0052] The verification item 35 includes an input label list 36 and an output label list 37. The input label list 36 is data obtained by grouping a plurality of input label settings 38. The output label list 37 is data obtained by grouping a plurality of output label settings 39.

[0053] The input tag setting 38 is data that sets the input tag 40 and the input tag setting value 41 extracted from the module program 31 as a group. The input tag setting value 41 is the first setting value set for the input tag 40. The input tag setting value 41 is written to the PLC 12 or the simulator 13 together with the module program 31 when the operation of the module program 31 is verified. The input tag setting value 41 is used to confirm the output value of the module program 31 corresponding to the input to the module program 31.

[0054] The output label setting 39 is data that sets the output label 42 extracted from the module program 31, the output label setting value 43, the setting category 44, and the read timing 45 as a group. The output label setting value 43 is the second setting value set for the output label 42. The setting category 44 is information indicating the method of comparing the output value of the module program 31 with the output label setting value 43 in the action verification. The debug control unit 24 compares the output value of the module program 31 with the output label setting value 43 according to the setting category 44. The details of the setting category 44 will be described later. The read timing 45 is information indicating the timing of the debug assisting device reading the output value of the module program 31.

[0055] Figure 4 FIG. 1 is a first diagram showing an example of a module program which is a debugging target in the first embodiment. Figure 5 FIG. 2 is a diagram showing an example of a module program that is the object of debugging in Embodiment 1. Module program 31 is a component obtained by componentizing a sequence program for each function, and is a function or a function module. In Embodiment 1, module program 31 is a ladder program written in ladder language. Module program 31 may also be a program written in a language other than ladder language.

[0056] Figure 4 and Figure 5 The module program 31 shown is composed of input tags 40 and output tags 42. Figure 6 Yes means Figure 4 and Figure 5 The diagram shows the label names, data types and categories of labels included in the module program 31. The input label 40 and the output label 42 are both bit type labels. Figure 6 The data type of the label shown is just an example, and the data type of the label is not limited to the bit type. Whether a label is an input label or an output label is determined by the label type. Labels with the category of VAR_INPUT or VAR_IN_OUT are input labels. Labels with the category of VAR_OUTPUT, VAR_OUTPUT_RETAIN, or VAR_IN_OUT are output labels.

[0057] Figure 4 and Figure 5 The module program 31 shown is a process for outputting a TRUE value to an output tag 42 when a TRUE value is input to an input tag 40. Figure 4 and Figure 5 The module program 31 shown is a process for outputting a FALSE value to an output tag 42 when a FALSE value is input to an input tag 40 .

[0058] Used for Figure 4 and Figure 5 The verification mode 33 for verifying whether the operation of the module program 31 shown is normal needs to include a verification item 35 for verifying that the value of the output tag 42 becomes a TRUE value by inputting a TRUE value to the input tag 40, and a verification item 35 for verifying that the value of the output tag 42 becomes a FALSE value by inputting a FALSE value to the input tag 40. Alternatively, the operation of the module program 31 can also be judged to be normal by the verification mode 33 for verifying whether the operation of the module program 31 is abnormal. For example, by verifying that the operation of the module program 31 is not abnormal by using the verification item 35 for verifying that the value of the output tag 42 becomes a TRUE value by inputting a FALSE value to the input tag 40, the operation can be judged to be normal.

[0059] Figure 7 This is a diagram showing a specific example of the verification pattern 33 used for debugging the module program 31 in Embodiment 1. Here, an example in which two verification patterns 33 are created to verify normal operation and abnormal operation in debugging the module program 31 will be described.

[0060] Figure 7 The "Verification Mode 1" shown is a verification mode 33 for verifying normal operation. "Verification Mode 1" is composed of two verification items 35, namely "Verification Item 1" and "Verification Item 2". "Verification Item 1" is a verification item 35 for verifying that the value of the output label 42 becomes a TRUE value by inputting a TRUE value to the input label 40. "Verification Item 2" is a verification item 35 for verifying that the value of the output label 42 becomes a FALSE value by inputting a FALSE value to the input label 40. The debug control unit 24 can determine that the operation of the module program 31 is normal based on the establishment of "Verification Item 1" and "Verification Item 2". In addition, in Figure 7 In the example, the TRUE value and FALSE value are represented as "ON" and "OFF", respectively. Figure 7 The “input data” shown indicates data input to the tag 40 . The “output data” shown indicates data output to the tag 42 .

[0061] Figure 7 The "verification mode 2" shown is a verification mode 33 for verifying abnormal operation. "Verification mode 2" is composed of one verification item 35, namely "verification item 1". "Verification item 1" is a verification item 35 for verifying that the value of output tag 42 becomes TRUE value by inputting FALSE value to input tag 40. The debug control unit 24 can determine that the operation of module program 31 is abnormal based on the establishment of "verification item 1".

[0062] exist Figure 7 , for each of "Verification Item 1" and "Verification Item 2" of "Verification Mode 1" and "Verification Item 1" of "Verification Mode 2", "Tag Name", "Data Type", "Setting Category", and "Input Value" of input tag 40, and "Tag Name", "Data Type", "Setting Category", and "Output Value" of output tag 42 are shown. "Input Value" is input tag setting value 41. "Output Value" is output tag setting value 43.

[0063] Regarding the input tag 40, "equal to the value behind" written in the column of "setting category" indicates a setting category 44 that is equal to the value in the column next to the column of "setting category", that is, the input tag setting value 41. Regarding the output tag 42, "equal to the value behind" written in the column of "setting category" indicates a setting category 44 that is equal to the output tag setting value 43. As setting categories 44, in addition to "equal to the value behind", there are "not equal to the value behind", "other than the value behind", "larger than the value behind", "smaller than the value behind", "greater than or equal to the value behind", "smaller than or equal to the value behind", etc.

[0064] Next, extraction of labels performed by the input / output label extraction unit 20 will be described. Figure 8 Yes means Figure 2 Flowchart showing the operation flow of the input / output label extraction unit 20 .

[0065] In step S1, the input / output label extraction unit 20 extracts all labels from the module program 31 and stores the extracted labels in a label list. The label list is data obtained by grouping the extracted labels. The label extraction method can adopt the method described in the above-mentioned patent document 1. The label extraction method can also be a method other than the method of patent document 1.

[0066] In step S2, the input / output label extraction unit 20 extracts one label from the label list. In step S3, the input / output label extraction unit 20 determines whether the category of the extracted label is VAR_INPUT or VAR_IN_OUT. In other words, the input / output label extraction unit 20 determines whether the extracted label is the input label 40.

[0067] When the type of the extracted label is VAR_INPUT or VAR_IN_OUT (step S3, Yes), the input / output label extraction unit 20 determines that the extracted label is the input label 40. In this case, in step S4, the input / output label extraction unit 20 registers the extracted label in the input label list 36. Thereafter, the input / output label extraction unit 20 advances the flow to step S5.

[0068] On the other hand, when the type of the extracted label is not VAR_INPUT or VAR_IN_OUT (step S3, No), the input / output label extraction unit 20 determines that the extracted label is not the input label 40. In this case, the input / output label extraction unit 20 advances the flow to step S5.

[0069] In step S5 , the input / output label extraction unit 20 determines whether the type of the extracted label is VAR_OUTPUT, VAR_OUTPUT_RETAIN, or VAR_IN_OUT. In other words, the input / output label extraction unit 20 determines whether the extracted label is the output label 42 .

[0070] When the type of the extracted label is VAR_OUTPUT, VAR_OUTPUT_RETAIN, or VAR_IN_OUT (step S5, Yes), the input / output label extraction unit 20 determines that the extracted label is the output label 42. In this case, in step S6, the input / output label extraction unit 20 registers the extracted label in the output label list 37. Thereafter, the input / output label extraction unit 20 advances the flow to step S7.

[0071] On the other hand, when the type of the extracted label is not VAR_OUTPUT, VAR_OUTPUT_RETAIN, or VAR_IN_OUT (step S5 , No), the input / output label extraction unit 20 advances the flow to step S7 .

[0072] In step S7, the input / output label extraction unit 20 determines whether the classification of all extracted labels has been completed. If the classification of all labels has not been completed (step S7, No), the input / output label extraction unit 20 returns the process to step S2. The input / output label extraction unit 20 repeats the process from step S2 to continue the classification of labels. On the other hand, if the classification of all labels has been completed (step S7, Yes), the input / output label extraction unit 20 returns the classification of all labels to step S2. Figure 8 The operation implemented by the flow shown is completed. Thus, the input / output label extraction unit 20 extracts labels from the module program 31 and classifies the extracted labels.

[0073] Next, the display of the verification pattern 33 by the verification pattern display editing unit 22 will be described. Fig. 9 It means by Figure 2 The verification mode display editing unit 22 shows a display example of the verification mode 33. Fig. 9 , an example of a window showing a list of verification modes 33 applied to the module program 31 is shown.

[0074] The verification mode display editing unit 22 can switch the window displayed on the screen in units of module programs 31. In addition, the operator can Fig. 9 In the window shown, an editing operation is performed to create a new authentication pattern 33. The newly created authentication pattern 33 is stored in the internal storage unit 28 or the external storage unit 29.

[0075] Fig.10 Yes means through Figure 2 The illustrated diagram is a diagram of an example of an editing screen of the verification mode 33 implemented by the verification mode display editing unit 22. The editing screen of the verification mode 33 is Fig. 9 The window shown is opened when an operation for creating a new authentication mode 33 is performed. The operator can input the name of the authentication mode 33 and the authentication type 34 from the editing screen of the authentication mode 33. Fig.10 The “mode name” shown is the name of the authentication mode 33 .

[0076] The list of verification items 35 is displayed on the editing screen of the verification mode 33. The operator can perform editing operations for creating a new verification item 35 or changing an existing verification item 35 from the list of verification items 35. In addition, the operator can understand the creation date and time of the verification item 35, the creator, etc. from the list of verification items 35.

[0077] Fig.11 Yes means through Figure 2 The figure shows an example of an editing screen of the verification item 35 implemented by the verification item display editing unit 21. The editing screen of the verification item 35 is Fig.10 The editing screen of the verification mode 33 shown is opened when an operation for creating a new verification item 35 or an operation for changing an existing verification item 35 is performed. The operator can input the name of the verification item 35, the creator name of the verification item 35, the input tag setting value 41, the output tag setting value 43, etc. from the editing screen of the verification item 35.

[0078] Next, the operation of the debug control unit 24 when debugging the module program 31 will be described. Fig.12 FIG. 1 is a first flow chart showing the operation flow of the debug control unit 24 constituting the debug assisting device according to the first embodiment. Fig.12 2 shows an operation flow when the operation verification of the module program 31 is performed by causing the PLC 12 to execute the module program 31 .

[0079] In step S11 , the debug control unit 24 acquires the module program 31 to be debugged from the sequence program 30 .

[0080] In step S12, the debug control unit 24 obtains the verification mode 33 corresponding to the obtained module program 31. Here, the debug control unit 24 instructs the verification mode input / output unit 23 to read the verification mode 33 corresponding to the obtained module program 31. The verification mode input / output unit 23 reads the verification mode file 32 corresponding to the module program 31 from the internal storage unit 28 or the external storage unit 29 according to the instruction from the debug control unit 24. The verification mode input / output unit 23 sends the read verification mode file 32 to the debug control unit 24. In this way, the debug control unit 24 obtains the verification mode 33 via the verification mode input / output unit 23.

[0081] In step S13, the debug control unit 24 extracts one verification item 35 from the obtained verification pattern 33, and obtains an input label setting 38 and an output label setting 39. The debug control unit 24 obtains the input label setting 38 from the input label list 36 included in the verification item 35. The debug control unit 24 obtains the output label setting 39 from the output label list 37 included in the verification item 35.

[0082] In step S14, the debug control unit 24 sets the output tag 42 read by the PLC transceiver 26 and the timing of obtaining the output value. The debug control unit 24 sets the output tag 42 included in the output tag setting 39 to the output tag 42 read by the PLC transceiver 26. The debug control unit 24 sets the read timing 45 included in the output tag setting 39 to the timing of obtaining the output value of the PLC 12 through the PLC transceiver 26.

[0083] In step S15, the debug control unit 24 writes the module program 31 to the PLC 12, sets the value to the input tag 40 of the module program 31, and causes the PLC 12 to operate. The debug control unit 24 writes the module program 31 to the PLC 12 via the PLC transceiver 26. The debug control unit 24 sets the input tag setting value 41 included in the input tag setting 38 to the value of the input tag 40 of the module program 31.

[0084] The debug control unit 24 monitors the value of the output tag 42 of the module program 31 executed by the PLC 12 via the PLC transceiver 26. In step S16, the debug control unit 24 determines whether the set read timing 45 has been reached. If the read timing 45 has not been reached (step S16, No), the debug control unit 24 waits until the read timing 45 is reached. If the read timing 45 has been reached (step S16, Yes), the debug control unit 24 advances the flow to step S17.

[0085] In step S17, the debug control unit 24 obtains the value output by the output tag 42 of the module program 31. The debug control unit 24 obtains the value of the output tag 42 in the module program 31 from the PLC 12 via the PLC transceiver 26.

[0086] In step S18, the debug control unit 24 compares the value obtained from the PLC 12 and the output tag setting value 43 according to the setting category 44. The debug control unit 24 uses the output tag setting value 43 included in the output tag setting 39 for comparison. The debug control unit 24 compares according to the setting category 44 included in the output tag setting 39. For example, when the setting category 44 is "equal to the following value", the debug control unit 24 compares the value obtained from the PLC 12 with the output tag setting value 43 to determine whether the value obtained from the PLC 12 is the same as the output tag setting value 43.

[0087] The debug control unit 24 determines the result of the operation verification based on the comparison result in step S18. The debug control unit 24 obtains the result of the operation verification according to the verification type 34 assigned to the verification mode 33.

[0088] In step S19, the debug control unit 24 outputs the result of the operation verification to the verification result display unit 25. The verification result display unit 25 displays the result of the operation verification.

[0089] In step S20, the debug control unit 24 determines whether the action verification has been completed for all the verification items 35 of the verification mode 33. When there are verification items 35 for which the action verification has not been performed (step S20, No), the debug control unit 24 returns the process to step S13, and performs the process of step S13 and thereafter for the verification items 35 for which the action verification has not been performed. On the other hand, when the action verification for all the verification items 35 has been completed (step S20, Yes), the debug control unit 24 stops the PLC 12 in step S21. The debug control unit 24 sends a stop command to the PLC 12 via the PLC transceiver 26, thereby stopping the PLC 12. As a result, the debug control unit 24 stops the PLC 12. Fig.12 The actions implemented by the shown flow are completed.

[0090] Fig.13 2 is a second flow chart showing the operation flow of the debug control unit 24 constituting the debug assisting device according to the first embodiment. Fig.13 , the operation flow in the case of performing operation verification of the module program 31 by causing the simulator 13 to execute the module program 31 is shown. Fig.13 The illustrated flow is based on the premise that the debugging support tool 11 and the simulator 13 are installed on the same computer 10 and the simulator 13 is already started.

[0091] In step S31, the debug control unit 24 obtains the module program 31 to be debugged from the sequence program 30. In step S32, the debug control unit 24 obtains the verification mode 33 corresponding to the obtained module program 31. The details of step S32 are as follows. Fig.12 The step S12 shown is the same.

[0092] In step S33, the debug control unit 24 extracts one verification item 35 from the obtained verification pattern 33, and obtains the input label setting 38 and the output label setting 39. The details of step S33 are as follows: Fig.12 The step S13 shown is the same.

[0093] In step S34, the debug control unit 24 sets the output label 42 read by the simulator transceiver 27 and the timing of obtaining the output value. The debug control unit 24 sets the output label 42 included in the output label setting 39 to the output label 42 read by the simulator transceiver 27. The debug control unit 24 sets the read timing 45 included in the output label setting 39 to the timing of obtaining the output value of the simulator 13 through the simulator transceiver 27.

[0094] In step S35, the debug control unit 24 writes the module program 31 to the simulator 13, sets the value to the input tag 40 of the module program 31, and executes the simulator 13. The debug control unit 24 writes the module program 31 to the simulator 13 via the simulator transceiver 27. The debug control unit 24 sets the input tag setting value 41 included in the input tag setting 38 to the value of the input tag 40 of the module program 31.

[0095] The debug control unit 24 monitors the value of the output tag 42 of the module program 31 executed by the simulator 13 via the simulator transceiver 27. In step S36, the debug control unit 24 determines whether the set read timing 45 has been reached. If the read timing 45 has not been reached (step S36, No), the debug control unit 24 waits until the read timing 45 is reached. If the read timing 45 has been reached (step S36, Yes), the debug control unit 24 advances the flow to step S37.

[0096] In step S37 , the debug control unit 24 obtains the value output by the output tag 42 of the module program 31 . The debug control unit 24 obtains the value of the output tag 42 in the module program 31 from the simulator 13 via the simulator transceiver 27 .

[0097] In step S38, the debug control unit 24 compares the value obtained from the simulator 13 with the output tag setting value 43 according to the setting type 44. Fig.12 The step S18 shown is the same.

[0098] In step S39, the debug control unit 24 outputs the result of the operation verification to the verification result display unit 25. The verification result display unit 25 displays the result of the operation verification.

[0099] In step S40, the debug control unit 24 determines whether the action verification has been completed for all the verification items 35 of the verification mode 33. If there are verification items 35 for which the action verification has not been performed (step S40, No), the debug control unit 24 returns the process to step S33, and performs the process of step S33 and thereafter for the verification items 35 for which the action verification has not been performed. On the other hand, if the action verification has been completed for all the verification items 35 (step S40, Yes), the debug control unit 24 stops the simulator 13 in step S41. The debug control unit 24 sends a stop instruction to the simulator 13 via the simulator transceiver unit 27, thereby stopping the simulator 13. As a result, the debug control unit 24 stops the simulator 13. Fig.13 The actions implemented by the shown flow are completed.

[0100] Next, the display performed by the verification result display unit 25 will be described. Fig.14 Yes means through Figure 2 FIG. 2 is a diagram showing an example of a verification result display screen implemented by the verification result display unit 25. The verification result display screen is a screen that displays the result of the action verification. Fig.12 In the case of the operation verification realized by the process shown in FIG. 1 , the verification result display unit 25 displays the verification result display screen when the process from step S11 to step S19 is completed. Fig.13 In the case of the operation verification realized by the flow shown, the verification result display unit 25 displays the verification result display screen when the flow from step S31 to step S39 is completed.

[0101] The verification result display screen includes a verification result display column and a verification mode display column. The verification result display column displays the result of the action verification of each verification item 35. Fig.10 The same verification item list and the result of the operation verification of each verification item 35 are displayed.

[0102] The verification mode display column displays the results of the operation verification of each verification mode 33. Fig. 9The same verification mode list and the results of the action verification of each verification mode 33 are displayed. In the verification result display column and the verification mode display column, the results of the action verification are displayed by distinguishing the colors of the columns. Information indicating the results of the action verification can also be displayed in the verification result display screen. The result can be confirmed by visual observation, and the method of displaying the results of the action verification is arbitrary. The operator can easily confirm the results of the action verification from the verification result display screen.

[0103] According to the first embodiment, the debugging assistance device creates a verification item 35 including an input tag setting value 41 and an output tag setting value 43, and performs action verification of the module program 31 based on the verification item 35. The debugging assistance device can set a free value for each of the input tag setting value 41 and the output tag setting value 43, so that debugging with a high degree of freedom can be performed. The debugging assistance device can set both the input tag setting value 41 and the output tag setting value 43, thereby enabling verification of whether the action is normal and whether the action is abnormal. The debugging assistance device can create the verification item 35 by inputting a value, thereby enabling verification item 35 to be created easily and efficiently. Compared with the case where the processing for verification needs to be described in advance by a script language, etc., the debugging assistance device can achieve efficient debugging work.

[0104] The debugging assistance device automatically compares the output value of the module program 31 and the output tag setting value 43 according to the setting category 44, and obtains the result of the action verification according to the verification category 34. Compared with the case where the expected output value corresponding to the set input value is not set and the action verification is performed only based on the monitored output value, the debugging assistance device can easily obtain the result of the action verification. In addition, the operator can easily confirm the result of the action verification output by the debugging control unit 24 in the verification result display screen. As a result, the debugging assistance device can realize the efficiency of the operation for debugging.

[0105] The debugging support device can store the verification mode file 32 not only in the internal storage unit 28 but also in the external storage unit 29, so that multiple operators can share the verification mode file 32. Since multiple operators can share the verification mode file 32, it is easy to share debugging among multiple operators. In addition, when the verification mode 33 is created in consideration of the dependency relationship between the module programs 31 in the sequencer 30, it is possible to prevent omission of verification caused by sharing debugging among multiple operators, and to achieve detailed debugging.

[0106] In the operation verification of the module program 31, the module program 31 can be executed not only in the PLC 12 but also in the simulator 13. By using the simulator 13, the debugging support device can perform background operation verification, which can reduce the man-hours required for debugging. In the operation verification of the module program 31, the operator can arbitrarily select the PLC 12 and the simulator 13 to execute the module program 31.

[0107] Furthermore, in order to share the debugging among multiple operators, multiple computers 10 are used, each of which is installed with the debugging support tool 11. In this case, each of the multiple operators can use a different computer 10 to debug the sequence program 30. Alternatively, multiple operators may share the debugging using the computer 10 installed with the debugging support tool 11. In either case, by sharing the work among multiple operators, the debugging efficiency can be improved.

[0108] Therefore, according to the first embodiment, the debug support tool 11 and the debug support device achieve the effect of enabling efficient debugging of the sequence program.

[0109] Implementation Method 2

[0110] In the second embodiment, a case where machine learning is used for creating the verification item 35 is described. Fig.15 1 is a diagram showing a machine learning device according to Embodiment 2. A learning device 50 which is a machine learning device according to Embodiment 2 learns verification items 35 for operation verification of a module program 31 while assisting debugging of a sequence program 30 by a debugging assisting tool 11 .

[0111] The learning device 50 includes a verification item acquisition unit 52, a learning unit 53, and an inference unit 56. The verification item acquisition unit 52 acquires the verification item 35 from a verification pattern storage unit 51 outside the learning device 50. The verification pattern storage unit 51 is Figure 2 The internal storage unit 28 or the external storage unit 29 is shown.

[0112] The learning unit 53 uses a data set including the verification items 35 input from the verification item acquisition unit 52, i.e., two input verification items, to generate a trained model for inferring the output verification items. "Input verification item 1" is the first of the two input verification items. "Input verification item 2" is the second of the two input verification items. The label names of the input labels or the label names of the output labels defined in each of the verification items 35 of "Input verification item 1" and "Input verification item 2" contain at least one label name that is consistent with each other. The output verification item is a new and optimal verification item 35 used in action verification. The trained model storage unit 54 stores the generated trained model. Fig.15 In the example, the trained model storage unit 54 is a storage unit outside the learning device 50. The trained model storage unit 54 may also be provided inside the learning device 50.

[0113] The inference unit 56 receives the input verification item from the verification item acquisition unit 52, and infers the output verification item using the trained model. The inference unit 56 outputs the output verification item by inputting the input verification item to the trained model.

[0114] The learning unit 53 learns the input verification items by so-called supervised learning, for example, according to a neural network model. The neural network of the learning unit 53 learns the characteristics of the input verification items according to the created data set by so-called supervised learning. Here, supervised learning refers to a model in which a set of input and result data is provided to the learning device 50, thereby learning the characteristics of the data set and inferring the result based on the input.

[0115] The data set contains an input and the result corresponding to the input, i.e., a label. "Input verification item 1" is equivalent to the input, and "Input verification item 2" is equivalent to the label. The neural network is composed of the following layers, i.e., an input layer composed of multiple neurons, an intermediate layer, i.e., a hidden layer, composed of multiple neurons, and an output layer composed of multiple neurons. The intermediate layer can be 1 layer or greater than or equal to 2 layers.

[0116] Fig.16 This is a diagram showing a structural example of a neural network used for learning in a machine learning device involved in Implementation Example 2. Fig.16 The neural network shown is a 3-layer neural network. The input layer includes neurons X1, X2, and X3. The middle layer includes neurons Y1 and Y2. The output layer includes neurons Z1, Z2, and Z3. In addition, the number of neurons in each layer is arbitrary. Multiple values ​​input to the input layer are multiplied by weights W1, i.e., w11, w12, w13, w14, w15, and w16, and input to the middle layer. Multiple values ​​input to the middle layer are multiplied by weights W2, i.e., w21, w22, w23, w24, w25, and w26, and output from the output layer. The output result output from the output layer changes according to the values ​​of weights W1 and W2.

[0117] The learning unit 53 creates a data set based on the combination of "input verification item 1" and "input verification item 2". The neural network learns the output verification item according to the created data set through so-called teacher learning. That is, the neural network learns the output verification item by adjusting the weights W1 and W2 in such a way that the result output from the output layer when "input verification item 1" is input to the input layer is close to "input verification item 2". The learning device 50 generates a trained model by performing the above-mentioned learning, and stores the trained model in the trained model storage unit 54.

[0118] The inference unit 56 acquires the trained model from the trained model storage unit 54. The inference unit 56 inputs the input verification item to the trained model, thereby outputting the output verification item inferred from the input verification item.

[0119] The learning device 50 is not limited to inferring the output verification event using the trained model generated by the learning unit 53 in the learning device 50. The learning device 50 may acquire a trained model created outside the learning device 50 and infer the output verification event using the acquired trained model.

[0120] In the second embodiment, the function of the learning device 50 is built into the debugging support tool 11. That is, the learning device 50 is built into the debugging support device. The learning device 50 may be a device existing on a cloud server that can communicate with the debugging support device.

[0121] According to the second embodiment, the learning device 50 can create a new verification item 35 , namely, an output verification item, based on an existing verification item 35 , namely, an input verification item.

[0122] Next, hardware for realizing the debugging support device according to the first embodiment will be described. Fig.17 This is a diagram showing a configuration example of hardware for realizing the debugging support device according to the first embodiment. Fig.17 The hardware shown is, for example, a computer 10. Fig.17 2 shows a configuration in which the main parts of the debug support device, specifically, the input / output label extraction unit 20, the verification item display editing unit 21, the verification mode display editing unit 22, and the debug control unit 24 are realized by a processing circuit 61 having a processor 63 and a memory 64.

[0123] The input unit 62 is a circuit that receives input signals for the debugging assistance device from the outside. The input unit 62 is responsible for receiving the module program 31, receiving the verification mode file 32 from the external storage unit 29, receiving the information output from the PLC 12, and receiving the information output from the simulator 13. The output unit 65 is a circuit that outputs the signal generated by the debugging assistance device to the outside. The output unit 65 is responsible for sending the verification mode file 32 to the external storage unit 29, sending the module program 31 to the PLC 12, and sending the module program 31 to the simulator 13. The verification mode input and output unit 23, the PLC transceiver unit 26, and the simulator transceiver unit 27 are implemented by the input unit 62 and the output unit 65.

[0124] The processor 63 is a CPU. The processor 63 may also be a computing device, a microprocessor, a microcomputer, or a DSP (Digital Signal Processor). The memory 64 is, for example, a nonvolatile or volatile memory such as a RAM (Random Access Memory), a ROM (Read Only Memory), a flash memory, an EPROM (Erasable Programmable Read Only Memory), or an EEPROM (registered trademark) (Electrically Erasable Programmable Read Only Memory).

[0125] When the main parts of the debugging support device are realized by the processor 63 and the memory 64, the above parts are realized by the processor 63 executing the debugging support tool 11 in which the processing for operating as the input / output label extraction unit 20, the verification item display editing unit 21, the verification mode display editing unit 22, and the debugging control unit 24 is described. The debugging support tool 11 is stored in advance in the memory 64. The processor 63 reads and executes the debugging support tool 11 stored in the memory 64, thereby operating as the input / output label extraction unit 20, the verification item display editing unit 21, the verification mode display editing unit 22, and the debugging control unit 24. The internal storage unit 28 is realized by the memory 64.

[0126] The debugging assistance tool 11 is not limited to being pre-stored in the memory 64. The debugging assistance tool 11 may also be stored in a storage medium that can be read by the computer system. The debugging assistance tool 11 stored in the storage medium may also be stored in the memory 64. The storage medium may also be a floppy disk, i.e., a portable storage medium, or a semiconductor memory, i.e., a flash memory. The debugging assistance tool 11 may also be installed in the computer 10 from another computer or a server device via a communication network.

[0127] The display unit 66 is a display for displaying information. The display unit is, for example, a liquid crystal display (LCD). The display function of the verification item display editing unit 21 , the display function of the verification mode display editing unit 22 , and the verification result display unit 25 are realized by the display unit 66 .

[0128] Next, the hardware for realizing the machine learning device according to the second embodiment is described. Fig.18 FIG. 2 is a diagram showing a configuration example of hardware for realizing a machine learning device according to Embodiment 2. Fig.18 2 shows a configuration in which a machine learning device, namely, a learning unit 53 and an inference unit 56 of a learning device, is implemented by a processing circuit 71 having a processor 73 and a memory 74. In addition, the hardware implementing the debugging support device may also serve as the hardware implementing the machine learning device.

[0129] The input unit 72 is a circuit that receives input signals from the outside to the learning device 50. The output unit 75 is a circuit that outputs signals generated by the learning device 50 to the outside. The verification item acquisition unit 52 is implemented by the input unit 72. In addition, the input unit 72 is responsible for inputting the trained model. The output unit 75 is responsible for outputting the trained model and outputting the verification items.

[0130] The details of the processor 73 and the memory 74 are as follows Fig.17 The processor 63 and the memory 64 shown in the figure are the same. When the learning unit 53 and the inference unit 56 are implemented by the processor 73 and the memory 74, the above-mentioned units are implemented by executing a program in which a process for operating as the learning unit 53 and the inference unit 56 is recorded by the processor 73. The program is stored in the memory 74 in advance. The program can also be stored in a storage medium, similar to the case of the debugging support tool 11.

[0131] The structure shown in the above embodiments is an example of the content of the present invention. The structure of each embodiment can be combined with other known technologies. The structures of each embodiment can also be appropriately combined with each other. Without departing from the gist of the present invention, a part of the structure of each embodiment can be omitted or changed.

[0132] Description of the label

[0133] 10 computer, 11 debugging support tool, 12 PLC, 13 simulator, 14 virtual control network, 15 control network, 20 input and output label extraction unit, 21 verification item display editing unit, 22 verification mode display editing unit, 23 verification mode input and output unit, 24 debugging control unit, 25 verification result display unit, 26 PLC transceiver unit, 27 simulator transceiver unit, 28 internal storage unit, 29 external storage unit, 30 sequence program, 31 module program, 32 verification mode file, 33 verification mode, 34 verification category, 35 verification item , 36 input label list, 37 output label list, 38 input label setting, 39 output label setting, 40 input label, 41 input label setting value, 42 output label, 43 output label setting value, 44 set category, 45 read timing, 50 learning device, 51 verification mode storage unit, 52 verification item acquisition unit, 53 learning unit, 54 trained model storage unit, 56 inference unit, 61, 71 processing circuit, 62, 72 input unit, 63, 73 processor, 64, 74 memory, 65, 75 output unit, 66 display unit.

Claims

1. A storage medium storing a debugging assistance program for causing a computer to function as a debugging assistance device for assisting debugging of a sequence program executed by a control device, The storage medium is characterized in that the debugging auxiliary program enables the computer to execute the following steps: extracting, from a module program constituting the sequence program, a first variable assigned to an input to the module program and a second variable assigned to an output from the module program; creating a verification item for verifying the operation of the module program, the verification item including a first setting value set to the first variable and a second setting value set to the second variable; performing operation verification of the module program by comparing the value of the second variable with the second set value included in the verification item; and Output the result of verifying the action of the module program, The verification items are saved in the form of files, and names are given to the verification items. The verification item is composed of the first setting value and the second setting value related to the first variable and the second variable having a dependent relationship with each other, The dependency relationship is a relationship in which the value of the second variable is determined by the value of the first variable.

2. The storage medium according to claim 1, characterized in that The steps of performing the action verification include the following steps: acquiring a value of the second variable obtained by executing the module program that writes the first setting value into the first variable; and The acquired value of the second variable is compared with the second set value.

3. The storage medium according to claim 2, characterized in that The verification item includes information on a setting type indicating a method of comparing the value of the second variable with the second setting value.

4. The storage medium according to claim 1, characterized in that The verification items include information on a reading timing which is a timing for acquiring a value of the second variable obtained by executing the module program.

5. The storage medium according to claim 1, characterized in that Further causing the computer to execute the following steps: A verification pattern is created in which a plurality of the verification items for detecting the operation of the module program are grouped.

6. The storage medium according to claim 5, characterized in that Further causing the computer to execute the following steps: storing the verification pattern in a storage unit inside the debugging assistance device or outside the debugging assistance device, In the step of performing the operation verification, the operation verification is performed based on each of the plurality of verification items included in the verification pattern read out from the storage unit.

7. The storage medium according to claim 5, characterized in that The action verification is classified into the first verification, which is the verification of normal action, and the second verification, which is the verification of abnormal action. The verification mode is assigned a verification type indicating the first verification or the second verification, In the step of performing the action verification, the action verification is performed according to the verification type.

8. The storage medium according to claim 6, characterized in that The action verification is classified into the first verification, which is the verification of normal action, and the second verification, which is the verification of abnormal action. The verification mode is assigned a verification type indicating the first verification or the second verification, In the step of performing the action verification, the action verification is performed according to the verification type.

9. The storage medium according to claim 1, characterized in that In the step of performing the operation verification, the operation verification is performed by causing the control device to execute the module program.

10. The storage medium according to claim 1, characterized in that In the step of performing the operation verification, the operation verification is performed by causing a simulator that simulates the control device to execute the module program.

11. The storage medium according to claim 1, characterized in that Further causing the computer to execute the following steps: The results of verifying the operation of the module program are displayed.

12. A debugging assistance device for assisting the debugging of a sequence program executed by a control device, The debugging auxiliary device is characterized in that it has: an extracting unit that extracts, from a module program constituting the sequence program, a first variable assigned to an input to the module program and a second variable assigned to an output from the module program; a verification item creation unit that creates a verification item for verifying the operation of the module program, the verification item including a first setting value set to the first variable and a second setting value set to the second variable; a debug control unit that performs operation verification of the module program by comparing the value of the second variable with the second set value included in the verification item; and a verification result output unit that outputs the result of verifying the operation of the module program, The verification items are saved in the form of files, and names are given to the verification items. The verification item is composed of the first setting value and the second setting value related to the first variable and the second variable having a dependent relationship with each other, The dependency relationship is a relationship in which the value of the second variable is determined by the value of the first variable.

13. A debugging assistance method, which is performed by a debugging assistance device, the debugging assistance device assisting the debugging of a sequence program executed by a control device, The debugging auxiliary method is characterized by comprising the following steps: extracting, from a module program constituting the sequence program, a first variable assigned to an input to the module program and a second variable assigned to an output from the module program; creating a verification item for verifying the operation of the module program, the verification item including a first setting value set to the first variable and a second setting value set to the second variable; performing operation verification of the module program by comparing the value of the second variable with the second set value included in the verification item; and Output the result of verifying the action of the module program, The verification items are saved in the form of files, and names are given to the verification items. The verification item is composed of the first setting value and the second setting value related to the first variable and the second variable having a dependent relationship with each other, The dependency relationship is a relationship in which the value of the second variable is determined by the value of the first variable.

14. A machine learning device for learning verification items used for operation verification of module programs constituting a sequence program in assisting debugging of the sequence program by the debugging assisting program according to any one of claims 1 to 11, The machine learning device is characterized by having: a verification item acquisition unit that acquires the verification item; and A learning unit generates a trained model using a data set including the verification items, i.e., two input verification items, input from the verification item acquisition unit. The trained model is used to infer new verification items, i.e., output verification items, used for the action verification based on the input verification items.

15. The machine learning device according to claim 14, characterized in that The system further includes an inference unit that receives the input verification item and uses the trained model to infer the output verification item.

Images