Resource scheduling methods, devices, and cloud-based base stations

Abstract

This disclosure provides a resource scheduling method, apparatus, and cloud-based base station, relating to the field of communication technology. The method includes: creating a cache resource pool; sending the address of the cache resource pool to an application so that the application stores first data required to execute a computing task into the cache resource pool, the computing task being offloaded from a general-purpose processor to a hardware accelerator; using a logic processing unit allocated to the application, generating instructions corresponding to the configuration file required by the hardware accelerator to execute the computing task; and adding the instructions and the first data to a queue so that the hardware accelerator can execute the computing task from the queue by calling the instructions and the first data.

Description

Technical Field

[0001] This disclosure relates to the field of communication technology, and in particular to a resource scheduling method, apparatus and cloud-based base station. Background Technology

[0002] Deploying 6G cloud base stations and mobile edge computing (MEC) on a co-platform can meet the elastic scaling requirements of various 6G services for underlying wireless infrastructure resources, achieving pooled gains.

[0003] Container technology can be used to deploy large-scale clustered edge applications for mobile edge computing platforms. Summary of the Invention

[0004] In related technologies, hardware accelerators can be used to offload the computing tasks of containers, thereby saving computing resources of general-purpose processors (such as CPUs).

[0005] The inventors noticed that the processing speed of hardware accelerators in related technologies is relatively low. Through analysis, the inventors discovered that in related technologies, hardware accelerators read and write data from their own memory. However, the processing speed of the hardware accelerator is faster than the memory read / write speed, causing the hardware accelerator to spend a considerable amount of time waiting for data to be transferred from memory or writing data to memory, thus reducing the processing speed of the hardware accelerator.

[0006] To address the aforementioned problems, the present disclosure proposes the following solutions.

[0007] According to one aspect of the present disclosure, a resource scheduling method is provided, comprising: creating a cache resource pool; sending the address of the cache resource pool to an application so that the application stores first data required for a computing task of the application into the cache resource pool, the computing task being offloaded from a general-purpose processor to a hardware accelerator; using a logic processing unit allocated to the application, generating instructions corresponding to the configuration file based on a configuration file required by the hardware accelerator to execute the computing task; adding the instructions and the first data in the cache resource pool to a queue so that the hardware accelerator can execute the computing task from the queue by calling the instructions and the first data.

[0008] In some embodiments, multiple logic processing units are used to generate instructions corresponding to the configuration file required by the hardware accelerator to execute the computing task.

[0009] In some embodiments, using multiple logical processing units to generate instructions corresponding to the configuration file required for executing the computing task based on the hardware accelerator includes: using each of the multiple logical processing units to generate a sub-instruction corresponding to the sub-configuration file required by the sub-task corresponding to each logical processing unit, wherein the computing task includes the sub-task; adding the sub-instruction and the second data required by the sub-task to a sub-queue so that the hardware accelerator can execute the sub-task from the sub-queue by calling the sub-instruction and the second data.

[0010] In some embodiments, creating the cache resource pool includes: receiving first information from the application, the first information indicating the size and number of the cache resource pool; and creating the cache resource pool based on the first information.

[0011] In some embodiments, the resource scheduling method further includes: after the computing task is executed, moving the first data from the queue to the cache resource pool.

[0012] In some embodiments, the resource scheduling method further includes: clearing the first data from the cached resource pool when the first data is not needed.

[0013] In some embodiments, the application resides in a container group.

[0014] According to another aspect of the present disclosure, a resource scheduling apparatus is provided, comprising: a module that performs the method described in any of the above embodiments.

[0015] According to another aspect of the present disclosure, a resource scheduling apparatus is provided, comprising: a memory; and a processor coupled to the memory, the processor being configured to execute the method described in any of the above embodiments based on instructions stored in the memory.

[0016] According to another aspect of the present disclosure, a cloud-based base station is provided, comprising: an apparatus for performing any of the above embodiments.

[0017] According to another aspect of the present disclosure, a computer-readable storage medium is provided, including computer program instructions, wherein the computer program instructions, when executed by a processor, implement the method described in any of the above embodiments.

[0018] According to another aspect of the present disclosure, a computer program product is provided, including a computer program, wherein the computer program, when executed by a processor, implements the method described in any of the above embodiments.

[0019] In this embodiment, by creating a cache resource pool, the application can store the first data required for the computing task into the cache resource pool. The application then uses its allocated logic processing unit and hardware accelerator to execute the configuration file required for the computing task, generating instructions corresponding to the configuration file. Subsequently, the instructions and the first data from the cache resource pool are added to a queue, allowing the hardware accelerator to execute the computing task from the queue by calling the instructions and the first data. This enables the hardware accelerator to quickly execute computing tasks by calling the instructions and the first data in the queue, improving the processing speed of the hardware accelerator.

[0020] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a flowchart illustrating a resource scheduling method according to some embodiments of the present disclosure;

[0023] Figure 2 This is a schematic diagram of the architecture of an AAL-C-APP model according to some embodiments of this disclosure;

[0024] Figure 3A This is a basic mapping diagram of logical processing units according to some embodiments of the present disclosure;

[0025] Figure 3B This is a basic mapping diagram of the logic processing units according to some embodiments of the present disclosure;

[0026] Figure 3C This is a basic mapping diagram of multiple logical processing units according to some embodiments of the present disclosure;

[0027] Figure 3D This is a basic mapping diagram of multiple logical processing units according to some embodiments of the present disclosure;

[0028] Figure 4 This is a schematic diagram of the architecture of a cloud-based base station according to other embodiments of this disclosure;

[0029] Figure 5 This is a schematic diagram of the structure of a resource scheduling apparatus according to other embodiments of the present disclosure;

[0030] Figure 6This is a schematic diagram of the structure of a resource scheduling apparatus according to some embodiments of the present disclosure. Detailed Implementation

[0031] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0032] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0033] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0034] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0035] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0036] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0037] Figure 1 This is a flowchart illustrating a resource scheduling method according to some embodiments of the present disclosure.

[0038] In step 102, a cache resource pool is created.

[0039] For example, a cache resource pool can be created based on the application's needs; or, for example, a cache resource pool can be created based on a preset algorithm. In some embodiments, the application resides in a container group.

[0040] In some embodiments, prior to step 102, in response to a request from the application, the number of logical processing units (LPUs) allocated to the application and the configuration file required for the hardware accelerator to perform computing tasks are sent to the application.

[0041] In step 104, the address of the cache resource pool is sent to the application so that the application can store the first data required for the application to perform a computing task that is offloaded from the general-purpose processor to the hardware accelerator.

[0042] For example, in response to a request from an application, the address of a cache resource pool is sent to the application. In some embodiments, the size of the cache resource pool is also sent to the application.

[0043] In step 106, the logic processing unit allocated to the application generates the instructions corresponding to the configuration file based on the configuration file required for the computing task to be executed by the hardware accelerator.

[0044] For example, in response to a request from an application, step 106 is executed. In some embodiments, the request carries a configuration file.

[0045] In some embodiments, after starting the logic processing unit, an instance of the computing task is created according to the configuration file required by the computing task, and the instance is started. After starting the instance, the logic processing unit generates the instructions corresponding to the configuration file.

[0046] In some embodiments, the instructions corresponding to the configuration file are obtained by inputting the configuration file required by the hardware accelerator to perform computing tasks into the logic processing unit.

[0047] In step 108, the instruction and first data in the cache resource pool are added to the queue so that the hardware accelerator can execute computation tasks from the queue by calling the instruction and the first data.

[0048] As one implementation, threads executing computational tasks on a hardware accelerator can invoke instructions in a queue to retrieve the corresponding configuration files. Additionally, threads executing computational tasks on a hardware accelerator can also invoke the first data in the queue, thereby utilizing both the configuration file and the first data to execute the computational task.

[0049] In some embodiments, after a computation task is executed, the first data is moved from the queue to a cache resource pool so that the first data can also be used to execute other computation tasks, such as computation tasks of other applications. For example, after a computation task is executed, the application may send an indication that the computation task has been completed, and in response to the indication, move the first data from the queue to the cache resource pool.

[0050] In some implementations, when the first data is no longer needed, i.e., after confirming that the first data will no longer be used by any computing task, the first data is removed from the cache resource pool to release the cache area occupied by the first data. In some embodiments, after the first data is removed from the cache resource pool, the cache area storing the first data is marked as available so that new data can be stored in the cache area.

[0051] As one implementation, the cache resource pool is destroyed once it is determined that it is no longer needed.

[0052] In some embodiments, after the first data is moved from the queue to the cache resource pool, the instance is terminated and deleted.

[0053] In the above embodiments, by creating a cache resource pool, the application can store the first data required for the computing task into the cache resource pool. Using the logic processing unit allocated to the application and the hardware accelerator, the configuration file required to execute the computing task is used to generate instructions corresponding to the configuration file. Subsequently, by adding the instructions and the first data from the cache resource pool to a queue, the hardware accelerator can execute the computing task from the queue by calling the instructions and the first data. This allows the hardware accelerator to quickly execute computing tasks by calling the instructions and the first data in the queue, improving the processing speed of the hardware accelerator.

[0054] In some embodiments, step 102 is implemented in the following manner.

[0055] First, receive initial information from the application, which indicates the size and number of cache resource pools.

[0056] As one implementation method, applications determine the size and number of cache resource pools based on computing needs.

[0057] In some implementations, in 6G cloud-based base stations, user terminals (UEs) call applications in the MEC platform, and the applications determine the size and number of cache resource pools based on the computing services that the UE needs to perform.

[0058] Then, a cache resource pool is created based on the first piece of information.

[0059] In the above embodiments, by having the application determine the size and number of cache resource pools, the waste of hardware resources caused by excessively large cache resource pools or the reduction in the speed of hardware processors in processing computing tasks due to excessively small cache resource pools are avoided.

[0060] In some embodiments, multiple logical processing units are used to generate instructions corresponding to the configuration file required by the hardware accelerator to execute the computing task, thereby improving the speed at which the hardware processor handles the computing task. For example, multiple logical processing units are used to process larger computing tasks, thereby improving the speed at which the hardware processor handles larger computing tasks.

[0061] As one implementation method, applications can break down computational tasks into multiple subtasks. In this case, step 106 can be implemented as follows.

[0062] First, each of the multiple logical processing units generates sub-instructions corresponding to its sub-configuration file based on the sub-configuration file required by the sub-task of each logical processing unit. Here, the computational tasks to be executed by the hardware accelerator include the sub-tasks corresponding to each logical processing unit.

[0063] Then, the sub-instruction and the second data required by the sub-task are added to the sub-queue so that the hardware accelerator can execute the sub-task from the sub-queue by calling the sub-instruction and the second data.

[0064] It should be understood that multiple logical processing units can generate multiple sub-instructions based on the sub-configuration files required by multiple sub-tasks. By adding each sub-instruction and the corresponding second data required by the sub-task to a sub-queue, multiple sub-queues can be obtained. The hardware accelerator can execute the corresponding sub-task from each sub-queue by calling the sub-instruction and the second data, thereby completing the entire computation task.

[0065] In the above embodiments, by dividing the computing task into multiple sub-tasks and using multiple logic processing units to process them in parallel, the speed of the hardware processor in processing computing tasks is further improved.

[0066] Figure 2 This is a schematic diagram of the architecture of the AAL-C-APP model according to some embodiments of this disclosure.

[0067] As one implementation approach, an AAL-C-APP model is set up between the application and the hardware accelerator to abstract the hardware acceleration functionality, thereby decoupling the application and the hardware accelerator. For example... Figure 2 As shown, the architecture of the AAL-C-APP model includes a hardware accelerator (Accelerator), a logic processing unit (LPU), and an application (APP). The logic processing unit is the logical representation of the computing resources of the hardware accelerator. Acceleration functions are the functions used by the hardware accelerator to process computing tasks, and the hardware acceleration manager is used for the management, updates, and fault handling of the hardware accelerator's lifecycle.

[0068] Figure 3A This is a basic mapping diagram of logical processing units according to some embodiments of this disclosure. For example... Figure 3A As shown, one application corresponds to one computing service. By inputting the configuration file related to the computing service into the logic processing unit, an instruction queue for executing computing tasks is obtained. The computing service can be offloaded to the hardware accelerator for execution through the driver of the hardware accelerator.

[0069] Figure 3B This is a basic mapping diagram of logical processing units according to some embodiments of the present disclosure. For example... Figure 3B As shown, an application breaks down computing tasks into multiple subtasks. By inputting configuration files related to these subtasks into the logic processing unit, multiple instruction queues for executing the subtasks are obtained. Through the driver of the hardware accelerator, multiple subtasks can be offloaded to the same hardware accelerator for execution.

[0070] Figure 3CThis is a basic mapping diagram of multiple logical processing units according to some embodiments of the present disclosure. For example... Figure 3C As shown, the computing services of multiple applications are processed by inputting the configuration files required for each computing service into the corresponding logical processing unit to obtain multiple instruction queues for executing computing tasks. These queues are then offloaded to multiple hardware accelerators for execution via the hardware accelerator driver.

[0071] Figure 3D This is a basic mapping diagram of multiple logical processing units according to some embodiments of the present disclosure. For example... Figure 3D As shown, an application breaks down computing tasks into multiple subtasks. By inputting the configuration file associated with each subtask into the corresponding logical processing unit, the corresponding instruction queue for executing the subtask is obtained. The multiple subtasks are then offloaded to multiple hardware accelerators for execution through the hardware accelerator driver.

[0072] Figure 4 This is a schematic diagram of the architecture of a cloud-based base station according to other embodiments of this disclosure.

[0073] As some implementation methods, such Figure 4 As shown, a cloud-based base station (e.g., a 6G cloud-based base station) includes a baseband processing unit (BBU), a hub (HUB), and a radio frequency processing unit (RRU). The baseband processing unit includes centralized and distributed units. The 6G cloud-based base station is deployed on a shared platform with the MEC (Multi-access Edge Computing) system, enabling service data from the UE to be computed on the MEC platform. Large-scale cluster edge applications are deployed on the MEC platform using container groups (PODs), with applications running various services within the container groups. Computational tasks from the user terminal (UE) are executed on general-purpose processors and hardware accelerators.

[0074] According to other embodiments of this disclosure, the resource scheduling method includes one or more of steps S1 to S38.

[0075] The following steps S1 to S38 initialize the configuration of AAL-C-AAP through the Service Management Architecture (SMO).

[0076] In step S1, the SMO sends a query request to the Infrastructure Management Service (IMS) to query the basic information of the cloud platform.

[0077] In step S2, IMS sends a query request to the general manager of AAL-C-AAP (AALI-C-Mgmt) to query relevant information about AAL-C-AAP.

[0078] In step S3, IMS sends a configuration request to AALI-C-Mgmt to configure AAL-C-AAP, including configuring the configuration files for the logic processing unit and the hardware accelerator.

[0079] Steps S1 to S3 above are used to initialize and configure AAL-C-AAP through SMO.

[0080] In step S4, AAL-C-AAP initializes the hardware acceleration configuration of the application (APP), including allocating logical processing units and configuration files to the APP.

[0081] In step S5, the APP sends a request to AAL-C-AAP to obtain the number of logical processing units and the configuration file.

[0082] In step S6, AAL-C-AAP returns the number of logic processing units and configuration files to the APP.

[0083] In step S7, the APP sends a request to create a cache resource pool, the request content including the size and number of cache resource pools to be created.

[0084] In step S8, AAL-C-AAP sends a message to the APP indicating that creation was successful.

[0085] In step S9, the APP requests the address of the cache resource pool.

[0086] In step S10, AAL-C-APP returns the address of the cache resource pool to APP.

[0087] In step S11, the APP requests the size of the cache resource pool.

[0088] In step S12, AAL-C-APP returns the size of the cache resource pool to APP.

[0089] In step S13, the APP sends a request to AAL-C-APP to start the logic processing unit.

[0090] In step S14, AAL-C-APP returns a successful startup message to APP.

[0091] In step S15, the APP sends a request to AAL-C-APP to create an instance of the computing task (AAL-Profile-Instance).

[0092] In step S16, AAL-C-APP sends a message to APP indicating successful creation.

[0093] In step S17, the APP sends a request to AAL-C-APP to start the instance.

[0094] In step S18, AAL-C-APP returns a successful startup message to APP.

[0095] In step S19, the APP sends a request to AAL-C-APP to set up the queue.

[0096] In step S20, AAL-C-APP returns a successful setup message to APP.

[0097] As one implementation, AAL-C-APP inputs the configuration file required to execute the computing task into the logic processing unit to obtain instructions, and puts the instructions into a queue, thereby realizing the configuration of the queue.

[0098] In step S21, the APP sends a request to start the queue to AAL-C-APP.

[0099] In step S22, AAL-C-APP returns a successful startup message to APP.

[0100] In step S23, the APP sends the first data required to perform the computation task to the AAL-C-APP and adds it to the queue.

[0101] In step S24, AAL-C-APP adds the first data to the queue and returns the queue status to the APP.

[0102] In step S25, the APP sends a request to AAL-C-APP to allocate data in the queue to the thread. This thread is located on the hardware accelerator and is the program that performs the computing task.

[0103] In step S26, AAL-C-APP returns a success message to APP.

[0104] In step S27, after executing the computation task, the APP sends a request to AAL-C-APP to move the first data to the cache resource pool.

[0105] In step S28, AAL-C-APP returns the status of the cache resource pool to APP.

[0106] In step S29, the APP sends a message to AAL-C-APP to clear the first data and sets the status of the cache storing the first data to available.

[0107] In step S30, AAL-C-APP returns a success message to APP.

[0108] In step S31, after determining that the cache resource pool is no longer needed, the APP sends a message to AAL-C-APP to destroy the cache resource pool.

[0109] In step S32, AAL-C-APP returns a message to APP indicating successful destruction.

[0110] In step S33, the APP sends a request to terminate the queue to AAL-C-APP.

[0111] In step S34, AAL-C-APP returns a successful termination message to APP.

[0112] In step S35, the APP sends a request to terminate the instance to AAL-C-APP.

[0113] In step S36, AAL-C-APP returns a successful termination message to APP.

[0114] In step S37, the APP sends a request to AAL-C-APP to delete the instance.

[0115] In step S38, AAL-C-APP returns a message to APP indicating that the deletion was successful.

[0116] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus embodiments, since they largely correspond to the method embodiments, the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0117] This disclosure provides a resource scheduling apparatus, including a module configured to execute any of the above embodiments.

[0118] Figure 5 This is a schematic diagram of the structure of a resource scheduling apparatus according to some embodiments of the present disclosure.

[0119] like Figure 5 As shown, the resource scheduling device includes a creation module 501, a sending module 502, a generation module 503, and an joining module 504.

[0120] Module 501 is configured to create a cache resource pool.

[0121] The sending module 502 is configured to send the address of the cache resource pool to the application so that the application can store the first data required to perform the computing task into the cache resource pool, and the computing task is offloaded from the general-purpose processor to the hardware accelerator.

[0122] The generation module 503 is configured to use the logic processing unit allocated to the application to generate instructions corresponding to the configuration file based on the configuration file required for the computing task to be executed by the hardware accelerator.

[0123] The add module 504 is configured to add instructions and first data to a queue so that the hardware accelerator can perform computational tasks from the queue by invoking the instructions and first data.

[0124] In some embodiments, the resource scheduling apparatus further includes other modules to execute the resource scheduling method of any of the above embodiments.

[0125] Figure 6 This is a schematic diagram of the structure of a resource scheduling apparatus according to some embodiments of the present disclosure.

[0126] like Figure 6 As shown, the resource scheduling device 600 includes a memory 601 and a processor 602 coupled to the memory 601. The processor 602 is configured to execute the method of any of the foregoing embodiments based on instructions stored in the memory 601.

[0127] The memory 601 may include, for example, system memory, fixed non-volatile storage media, etc. The system memory may store, for example, an operating system, application programs, a boot loader, and other programs.

[0128] The resource scheduling device 600 may also include an input / output interface 603, a network interface 604, and a storage interface 605. These interfaces 603, 604, and 605, as well as the memory 601 and processor 602, can be connected via, for example, a bus 506. The input / output interface 603 provides a connection interface for input / output devices such as monitors, mice, keyboards, and touchscreens. The network interface 604 provides a connection interface for various networked devices. The storage interface 605 provides a connection interface for external storage devices such as SD cards and USB flash drives.

[0129] This disclosure also provides a cloud-based base station, including the resource scheduling device of any of the above embodiments.

[0130] This disclosure also provides a computer-readable storage medium including computer program instructions that, when executed by a processor, implement the method of any of the above embodiments.

[0131] This disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the method of any of the above embodiments.

[0132] The embodiments of this disclosure have now been described in detail. To avoid obscuring the concept of this disclosure, some details known in the art have not been described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.

[0133] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product embodied on one or more computer-usable non-transitory storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0134] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that the functions specified in one or more flowchart illustrations and / or one or more blocks in a block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate functions for implementing the functions in the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0135] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0136] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide the steps of the function specified in the box.

[0137] While specific embodiments of this disclosure have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. Those skilled in the art should understand that modifications can be made to the above embodiments or equivalent substitutions can be made to some technical features without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A resource scheduling method, executed by an AAL-C-APP model located between an application and a hardware accelerator, the method comprising: Create a cache resource pool; The address of the cache resource pool is sent to the application so that the application stores the first data required for the application's computing task into the cache resource pool, the computing task being offloaded from the general-purpose processor to the hardware accelerator; Using the logic processing unit allocated to the application, instructions corresponding to the configuration file are generated based on the configuration file required by the hardware accelerator to execute the computing task. The instruction and the first data in the cache resource pool are added to a queue so that the hardware accelerator can execute the computing task from the queue by calling the instruction and the first data; After the computation task is executed, a request from the application to move the first data to the cache resource pool is received, so as to move the first data from the queue to the cache resource pool; If the first data is not needed, a request from the application to clear the first data is received to remove the first data from the cache resource pool; The method further includes: Before adding the first data to the queue, receive a request from the application to add the first data to the queue; Before the hardware accelerator invokes the first data, a request from the application to invoke the first data for use by a thread on the hardware accelerator is received.

2. The method according to claim 1, wherein, Using multiple logic processing units, instructions corresponding to the configuration file required for the computing task are generated based on the configuration file executed by the hardware accelerator.

3. The method according to claim 2, wherein, Using multiple logic processing units, and based on the configuration file required by the hardware accelerator to execute the computing task, the instructions corresponding to the configuration file include: Using each of the multiple logical processing units, sub-instructions corresponding to the sub-configuration file are generated based on the sub-configuration file required by the sub-task corresponding to each logical processing unit. The computation task includes the sub-task. The sub-instruction and the second data required by the sub-task are added to the sub-queue so that the hardware accelerator can execute the sub-task from the sub-queue by calling the sub-instruction and the second data.

4. The method according to claim 1, wherein, Creating the cache resource pool includes: Receive first information from the application, the first information indicating the size and quantity of the cache resource pool; The cache resource pool is created based on the first information.

5. The method according to any one of claims 1-4, wherein, The application resides within a container group.

6. A resource scheduling apparatus, comprising a module configured to perform the method of any one of claims 1-5.

7. A resource scheduling device, comprising: Memory; as well as A processor coupled to the memory is configured to execute the method of any one of claims 1-5 based on instructions stored in the memory.

8. A cloud-based base station, comprising the resource scheduling device as described in claim 6 or claim 7.

9. A computer-readable storage medium comprising computer program instructions, wherein, When the computer program instructions are executed by the processor, they implement the method described in any one of claims 1-5.

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