Image recognition method, device and related equipment

Abstract

The present application provides an image recognition method, apparatus and related equipment, wherein the method includes acquiring a target image, inputting the target image into an edge detection module, and obtaining an edge node graph. The edge node graph is input into a matching module to obtain an image recognition result, wherein the edge detection module is a module including a first memristor set based on an edge detection operator, and the matching module is a module including a second memristor set based on a template image. The image recognition method provided in the embodiment of the present application improves the speed of image recognition.

Description

Technical Field

[0001] The present application relates to the field of computer vision technology, and in particular to an image recognition method, apparatus and related equipment. Background Art

[0002] Image recognition technology refers to the technology of using computers to process, analyze and understand images to identify targets and objects of various different patterns. Image recognition is usually implemented based on machine learning, and the computing architecture of machine learning includes storage modules and computing modules.

[0003] At present, the storage module and the computing module are independent of each other. Each time a computing task is performed, the weight data needs to be transmitted back and forth between the storage module and the computing module, which reduces the computing speed and results in slower image recognition. Summary of the invention

[0004] The embodiments of the present application provide an image recognition method, apparatus and related equipment, which solve the problem of slow image recognition speed.

[0005] To achieve the above objectives, in a first aspect, an embodiment of the present application provides an image recognition method, comprising:

[0006] Get the target image;

[0007] Input the target image into an edge detection module to obtain an edge node graph;

[0008] Inputting the edge node graph into a matching module to obtain an image recognition result;

[0009] The edge detection module is a module including a first memristor and arranged based on an edge detection operator, and the matching module is a module including a second memristor and arranged based on a template image.

[0010] In a second aspect, an embodiment of the present application provides an image recognition device, including:

[0011] A first acquisition module, used for acquiring a target image;

[0012] A second acquisition module is used to input the target image into an edge detection module to obtain an edge node graph;

[0013] A third acquisition module is used to input the edge node graph into a matching module to obtain an image recognition result;

[0014] The edge detection module is a module including a first memristor and arranged based on an edge detection operator, and the matching module is a module including a second memristor and arranged based on a template image.

[0015] In a third aspect, an embodiment of the present application provides an electronic device, comprising a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the steps of the image recognition method described in the first aspect.

[0016] In a fourth aspect, an embodiment of the present application provides a readable storage medium, on which a program is stored, and when the program is executed by a processor, the steps in the image recognition method described in the first aspect are implemented.

[0017] In an embodiment of the present application, by acquiring a target image, the target image is input into an edge detection module to obtain an edge node graph. The edge node graph is input into a matching module to obtain an image recognition result. Among them, the edge detection module is a module including a first memristor set based on an edge detection operator, and the matching module is a module including a second memristor set based on a template image. The image recognition result can be obtained based on an edge detection module and a matching module having both storage and computing functions, so that the weight data required for the computing task does not need to be transmitted back and forth between the storage module and the computing module, thereby improving the computing speed and solving the problem of slow image recognition.

[0018] In addition, the storage module and computing module in the prior art are independent of each other. Each time a computing task is performed, the weight data needs to be transmitted back and forth between the storage module and the computing module, which also increases energy consumption. By using the image recognition method provided in the embodiment of the present application, the weight data does not need to be transmitted back and forth between the storage module and the computing module, thereby reducing energy consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following description is given to the drawings of the specification. Obviously, the following drawings are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the listed drawings without paying any creative work.

[0020] Figure 1 This is one of the flowcharts of the image recognition method provided in the embodiment of the present application;

[0021] Figure 2 is a schematic structural diagram of a first subunit provided in an embodiment of the present application;

[0022] Figure 3 is a schematic diagram of obtaining a third matrix provided in an embodiment of the present application;

[0023] Figure 4 It is a flowchart of the convolution operation provided in the embodiment of the present application;

[0024] Figure 5It is a structural schematic diagram of a storage-computing integrated array provided in an embodiment of the present application;

[0025] Figure 6 It is a flowchart of a method for obtaining a target result based on a storage-computation integrated array provided in an embodiment of the present application;

[0026] Figure 7 is a schematic diagram of the structure of an image recognition device provided in an embodiment of the present application;

[0027] Figure 8 It is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0029] The image recognition method provided in the embodiment of the present application can be used in the scenario of real-time target detection. At present, machine learning is widely used in the field of real-time target detection. Through machine learning, the target object can be identified from the image. The image recognition method provided in the embodiment of the present application is based on a storage-computation integrated array to realize computer vision operators in machine learning such as edge detection and template matching. The calculation speed is improved through parallel computing and algorithm improvement, which can meet the real-time and accuracy requirements in the target detection scenario, which is described in detail below.

[0030] See also Figure 1 , Figure 1 is one of the flow charts of the image recognition method provided in the embodiment of the present application, such as Figure 1 As shown, the image recognition method may include the following steps:

[0031] Step 101, acquiring a target image;

[0032] The target image is an image to be identified, which may be one or more images. In specific implementation, the target image may be acquired by real-time acquisition of the scene or product to be detected by a camera, or may be acquired by reading from a memory storing the image to be identified.

[0033] Step 102, inputting the target image into an edge detection module to obtain an edge node graph;

[0034] The edge of an image is where the attributes of the image suddenly change, and it is also where the information in the image is most concentrated. Under certain conditions, the edge of an image can contain all the information of the image. The edge of an image is composed of edge nodes, and the edge node graph can be used to represent the edge of the image.

[0035] The above-mentioned edge detection module is a module including a first memristor based on an edge detection operator, and is used to obtain an edge node graph of a target image. Due to the characteristics of the memristor itself, the edge detection module including a first memristor based on an edge detection operator has both storage and calculation functions. In this way, in the process of the edge detection module performing a calculation task on the target image to obtain an edge node graph, the weight data required for the calculation task does not need to be transmitted back and forth between the storage module and the calculation module, thereby improving the calculation speed and solving the problem of slow image recognition.

[0036] Step 103, inputting the edge node graph into a matching module to obtain an image recognition result;

[0037] In specific implementation, the matching module can perform matching based on the grayscale information of the image, or based on the feature space information of the image. Compared with the former, matching based on the feature space information of the image has better robustness and consistency, but the implementation process is more complicated and not suitable for hardware migration.

[0038] Matching based on the grayscale information of the image usually does not require complex preprocessing of the image. Some statistical features of the grayscale of the image itself can be used to measure the similarity between the image and the template image, and a certain search method can be used for matching. This type of algorithm is simple and easy to implement, can be processed in parallel, and is convenient for using hardware algorithms to increase its computing speed. The embodiment of the present application uses matching based on the grayscale information of the image.

[0039] The template matching algorithm is the most basic algorithm for matching based on the grayscale information of an image. It searches for a given known small image in a large image. Exemplarily, the matching module is used to match the edge node graph of the target image with the template image. For example, if the location of a circular object in the target image needs to be identified, the circular template image can be matched with the edge node graph of the target image to determine the location of the circular object in the target image. This location is the result of image recognition.

[0040] The above-mentioned matching module is a module including a second memristor set based on a template image. Due to the characteristics of the memristor itself, the module including a second memristor set based on a template image has both storage and calculation functions. In this way, in the calculation process in which the matching module matches the edge node graph of the target image with the template image to obtain the image recognition result, the weight data required for the calculation task does not need to be transmitted back and forth between the storage module and the calculation module, thereby improving the calculation speed and solving the problem of slow image recognition.

[0041] In an embodiment of the present application, by acquiring a target image, the target image is input into an edge detection module to obtain an edge node graph. The edge node graph is input into a matching module to obtain an image recognition result. Among them, the edge detection module is a module including a first memristor set based on an edge detection operator, and the matching module is a module including a second memristor set based on a template image. The image recognition result can be obtained based on an edge detection module and a matching module having both storage and computing functions, so that the weight data required for the computing task does not need to be transmitted back and forth between the storage module and the computing module, thereby improving the computing speed and solving the problem of slow image recognition.

[0042] In addition, the storage module and computing module in the prior art are independent of each other. Each time a computing task is performed, the weight data needs to be transmitted back and forth between the storage module and the computing module, which also increases energy consumption. By using the image recognition method provided in the embodiment of the present application, the weight data does not need to be transmitted back and forth between the storage module and the computing module, thereby reducing energy consumption.

[0043] Optionally, step 101 includes:

[0044] Acquire an initial image of the target object;

[0045] Inputting the initial image into a preprocessing module to obtain the target image;

[0046] Wherein, the preprocessing module is a module including a third memristor and arranged based on a Gaussian operator.

[0047] In specific implementation, a photograph of the target object can be collected by a camera device as an initial image. The target object can be a specific scene or product, etc. By inputting the initial image into a preprocessing module set based on a Gaussian operator for processing, the target image is obtained, and the image effect of the target image at different scales can be enhanced, thereby achieving a better image recognition effect.

[0048] In addition, the preprocessing module is a module including a third memristor based on a Gaussian operator. Due to the characteristics of the memristor itself, the module including a third memristor based on a Gaussian operator has both storage and calculation functions. In this way, during the calculation process in which the preprocessing module preprocesses the initial image, the weight data required for the calculation task does not need to be transmitted back and forth between the storage module and the calculation module, thereby improving the calculation speed and further improving the speed of image recognition.

[0049] Optionally, the acquisition process of the preprocessing module includes:

[0050] Decomposing the first matrix corresponding to the Gaussian operator into a linear combination of a plurality of first sub-matrices, wherein an element in each of the first sub-matrices is 0 or 1;

[0051] The preprocessing module is determined according to the multiple first sub-matrices.

[0052] The process of inputting the initial image into the preprocessing module to obtain the target image is the Gaussian blur process of the target image. From a mathematical point of view, the Gaussian blur process of the target image is the convolution of the target image with the normal distribution. This embodiment of the present application takes the 3*3 neighborhood Gaussian operator as shown below as an example to illustrate how to complete Gaussian smoothing (i.e., how to preprocess the initial image).

[0053] The weight matrix representing the Gaussian operator is:

[0054]

[0055] First, decompose the above weight matrix into a linear combination of multiple first sub-matrices consisting of only two elements, 0 and 1, as follows:

[0056]

[0057] Then, the decomposed multiple first sub-matrices are respectively mapped to the storage and computing integrated array based on the third memristor to obtain a preprocessing module. Finally, the initial image is input into the preprocessing module to calculate the convolution results of each first sub-matrix respectively, and the target image is obtained after linear combination.

[0058] The target image is obtained by pre-processing the initial image through Gaussian smoothing, which can enhance the image effect of the target image at different scales.

[0059] Optionally, the preprocessing module includes a first submodule corresponding to the target first submatrix, the first submodule includes a plurality of first subunits, each of the first subunits corresponds to an element in the target first submatrix, and an arrangement order of each of the first subunits corresponds to an arrangement order of elements in the target first submatrix;

[0060] The target first sub-matrix is ​​any one of the multiple first sub-matrices, and each of the first sub-units includes at least two transistors and at least two memristors.

[0061] In specific implementation, the target first submatrix corresponds to a column of first submodules composed of multiple first subunits connected in series, and the arrangement order of each first subunit corresponds to the arrangement order of elements in the target first submatrix, which means that the order of rows of the first submatrix corresponds to the arrangement order of the first subunits. For example, if the target first submatrix is ​​a 2×2 matrix, the elements in the first row and the first column correspond to the first first subunit in the first submodule; the elements in the first row and the second column correspond to the second first subunit in the first submodule; the elements in the second row and the first column correspond to the third first subunit in the first submodule; and the elements in the second row and the second column correspond to the fourth first subunit in the first submodule.

[0062] See also Figure 2 , Figure 2 1 is a schematic diagram of the structure of the first subunit provided in an embodiment of the present application. The first subunit may be composed of a first memristor 11, a first transistor 12, a second transistor 13, and a second memristor 14 connected in series in sequence. The value of the element represented by the first subunit can be changed by adjusting the resistance values ​​of the first memristor 1 and the second memristor 14.

[0063] Optionally, step 102 includes:

[0064] Obtaining the edge detection module according to the second matrix corresponding to the edge detection operator;

[0065] Inputting the target image into the edge detection module to obtain the horizontal grayscale value and the vertical grayscale value of each first pixel in the target image;

[0066] For each first pixel, determining a gradient of the first pixel according to the horizontal grayscale value and the vertical grayscale value;

[0067] When the gradient is greater than a first preset value, determining the first pixel point as an edge node;

[0068] The edge node graph is determined according to the edge nodes.

[0069] In specific implementation, the embodiment of the present application takes the third-order Sobel edge detection operator Hx and Hy as shown below as an example, with A representing the target image, Gx representing the horizontal grayscale value of the target image after edge detection, and Gy representing the vertical grayscale value of the target image after edge detection. The second matrix corresponding to the edge detection operator is Hx and Hy.

[0070]

[0071]

[0072] In order to improve the accuracy of the calculation, the matrices Hx and Hy representing the Sobel edge detection operator are decomposed into a linear combination of multiple sub-matrices consisting of only two elements, 0 and 1, as follows:

[0073]

[0074]

[0075] The decomposed edge detection operator matrices Hx and Hy (i.e., the second matrix) are mapped to the storage-computation integrated array based on the first memristor. The mapping rules can be consistent with the rules for mapping the first matrix to the preprocessing module, which will not be repeated here. Then, the convolution results of each sub-matrix are calculated for the target image, and Gx and Gy are obtained after linear combination.

[0076] According to the horizontal and vertical grayscale values ​​of each pixel in the target image, the gradient G of each pixel is calculated by the following formula:

[0077]

[0078] The gradient of each pixel in the target image is calculated in turn. When the gradient is greater than a first preset value, the pixel is determined as an edge node. An edge node graph can be determined based on all edge nodes in the target image.

[0079] Alternatively, see Figure 3 , Figure 3 is a schematic diagram of obtaining a third matrix provided in an embodiment of the present application, and the acquisition process of the matching module includes:

[0080] The grayscale matrix corresponding to the template image is respectively translated and copied to the left and right according to a preset rule to obtain a third matrix;

[0081] The matching module is obtained according to the third matrix.

[0082] When implementing it, press Figure 3The gray value matrix corresponding to the template image is respectively shifted and copied to the left and right in the manner shown to obtain a third matrix. The third matrix is ​​mapped to the storage and computing integrated array based on the second memristor to obtain a matching module. The mapping rule can be consistent with the rule of mapping the first matrix to the preprocessing module, which will not be repeated here. In this way, when performing a convolution operation, the sliding window size changes from M*N to M*(N+2), and the horizontal sliding slides three grids at a time. Based on the parallel calculation of the storage and computing integrated array, the matching speed can be increased by three times, that is, the speed of image recognition is further improved. If the size of the storage and computing integrated array allows, vertical copying can also be performed (that is, the gray matrix corresponding to the template image is respectively shifted and copied upward and downward according to preset rules) to further improve the speed of matching the target image with the template image.

[0083] Optionally, step 103 includes:

[0084] Inputting the edge node graph into a matching module to obtain matching values ​​between the edge node graph and each second pixel point in the template image;

[0085] For each second pixel point, when the matching value is greater than a second preset value, determining the position of the second pixel point as the target position;

[0086] An image recognition result is determined according to the target position.

[0087] In specific implementation, the matching value R(x, y) between the edge node graph and each second pixel point in the template image can be obtained using the following expression 1:

[0088] R(x,y)=∑ x′,y′ (T(x′,y′)*I(x+x′,y+y′)) (Expression 1)

[0089] Among them, R(x, y) represents the matching value of the pixel in the xth row and yth column, T(x′, y′) represents the grayscale value of the pixel in the x′th row and y′th column in the template image, and I(x+x′, y+y′) represents the grayscale value of the pixel in the x+x′th row and y+y′th column in the target image.

[0090] The matching value of each pixel in the template image and the target image is calculated based on Expression 1. If the matching value is greater than the second preset value, the position of the pixel can be determined as the target position. In actual application, only one target position or multiple target positions may be obtained. If only one target position is obtained, the target position is the center position of the object to be identified. If multiple target positions are obtained, the range determined by the multiple target positions is the position of the object to be identified.

[0091] In order to reduce the computational noise of the memristor and further improve the speed and accuracy of image recognition, the embodiment of the present application also provides a method for obtaining a preprocessing module / edge detection module / matching module and obtaining a target result based on the above modules.

[0092] As mentioned above, the preprocessing module / edge detection module / matching module are all based on mapping the matrix to the storage-computation integrated array based on the memristor setting. The process of inputting the initial image into the preprocessing module to obtain the target image; the process of inputting the target image into the edge detection module to obtain the edge node graph; the process of inputting the edge node graph into the matching module to obtain the image recognition result are all based on the convolution operation of the storage-computation integrated array. Therefore, the matrix can be amplified several times to reduce the computational noise and further improve the speed and accuracy of image recognition. The storage-computation integrated array obtained by mapping the input signal to the amplified matrix, the output signal is converted according to the converted range and reorganized for output, and the target result can be obtained, which is described in detail below.

[0093] like Figure 4 As shown, Figure 4 This is a flow chart of the convolution operation provided by the embodiment of the present application. The convolution operation uses a matrix called a convolution kernel (weight matrix W) to slide from top to bottom and from left to right on the image (input matrix X), multiplying each element of the convolution kernel matrix with the element of the corresponding position covered by it on the image, and then summing them to obtain the output pixel value (output matrix Y). However, this convolution multiplication and addition method is difficult to implement using traditional storage arrays. The main difficulty is that it is impossible to simply superimpose the product values ​​in different rows together, and it is also impossible to simply calculate multiple convolution output values ​​at the same time.

[0094] As a new computing architecture, the integrated storage and computing array perfectly overcomes the above difficulties. The calculation form of the output current of the integrated storage and computing array is as follows:

[0095]

[0096] This is the same as the calculation form of convolution. Therefore, taking the expression 3 shown below as an example, we only need to straighten the convolution kernel matrix into the column vector form on the right and store it in Figure 5 By using the unit devices [R11, R21, …, R91] of the storage-computation-in-one array shown in the figure, the analog characteristics of the memristor can be used to perform corresponding calculations based on the form of expressions.

[0097]

[0098] Compared with the traditional computer architecture with separated storage and computation, the use of storage-computation integrated array to complete convolution calculation does not require the weight data to be called back and forth. It only needs to input the signal at the input end, and the convolution result will be output in the form of current, which can significantly improve the operation speed. In addition, the embodiment of the present application can adopt a storage-computation integrated computing array based on two transistors + two memristors (2T2R) units. A 2T2R unit can store data with a value range of -8 to 7 (4 bits), further improving the operation efficiency.

[0099] In addition, in order to solve the problem of noise generated during the convolution calculation process due to hardware instability and quantization noise of peripheral circuits, the weight decomposition and scaling operation in the storage-computation-in-one array proposed in the embodiment of the present application can effectively improve the accuracy of the convolution calculation results of the storage-computation-in-one array, as follows:

[0100] Considering the limited range in the analog-to-digital conversion (ADC) process, the result of the output current of the storage-computation integrated array will be different from the theoretical value in Expression 2. Through experimental testing, the storage-computation integrated array used in this application has the best linearity when the integration time of the analog-to-digital conversion is adjusted so that the theoretical current output value of the memristor array is 3 times the actual output value. Therefore, the actual output value calculated is shown in the following formula:

[0101]

[0102] Since both the input and output are integers, based on Expression 3, in order to avoid output value loss and make the actual current value the same as the theoretical value, the convolution kernel needs to be enlarged to three times the original value before mapping, that is, 3*w ij It is mapped as a weight matrix to the storage-computation integrated array.

[0103] In the actual test process, it was found that the output results had a large deviation. The above method alone could not effectively improve the calculation accuracy. Therefore, it was considered to sacrifice the range in exchange for calculation accuracy. Specifically, the convolution kernel was repeatedly mapped three times in the same column, that is, […3*w ij …] is copied as […3*w ij …3*w ij …3*w ij …] and make a corresponding copy of the input data before inputting it.

[0104] At this time, it is equivalent to enlarging the weight matrix to 9 times the original size for mapping, so the input and output ranges are compressed from the original -8 to 7 to -2 to 2. The specific output range correspondence is shown in Table 1. The weight matrix W also needs to be decomposed, and the absolute value of the sum of elements with the same sign in the decomposed matrix must be less than or equal to 2. After the decomposed weight matrix, when performing weight mapping, elements with the same position must be mapped to the same row of the storage and computing integrated array.

[0105]

[0106] Table 1 (ADC range compression comparison table)

[0107] After amplifying the weight by 9 times, its base value can be slightly adjusted to keep the output as close to the given theoretical range as possible. For example, when some convolution results are too large, fine-tuning can be performed as shown in Expression 5. The fine-tuning is only for the processing of the ADC range and has nothing to do with the process of mapping the weight matrix into a storage-computation integrated array:

[0108] 9×w ij -1 (expression 5)

[0109] Among them, assuming that w ij The above decomposition and contraction operation of the convolution kernel weight matrix W is equivalent to shaping some adjustable parameters, which can minimize the influence on the output results and reduce the interference of non-ideal factors such as device characteristics and ADC noise on the output results.

[0110] See also Figure 6 , Figure 6 It is a flowchart of a method for obtaining a target result based on a storage-computing integrated array provided in an embodiment of the present application.

[0111] like Figure 6 As shown, a method for obtaining a target result based on a storage-computing integrated array provided in an embodiment of the present application includes the following steps:

[0112] Step 201, performing convolution kernel preprocessing, decomposing the convolution kernel into multiple matrices whose element absolute values ​​are not greater than 2;

[0113] Step 202, magnify the multiple matrices obtained by the decomposition by 3 times, and map each matrix to the same column of the storage-computation-in-one array after repeating 3 times; it should be understood that all matrices in the multiple matrices are mapped to different columns in the storage-computation-in-one array in this way;

[0114] Step 203, input the signal and perform convolution operation;

[0115] Step 204, convert the output signal according to the converted range and reorganize the output to obtain the convolution result.

[0116] The following takes the preprocessing module as an example to illustrate the above steps. The convolution kernel refers to the first matrix.

[0117] The first matrix can be decomposed into 5 first sub-matrices, the first first sub-matrix is ​​repeated 3 times and mapped to the first column of the pre-processing module; the second first sub-matrix is ​​repeated 3 times and mapped to the second column of the pre-processing module, and so on, the fifth first sub-matrix is ​​repeated 3 times and mapped to the fifth column of the pre-processing module. If the first first sub-matrix corresponds to the first sub-module, the first first sub-matrix is ​​repeated 3 times and mapped to the first column of the pre-processing module means that three first sub-modules are connected in series.

[0118] In the process of inputting the initial image into the preprocessing module to obtain the target image, the input signal refers to the initial image, and the convolution result refers to the target image.

[0119] See also Figure 7 , the embodiment of the present application provides an image recognition device 300, including:

[0120] A first acquisition module 301 is used to acquire a target image;

[0121] A second acquisition module 302 is used to input the target image into an edge detection module to obtain an edge node graph;

[0122] A third acquisition module 303 is used to input the edge node graph into a matching module to obtain an image recognition result;

[0123] The edge detection module is a module including a first memristor and arranged based on an edge detection operator, and the matching module is a module including a second memristor and arranged based on a template image.

[0124] Optionally, the first acquisition module 301 includes:

[0125] Acquire an initial image of the target object;

[0126] Inputting the initial image into a preprocessing module to obtain the target image;

[0127] Wherein, the preprocessing module is a module including a third memristor and arranged based on a Gaussian operator.

[0128] Optionally, the acquisition process of the preprocessing module includes:

[0129] Decomposing the first matrix corresponding to the Gaussian operator into a linear combination of a plurality of first sub-matrices, wherein an element in each of the first sub-matrices is 0 or 1;

[0130] The preprocessing module is determined according to the multiple first sub-matrices.

[0131] Optionally, the preprocessing module includes a first submodule corresponding to the target first submatrix, the first submodule includes a plurality of first subunits, each of the first subunits corresponds to an element in the target first submatrix, and an arrangement order of each of the first subunits corresponds to an arrangement order of elements in the target first submatrix;

[0132] The target first sub-matrix is ​​any one of the multiple first sub-matrices, and each of the first sub-units includes at least two transistors and at least two memristors.

[0133] Optionally, the second acquisition module 302 includes:

[0134] Obtaining the edge detection module according to the second matrix corresponding to the edge detection operator;

[0135] Inputting the target image into the edge detection module to obtain the horizontal grayscale value and the vertical grayscale value of each first pixel in the target image;

[0136] For each first pixel, determining a gradient of the first pixel according to the horizontal grayscale value and the vertical grayscale value;

[0137] When the gradient is greater than a first preset value, determining the first pixel point as an edge node;

[0138] The edge node graph is determined according to the edge nodes.

[0139] Optionally, the process of acquiring the matching module includes:

[0140] The grayscale matrix corresponding to the template image is respectively translated and copied to the left and right according to a preset rule to obtain a third matrix;

[0141] The matching module is obtained according to the third matrix.

[0142] Optionally, the third acquisition module 303 includes:

[0143] Inputting the edge node graph into a matching module to obtain matching values ​​between the edge node graph and each second pixel point in the template image;

[0144] For each second pixel point, when the matching value is greater than a second preset value, determining the position of the second pixel point as the target position;

[0145] An image recognition result is determined according to the target position.

[0146] The image recognition device 300 provided in the embodiment of the present application can implement each process that can be implemented in the embodiment of the image recognition method of the present application, and achieve the same beneficial effects. To avoid repetition, it will not be described here.

[0147] The present application embodiment provides an electronic device. Figure 8 As shown, the electronic device 400 includes: a processor 401, a memory 402, and a computer program stored in the memory 402 and executable on the processor, and the various components in the electronic device 400 are coupled together via a bus system 403. It can be understood that the bus system 403 is used to realize connection and communication between these components.

[0148] Wherein, the processor 401 is used to obtain a target image;

[0149] Input the target image into an edge detection module to obtain an edge node graph;

[0150] Inputting the edge node graph into a matching module to obtain an image recognition result;

[0151] The edge detection module is a module including a first memristor and arranged based on an edge detection operator, and the matching module is a module including a second memristor and arranged based on a template image.

[0152] Optionally, the processor 401 is further configured to acquire an initial image of the target object;

[0153] Inputting the initial image into a preprocessing module to obtain the target image;

[0154] Wherein, the preprocessing module is a module including a third memristor and arranged based on a Gaussian operator.

[0155] Optionally, the processor 401 is further configured to decompose the first matrix corresponding to the Gaussian operator into a linear combination of a plurality of first sub-matrices, where an element in each of the first sub-matrices is 0 or 1;

[0156] The preprocessing module is determined according to the multiple first sub-matrices.

[0157] Optionally, the preprocessing module includes a first submodule corresponding to the target first submatrix, the first submodule includes a plurality of first subunits, each of the first subunits corresponds to an element in the target first submatrix, and an arrangement order of each of the first subunits corresponds to an arrangement order of elements in the target first submatrix;

[0158] The target first sub-matrix is ​​any one of the multiple first sub-matrices, and each of the first sub-units includes at least two transistors and at least two memristors.

[0159] Optionally, the processor 401 is further configured to obtain the edge detection module according to a second matrix corresponding to the edge detection operator;

[0160] Inputting the target image into the edge detection module to obtain the horizontal grayscale value and the vertical grayscale value of each first pixel in the target image;

[0161] For each first pixel, determining a gradient of the first pixel according to the horizontal grayscale value and the vertical grayscale value;

[0162] When the gradient is greater than a first preset value, determining the first pixel point as an edge node;

[0163] The edge node graph is determined according to the edge nodes.

[0164] Optionally, the processor 401 is further configured to translate and copy the grayscale matrix corresponding to the template image to the left and to the right respectively according to a preset rule to obtain a third matrix;

[0165] The matching module is obtained according to the third matrix.

[0166] Optionally, the processor 401 is further configured to input the edge node graph into a matching module to obtain a matching value between the edge node graph and each second pixel point in the template image;

[0167] For each second pixel point, when the matching value is greater than a second preset value, determining the position of the second pixel point as the target position;

[0168] An image recognition result is determined according to the target position.

[0169] The electronic device 400 provided in the embodiment of the present application can implement each process that can be implemented in the embodiment of the image recognition method of the present application, and achieve the same beneficial effects. To avoid repetition, it will not be described here.

[0170] The embodiment of the present application also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, each process of the above-mentioned image recognition method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it is not repeated here. The computer-readable storage medium is, for example, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0171] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. An image recognition method, characterized in that: include: Get the target image; Input the target image into an edge detection module to obtain an edge node graph; Inputting the edge node graph into a matching module to obtain an image recognition result; Wherein, the edge detection module is a module including a first memristor and arranged based on an edge detection operator, and the matching module is a module including a second memristor and arranged based on a template image; Wherein, acquiring the target image comprises: Acquire an initial image of the target object; Inputting the initial image into a preprocessing module to obtain the target image; Wherein, the preprocessing module is a module including a third memristor arranged based on a Gaussian operator; The acquisition process of the preprocessing module includes: Decomposing the first matrix corresponding to the Gaussian operator into a linear combination of a plurality of first sub-matrices, wherein an element in each of the first sub-matrices is 0 or 1; Determining the preprocessing module according to the multiple first sub-matrices; The preprocessing module includes a first submodule corresponding to the target first submatrix, the first submodule includes a plurality of first subunits, each of the first subunits corresponds to an element in the target first submatrix, and the arrangement order of each of the first subunits corresponds to the arrangement order of the elements in the target first submatrix; The target first sub-matrix is ​​any one of the multiple first sub-matrices, and each of the first sub-units includes at least two transistors and at least two memristors.

2. The method according to claim 1, characterized in that The step of inputting the target image into an edge detection module to obtain an edge node graph comprises: Obtaining the edge detection module according to the second matrix corresponding to the edge detection operator; Inputting the target image into the edge detection module to obtain the horizontal grayscale value and the vertical grayscale value of each first pixel in the target image; For each first pixel, determining a gradient of the first pixel according to the horizontal grayscale value and the vertical grayscale value; When the gradient is greater than a first preset value, determining the first pixel point as an edge node; The edge node graph is determined according to the edge nodes.

3. The method according to claim 1, characterized in that The acquisition process of the matching module includes: The grayscale matrix corresponding to the template image is respectively translated and copied to the left and right according to a preset rule to obtain a third matrix; The matching module is obtained according to the third matrix.

4. The method according to claim 3, characterized in that The step of inputting the edge node graph into a matching module to obtain an image recognition result includes: Inputting the edge node graph into a matching module to obtain matching values ​​between the edge node graph and each second pixel point in the template image; For each second pixel point, when the matching value is greater than a second preset value, determining the position of the second pixel point as the target position; An image recognition result is determined according to the target position.

5. An image recognition device, characterized in that: include: A first acquisition module, used for acquiring a target image; A second acquisition module is used to input the target image into an edge detection module to obtain an edge node graph; A third acquisition module is used to input the edge node graph into a matching module to obtain an image recognition result; Wherein, the edge detection module is a module including a first memristor and arranged based on an edge detection operator, and the matching module is a module including a second memristor and arranged based on a template image; Wherein, acquiring the target image comprises: Acquire an initial image of the target object; Inputting the initial image into a preprocessing module to obtain the target image; Wherein, the preprocessing module is a module including a third memristor arranged based on a Gaussian operator; The acquisition process of the preprocessing module includes: Decomposing the first matrix corresponding to the Gaussian operator into a linear combination of a plurality of first sub-matrices, wherein an element in each of the first sub-matrices is 0 or 1; Determining the preprocessing module according to the multiple first sub-matrices; The preprocessing module includes a first submodule corresponding to the target first submatrix, the first submodule includes a plurality of first subunits, each of the first subunits corresponds to an element in the target first submatrix, and the arrangement order of each of the first subunits corresponds to the arrangement order of the elements in the target first submatrix; The target first sub-matrix is ​​any one of the multiple first sub-matrices, and each of the first sub-units includes at least two transistors and at least two memristors.

6. An electronic device, characterized in that: The method comprises a processor, a memory and a computer program stored in the memory and executable on the processor, wherein the computer program implements the steps of the image recognition method according to any one of claims 1 to 4 when executed by the processor.

7. A readable storage medium, characterized in that: The readable storage medium stores a program, and when the program is executed by a processor, the steps in the image recognition method according to any one of claims 1 to 4 are implemented.

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