A neural network search chip based on RISC-V architecture

Abstract

The present invention provides a neural network search chip based on RISC‑V architecture, which belongs to the field of neural network chip technology, including: a CPU controller module, which is connected to the memory storage unit for communication, and is used to process input data and model parameters based on the Resnet neural network search task of the host computer to obtain the searched neural network structure; a DMA unit, which is connected to the CPU controller module, the memory unit and the on-chip storage module respectively; and a digital storage and computing integrated core module, which is used to train the searched neural network structure according to data instructions. The present invention completes the training and search of the neural network through the digital storage and computing integrated core and the CPU of the RISC‑V architecture, which can improve the scheduling efficiency of bus transmission data. At the same time, the digital storage and computing integrated core under the architecture can make full use of computing power resources to realize network reasoning tasks, overcome the limitations of traditional storage computing power, and realize faster and more accurate neural network search.

Description

Technical Field

[0001] The present invention relates to the technical field of neural network chips, and in particular to a neural network search chip based on RISC-V architecture. Background Art

[0002] In recent years, with the development of society, artificial intelligence (AI) has been widely used in cloud data centers, smart devices and edge devices. At the same time, neural networks have demonstrated powerful capabilities in various AI tasks, including but not limited to image recognition, face recognition, keyword detection and text processing. The performance of artificial neural networks has been continuously improved, and deep neural networks containing a large number of parameters and operations have been widely used. In the calculation process of AI, due to operations such as convolution, pooling and activation, a large amount of intermediate data will be generated and a large amount of data movement will be required, which puts higher requirements on the performance and power consumption of AI chips.

[0003] There are many limitations when training neural networks on the traditional von Neumann architecture with separated storage and computing: the bus bandwidth for transferring data between the processor and the memory is limited; in the hierarchical memory structure, the storage level far away from the processor has a large capacity, but the bandwidth is low and the latency is high; the amount of data calculated by the neural network is large, the degree of parallelism is high, and a large amount of data movement is required. During training, a lot of time and energy are consumed in data transfer and memory reading and writing. Improving computing power requires high-bandwidth memory and a new computing architecture. And with the continuous advancement of circuit technology, the performance gap between processors and memories is getting bigger and bigger, and the system performance is mainly limited by memory performance. In addition, frequent data movement occurs in the neural network algorithm under the von Neumann architecture, and the high power consumption generated is much higher than the power consumption generated by the calculation. In this neural network architecture, more data occupies the CPU resource bandwidth, resulting in low CPU computing efficiency and high power consumption.

[0004] The integrated storage and computing chip provides a new method for neural network accelerators: the integrated storage and computing chip embeds computing operations into the storage unit, eliminating the boundary between the memory and the processing unit. Compared with the serial data processing under the traditional von Neumann architecture, the increasing performance difference between the processor and the off-chip memory has led to the processor's memory access computing performance greatly affecting the system performance. In addition, the integrated storage and computing chip processes data in parallel. During the calculation process, the movement of intermediate data is reduced, and there are fewer off-chip storage accesses. Therefore, the computing efficiency of the integrated storage and computing architecture is much higher than that of the von Neumann computing architecture, which is particularly evident in convolutional computing and big data processing scenarios.

[0005] At present, neural network models emerge in an endless stream, and various models play a pivotal role in deep learning tasks such as image processing and machine translation. The network structure in the model is a special hyperparameter. For example, network structures such as Transformer and ResNet need to be designed more accurately to achieve the performance of deep learning models. Neural Architecture Search (NAS) represents the transformation of traditional manual network structure design into automated design. At present, Google and others have used reinforcement learning to search for neural network structures, surpassing previously manually designed networks in image classification and language modeling tasks.

[0006] However, there are many types of neural networks currently, and relying on empirical models often fails to achieve ideal results. Summary of the invention

[0007] In order to overcome the shortcomings of the prior art, the object of the present invention is to provide a neural network search chip based on RISC-V architecture.

[0008] To achieve the above object, the present invention provides the following solutions:

[0009] A neural network search chip based on RISC-V architecture, comprising:

[0010] The CPU controller module is connected to the memory storage unit for processing input data and model parameters based on the Resnet neural network search task of the host computer to obtain the searched neural network structure; wherein the CPU controller module uses the RISC-V reduced instruction set architecture to control data flow and data buffering;

[0011] The DMA unit is respectively connected to the CPU controller module, the Memory storage unit and the on-chip storage module for communication;

[0012] The digital storage and computing integrated core module is connected to the on-chip storage module for training the searched neural network structure according to data instructions.

[0013] Preferably, the step of training the searched neural network structure according to the data instruction includes:

[0014] The task scheduler is used to directly access memory data instructions through the DMA unit and save them in the buffer of the on-chip storage module. The CPU controller module is used to compile specific instruction bits through machine code, identify instruction requirements and issue control signals, and convert the control signals into a group of 8-bit data through data conversion and transmit them to the digital storage and computing integrated core module, so as to configure the digital storage and computing integrated core module to train the searched neural network structure.

[0015] Preferably, during the neural network search process, the neural network structure is searched and trained using a pipeline approach.

[0016] Preferably, the digital storage and computing integrated core module includes an ALU unit.

[0017] Preferably, the ALU unit includes an adder, a multiplier and a shift accumulator; when performing an operation process, the multiplier is used to implement the multiplication operation of data and address, and then the adder is used to perform addition operation on the data and address after the multiplication operation, and finally the data and address after the addition operation are processed by the shift accumulator to obtain the operation result.

[0018] Preferably, the on-chip storage module contains multiple layers of data buffers, and each layer of data buffers is buffered by FIFO.

[0019] Preferably, the digital storage and computing integrated core module is communicatively connected to the on-chip storage module via an on-chip bus interface.

[0020] Preferably, the Memory storage unit is an SRAM memory.

[0021] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0022] The present invention provides a neural network search chip based on RISC-V architecture, including: a CPU controller module, which is connected to the memory storage unit for communication, and is used to process input data and model parameters based on the Resnet neural network search task of the host computer to obtain the searched neural network structure; wherein the CPU controller module uses the RISC-V reduced instruction set architecture to control data flow and data buffering; a DMA unit, which is connected to the CPU controller module, the memory storage unit and the on-chip storage module respectively; a digital storage and computing integrated core module, which is connected to the on-chip storage module for training the searched neural network structure according to data instructions. The present invention completes the training and search of the neural network by using the digital storage and computing integrated core and the CPU of the RISC-V architecture, which can improve the scheduling efficiency of bus transmission data. At the same time, the digital storage and computing integrated core under the architecture can make full use of computing power resources to realize network reasoning tasks, overcome the limitations of traditional storage computing power, and realize faster and more accurate neural network search. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0024] Figure 1 A neural network structure search architecture diagram provided for an embodiment of the present invention;

[0025] Figure 2 A schematic diagram of the neural network search hardware channel design provided by an embodiment of the present invention;

[0026] Figure 3 A schematic diagram of the logical architecture of a RISC-V digital storage and computing processor provided in an embodiment of the present invention;

[0027] Figure 4 The overall structure diagram of the RISC-V controlled digital storage and computing integrated neural network search provided in the embodiment of the present invention;

[0028] Figure 5 A digital storage and calculation integrated operation flow chart provided for an embodiment of the present invention;

[0029] Figure 6 A schematic diagram of the structure of a digital storage and computing unit provided in an embodiment of the present invention;

[0030] Figure 7 A schematic diagram of a hardware pipeline structure in a search space provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] The purpose of the present invention is to provide a neural network search chip based on RISC-V architecture, comprising:

[0033] The CPU controller module is communicatively connected with the Memory storage unit, and is used to process input data and model parameters based on the Resnet neural network search task of the host computer to obtain the searched neural network structure; wherein, the CPU controller module uses the RISC-V reduced instruction set architecture to control data flow and data buffering; during the neural network search process, the present invention uses a pipeline method to search and train the neural network structure.

[0034] The DMA unit is respectively connected to the CPU controller module, the Memory storage unit and the on-chip storage module for communication;

[0035] The digital storage and computing integrated core module is connected to the on-chip storage module for training the searched neural network structure according to the data instruction. It should be noted that the on-chip storage module contains multiple layers of data buffers, and each layer of data buffers is buffered by FIFO. The digital storage and computing integrated core module is connected to the on-chip storage module through an on-chip bus interface.

[0036] Specifically, the training of the searched neural network structure according to the data instruction includes:

[0037] The task scheduler is used to directly access memory data instructions through the DMA unit and save them in the buffer of the on-chip storage module. The CPU controller module is used to compile specific instruction bits through machine code, identify instruction requirements and issue control signals, and convert the control signals into a group of 8-bit data through data conversion and transmit them to the digital storage and computing integrated core module, so as to configure the digital storage and computing integrated core module to train the searched neural network structure.

[0038] Furthermore, the digital storage and computing integrated core module includes an ALU unit; the ALU unit includes an adder, a multiplier and a shift accumulator; when performing an operation process, the multiplier is used to implement the multiplication operation of data and address, and then the adder is used to perform addition operation on the data and address after the multiplication operation, and finally the data and address after the addition operation are processed by the shift accumulator to obtain the operation result.

[0039] The present invention uses a digital storage and computing integrated core and a RISC-V architecture CPU to complete the training and search of neural networks, which can improve the scheduling efficiency of bus data transmission. At the same time, the digital storage and computing integrated core under this architecture can make full use of computing power resources to realize network reasoning tasks, overcome the limitations of traditional storage computing power, and achieve faster and more accurate neural network searches.

[0040] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0041] See also Figure 1 RISC-V is an open source architecture based on a reduced instruction set. It has the characteristics of simple architecture, easy portability, and modularity. It can add more than 40 basic instructions and custom instruction sets, and can be flexibly applied to low-power and fast scenarios. The RISC-V processor consists of a processor core, physical memory, input and output units, and fixed-function accelerators.

[0042] The present invention divides the construction of a neural network into two parts: neural network search and neural network training. The neural network search uses genetic algorithms, reinforcement learning, etc. to generate a neural network structure, which is mostly serial calculation and suitable for execution on a CPU. Therefore, the present invention designs a CPU based on the RISC-V instruction set, and the neural network training is to train the searched network structure, which is mostly parallel calculation and suitable for execution on a storage and computing integrated processor. Therefore, the present invention designs a digital storage and computing coprocessor; finally, the above two parts are combined to design a neural network search storage and computing integrated chip system that supports the RISC-V architecture.

[0043] Compared with the traditional von Neumann architecture, the integrated storage and computing architecture can integrate storage and computing, overcome the "storage wall" and "power wall" storage problems, and reduce the data interaction overhead between computing and storage units, greatly increasing computing energy efficiency. Currently, AI chips based on analog arrays are widely used. The computing process limits the accuracy. Due to the fixed array, the computing function is limited. Analog storage and computing are mostly used in scenarios with low functional flexibility and low computing accuracy. They are not suitable for high-precision, high-flexibility, low-power, high-computing cloud AI scenarios, as well as neural network training with high requirements. In the integrated storage and computing architecture, the low precision and fixed array structure of the analog integrated storage and computing chip limit the complex neural network application functions. Digital storage and computing can integrate computing units and memory to better implement the multiplication and addition calculations in AI algorithms. A large number of multiplication and addition operations are used in neural networks, which need to be implemented in memory on SRAM and other memories. In actual network training, it is suitable to be combined with integrated storage and computing chips to create larger capacity, high-performance, and high-precision products, such as smart driving and data centers.

[0044] The present invention integrates the RISC-V coprocessor with the storage-computing integrated architecture, making full use of the excellent low-power performance and computing energy efficiency of the extended instructions of RISC-V. The digital storage-computing integrated hardware accelerator built with a hardware accelerator has the characteristics of openness and efficiency, embeds efficient computing capabilities in storage resources, and reduces the delay time and energy consumption overhead of frequently moving data. The present invention utilizes a digital storage-computing integrated unit based on logical operations and multiplication-addition operations. Based on the digital storage-computing integrated, it is widely used in high-precision and high-computing scenarios, has good development prospects, and is favored by academia and industry.

[0045] In this invention, ResNet is mainly used as an effective model of neural network, which uses residual blocks to solve the degradation problem in deep networks. The need to continuously store the feature map data of each layer in residual learning increases the consumption and storage of hardware resources, so we generate a neural network architecture with 3*3 convolution kernels in the network structure to support training and hardware reasoning.

[0046] Figure 2 A schematic diagram is designed for the neural network search hardware channel. During the neural network search process, floating-point numbers are converted into fixed-point numbers through a digital storage and computing core. Each PE unit trains the neural network structure through nonlinear functions, pooling layers, batch normalization layers, and activation function layers under the control of the controller. At the same time, the model accuracy of the neural network is maintained during the training process, and multiple training of the neural network can be facilitated.

[0047] The neural network architecture can separate tasks through a task block strategy, and transmit data to the controller and processor to obtain the processor hierarchical training strategy. The efficient NAS strategy reduces the prediction time during the neural network structure search process, improves the accuracy of the training time for each epoch, and updates the activation function in real time, giving the task data set results after each NN sampling and continuously updating the sampling network during the inference process.

[0048] The high-speed pipeline architecture can flexibly store the convolution results and training data of the neural network in the on-chip memory, which contains multiple layers of data buffers and uses FIFO hardware resources to buffer the data of each layer. The input and output bit widths, the size of the buffer, and the multi-level storage structure are arbitrated by the task scheduler, which facilitates the management of resource data and increases the hardware resource throughput. Data is accelerated through multiple processing unit arrays to train the network model, and the cache architecture of the multi-stage pipeline reduces the delay and power consumption of data handling.

[0049] The digital storage and computing core based on the RISC-V architecture integrates the advantages of the RISC-V reduced instruction set architecture, implements multiple instructions in the RISC-V architecture, and the storage and computing integrated core implements multiplication and addition operations, which innovates the computing paradigm of AI chips. The computing unit frequently accesses the memory data many times. The upper computer implements neural network search and training for AI algorithms, and connects to the digital storage and computing core through the bus. Each core in the multiple digital storage and computing integrated cores runs independently. After parallel pipeline arbitration scheduling, it achieves unified bandwidth, low power consumption and training inference.

[0050] Figure 3Based on the RISC-V digital storage and computing processor logic architecture, the digital storage and computing integrated core processes MAC calculations, the task scheduler is responsible for scheduling multiple digital storage and computing integrated cores, the RISC-V CPU uses the RISC-V reduced instruction set architecture as a controller to control data flow and data buffering, the main memory and buffer can cache instructions, the bus links and controls the RISC-V interface, the storage and computing integrated core processor and the host computer interface. The digital storage and computing integrated core is the system computing core, responsible for executing matrix-vector intensive tasks in structural search, the hierarchical storage structure in the present invention integrates multiple digital storage and computing cores, DDR and buffer, and the cache unit accesses the digital storage and computing integrated core and the RISC-V CPU through higher bandwidth and higher speed.

[0051] Figure 4 This is the overall structure diagram of the RISC-V controlled digital storage and computing integrated neural network search. Its overall structure mainly includes on-chip storage module, off-chip SRAM memory module, digital storage and computing integrated core module, RISC-V based CPU controller module, bus interface, and data FIFO (First In Firsr Out) module.

[0052] The working process of the neural network search chip in the present invention is as follows: first, the data stream is compressed after the neural network search task is completed in the host computer, the input data and model parameters are processed based on the Resnet neural network search task, the data can be directly accessed through the bus, the 64-bit data of data, keep, and last are read into the cache, and the search training of the neural network structure is performed.

[0053] Deploy reasoning on data in the integrated storage and computing processor. The task scheduler can directly access data instructions through DMA, pre-process the read-in cache instructions and save them in the on-chip buffer, configure the digital storage and computing core at the same time, and the DMA is also connected to the controller. The RISC-V architecture controller uses the specific instruction bits compiled by the machine code to identify the instruction requirements and issue control signals to maintain and process the data in the on-chip cache stream, and convert it into a group of 8-bit data for transmission through data conversion. Finally, the digital storage and computing coprocessor is configured to perform tasks, read weights and input data including the number of channels, length, width and height of the data. After calculating the reasoning under the control of the instruction, a signal is sent to the RISC-V coprocessor, and the task scheduler is enabled to check and perform the next neural network reasoning process. When all AI operations are completed, all stored input data and output score result reports are output.

[0054] The RISC-V 64-bit architecture is responsible for task scheduling and control, can divide the neural network reasoning part, and can connect the digital storage and computing integrated chip core and the RISC-V CPU. Each Line Buffer will process the PE input data in blocks, separate the data and weights in the Line Buffer, and store the Line Buffer bit width information in the digital storage and computing integrated processor.

[0055] The ALU unit in the digital storage and computing integrated processor contains adders and multipliers. Figure 5 It represents the digital storage and computing integrated operation process. When the digital storage and computing processor completes the operation process, there will be data and address operations, first realizing multiplication operations and then addition operations, and finally obtaining data through the shift accumulator. At the same time, it is mapped to the multi-layer convolution structure in the neural network. Through the propagation training of each layer of convolution calculation results, when deploying the chip, it is necessary to consider the resource utilization of data flow bandwidth under multi-layer convolution training and increase the parallelism of convolution calculation units. Reduce the data movement distance and reduce the data movement overhead.

[0056] The RISC-V instruction set used in the present invention is an open source reduced instruction set, which contains multiple instructions and custom instructions to control the processor and better schedule tasks and data for the coprocessor core.

[0057] Since the chip computing and storage resources are limited, the present invention uses an effective block tiling strategy to improve parallelism and improve the resource utilization of the limited on-chip cache. The large-block matrix resources are reasonably divided into multiple sub-matrices. The multiple sub-matrices can be calculated in sequence in the on-chip cache to obtain results. By utilizing the locality principle of blocking, the sub-matrix data is reused and then the new sub-matrix is ​​read in for calculation and data is moved in sequence, which greatly improves the resource utilization.

[0058] The computing unit mainly includes the computing unit contained in the digital storage and computing integrated core. Figure 6 It is a digital storage unit structure. Preprocessing is performed through row decoders, column decoders, read decoders, etc. From the perspective of computational complexity, most operations in neural networks are matrix multiplication and addition operations, and digital storage design is more suitable for neural network operations. The matrix computing unit, vector computing unit, and scalar unit in the computing architecture are better adapted to digital storage operations.

[0059] The storage system mainly includes the on-chip storage unit of the storage and computing integrated core and the corresponding data path.

[0060] The entire control unit is completed by the RISC-V coprocessor, which is responsible for controlling the completion of the entire processor core task.

[0061] The RISC-V CPU can be flexibly connected to other modules through the bus. It also has a complete tool chain and good code porting capabilities, and can provide users with a reconfigurable storage and computing integrated architecture.

[0062] Embedding computing power in the memory and completing matrix multiplication and addition calculations in the integrated storage and computing architecture can reduce resource consumption and delay time in data movement, allowing storage units to directly perform logical computing operations, scale the number of core operations in storage and computing, and improve the computing power in logical operations. This can improve the efficiency of neural network operations, reduce power consumption and costs, and break down storage wall barriers.

[0063] The matrix calculation unit and accumulator complete the corresponding matrix calculation in the convolution. Using the int8 input type, one shot can complete the 32*32*3 input convolution in the neural network search. The control branch judgment of the program can add the current matrix result to the previous result, as well as the bias operation in the convolution.

[0064] Figure 7 The hardware pipeline structure in the search space is improved. The storage and calculation of the search space are mapped to the storage unit for logical calculation operations, which reduces the delay time and energy consumption ratio. Digital operations achieve high-precision operations without precision loss. The adder pipeline operation improves the efficiency of digital storage and calculation. By searching for the resources used by each layer of PE, each layer of the neural network can be efficiently and flexibly parallelized.

[0065] The beneficial effects of the present invention are as follows:

[0066] (1) The RISC-V instruction set parallel data transmission method is used to implement the read and write functions. The traditional data transmission method is to transmit alternately after the access request is issued and the read operation is completed, and then read the data from the FIFO. The transmission process is relatively simple and inefficient. The pipeline parallel processing data FIFO used can ensure parallel reading and writing of different read and write lengths, and ensure that the system is assigned to different banks for operation at irrelevant operation times. The parallel pipeline design of the bank greatly improves the data transmission rate.

[0067] (2) Applied to data-intensive neural network search. It has the characteristics of inference block, high parallelization, and high utilization of hardware mapping resources, including large matrix multiplication units with spatial locality, large-scale vector convolution data weights, and deep learning fields of complex structure network models. Since it has a large number of resource access requests and requires a large number of thread parallel operations, the present invention can provide guarantees for the needs of the user side and greatly improve the structural search performance of the system.

[0068] (3) The array structure in the storage-computation integrated core of this design can well handle the data of the neural network inference architecture. At the same time, the design completes multiple hardware resource hierarchical scheduling tasks through the on-chip bus, uses bus resources to access the memory, and mounts the bus on the RISC-V controller interface. The configuration of the corresponding data width is required, which enriches the content of this design. The memory interface is mounted in the on-chip network layout, and the interface input requires a data layer interface and a status interface, and at the same time supplements the design with bus resources for data control.

[0069] (4) In order to overcome the problems of poor accuracy and insufficient resource utilization, this design uses a quantized approach to build a neural network while ensuring accuracy. By quantizing the network parameters and the number of activated bits as required, networks with different accuracy and resource occupancy are obtained to meet different needs, thereby achieving a balance between accuracy, hardware resource occupancy, and power consumption. At the same time, a customized pipeline mode is adopted to overcome the disadvantage that the NN network is not conducive to parallel processing due to its own structural limitations.

[0070] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0071] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A neural network search chip based on RISC-V architecture, characterized in that: include: The CPU controller module is connected to the memory storage unit for processing input data and model parameters based on the Resnet neural network search task of the host computer to obtain the searched neural network structure; wherein the CPU controller module uses the RISC-V reduced instruction set architecture to control data flow and data buffering; The DMA unit is respectively connected to the CPU controller module, the Memory storage unit and the on-chip storage module for communication; A digital storage and computing integrated core module is connected to the on-chip storage module for training the searched neural network structure according to data instructions; The searched neural network structure is trained according to the data instructions, including: The task scheduler is used to directly access memory data instructions through the DMA unit and save them in the buffer of the on-chip storage module. The CPU controller module is used to compile specific instruction bits through machine code, identify instruction requirements and issue control signals, and convert the control signals into a group of 8-bit data through data conversion and transmit them to the digital storage and computing integrated core module, so as to configure the digital storage and computing integrated core module to train the searched neural network structure.

2. The neural network search chip based on RISC-V architecture according to claim 1, characterized in that: In the neural network search process, the neural network structure is searched and trained using a pipeline approach.

3. The neural network search chip based on RISC-V architecture according to claim 1, characterized in that: The digital storage and computing integrated core module includes an ALU unit.

4. The neural network search chip based on RISC-V architecture according to claim 3, characterized in that: The ALU unit includes an adder, a multiplier and a shift accumulator; when performing an operation process, the multiplier is used to implement the multiplication operation of data and address, and then the adder is used to perform addition operation on the data and address after the multiplication operation, and finally the shift accumulator is used to process the data and address after the addition operation to obtain the operation result.

5. The neural network search chip based on RISC-V architecture according to claim 1, characterized in that: The on-chip storage module contains multiple layers of data buffers, and each layer of data buffer is buffered by FIFO.

6. The neural network search chip based on RISC-V architecture according to claim 1, characterized in that: The digital storage and computing integrated core module is communicatively connected with the on-chip storage module via an on-chip bus interface.

7. The neural network search chip based on RISC-V architecture according to claim 1, characterized in that: The Memory storage unit is an SRAM memory.

Images