Low dropout regulator circuit, corresponding equipment and methods

Abstract

The LDO regulator circuit includes an input comparator and a driver circuit. The driver circuit includes a transistor through which a current path coupled to the output node of the regulator passes. Each of the first and second drivers includes: a driver transistor through which a current path coupled to the output node passes, and a capacitor boost circuit that applies a voltage pump copy of the comparator signal to the driver transistor. A voltage refresh transistor circuit coupled to the capacitor boost circuit delivers the voltage pump copy to the capacitor boost circuit. The first and second drivers can be controllably switched between a first operating mode and a second mode. In the first operating mode, the current path through the driver transistor is either conductive or non-conductive based on the voltage pump copy of the comparator signal. In the second mode, the voltage refresh transistor circuit is activated to deliver the voltage pump copy of the comparator signal, and the current path through the driver transistor is non-conductive.

Description

Technical Field

[0001] This disclosure relates to low dropout (LDO) regulators and LDO regulators in battery-operated products such as small portable devices. Background Technology

[0002] The name "low dropout (LDO) regulator" indicates that it is a DC voltage regulator that can adjust the output voltage even when the input or supply voltage is close to the output voltage.

[0003] LDO regulators are widely used in industrial and automotive applications. The increasing demand for portable and battery-operated products necessitates that these circuits operate across a wide range of supply voltages and multi-voltage platforms. Therefore, standby and quiescent current are key concerns, given that these regulators are expected to operate over a broad temperature range (typically -40°C to 125°C). Summary of the Invention

[0004] According to one or more embodiments, a circuit is provided.

[0005] One or more embodiments relate to the corresponding devices.

[0006] Small, portable, battery-operated products used in consumer or professional electronics are examples of such devices.

[0007] One or more embodiments relate to the corresponding methods.

[0008] In the example given in this paper, due to the use of a cascode structure, the on / off output stage is used to drive an LDO with a propagation time of several hundred picoseconds. This is driven by a shift capacitor that refreshes in a manner that allows the response to be completely independent of the refresh clock frequency. Such an arrangement eliminates the need for conventional types of level shifters and charge pumps.

[0009] The example given in this article uses an output driver with a response time comparable to that of a low-voltage (LV) comparator; the corresponding LDO will therefore exhibit an improved response time.

[0010] The example given in this article involves voltage shift due to pulses on the base plate of the charging capacitor. The short pulses in the LV comparator are not filtered, which improves the efficiency of the LDO.

[0011] The examples given in this article include (very) small boost pumps: they are used only to refresh small boost capacitors, not the gates of the output drivers; area and current consumption are reduced because the low efficiency introduced by the small pump is negligible.

[0012] The examples given in this article involve two symmetrical and alternating drivers: when one driver is in the pulse phase, the other is in the refresh phase, and vice versa. Consider overlapping phases, where both drivers are in the pulse phase for continuous adjustment.

[0013] The examples given in this article include a phase generator that generates signals from the start of the refresh clock to manage different operating phases of the master driver.

[0014] In the example shown in this article, the response time of the output driver is comparable to that of a low-voltage (LV) comparator; the LDO will therefore exhibit improved response time performance. Attached Figure Description

[0015] One or more embodiments will now be described by way of example only, with reference to the accompanying drawings, in which:

[0016] Figure 1 This is a circuit diagram for a conventional low dropout (LDO) regulator.

[0017] Figure 2 This refers to the boost pump and phase generator used in the circuit discussed in this paper.

[0018] Figure 3 Here is an example diagram of the circuit discussed in this article, and

[0019] Figures 4 to 7 The diagram illustrates the following: Figure 3 Possible operating conditions for the circuit shown.

[0020] Unless otherwise stated, corresponding reference numerals in different figures usually refer to the corresponding parts.

[0021] Furthermore, for the sake of brevity, the same name can be used throughout the description:

[0022] Specific nodes or lines and the signals that appear at the nodes or lines, and

[0023] Specific components (e.g., capacitors or resistors) and their electrical parameters (e.g., capacitance or resistance / impedance). Detailed Implementation

[0024] In the following description, various specific details are illustrated to provide a thorough understanding of various examples of the embodiments described. Embodiments may be obtained without one or more specific details, or using other methods, components, materials, etc. In other instances, known structures, materials, or operations have not been shown or described in detail so as not to obscure the various aspects of the embodiments.

[0025] The references to "embodiment" or "one embodiment" within the framework of this specification are intended to indicate that a particular configuration, structure, or feature described with respect to an embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear at various points in this specification do not necessarily refer exactly to the same embodiment. Furthermore, in one or more embodiments, a particular configuration, structure, or feature may be combined in any suitable manner.

[0026] The title / reference numerals used herein are provided for convenience only and therefore do not limit the scope or range of protection of the embodiments.

[0027] As described in the introduction to this specification, low dropout (LDO) regulators are now widely used in industrial and automotive applications.

[0028] In devices such as portable and battery-operated products, there is a growing demand for LDO regulators capable of operating over a wide range of supply voltages, for example in multi-voltage platforms: values ​​such as Vcc [1.6V-3.6V] and Vdd [0.8V-1.15V] are examples of possible desired operating domains or ranges. Standby and quiescent currents are particularly important parameters for devices expected to operate over a wide temperature range (e.g., -40°C to 125°C).

[0029] A so-called on-off LDO regulator is a circuit (e.g., an integrated circuit or IC) designed to provide (e.g., a fixed) output voltage to a varying load with minimal voltage drop and (very) fast response time.

[0030] Figure 1 This is a circuit diagram of a conventional on-off, high-speed, low-dropout (LDO) regulator capable of operating in multiple voltage ranges: VCC [1.6V-3.6V] and VDD [0.8V-1.15V] (these values ​​are merely illustrative).

[0031] Figure 1 The LDO regulator includes a comparator (error amplifier) ​​10, which is powered by a voltage vdd and configured to compare a (feedback) voltage vfb with a stable reference voltage vref (e.g., a bandgap reference). The voltage vfb is derived from the output voltage vout via a loop control network LC (e.g., as part of the output voltage sensed via a voltage divider).

[0032] Comparator 10 can be implemented using low-voltage transistors to achieve a fast response time. This results in the output of comparator 10 being a low-voltage signal COMP_OUT applied to the output driver 12.

[0033] When it is desired to apply a large current to a (e.g., capacitive) load Cload at the output node vout, the output driver 12 is powered by voltage vcc to generate a regulated voltage.

[0034] The output driver 12 includes a voltage pump powered by voltage vcc and configured to generate a (fixed) voltage signal vpump (e.g., 3.6V).

[0035] Level shifter 122 shifts the low-voltage signal COMP_OUT (e.g., [0, vdd]) from comparator 10 to the control (at node A) output transistor M. DRV The switching voltage vpump (e.g., [0, vpump]).

[0036] If the output voltage vout becomes higher than the desired value relative to the reference voltage, the regulator drives the power transistor M. DRV To maintain a constant output voltage vout.

[0037] like Figure 1 The structure and operation of the LDO regulator shown are well known to those skilled in the art, which makes it unnecessary to provide a more detailed description herein.

[0038] Output driver M DRV This can be achieved using a high-voltage (HV) transistor (e.g., a MOSFET transistor) whose gate is coupled to node A, and in which the source-drain current path is included in the current line between the node at voltage vcc and the load Cout (output node vout).

[0039] Transistor M DRV It is chosen to be large enough to achieve the maximum current for the regulated output voltage vout (e.g., 1.5V).

[0040] It should be noted again that the quantitative data described herein are merely exemplary and non-limiting.

[0041] Make transistor M DRV High output current involves M DRV Choose a “large” transistor with a correspondingly high gate capacitance.

[0042] The low-voltage comparator 10 provides a (very) fast response time, allowing the COMP_OUT signal to have a correspondingly high switching frequency. Therefore, as Figure 1 The conventional arrangement shown has many drawbacks.

[0043] For example, the response time of level shifter 122 may not be fast enough to fully follow the changes in signal COMP_OUT, resulting in undesirable (low-pass) filtering of short pulses in signal COMP_OUT.

[0044] The level shifter 122 may also introduce delay in its commutation (switching), and this reduces the output driver M DRV This reduces the overall response time of the LDO regulator.

[0045] It is expected that pump 121 can provide a high current to keep up with the commutation in level shifter 122 and drive output driver M. DRV The large gate capacitance results in the pump 121 potentially introducing current into the system inefficiently; furthermore, the use of a large pump 121 leads to a considerable area consumption.

[0046] In contrast, the examples discussed in this article (for example, see...) Figure 3 It includes two drivers, 12A (driver A) and 12B (driver B), which are considered to be symmetrical components and operate primarily on the signal COMP_OUT from the comparator in an alternating manner: when one driver is in the pulse phase, the other driver is in the refresh phase, and vice versa.

[0047] In the alternative approach, when referring to the "primary" operation, it is anticipated that there may be overlapping or coincident phases, in which both drivers pulsate to facilitate continuous adjustment, as described below.

[0048] The drivers 12A and 12B discussed herein are configured to cooperate within the framework of an LDO regulator, which includes:

[0049] Comparator 10 (basically as) Figure 1 As shown), it is powered by voltage vdd and configured to compare the (feedback) voltage vfb with the reference voltage vref.

[0050] Phase generator 100A, starting from the refresh clock CK_REFRESH, generates various drive signals PA_LV, PB_LV, PA, and PB to manage the different operating phases of drivers DRIVER A and DRIVER B.

[0051] Boost Pump 100B: This is a small charge pump that generates a "boosted" output voltage vbl_boost = vdd + vout, starting from the signal vout and signals PA and PB, plus various other signals PA_TOP_ana, PA_BST_TOP_ana, PB_TOP_ana, and PB_BST_TOP_ana, to drive drivers DRIVER A and DRIVER B as described below.

[0052] Phase generator 100A and booster pump 100B in Figure 2 The components shown are distinct from each other and are also different from drivers 12A and 12B; this is only as an example, as in some examples these components may be integrated with each other and / or with drivers 12A and 12B.

[0053] Based on the explanation provided below, the phase generator 100A and the booster pump 100B can be implemented in a manner known to those skilled in the art (e.g., the phase generator 100 can be implemented as a finite state machine – FSM).

[0054] The comparator 10 (indicated twice at the nodes where the signal COMP_OUT is injected into drivers 12A and 12B), the phase generator 100A, and the boost pump 100B are combined in a full LDO regulator configuration. Figure 3 The diagram in the middle is shown. Figures 4 to 7 The focus is on a driver architecture designed to generate a signal vout applied to the load Cout, starting from the signal COMP_OUT of comparator 10.

[0055] like Figures 3 to 7 As shown, drivers 12A (DRIVER A) and 12B (DRIVER B) are symmetrical.

[0056] The reference numerals 12A and 12B in the accompanying drawings are intended to emphasize the fact that drives 12A and 12B are designed to function in conjunction with... Figure 1 The output driver 12 plays a similar role in generating the output voltage vout, starting from the low-voltage signal COMP_OUT of the comparator 10.

[0057] This article Figures 3 to 7 This is an example of the field-effect (MOSFET) implementation of drivers 12A and 12B.

[0058] At least in principle, the bipolar junction transistor (BJT) implementation of the circuits discussed in this specification is also possible. In such a BJT implementation, the control terminal would be the base of these transistors (instead of the gate of the field-effect transistor), and the current path through them would be represented by the emitter-collector current path (instead of the source-drain current path of the field-effect transistor).

[0059] Figures 3 to 7 This is an example of how drivers 12A and 12B are implemented, where it is assumed that voltages such as Vcc or Vdd are positive, and the polarity of the transistors (e.g., p-channel / n-channel MOSFETs) is selected accordingly. When voltages such as Vcc or Vdd are negative, those skilled in the art can easily design corresponding polarity adapters.

[0060] First consider driver 12A (DRIVER A). The reference numerals MCASC_2A and MDRV_1A indicate two transistors (e.g., two MOSFET transistors) with current paths (source-drain in the case of field-effect transistors such as MOSFETs) cascaded through them. These current paths are connected at a node at voltage vcc with the output node or line vout (which is common to both drivers 12A and 12B and is intended to be connected to a load, such as, for example, a capacitive load Cload). See also... Figure 1 )between.

[0061] MDRV_1A is the master driver transistor and can be selected as a low-voltage (LV) transistor.

[0062] In the implementation shown in the figure, the source of transistor MDRV_1A is coupled to the output node vout, and the gate is coupled to node B1. When a pulse appears in the signal COMP_OUT from comparator 10, node B1 is shifted from vout pulse to vout+vdd.

[0063] As mentioned above, for the sake of brevity, the same names (e.g., vout, vdd) are used throughout the description to specify a node or line and the signal that appears at that node or line.

[0064] Therefore, the reference numeral vout indicates the regulated voltage, and vdd is a low-voltage supply (e.g., [0.8V, 1.15V]: the quantitative values ​​provided throughout this specification are merely exemplary and non-limiting).

[0065] The transistor MCASC_2A is a high-voltage (HV) transistor (such as a MOSFET) that helps to obtain a common-source, common-gate signal at the drain of the transistor MDRV_1A, so as to protect it under various operating conditions.

[0066] When a pulse appears in the signal COMP_OUT from comparator 10, the control electrode (gate in the case of a field-effect transistor such as a MOSFET) C1 is pulsed (shifted) from vout+vdd to vout+2vdd.

[0067] As shown in this article, transistors MDRV_1A and MCASC_2A are “on” (conduct) during the pulse phase as described below.

[0068] The attached diagram shows C1A and C1B, which represent boost capacitors that are refreshed during the refresh phase to make node B1 become vout and node C1 become vbl_boost = vout + vdd.

[0069] Nodes C1 and B1 are arranged at a voltage of vbl_boost (from... Figure 2 In the current line between the node and the output node vout of the booster pump 100B, the current line includes the following cascaded arrangement:

[0070] The current path through the transistor M2A arranged between the node with voltage vbl_boost and node C1 (source-drain in the case of a field-effect transistor such as a MOSFET),

[0071] Capacitor C1B between node C1 and node A1;

[0072] Capacitor C1A between node A1 and node B1;

[0073] The current path through the transistor M1A arranged between node B1 and output node vout (source-drain in the case of a field-effect transistor such as a MOSFET).

[0074] Transistors M1A and M2A are used to refresh capacitors C1A (node ​​B1) and C1B (node ​​C1).

[0075] The control electrodes (gates in the case of field-effect transistors such as MOSFETs) of transistors M1A and M2A receive signals PA_TOP_ana and PA_BST_TOP_ana (values ​​vout+vdd and vout+2vdd, respectively) from boost pump 100B to turn on the two transistors M1A and M2A (making them conductive) during the refresh phase as described below.

[0076] The reference numerals M3A and M4A in the attached diagram indicate two additional transistors (e.g., MOSFETs) arranged as follows:

[0077] The current path (source-drain) of transistor M3A between the control electrode (gate) C11 of cascode transistor MCASC_2A and the reference node (e.g., ground), and

[0078] The current path through transistor M4A between nodes C1 and C11 (source-drain) is such that the control electrode G1 of transistor M4A is coupled to the control electrode (gate) of transistor M3A.

[0079] Transistors M3A and M4A (n-channel and p-channel) are used to disconnect node C11 from node C1 and ground it when the regulator and therefore the output driver are turned off (EN=0). Under the off condition, nodes B1 and C11 are grounded.

[0080] AND gate N1 provides gating to signal COMP_OUT from comparator 10 via signal PA_LV, which is "0" under refresh condition (therefore signal COMP_OUT is ignored) and "1" under pulse condition.

[0081] Figure 3 The bottom (and) Figures 4 to 7 An exemplary demonstration is provided via direct reference, showing how the signals at nodes B1 and G1 are based on the general enable signal EN, via the inverter of reference node vdd (the signal at node B1), and via the inverter of reference node vdd and the reference signal from... Figure 2 An exemplary representation of the cascaded arrangement of the level shifter LS (signal at node G1) of node vdd_boost of the boost pump 100B (any known type for this purpose) to obtain (asserted, also known as "activated")

[0082] Now consider driver 12B (DRIVER B), where reference numerals MCASC_2B and MDRV_1B indicate two transistors (e.g., two MOSFET transistors) with current paths (source-drain in the case of field-effect transistors such as MOSFETs) arranged through them. The current paths are cascaded between a node with voltage vcc and an output node or line vout (which, as described, is common to both drivers 12A and 12B).

[0083] MDRV_1B is the master driver transistor and can be selected as a low-voltage (LV) transistor.

[0084] In the implementation shown in the figure, the source of transistor MDRV_1B is coupled to the output node vout, and the gate is coupled to node B2. When a pulse appears in the signal COMP_OUT from comparator 10, node B2 is shifted from vout pulse to vout+vdd.

[0085] Transistor MCASC_2B is a high-voltage (HV) transistor (e.g., MOSFET) that helps to obtain a cascode signal at the drain of transistor MDRV_1B to protect it under various operating conditions.

[0086] When a pulse appears in the signal COMP_OUT from comparator 10, the control electrode (gate in the case of a field-effect transistor such as a MOSFET) C2 is pulsed (shifted) from vout+vdd to vout+2vdd.

[0087] As shown in this article, transistors MDRV_1B and MCASC_2B are “on” (conduct) during the pulse phase as described below.

[0088] The attached diagram shows C2B and C2A, which represent boost capacitors that are refreshed during the refresh phase to make node B2 become vout and node C2 become vbl_boost = vout + vdd.

[0089] Nodes C2 and B2 are placed on the node with voltage vbl_boost (from...) Figure 2 The current line between the booster pump 100B and the output node vout includes the following cascaded arrangement:

[0090] The current path through the transistor M2B arranged between the node with voltage vbl_boost and node C2 (source-drain in the case of a field-effect transistor such as a MOSFET),

[0091] Capacitor C2B between node C2 and node A2;

[0092] Capacitor C1B between node A2 and node B2;

[0093] The current path through the transistor M1B arranged between node B2 and output node vout (source-drain in the case of a field-effect transistor such as a MOSFET).

[0094] Transistors M1B and M2B are used to refresh capacitors C2A (node ​​B2) and C2B (node ​​C2).

[0095] The control electrodes (gates in the case of field-effect transistors such as MOSFETs) of transistors M1B and M2B receive signals PB_TOP_ana and PB_BST_TOP_ana (values ​​vout+vdd and vout+2vdd, respectively) from boost pump 100B to turn on the two transistors M1B and M2B (make them conductive) during the refresh phase as described below.

[0096] The reference numerals M3B and M4B in the attached diagram indicate two additional transistors (e.g., MOSFETs) arranged as follows:

[0097] The current path (source-drain) of transistor M3B between the control electrode (gate) C22 of cascode transistor MCASC_2B and the reference node (e.g., ground), and

[0098] The current path through transistor M4B between nodes C2 and C22 (source-drain) is such that the control electrode (gate) G1 of transistor M4B is coupled to the control electrode (gate) of transistor M3B.

[0099] Transistors M3B and M4B (n-channel and p-channel) are used to disconnect node C22 from node C2 and ground it when the regulator and therefore the output driver are turned off (EN=0). Nodes B2 and C22 are grounded under the off-condition.

[0100] AND gate N2 provides gating to signal COMP_OUT from comparator 10 via signal PB_LV, which is "0" under refresh condition (so that signal COMP_OUT is ignored) and "1" under pulse condition.

[0101] Figure 3 The bottom (and) Figures 4 to 7 This provides a direct reference method showing how the signals at nodes B2 and G2 are based on the general enable signal EN, via the inverter of the reference node vdd (the signal at node B2), and via the inverter of the reference node vdd and the reference... Figure 2 An exemplary representation of the cascaded arrangement of the level shifter LS (signal at node G2) of node vdd_boost of the boost pump 100B (any known type for this purpose) is obtained.

[0102] Figures 4 to 7 It is through the source Figure 2 An example of the (mainly alternating) operation of drivers 12A and 12B controlled by the phase generator 100A signals PA_LV, PB_LV, PA, PB.

[0103] Figures 4 to 7 The labels ON and OFF indicate the conductive / non-conductive state of the relevant transistor, and the logic state ("0" or "1") of some nodes is indicated against a direct reference.

[0104] Figure 4 Here are examples of the behavior of drivers 12A and 12B under the "on" condition, where:

[0105] Driver 12B is in pulse phase, where transistors MDRV_1B and MCASC_2B are turned on / off according to the value of the signal COMP_OUT from comparator 10, and

[0106] Driver 12A is in the refresh phase, where boost capacitors C1A and C1B are charged through transistors M1A and M2A.

[0107] During the pulse phase of driver 12B:

[0108] The signal COMP_OUT from comparator 10 (switching between gnd and vdd) propagates via AND gate N2 (because PB_LV is "1").

[0109] Node C22 switches between vout+vdd and vout+2vdd, and

[0110] Node B2 switches between vout and vout+vdd.

[0111] During the refresh phase of driver 12A:

[0112] Node A1 is grounded (because LA_LV is "0", this is true even if the signal COMP_OUT pulsates between ground and Vdd).

[0113] Node B1 is brought to vout.

[0114] The gates of transistors M1A and M2A are boosted by PA_TOP_ana→vout+vdd and PA_BST_TOP_ana→(vout+vdd)+vdd, respectively.

[0115] Figure 5 Here is an example of the behavior of drivers 12A and 12B under complementary "on" conditions, where:

[0116] Driver 12A is in pulse phase, where transistors MDRV_1A and MCASC_2A are turned on / off according to the value of the signal COMP_OUT from comparator 10, and

[0117] Driver 12B is in the refresh phase, where boost capacitors C2A and C2B are charged through transistors M1B and M2B.

[0118] During the pulse phase of driver 12A:

[0119] The signal COMP_OUT from comparator 10 (switching between gnd and vdd) propagates via AND gate N1 (because PA_LV is "1").

[0120] Node C11 switches between vout+vdd and vout+2vdd, and

[0121] Node B1 switches between vout and vout+vdd.

[0122] During the refresh phase of driver 12B:

[0123] Node A2 is grounded (because PB_LV is "0", this is true even if the signal COMP_OUT pulsates between ground and Vdd).

[0124] Node 21 is brought to vout.

[0125] The gates of transistors M1B and M2B are boosted by PB_TOP_ana→vout+vdd and PB_BST_TOP_ana→(vout+vdd)+vdd, respectively.

[0126] In order to ensure that during the alternation of refresh phase and pulse phase between drivers 12A and 12B (from Figures 4 to 5 And from Figures 5 to 4 The conversion facilitates sufficient adjustment, with the phase signals (basically LA_LV and PB_LV) controlled by the phase generator 100A, temporarily forcing both drivers 12A and 12B to a state such that... Figure 6 The pulse conditions are shown.

[0127] The period during which both drivers are on (pulse) is (very) short, for example, a fraction of the “on” time of the signal COMP_OUT from comparator 10. Studies have found this to be sufficient to provide continuity of regulation as needed.

[0128] It was also found that a refresh rate of about 5 MHz was sufficient to provide satisfactory operation for the circuits illustrated in this article.

[0129] For example, suppose that driver 12B is in pulse mode while driver 12A is in refresh mode (i.e., Figure 4 Given the conditions shown, the possible phase sequences of the signal that contribute to a satisfactory transition are as follows:

[0130] Transistors M1A and M2A are turned on, → the refresh of driver 12A is interrupted.

[0131] Signal PA_LV is turned on (“1”) → driver 12A is set to pulse mode, so that both drivers 12A and 12B are in pulse mode.

[0132] Signal PB_LV off (“0”) → Pulse mode interrupt in driver 12B.

[0133] Transistors M1B and M2B are turned on (conducting electricity) → Driver 12B is set to refresh mode.

[0134] Conversely, assuming that driver 12A is in pulse mode and driver 12B is in refresh mode (i.e., Figure 5 If the conditions shown occur, the possible phase sequences of the signal that contribute to achieving a satisfactory transition are as follows:

[0135] Transistors M1B and M2B are turned off → refresh of driver 12B is interrupted.

[0136] When signal PB_LV is turned on (“1”), driver 12B is set to pulse mode, making both drivers 12A and 12B in pulse mode.

[0137] Signal PA_LV off (“0”) → Pulse mode interrupted in driver 12A.

[0138] Transistors M1B and M2B are turned on (conducting electricity) → Driver 12B is set to refresh mode.

[0139] Figure 7 This indicates that drivers 12A and 12B are in a shutdown condition (e.g., standby state), where near-zero current consumption is required even when VCC is active (e.g., 3.6V).

[0140] Under these conditions:

[0141] vout is set to ground.

[0142] The regulator is off, and EN is set to "0".

[0143] The MCASC_2A and MCASC_2B being turned off (non-conductive) helps protect the low-voltage drivers (MDRV_1A and MDRV_1B).

[0144] In summary, the architecture presented in this article offers the following advantages:

[0145] The response time of the output driver circuit is comparable to that of the low-voltage comparator, which improves the LDO performance in terms of response time (voltage shift is generated via pulses on the charging capacitor base plate).

[0146] The short pulses provided by the low-voltage comparator 10 are not filtered, which improves the efficiency of the LDO regulator.

[0147] A (very) small boost pump can be used, as long as the boost pump only refreshes the small boost capacitor and not the gate of the output driver.

[0148] Area consumption is reduced, and

[0149] Current consumption is also reduced because the inefficiency introduced by the small pump is negligible.

[0150] Without prejudice to the fundamental principles, details and embodiments may vary, even significantly, relative to the content described by way of example only, without departing from the scope of protection.

[0151] A circuit can be summarized as including: an output node (vout) configured to apply an output voltage to a load (Cload); an input comparator (10) configured to perform a comparison of a reference voltage (vref) and a voltage (vfb) as a function of the output voltage (LC), and to generate a comparison signal (COMP_OUT) having a first logic value or a second logic value based on the comparison result; and driver circuitry (12A, 12B) coupled to the input comparator (10) to receive the comparison signal (COMP_OUT) therefrom, the driver circuitry including at least one driver transistor. MDRV_1A, MCASC_2A, MDRV_1B, MCASC_2B), at least one driver transistor has a current path coupled to an output node (vout) therethrough and control terminals (B1, C1, B2, C2), the control terminals (B1, C1, B2, C2) being configured to receive a voltage pump (100A; vbl_boost) copy of the comparison signal (COMP_OUT), wherein the copy of the comparison signal (COMP_OUT) has a first corresponding logic value or a second corresponding second logic value based on the comparison result of the input comparator (10), wherein A copy of the voltage pump (100A; vbl_boost) in response to the comparison signal (COMP_OUT) has a first corresponding logic value or a second corresponding logic value, and the current path through at least one driver transistor (MDRV_1A, MCASC_2A, MDRV_1B, MCASC_2B) is either conductive or non-conductive, wherein the driver circuitry includes a first driver (12A) and a second driver (12B) coupled to the input comparator (10) to receive the comparison signal (COMP_OUT) therefrom, and the first driver (12A) and the second driver (12B) are... Each includes at least one driver transistor (MDRV_1A, MCASC_2A, MDRV_1B, MCASC_2B), a boost capacitor circuit (C1A, C1B, C2A, C2B), and a voltage refresh transistor circuit (M1A, M2A, M1B, M2B). The at least one driver transistor has a current path through it coupled to an output node (vout) and control terminals (B1, C1, B2, C2). The boost capacitor circuit (C1A, C1B, C2A, C2B) is configured to pump (100A) the voltage of the comparison signal (COMP_OUT).A copy of the voltage pump (100A; vbl_boost) is applied to the control terminals (B1, C1, B2, C2) of at least one driver transistor (MDRV_1A, MCASC_2A, MDRV_1B, MDRV_2B). A voltage refresh transistor circuit (M1A, M2A, M1B, M2B) is coupled to a boost capacitor circuit (C1A, C1B, C2A, C2B) to transmit the comparator signal (COMP_OUT) on the voltage pump (100A; vbl_boost) copy. The first driver (12A) and the second driver (12B) can be controllably switched (PA_LV, PB_LV) between a first operating mode and a second operating mode. During the first operating mode, a copy of the voltage pump (100A; vbl_boost) is applied through at least one driver transistor (MDRV_1A, MCASC_2A, MDRV_1B, MCAS). The current path of C_2B responds to the voltage pump (100A; vbl_boost) copy of the comparator signal (COMP_OUT) by having a first corresponding logic value or a second corresponding logic value and is either conductive or non-conductive, and the voltage refresh transistor circuits (M1A, M2A, M1B, M2B) are deactivated (OFF). During the second operating mode, the voltage refresh transistor circuits (M1A, M2A, M1B, M2B) coupled to the boost capacitor circuits (C1A, C1B, C2A, C2B) are activated (ON) to transmit the voltage pump (100A; vbl_boost) copy of the comparator signal (COMP_OUT) thereon, and the current path through at least one driver transistor (MDRV_1A, MCASC_2A, MDRV_1B, MCASC_2B) is non-conductive.

[0152] The circuit may include a mode control circuit (100A) configured (PA_LV, PB_LV) to alternately switch between a first driver (12A) and a second driver (12B) between a first operating condition and a second operating condition. Under the first operating condition, the first driver (12A) may be in a first operating mode and the second driver (12B) may be in a second operating mode. Under the second operating condition, the first driver (12A) may be in the second operating mode and the second driver (12B) may be in the first operating mode.

[0153] The mode control circuit (100A) can be configured (PA_LV, PB_LV) to switch the first driver (12A) and the second driver (12B) to transitional operating conditions, wherein both the first driver (12A) and the first driver (12B) can be in a first operating mode.

[0154] Each of the first driver (12A) and the second driver (12B) may include a current path between a power supply node (vcc) and an output node (vout), and may include a cascaded arrangement of current paths through the first driving transistor (MDRV_1A, MDRV_1B) and the second driving transistor (MCASC_2A, MCASC_2B), the first driving transistor having a current path therethrough coupled to the output node (vout), and the second driving transistor (MCASC_2A, MCASC_2B) being arranged to have a current path therethrough between the power supply node (vcc) and the first driving transistor (MDRV_1A, MDRV_1B).

[0155] The first driving transistor (MDRV_1A, MDRV_1B) and the second driving transistor (MCASC_2A, MCASC_2B) can be a low-voltage transistor and a high-voltage transistor, respectively.

[0156] The circuit may include a mode control circuit (100A) configured (EN) to switch the first driver (12A) and the second driver (12B) to a shutdown condition in which the output node (vout) may be grounded and the second driver transistors (MCASC_2A, MCASC_2B) in the first driver (12A) and the second driver (12B) may be non-conductive.

[0157] Each of the first driver (12A) and the second driver (12B) may include: circuit nodes (A1, A2) configured to have a comparator signal (COMP_OUT) applied thereto; a first boost capacitor (C1A, C2A) and a second boost capacitor (C1B, C2B) with the circuit nodes (A1, A2) arranged between the first boost capacitor and the second boost capacitor; a first voltage refresh transistor (M1A, M1B) with a current path passing through the first voltage refresh transistor (M1A, M1B) arranged between the first boost capacitor (C1A, C2A) and the output node (vout); and a second voltage refresh transistor (M2A, M2B) with a current path passing through the second voltage refresh transistor (M2A, M2B) arranged between the second boost capacitor (C1B, C2B) and the boost power supply node vbl_boost.

[0158] Each of the first driver (12A) and the second driver (12B) may include: a first driver transistor (MDRV_1A, MDRV_1B) whose control terminal is coupled to the current path of the first refresh transistor (M1A, M1B) between the first refresh transistor (M1A, M1B) and the first boost capacitor (C1A, C2A) via B1, B2; and a second driver transistor (MCASC_2A, MCASC_2B) whose control terminal is coupled to the current path of the second refresh transistor (M2A, M2B) between the second refresh transistor (M2A, M2B) and the boost power node (vbl_boost) via C1, C2.

[0159] Each of the first driver (12A) and the second driver (12B) may include: a control terminal of the second driver transistor (MCASC_2A, MCASC_2B) coupled via a transistor switch (M3A, M4A, M3B, M4B) to a current path passing through the second refresh transistor (M2A, M2B), the transistor switch being configured to not conduct in response to the circuit being disabled (EN=0) to decouple the control terminal of the second driver transistor (MCASC_2A, MCASC_2B) from the current path passing through the second refresh transistor (M2A, M2B).

[0160] The device can be summarized as including circuitry and an electrical load (Cload) coupled to the output node (vout) in the circuitry to receive a regulated voltage from it.

[0161] A method for operating a circuit or device, the method can be summarized as including: alternately switching (PA_LV, PB_LV) a first driver (12A) and a second driver (12B) between a first operating condition and a second operating condition, wherein under the first operating condition, the first driver (12A) is in a first operating mode and the second driver (12B) is in a second operating mode, and under the second operating condition, the first driver (12A) is in the second operating mode and the second driver (12B) is in the first operating mode.

[0162] The method may include switching the first driver (12A) and the second driver (12B) (PA_LV, PB_LV) to a transitional operating condition, in which both the first driver (12A) and the first driver (12B) may be in a first operating mode.

[0163] Switching the first driver (12A) and the second driver (12B) to the transition operating conditions (PA_LV, PB_LV) may include: interrupting the second operating mode in one of the first and second drivers (12A or 12B) to deactivate the voltage refresh transistor circuits (M1A, M2A, M1B, M2B) therein, while keeping the other of the first and second drivers (12B or 12A) in the first operating mode, wherein both the first (12A) and the second (12B) may be in the first operating mode, and interrupting the first operating mode in the other of the first and second drivers (12A or 12B) to activate the voltage refresh transistor circuits (M1A, M2A, M1B, M2B) therein.

[0164] The various embodiments described above can be combined to provide further embodiments. Based on the detailed description above, these and other changes can be made to the embodiments. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents enjoyed by these claims. Therefore, the claims are not limited by this disclosure.

Claims

1. A circuit comprising: An output node, which is configured to apply an output voltage to a load; The input comparator is configured as follows: A reference voltage is compared with a first voltage, which is a function of the output voltage; as well as Based on the result of comparing the reference voltage with the first voltage, a comparison signal having a first logic value or a second logic value is generated; as well as A driver circuit, coupled to the input comparator and configured to receive the comparison signal from the input comparator, the driver circuit comprising: A first driver and a second driver, coupled to the input comparator and configured to receive the comparison signal, each of the first driver and the second driver comprising: At least one driver transistor having a conductive terminal coupled to the output node and a control terminal configured to receive a copy of the voltage pump of the comparison signal, wherein the copy of the comparison signal has a first corresponding logic value or a second corresponding logic value based on the result of comparing the reference voltage with the first voltage, wherein the at least one driver transistor is conductive or non-conductive in response to the copy of the voltage pump of the comparison signal having the first corresponding logic value or the second corresponding logic value. A boost capacitor circuit configured to apply a copy of the voltage pump of the comparison signal to the control terminal of the at least one driver transistor; and A voltage refresh transistor circuit, coupled to the boost capacitor circuit, is configured to transmit a copy of the voltage pump of the comparison signal to the boost capacitor circuit. The first driver and the second driver can be controllably switched between the following: In a first operating mode, during which the at least one driver transistor is either conductive or non-conductive in response to a copy of the voltage pump of the comparison signal having either the first corresponding logic value or the second corresponding logic value, and the voltage refresh transistor circuit is deactivated, and In the second operating mode, the voltage refresh transistor circuit is activated to transmit a copy of the voltage pump of the comparison signal to the boost capacitor circuit, and the at least one driver transistor is not conductive.

2. The circuit according to claim 1, comprising: A mode control circuit is configured to alternately switch between the first driver and the second driver: A first operating condition, under which the first driver is in the first operating mode and the second driver is in the second operating mode, and The second operating condition is that, under the second operating condition, the first driver is in the second operating mode, and the second driver is in the first operating mode.

3. The circuit of claim 2, wherein the mode control circuit is configured to switch the first driver and the second driver to a transitional operating condition, wherein both the first driver and the second driver are in the first operating mode under the transitional operating condition.

4. The circuit of claim 1, wherein each of the first driver and the second driver includes a current path between the power supply node and the output node, the current path comprising a cascaded arrangement of current paths passing through: A first driver transistor, and a current path coupled to the output node passes through the first driver transistor, and A second driver transistor is arranged such that the current path between the power node and the first driver transistor passes through the second driver transistor.

5. The circuit according to claim 4, wherein the first driver transistor and the second driver transistor are a low-voltage transistor and a high-voltage transistor, respectively.

6. The circuit according to claim 4, comprising: A mode control circuit is configured to switch the first driver and the second driver to a shutdown condition, wherein the output node is grounded and the second driver transistors of the first driver and the second driver are not conductive.

7. The circuit of claim 1, wherein each of the first driver and the second driver comprises: A circuit node, configured to have the comparison signal applied thereto; A first boost capacitor and a second boost capacitor, wherein the circuit node is arranged between the first boost capacitor and the second boost capacitor; A first voltage refresh transistor, wherein a current path arranged between the first boost capacitor and the output node passes through the first voltage refresh transistor; as well as The second voltage refresh transistor is arranged between the second boost capacitor and the boost power supply node, and the current path passes through the second voltage refresh transistor.

8. The circuit of claim 7, wherein each of the first driver and the second driver comprises: A first driver transistor, the control terminal of which is coupled to a current path passing through the first voltage refresh transistor between the first voltage refresh transistor and the first boost capacitor; as well as The second driver transistor has its control terminal coupled to a current path passing through the second voltage refresh transistor between the second voltage refresh transistor and the boost power node.

9. The circuit of claim 8, wherein in each of the first driver and the second driver, the control terminal of the second driver transistor is coupled via a transistor switch to the current path through the second voltage refresh transistor, the transistor switch being configured to decouple the control terminal of the second driver transistor from the current path through the second voltage refresh transistor in response to the circuit being disabled.

10. An apparatus for a low-dropout LDO regulator, comprising: The circuit includes: An output node, which is configured to apply an output voltage to a load; The input comparator is configured as follows: A reference voltage is compared with a first voltage, which is a function of the output voltage; and Based on the result of comparing the reference voltage with the first voltage, a comparison signal having a first logic value or a second logic value is generated; and A driver circuit, coupled to the input comparator and configured to receive the comparison signal from the input comparator, the driver circuit comprising: A first driver and a second driver, coupled to the input comparator and configured to receive the comparison signal, each of the first driver and the second driver comprising: At least one driver transistor having a conductive terminal coupled to the output node and a control terminal configured to receive a copy of the voltage pump of the comparison signal, wherein the copy of the comparison signal has a first corresponding logic value or a second corresponding logic value based on the result of comparing the reference voltage with the first voltage, wherein the at least one driver transistor is conductive or non-conductive in response to the copy of the voltage pump of the comparison signal having the first corresponding logic value or the second corresponding logic value. A boost capacitor circuit configured to apply a copy of the voltage pump of the comparison signal to the control terminal of the at least one driver transistor; and A voltage refresh transistor circuit, coupled to the boost capacitor circuit and configured to transmit a copy of the voltage pump of the comparison signal to the boost capacitor circuit. The first driver and the second driver can be controllably switched between the following: In a first operating mode, during which the at least one driver transistor is either conductive or non-conductive in response to a copy of the voltage pump of the comparison signal having either the first corresponding logic value or the second corresponding logic value, and the voltage refresh transistor circuit is deactivated, and A second operating mode, during which the voltage refresh transistor circuit is activated to deliver a copy of the voltage pump of the comparison signal to the boost capacitor circuit, and the at least one driver transistor is not conducting; and An electrical load is coupled to the output node and configured to receive a regulated voltage from the circuit.

11. The device of claim 10, wherein the circuit comprises: A mode control circuit is configured to alternately switch between the first driver and the second driver: A first operating condition, under which the first driver is in the first operating mode and the second driver is in the second operating mode, and The second operating condition is that, under the second operating condition, the first driver is in the second operating mode, and the second driver is in the first operating mode.

12. The device of claim 11, wherein the mode control circuit is configured to switch the first driver and the second driver to a transitional operating condition, wherein both the first driver and the second driver are in the first operating mode under the transitional operating condition.

13. The device of claim 10, wherein each of the first driver and the second driver includes a current line between a power supply node and the output node, the current line comprising a cascaded arrangement of current paths passing through: A first driver transistor, and a current path coupled to the output node passes through the first driver transistor, and A second driver transistor is arranged such that the current path between the power node and the first driver transistor passes through the second driver transistor.

14. The device of claim 13, wherein the first driver transistor and the second driver transistor are a low-voltage transistor and a high-voltage transistor, respectively.

15. The device of claim 13, wherein the circuitry comprises: A mode control circuit is configured to switch the first driver and the second driver to a shutdown condition, wherein the output node is grounded and the second driver transistors of the first driver and the second driver are not conductive.

16. The device of claim 10, wherein each of the first driver and the second driver comprises: A circuit node, configured to have the comparison signal applied thereto; A first boost capacitor and a second boost capacitor, wherein the circuit node is arranged between the first boost capacitor and the second boost capacitor; A first voltage refresh transistor, wherein a current path arranged between the first boost capacitor and the output node passes through the first voltage refresh transistor; as well as The second voltage refresh transistor is arranged between the second boost capacitor and the boost power supply node, and the current path passes through the second voltage refresh transistor.

17. A method for a low-dropout LDO regulator, comprising: The reference voltage is compared with a first voltage, which is a function of the circuit's output voltage; as well as Based on the result of comparing the reference voltage with the first voltage, a comparison signal having a first logic value or a second logic value is generated; Generate a voltage-pumped copy of the comparison signal; For each of the first and second drives, The voltage refresh transistor circuit transmits the voltage pump copy of the comparison signal to the boost capacitor circuit. The voltage pump copy of the comparison signal is applied to the control terminal of at least one driver transistor via the boost capacitor circuit. as well as The first driver and the second driver can be switched controllably between the following: In a first operating mode, during which the at least one driver transistor conducts or does not conduct in response to the voltage pump copy of the comparison signal having a first corresponding logic value or a second corresponding logic value, and the voltage refresh transistor circuit is deactivated, and In the second operating mode, the voltage refresh transistor circuit is activated to deliver the voltage pump copy of the comparison signal to the boost capacitor circuit, and the at least one driver transistor is not conducting.

18. The method of claim 17, wherein: Under the first operating condition, the first driver is in the first operating mode, and the second driver is in the second operating mode. Under the second operating condition, the first driver is in the second operating mode, and the second driver is in the first operating mode.

19. The method of claim 17, comprising: Switch the first driver and the second driver to a transitional operating condition, wherein both the first driver and the second driver are in the first operating mode.

20. The method of claim 19, wherein switching the first driver and the second driver to the transitional operating condition comprises: The second operating mode of one of the first driver and the second driver is interrupted, and the voltage refresh transistor circuit therein is deactivated, while the other of the first driver and the second driver is kept in the first operating mode, wherein both the first driver and the second driver are in the first operating mode. The first operating mode of the other of the first driver and the second driver is interrupted, and the voltage refresh transistor circuit therein is activated.

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