A method and system for generating a grid-connected converter XOR modulation signal with dead zone

Abstract

The present invention discloses a method and system for generating a dead-zone XOR modulation signal for a grid-connected converter, and relates to the field of power electronics technology. The method generates a shadow signal corresponding to the original signal while a controller generates an original SPWM signal. By adjusting the carrier phase and the modulation wave amplitude, the phase and pulse width of the XOR logic signal generated by the shadow signal can be changed, thereby generating an XOR sinusoidal pulse width modulation signal with a double-sided dead zone, avoiding direct short circuit caused by simultaneous opening of power switch devices in the circuit, improving the reliability of systems such as modular series-parallel grid-connected converters, and having the advantages of being easy to implement, strong versatility, and not increasing hardware.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronics, and in particular to a method and system for generating a dead-zone XOR modulation signal of a grid-connected converter. Background Art

[0002] The statements in this section merely provide background information related to the present invention and do not necessarily constitute prior art.

[0003] Grid-connected converters are widely used in renewable energy power generation, electric vehicles, energy storage systems, etc. to complete the task of power conversion. Compared with traditional two-level grid-connected converters, modular series-parallel grid-connected converters have the advantages of small output harmonics, high withstand voltage, low cost of passive components and small size. However, modular series-parallel grid-connected converters need to generate multi-channel carrier phase-shifted sinusoidal pulse width modulation (SPWM) signals and their XOR logic signals to control the opening and closing of additional fully controlled power switching devices. To avoid short circuits, it is necessary to add a dead zone to the XOR signal, that is, the time when the two switches are turned off at the same time.

[0004] The traditional dead zone adding method usually uses software or hardware to delay the triggering moment of the driving pulse edge, and does not involve XOR logic. However, to generate an XOR logic signal with a dead zone, it is necessary to leave a dead zone time at both edges, which not only requires delaying the triggering of the rising edge of the XOR logic signal, but also requires advancing the triggering of the falling edge of the XOR logic signal. According to the causal nature of the signal in reality, it is impossible to process it in advance before the falling edge signal is triggered. Therefore, it is impossible to use the traditional edge trigger delay method to set the dead zone time. It is difficult to perform an XOR logic operation on the SPWM signal with a phase shift of the carrier first, and then add a dead zone time to the obtained XOR logic signal. Therefore, how the grid-connected converter generates an XOR sinusoidal pulse width modulation signal with a dead zone has become a problem to be solved in the prior art. Summary of the invention

[0005] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a method and system for generating a grid-connected converter XOR modulation signal with dead zone, and a shadow signal corresponding to the original signal is generated while the controller generates the original SPWM signal. By adjusting the carrier phase and the modulation wave amplitude, the phase and pulse width of the XOR logic signal generated by the shadow signal can be changed, thereby generating an XOR sinusoidal pulse width modulation signal with double-sided dead zone.

[0006] In order to achieve the above object, the present invention is implemented through the following technical solutions:

[0007] A first aspect of the present invention provides a method for generating a dead-zone XOR modulation signal of a grid-connected converter, comprising the following steps:

[0008] Acquire a modulation signal and a carrier signal, and generate an original sinusoidal pulse width modulation signal according to a signal modulation strategy;

[0009] Determine the duty cycle state of the original sinusoidal pulse width modulation signal;

[0010] The carrier phase of the original sinusoidal pulse width modulation signal is adjusted according to the judgment result to obtain a shadow carrier signal;

[0011] The modulation wave amplitude of the original sinusoidal pulse width modulation signal is adjusted according to the judgment result to obtain a shadow modulation signal;

[0012] Using the shadow carrier signal and the shadow modulation signal to perform signal modulation to generate a shadow sinusoidal pulse width modulation signal;

[0013] An exclusive OR logic operation is performed on the shadow sinusoidal pulse width modulation signal to obtain an exclusive OR logic signal.

[0014] Furthermore, the acquired modulation signal and carrier signal include two carrier signals and one modulation signal.

[0015] Furthermore, the duty cycle D of the original sinusoidal pulse width modulation signal is divided into: and Three states.

[0016] Furthermore, the carrier phase of the original sinusoidal pulse width modulation signal is adjusted, including two processing modes of carrier phase advance or carrier phase lag, wherein carrier phase advance causes the phase of the shadow sinusoidal pulse width modulation signal to advance, and carrier phase lag causes the phase of the shadow sinusoidal pulse width modulation signal to lag, thereby changing the phase of the generated XOR logic signal.

[0017] Furthermore, adjusting the modulation wave amplitude of the original sinusoidal pulse width modulation signal includes two processing modes: increasing or decreasing the modulation wave amplitude, wherein increasing the modulation wave amplitude increases the pulse width of the shadow sinusoidal pulse width modulation signal, and decreasing the modulation wave amplitude reduces the pulse width of the shadow sinusoidal pulse width modulation signal, thereby changing the pulse width of the generated XOR logic signal.

[0018] A second aspect of the present invention provides a system for generating a dead-zone XOR modulation signal of a grid-connected converter, comprising:

[0019] A signal acquisition module is configured to acquire a modulation signal and a carrier signal, and generate an original sinusoidal pulse width modulation signal according to a signal modulation strategy;

[0020] A state determination module is configured to determine a duty cycle state of the original sinusoidal pulse width modulation signal;

[0021] A phase adjustment module is configured to adjust the carrier phase of the original sinusoidal pulse width modulation signal according to the judgment result to obtain a shadow carrier signal;

[0022] an amplitude adjustment module, configured to adjust the modulation wave amplitude of the original sinusoidal pulse width modulation signal according to the judgment result to obtain a shadow modulation signal;

[0023] A signal modulation module is configured to perform signal modulation using a shadow carrier signal and a shadow modulation signal to generate a shadow sinusoidal pulse width modulation signal;

[0024] The signal generating module is configured to perform an XOR logic operation on the shadow sinusoidal pulse width modulation signal to obtain an XOR logic signal.

[0025] Furthermore, in the signal acquisition module, the acquired modulation signal and carrier signal include two carrier signals and one modulation signal.

[0026] Furthermore, the state judgment module includes a duty cycle state division module, which divides the duty cycle D of the original sinusoidal pulse width modulation signal into and Three states.

[0027] Furthermore, in the phase adjustment module, the carrier phase of the original sinusoidal pulse width modulation signal is adjusted, including two processing modes of carrier phase advance or lag, wherein the carrier phase advance makes the phase of the shadow sinusoidal pulse width modulation signal advance, and the carrier phase lag makes the phase of the shadow sinusoidal pulse width modulation signal lag, thereby changing the phase of the generated XOR logic signal.

[0028] Furthermore, in the amplitude adjustment module, the modulation wave amplitude of the original sinusoidal pulse width modulation signal is adjusted, including two processing modes of increasing or decreasing the modulation wave amplitude, wherein increasing the modulation wave amplitude increases the pulse width of the shadow sinusoidal pulse width modulation signal, and decreasing the modulation wave amplitude reduces the pulse width of the shadow sinusoidal pulse width modulation signal, thereby changing the pulse width of the generated XOR logic signal.

[0029] One or more of the above technical solutions have the following beneficial effects:

[0030] The present invention discloses a method and system for generating a grid-connected converter with a dead zone XOR modulation signal. When a controller generates an original SPWM signal, a shadow signal corresponding to the original signal is generated. By adjusting the carrier phase and the modulation wave amplitude, the phase and pulse width of the XOR logic signal generated by the shadow signal can be changed, thereby generating an XOR sinusoidal pulse width modulation signal with a double-sided dead zone, avoiding the direct short circuit caused by the simultaneous opening of power switching devices in the circuit, improving the reliability of systems such as modular series-parallel grid-connected converters, and having the advantages of being easy to implement, strong versatility, and not increasing hardware.

[0031] The method of the present invention does not require additional hardware equipment or increase costs, is easy to implement, convenient to apply, and has versatility. It can not only realize the delayed triggering of the rising edge of the XOR logic signal, but also realize the early triggering of the falling edge, thereby generating an XOR sinusoidal pulse width modulation signal with a double-sided dead zone.

[0032] Advantages of additional aspects of the present invention will be given in part in the following description, and in part will become obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings in the specification, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0034] Figure 1 This is a basic structural diagram of a symmetrical half-bridge submodule with three fully-controlled switches in Embodiment 1 of the present invention;

[0035] Figure 2 It is a basic structural diagram of a modular series-parallel grid-connected converter bridge arm composed of n three-fully-controlled switch symmetrical half-bridge sub-modules in the first embodiment of the present invention;

[0036] FIG3( a ) is a schematic diagram of a switching state of adjacent submodules of a bridge arm of a modular series-parallel grid-connected converter composed of three fully-controlled switch symmetrical half-bridge submodules in Embodiment 1 of the present invention;

[0037] FIG3( b ) is a schematic diagram of a switching state of adjacent submodules of a bridge arm of a modular series-parallel grid-connected converter composed of three fully-controlled switch symmetrical half-bridge submodules in Embodiment 1 of the present invention;

[0038] FIG3( c ) is a schematic diagram of a switching state of adjacent submodules of a bridge arm of a modular series-parallel grid-connected converter composed of three fully-controlled switch symmetrical half-bridge submodules in Embodiment 1 of the present invention;

[0039] FIG3( d ) is a schematic diagram of a switching state of adjacent submodules of a bridge arm of a modular series-parallel grid-connected converter composed of three fully-controlled switch symmetrical half-bridge submodules in Embodiment 1 of the present invention;

[0040] Figure 4 It is a schematic diagram of the carrier phase-shift pulse width modulation strategy of the existing modular series-parallel grid-connected converter;

[0041] Figure 5 It is a schematic diagram of a method for generating control signals of switches of an existing modular series-parallel grid-connected converter;

[0042] FIG6( a ) is a schematic diagram of the triggering conditions of gXOR when the gi duty ratio D∈[0,1 / 3] in the first embodiment of the present invention;

[0043] FIG6( b ) is a schematic diagram of the triggering conditions of gXOR when the gi duty ratio D∈(1 / 3, 2 / 3) in the first embodiment of the present invention;

[0044] FIG6( c ) is a schematic diagram of the triggering conditions of gXOR when the gi duty ratio D∈[2 / 3,1] in the first embodiment of the present invention;

[0045] Figure 7 Schematic diagram of the modulation strategy of an XOR sinusoidal pulse width modulation signal with a double-sided dead zone in the first embodiment of the present invention;

[0046] Figure 8 Schematic diagram of a method for generating gate drive signals for switches of a modular series-parallel grid-connected converter in Embodiment 1 of the present invention;

[0047] Fig. 9 Schematic diagram of a method for generating a target signal gXOR* in a switching cycle with different duty ratios of gi and g(i+1) in Embodiment 1 of the present invention;

[0048] Fig.10 This is a simulation waveform diagram of an XOR logic signal with a bilateral dead zone generated in the first embodiment of the present invention. DETAILED DESCRIPTION

[0049] It should be noted that the following detailed descriptions are exemplary and are intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs.

[0050] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "include" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or their combinations;

[0051] Embodiment 1:

[0052] Embodiment 1 of the present invention provides a method for generating a dead-zone XOR modulation signal for a grid-connected converter. Taking a modular series-parallel grid-connected converter composed of three fully-controlled switch symmetrical half-bridge submodules as an example, the basic structure of the three fully-controlled switch symmetrical half-bridge submodules is as follows: Figure 1 As shown, it includes a conventional half-bridge module (101) and an additional bidirectional fully controlled power switch device S1 * The conventional half-bridge module (101) is consistent with the prior art, and each of the upper and lower bridge arms has a fully controlled power switch device: S 1u and S 1d Each fully controlled power switch device is connected in anti-parallel with a diode. Two large-capacity capacitors are connected in series on the DC side: C dc1u and C dc1d , the connection point between the two is the DC midpoint; the two ports formed by the upper and lower bridge arm connection points and the DC midpoint are the hubs for the symmetrical half-bridge module to convert power with the external power grid. More specifically, S 1u The drain and C dc1u The positive electrode of C dc1u The negative electrode and C dc1d The positive electrode of C dc1d The negative electrode and S 1d The source of S 1d The drain and S 1u The source of S1 is connected. * Similarly, a diode is connected in anti-parallel, and four diodes are set around it to realize the bidirectional flow of current. The four diodes are the first diode, the second diode, the third diode and the fourth diode. The cathode of the first diode is connected to the cathode of the second diode, the anode of the second diode is connected to the cathode of the third diode, the anode of the third diode is connected to the anode of the fourth diode, and the cathode of the fourth diode is connected to the anode of the first diode. S1 * The source of S1 is connected to the anode of the third diode. * The drain of the first diode is connected to the cathode of the first diode. dc1u The cathode of the first diode is also connected to S 1d The drain of the controller is connected to realize the connection with the half-bridge module (101). The external controller outputs an SPWM signal to control the S 1u With S 1d When the module is working, S 1u With S 1d The switch states are complementary, and an appropriate dead time is set when the state changes. The basic structure of the bridge arm of the grid-connected converter is composed of a modular series-parallel connection of n three-fully-controlled switch symmetrical half-bridge sub-modules, such as Figure 2 As shown, taking the first module and the second module in series as an example, the C of the first module dc1uThe negative terminal of the second module is connected to the S 2u The source of the first module is connected to the anode of the second diode of the second module. dc2u The negative pole of the first module is connected to the negative pole of the second module, thereby realizing the series connection of the first module and the second module, and so on to realize the series connection of all modules. Among them, the four modes of realizing voltage balancing by connecting the diagonal capacitors of two adjacent symmetrical half-bridge sub-modules in parallel are shown in Figure 3(a), Figure 3(b), Figure 3(c) and Figure 3(d). In Figure 3(a) and Figure 3(b), when the switch S iu Disconnect, switch S (i+1)u When closed, the bidirectional switch S is triggered i * , capacitor C dcid and C dc(i+1)u When the switch S is connected in parallel, the voltages at both ends converge to achieve voltage balance. iu Close, switch S (i+1)u When disconnected, open the bidirectional switch S i * , capacitor C dciu and C dc(i+1)d When the switch S is connected in parallel, the voltages at both ends converge to achieve voltage balance. iu With switch S (i+1)u When the state is XOR, the bidirectional switch S is turned on i * , so that the diagonal capacitors of two adjacent sub-modules are connected in parallel to achieve voltage balance.

[0053] Figure 4 The figure shows the carrier phase shift pulse width modulation strategy (400) of the switch state of the submodule of the existing modular series-parallel grid-connected converter. i and c (i+1) is a bipolar triangular carrier signal with the same and fixed frequency, c i Relative c (i+1) The phase leads by 120 degrees, the amplitude is the same, the amplitude ∈ [-1, 1]; the modulation signal m sin is a sine wave with fixed phase, frequency and amplitude. Without considering overmodulation, the amplitude is ∈ [-1, 1]. sin Respectively with c i and c (i+1) Compare and generate SPWM signal g i and g (i+1) . g i and g (i+1) It has two states, 0 and 1. When the amplitude of the modulated signal is less than the amplitude of the carrier signal at any time, g i =0; at any moment when the modulation signal amplitude is greater than the carrier signal amplitude, g i =1. g i= 0, the SPWM signal is set to low level, and the fully controlled power switch device is turned off; g i =1, the SPWM signal is set to high level, and the fully controlled power switch device is turned on; the duty cycle D is defined as the g i =1 to the total switching cycle time, D∈[0,1], and the corresponding switching cycle g i With g (i+1) The duty cycle is equal.

[0054] Figure 5 FIG. 1 is a schematic diagram of a method for generating drive signals of each submodule in the prior art. i Control switch S iu The state of g is converted by the inversion logic operation module (501). i After inversion, it is used to control the switch S id The state of SPWM signal g (i+1) Control switch S (i+1)u The state of g is converted by the inversion logic operation module (501). (i+1) After inversion, it is used to control the switch S (i+1)d state; g i and g (i+1) The XOR logic signal g is obtained by the XOR logic operation module (502) XOR , to control the bidirectional switch S i * In practical applications, S iu With S id Dead time needs to be set to avoid loop short circuit. i * Cannot be used with S iu and S (i+1)d At the same time, g XOR Need to be with g i and g (i+1) Set a suitable dead time between XOR The trigger conditions have timing changes and cannot be achieved simply through the commonly used delay technology.

[0055] Based on the problems existing in the above-mentioned prior art, this embodiment generates a shadow signal corresponding to the original signal, and by adjusting the carrier phase and the modulation wave amplitude, the phase and pulse width of the XOR logic signal generated by the shadow signal can be changed, thereby generating an XOR sinusoidal pulse width modulation signal with a double-sided dead zone, and specifically includes the following steps:

[0056] Step 1, obtain the modulation signal and the carrier signal, and generate the original sinusoidal pulse width modulation signal according to the signal modulation strategy. The obtained modulation signal and carrier signal include two carrier signals c i* and c (i+1) * and a modulation signal m sin * .

[0057] Step 2, determine the duty cycle state of the original sinusoidal pulse width modulation signal. Different modulation strategies need to be changed according to different duty cycles to ensure that the edge sequence is not chaotic. Therefore, the duty cycle D of the original sinusoidal pulse width modulation signal is divided into and There are three states, namely D∈[0,1 / 3], D∈(1 / 3,2 / 3) and D∈(2 / 3,1].

[0058] More specifically, FIG6(a) shows g i Duty cycle D∈[0,1 / 3]g XOR The triggering condition. In any switching cycle, g XOR The first rising edge of the pulse is i The rising edge is triggered by g i The falling edge triggers; g XOR The second rising edge of the pulse is g (i+1) The rising edge is triggered by g (i+1) The falling edge of .

[0059] Figure 6(b) shows g i Duty cycle D∈(1 / 3,2 / 3)g XOR The triggering condition of g XOR The first rising edge of the pulse is i The rising edge is triggered by g (i+1) The rising edge triggers; g XOR The second rising edge of the pulse is g i The falling edge is triggered by g (i+1) The falling edge of .

[0060] Figure 6(c) shows g i Duty cycle D∈(2 / 3,1]g XOR The triggering condition. In any switching cycle, g XOR The first rising edge of the pulse is (i+1) The falling edge is triggered by g (i+1) The rising edge triggers; g XOR The second rising edge of the pulse is i The falling edge is triggered by g i The rising edge of .

[0061] Step 3: adjust the carrier phase of the original sinusoidal pulse width modulation signal according to the judgment result to obtain a shadow carrier signal.

[0062] Among them, adjusting the carrier phase of the original sinusoidal pulse width modulation signal includes two processing modes: carrier phase advance or carrier phase lag. Among them, carrier phase advance makes the phase of the shadow sinusoidal pulse width modulation signal advance, and carrier phase lag makes the phase of the shadow sinusoidal pulse width modulation signal lag, thereby changing the phase of the generated XOR logic signal.

[0063] Step 4: adjust the modulation wave amplitude of the original sinusoidal pulse width modulation signal according to the judgment result to obtain a shadow modulation signal.

[0064] Among them, adjusting the modulation wave amplitude of the original sinusoidal pulse width modulation signal includes two processing modes of increasing or decreasing the modulation wave amplitude. Increasing the modulation wave amplitude increases the pulse width of the shadow sinusoidal pulse width modulation signal, and decreasing the modulation wave amplitude reduces the pulse width of the shadow sinusoidal pulse width modulation signal, thereby changing the pulse width of the generated XOR logic signal.

[0065] Step 5: Use the shadow carrier signal and the shadow modulation signal to perform signal modulation to generate a shadow sinusoidal pulse width modulation signal.

[0066] Step 6, performing an XOR logic operation on the shadow sinusoidal pulse width modulation signal to obtain an XOR logic signal.

[0067] In a specific embodiment, Figure 7 The figure shows the modulation strategy for generating an XOR sinusoidal pulse width modulation signal with double-sided dead zone proposed in this embodiment. This method sets up shadow signals based on the existing modulation technology, which are two carrier signals c i * and c (i+1) * , a modulation signal m sin * .c i , c (i+1) , c i * and c (i+1) * is a bipolar triangular carrier signal with the same and fixed frequency and amplitude, and the amplitude is ∈[-1,1]; where c i Relative c (i+1) Phase advance 120 degrees, c i With c i * The initial phase is the same, c (i+1) With c (i+1) * The initial phase is the same. The modulation signal msin , m sin * Initially, it is a sine wave with the same phase, frequency and amplitude, and the amplitude is ∈ [-1, 1]; where m sin For use with c i and c (i+1) Compare and generate the original SPWM signal g i and g (i+1) ;m sin * For use with c i * and c (i+1) * Comparison produces the shadow SPWM signal g i * and g (i+1) * , for g i * and g (i+1) * Perform XOR operation to get the target signal g XOR * By adjusting g i * and g (i+1) * The modulation wave amplitude and carrier phase can change g i * and g (i+1) * Pulse width and phase, and then freely determine the XOR logic signal g without affecting the original signal XOR * The pulse width and phase of the target signal. Let the target signal g XOR * The rising and falling edges are placed on the original signal to generate the exclusive OR logic signal g XOR Within the pulse, the delayed triggering of the rising edge and the early triggering of the falling edge of the original XOR logic signal are equivalently realized, thereby generating an XOR sinusoidal pulse width modulation signal with a double-side dead zone.

[0068] The specific modulation process is as follows: Figure 8 As shown, the modulation signal m sin Respectively with the carrier signal c i and c (i+1) The original SPWM signal g is generated by the signal modulation strategy (400) i and g (i+1) By judging the original SPWM duty cycle state, the carrier signal c is adjusted according to the duty cycle state. i and c (i+1) The phase (802) produces c i * and c(i+1) * , or adjust the modulation signal m sin The amplitude (803) produces m sin * , m sin * Respectively with c i * and c (i+1) * After signal modulation (400), a shadow SPWM signal g is generated. i * and g (i+1) * , g i * and g (i+1) * After XOR logic operation, the XOR logic signal g is obtained XOR * (Target signal).

[0069] In a specific implementation, the carrier phase of the original sinusoidal pulse width modulation signal is adjusted according to the judgment result to obtain the shadow carrier signal, and the modulation wave amplitude of the original sinusoidal pulse width modulation signal is adjusted according to the judgment result to obtain the shadow modulation signal. The specific process is as follows: Fig. 9 As shown:

[0070] Fig. 9 The first part shows that in g i With g (i+1) The target signal g is generated in the switching cycle with duty cycle D∈[0,1 / 3] XOR * Method. i * and c (i+1) * The phase is reset to c i and c (i+1) The phase is the same, and the modulation signal m is quantitatively reduced according to the dead time requirement sin * The amplitude of the modulated shadow signal g i * and g (i+1) * The pulse width is narrowed, and the g i * and g (i+1) * Perform an XOR logic operation to obtain g in this case XOR * , that is, an XOR logic signal with bilateral dead zone.

[0071] Fig. 9 The second part shows that in gi With g (i+1) The target signal g is generated in the switching cycle with duty cycle D∈(1 / 3,2 / 3) XOR * The modulation signal m sin * The amplitude is reset to the same value as m sin The amplitude is the same, and the quantitative hysteresis c is required according to the dead time i * phase, and quantitatively advance c (i+1) * The phase of the modulated shadow signal g i * and g (i+1) * The phase shifts of g i * and g (i+1) * Perform an XOR logic operation to obtain g in this case XOR * , that is, an XOR logic signal with bilateral dead zone.

[0072] Fig. 9 The third part shows that in g i With g (i+1) The target signal g is generated in the switching cycle with duty cycle D∈[2 / 3,1] XOR * Method. i * and c (i+1) * The phase is reset to c i and c (i+1) The phase is the same, and the modulation signal m is quantitatively increased according to the dead time requirement. sin * The amplitude of the modulated shadow signal g i * and g (i+1) * The pulse width is widened, for g i * and g (i+1) * Perform an XOR logic operation to obtain g in this case XOR * , that is, an XOR logic signal with bilateral dead zone.

[0073] Fig.10 The figure shows the simulation waveform of the XOR logic signal with double-sided dead zone generated by the method of this embodiment. The simulation model is built by MATLAB / Simulink, and the XOR logic signal g generated by this embodiment is XOR* With g i and g (i+1) Directly perform logical operations to generate the XOR signal g XOR By comparison, it can be seen that under each trigger condition, the method of this embodiment can effectively generate an XOR logic signal with a double-side dead zone.

[0074] Embodiment 2:

[0075] Embodiment 2 of the present invention provides a system for generating a dead-zone XOR modulation signal of a grid-connected converter, comprising:

[0076] The signal acquisition module is configured to acquire the modulation signal and the carrier signal, and generate the original sinusoidal pulse width modulation signal according to the signal modulation strategy. In the signal acquisition module, the acquired modulation signal and the carrier signal include two carrier signals and one modulation signal.

[0077] A state determination module is configured to determine a duty cycle state of the original sinusoidal pulse width modulation signal;

[0078] A phase adjustment module is configured to adjust the carrier phase of the original sinusoidal pulse width modulation signal according to the judgment result to obtain a shadow carrier signal;

[0079] an amplitude adjustment module, configured to adjust the modulation wave amplitude of the original sinusoidal pulse width modulation signal according to the judgment result to obtain a shadow modulation signal;

[0080] A signal modulation module is configured to perform signal modulation using a shadow carrier signal and a shadow modulation signal to generate a shadow sinusoidal pulse width modulation signal;

[0081] The signal generating module is configured to perform an XOR logic operation on the shadow sinusoidal pulse width modulation signal to obtain an XOR logic signal.

[0082] In a specific implementation, the state judgment module includes a duty cycle state division module, which divides the duty cycle D of the original sinusoidal pulse width modulation signal into: and Three states.

[0083] In the phase adjustment module, the carrier phase of the original sinusoidal pulse width modulation signal is adjusted, including two processing modes: carrier phase advance or carrier phase lag. The carrier phase advance makes the shadow sinusoidal pulse width modulation signal phase advance, and the carrier phase lag makes the shadow sinusoidal pulse width modulation signal phase lag, thereby changing the phase of the generated XOR logic signal.

[0084] In the amplitude adjustment module, the modulation wave amplitude of the original sinusoidal pulse width modulation signal is adjusted, including two processing modes: increasing or decreasing the modulation wave amplitude. Increasing the modulation wave amplitude increases the pulse width of the shadow sinusoidal pulse width modulation signal, and decreasing the modulation wave amplitude reduces the pulse width of the shadow sinusoidal pulse width modulation signal, thereby changing the pulse width of the generated XOR logic signal.

[0085] The steps involved in the above embodiment 2 correspond to those in embodiment 1. For the specific implementation method, please refer to the relevant description part of embodiment 1.

[0086] Those skilled in the art should understand that the modules or steps of the present invention described above can be implemented by a general-purpose computer device, or alternatively, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. The present invention is not limited to any specific combination of hardware and software.

[0087] Although the above describes the specific implementation mode of the present invention in conjunction with the accompanying drawings, it is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art on the basis of the technical solution of the present invention without creative work are still within the scope of protection of the present invention.

Claims

1. A method for generating a dead-zone XOR modulation signal for a grid-connected converter, characterized in that: The following steps are involved: Acquire a modulation signal and a carrier signal, and generate an original sinusoidal pulse width modulation signal according to a signal modulation strategy; Determine the duty cycle state of the original sinusoidal pulse width modulation signal; The duty cycle D of the original sinusoidal pulse width modulation signal is divided into: and Three states; Different modulation strategies need to be changed according to different duty cycles; The carrier phase of the original sinusoidal pulse width modulation signal is adjusted according to the judgment result to obtain a shadow carrier signal; The modulation wave amplitude of the original sinusoidal pulse width modulation signal is adjusted according to the judgment result to obtain a shadow modulation signal; Using the shadow carrier signal and the shadow modulation signal to perform signal modulation to generate a shadow sinusoidal pulse width modulation signal; An exclusive OR logic operation is performed on the shadow sinusoidal pulse width modulation signal to obtain an exclusive OR logic signal.

2. The method for generating a grid-connected converter with a dead-zone XOR modulation signal according to claim 1, characterized in that: The acquired modulation signals and carrier signals include two carrier signals and one modulation signal.

3. The method for generating a grid-connected converter with a dead-zone XOR modulation signal according to claim 1, characterized in that: Adjusting the carrier phase of the original sinusoidal pulse width modulation signal includes two processing modes: carrier phase advance or carrier phase lag. The carrier phase advance makes the shadow sinusoidal pulse width modulation signal phase advance, and the carrier phase lag makes the shadow sinusoidal pulse width modulation signal phase lag, thereby changing the phase of the generated XOR logic signal.

4. The method for generating a grid-connected converter with a dead-zone XOR modulation signal according to claim 1, characterized in that: Adjusting the modulation wave amplitude of the original sinusoidal pulse width modulation signal includes two processing modes: increasing or decreasing the modulation wave amplitude. Increasing the modulation wave amplitude increases the pulse width of the shadow sinusoidal pulse width modulation signal, while decreasing the modulation wave amplitude reduces the pulse width of the shadow sinusoidal pulse width modulation signal, thereby changing the pulse width of the generated XOR logic signal.

5. A system for generating a dead-zone XOR modulation signal for a grid-connected converter, characterized in that: include: A signal acquisition module is configured to acquire a modulation signal and a carrier signal, and generate an original sinusoidal pulse width modulation signal according to a signal modulation strategy; A state determination module is configured to determine a duty cycle state of the original sinusoidal pulse width modulation signal; The duty cycle D of the original sinusoidal pulse width modulation signal is divided into: and Three states; Different modulation strategies need to be changed according to different duty cycles; A phase adjustment module is configured to adjust the carrier phase of the original sinusoidal pulse width modulation signal according to the judgment result to obtain a shadow carrier signal; an amplitude adjustment module, configured to adjust the modulation wave amplitude of the original sinusoidal pulse width modulation signal according to the judgment result to obtain a shadow modulation signal; A signal modulation module is configured to perform signal modulation using a shadow carrier signal and a shadow modulation signal to generate a shadow sinusoidal pulse width modulation signal; The signal generating module is configured to perform an XOR logic operation on the shadow sinusoidal pulse width modulation signal to obtain an XOR logic signal.

6. The system for generating a grid-connected converter with a dead-zone XOR modulation signal according to claim 5, characterized in that: In the signal acquisition module, the acquired modulation signals and carrier signals include two carrier signals and one modulation signal.

7. The system for generating a grid-connected converter with a dead-zone XOR modulation signal according to claim 5, characterized in that: In the phase adjustment module, the carrier phase of the original sinusoidal pulse width modulation signal is adjusted, including two processing modes: carrier phase advance or carrier phase lag. The carrier phase advance makes the shadow sinusoidal pulse width modulation signal phase advance, and the carrier phase lag makes the shadow sinusoidal pulse width modulation signal phase lag, thereby changing the phase of the generated XOR logic signal.

8. The system for generating a grid-connected converter with a dead-zone XOR modulation signal according to claim 5, characterized in that: In the amplitude adjustment module, the modulation wave amplitude of the original sinusoidal pulse width modulation signal is adjusted, including two processing modes: increasing or decreasing the modulation wave amplitude. Increasing the modulation wave amplitude increases the pulse width of the shadow sinusoidal pulse width modulation signal, and decreasing the modulation wave amplitude reduces the pulse width of the shadow sinusoidal pulse width modulation signal, thereby changing the pulse width of the generated XOR logic signal.

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