Quantum circuit mapping method, device and electronic device

Abstract

The present disclosure provides a quantum circuit mapping method, device and electronic device, which relates to the field of quantum computing technology, and specifically to the field of quantum circuit technology. The specific implementation scheme is: based on the arrangement structure information of quantum bits on the quantum chip, obtain the coupling graph and node index of the quantum chip; obtain the interaction graph of the first logical quantum circuit precompiled on the quantum chip; search for the first subgraph isomorphic to the interaction graph in the reduced search space of the coupling graph, and the reduced search space includes a set of nodes in the coupling graph whose distance from the generation set does not exceed a specified distance; based on the node index, use the brick array structure of the coupling graph to perform a translation operation on the first subgraph on the coupling graph to match the generation set, and obtain a second subgraph; determine the first mapping scheme corresponding to each subgraph in the subgraph set; based on the fidelity of the physical quantum gate on the quantum chip, determine the target mapping scheme from the first mapping scheme corresponding to the subgraph set.

Description

Technical Field

[0001] The present disclosure relates to the field of quantum computing technology, in particular to the field of quantum circuit technology, and specifically to a quantum circuit mapping method, device and electronic device. Background Art

[0002] Quantum circuit mapping is an important problem in quantum computing and plays an important role in alleviating the impact of noise on quantum computing. It involves selecting a set of physical quantum bits in a quantum processor (also known as a quantum chip) to construct quantum gates to execute a given logical quantum circuit.

[0003] In essence, the quantum circuit mapping problem is about determining the mapping relationship between the quantum bits (or quantum gates) in the logical quantum circuit and the physical quantum bits (or quantum gates) in the quantum processor. Due to the limitations of existing micro-nano processing and measurement and control technologies, the performance of the quantum bits (or quantum gates) on the quantum processor varies.

[0004] Generally, quantum circuit mapping should avoid quantum bits and quantum gates with poor quality, and select appropriate quantum bits and quantum gates to execute quantum algorithms to reduce errors that may occur during the operation of quantum circuits and obtain high-fidelity computing results. Summary of the invention

[0005] The present disclosure provides a quantum circuit mapping method, device and electronic device.

[0006] According to a first aspect of the present disclosure, a quantum circuit mapping method is provided, comprising:

[0007] Based on the arrangement structure information of the quantum bits on the quantum chip, a coupling graph of the quantum chip and a node index of the coupling graph are obtained; and an interaction graph of a first logic quantum circuit precompiled onto the quantum chip is obtained; the arrangement structure information indicates that the quantum bits on the quantum chip are arranged in a brick array structure, and the node index indicates a mapping relationship between the node position coordinates of the quantum bits and the node labels, and the brick array structure is formed by stacking a first type of brick structure and a second type of brick structure, and the second type of brick structure is stacked between two adjacent first type of brick structures;

[0008] searching for a first subgraph isomorphic to the interaction graph in a reduced search space of the coupling graph, the reduced search space comprising a set of nodes in the coupling graph whose distances to a spanning set do not exceed a specified distance, the specified distance being greater than or equal to a radius of the interaction graph, and the spanning set covering the coupling graph under a matching translation operation;

[0009] Based on the node index, using the brick array structure of the coupling graph, a translation operation matching the generation set is performed on the first subgraph on the coupling graph to obtain a second subgraph isomorphic to the interaction graph;

[0010] Determine each subgraph in the subgraph collection Figure 1 a corresponding first mapping scheme, wherein the first mapping scheme is a mapping scheme from the first logic quantum circuit to the quantum chip, and the subgraph set includes the first subgraph and the second subgraph;

[0011] Based on the fidelity of the physical quantum gates on the quantum chip, a target mapping scheme from the first logical quantum circuit to the quantum chip is determined from the first mapping schemes corresponding to the subgraph set.

[0012] According to a second aspect of the present disclosure, a quantum circuit mapping device is provided, comprising:

[0013] An acquisition module is used to acquire a coupling graph of the quantum chip and a node index of the coupling graph based on the arrangement structure information of the quantum bits on the quantum chip; and to acquire an interaction graph of a first logic quantum circuit precompiled onto the quantum chip; the arrangement structure information indicates that the quantum bits on the quantum chip are arranged in a brick array structure, and the node index indicates a mapping relationship between the node position coordinates of the quantum bits and the node labels, and the brick array structure is formed by stacking a first type of brick structure and a second type of brick structure, and the second type of brick structure is stacked between two adjacent first type of brick structures;

[0014] A search module, configured to search a first subgraph isomorphic to the interaction graph in a reduced search space of the coupling graph, the reduced search space comprising a set of nodes in the coupling graph whose distances from a generated set do not exceed a specified distance, the specified distance being greater than or equal to a radius of the interaction graph, and the generated set covering the coupling graph under a matching translation operation;

[0015] A translation operation module, configured to perform a translation operation on the first subgraph on the coupling graph that matches the generated set based on the node index and utilize the brick array structure of the coupling graph to obtain a second subgraph that is isomorphic to the interaction graph;

[0016] The first determination module is used to determine each subgraph in the subgraph set. Figure 1 a corresponding first mapping scheme, wherein the first mapping scheme is a mapping scheme from the first logic quantum circuit to the quantum chip, and the subgraph set includes the first subgraph and the second subgraph;

[0017] The second determination module is used to determine a target mapping scheme from the first logical quantum circuit to the quantum chip from the first mapping scheme corresponding to the subgraph set based on the fidelity of the physical quantum gate on the quantum chip.

[0018] According to a third aspect of the present disclosure, there is provided an electronic device, including:

[0019] at least one processor; and

[0020] a memory communicatively connected to at least one processor; wherein,

[0021] The memory stores instructions that can be executed by at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform any method in the first aspect.

[0022] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause a computer to execute any one of the methods in the first aspect.

[0023] According to a fifth aspect of the present disclosure, a computer program product is provided, comprising a computer program, which implements any one of the methods in the first aspect when executed by a processor.

[0024] The technology disclosed in the present invention solves the problem of low mapping efficiency of quantum circuits on quantum chips with brick structures in related technologies, and can improve the mapping efficiency of quantum circuits on quantum chips with brick structures.

[0025] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure.

[0027] Figure 1 is a flowchart of a quantum circuit mapping method according to the first embodiment of the present disclosure;

[0028] Figure 2 Schematic diagram of the structure of a quantum chip with a coupled diagram of a brick array structure;

[0029] Figure 3 It is a schematic diagram of the node numbering of quantum bits;

[0030] Figure 4 It is a schematic diagram of the structure of an example of a logic quantum circuit;

[0031] Figure 5 It is a schematic diagram of the structure of an interaction diagram of an example logic quantum circuit;

[0032] Figure 6 is a schematic diagram of the structure of a coupling diagram of an example quantum chip;

[0033] Figure 7 It is a performance operation diagram of different subgraph matching schemes;

[0034] Figure 8 It is a performance operation diagram of different circuit mapping schemes;

[0035] Fig. 9 is a schematic structural diagram of a quantum circuit mapping device according to a second embodiment of the present disclosure;

[0036] Fig.10 is a schematic block diagram of an example electronic device for implementing an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0038] First embodiment

[0039] like Figure 1 As shown, the present disclosure provides a quantum circuit mapping method, comprising the following steps:

[0040] Step S101: Based on the arrangement structure information of the quantum bits on the quantum chip, obtain the coupling graph of the quantum chip and the node index of the coupling graph; and obtain the interaction graph of the first logic quantum circuit precompiled onto the quantum chip; the arrangement structure information indicates that the quantum bits on the quantum chip are arranged in a brick array structure, and the node index indicates the mapping relationship between the node position coordinates of the quantum bit and the node label, and the brick array structure is formed by stacking a first type of brick structure and a second type of brick structure, and the second type of brick structure is stacked between two adjacent first type of brick structures.

[0041] Among them, the coupling diagram is used to characterize the physical connection between quantum bits on the quantum chip, the coupling diagram is a brick array structure, and the interaction diagram is used to characterize the interaction between quantum bits involved in the execution process of the first logical quantum circuit.

[0042] In this embodiment, the quantum circuit mapping method relates to the field of quantum computing technology, and in particular to the field of quantum circuit technology. It can be widely used in quantum circuit mapping scenarios, and has important significance for the practical applications of quantum computing, such as code breaking, drug development, and machine learning. The quantum circuit mapping method of the disclosed embodiment can be performed by the quantum circuit mapping device of the disclosed embodiment. The quantum circuit mapping device of the disclosed embodiment can be configured in any electronic device to perform the quantum circuit mapping method of the disclosed embodiment.

[0043] Quantum computing is a new computing model that uses the characteristics of quantum mechanics to perform calculations. Unlike classical computing, quantum computing uses phenomena such as quantum superposition and entanglement of quantum bits (qubits), allowing more efficient calculations in some cases. In quantum computing, calculations are no longer based solely on the 0 and 1 of classical bits, but allow for a certain degree of superposition of 0 and 1 at the same time, as well as entanglement between different quantum bits.

[0044] These quantum properties allow the design of quantum algorithms that are more efficient than classical algorithms. For example, Shor's algorithm can speed up the factorization of large numbers, which helps in password cracking; quantum algorithms such as the HHL algorithm can speed up the solution of linear equations and have great application value in engineering practice.

[0045] Noise is a major challenge facing quantum computers, limiting their performance and reliability. Noise can come from many sources, including hardware processing defects, environmental interference, and crosstalk between quantum bits. In order to reduce the impact of noise on quantum computing, a variety of solutions have been proposed, including hardware technologies such as environmental isolation, and software technologies such as quantum error correction codes and quantum circuit mapping.

[0046] This embodiment is aimed at quantum circuit mapping in software to reduce noise during the operation of logical quantum circuits. Quantum circuit mapping is an important issue in quantum computing and plays an important role in alleviating the impact of noise on quantum computing. It involves selecting a set of physical quantum bits and quantum gates in a quantum processor (also known as a quantum chip) to execute a given quantum algorithm (i.e., a logical quantum circuit).

[0047] In essence, the quantum circuit mapping problem is about determining the mapping relationship between the qubits (or quantum gates) in the logical quantum circuit and the physical qubits (or quantum gates) in the quantum processor. In particular, due to the limitations of existing micro-nano processing and measurement and control technologies, the performance of qubits (or quantum gates) on quantum processors varies. An ideal quantum circuit mapping should avoid qubits and quantum gates of poor quality, thereby reducing the error rate of the quantum circuit operation process.

[0048] Due to the complex entanglement and coupling between quantum bits, and the fact that actual quantum gate operations may be affected by noise and errors, mapping logical quantum circuits to physical quantum circuits is a complex optimization problem. This usually involves solving problems such as quantum bit connection restrictions, noise tolerance, and reordering and optimization of quantum gates.

[0049] Current quantum processors are susceptible to environmental noise during operation. Specifically, as the depth of the quantum circuit and the number of quantum gates increase, the fidelity of the quantum circuit decays exponentially, and the decrease in fidelity means that the probability of obtaining the correct result of the quantum computing operation decreases. Therefore, in order to achieve large-scale quantum computing, an effective error mitigation scheme must be used to suppress the decrease in the fidelity of the quantum circuit.

[0050] Quantum circuit mapping reduces the impact of noise during the operation of quantum circuits by selecting a set of high-quality quantum bits and quantum gates to run a given quantum algorithm. The use of appropriate quantum circuit mapping can significantly improve the fidelity of quantum algorithm operation. However, selecting a better quantum circuit mapping is itself an NP-hard problem, which means that searching for a better quantum circuit mapping is usually accompanied by a lot of computational overhead. Therefore, how to design an efficient quantum circuit mapping algorithm is a key problem that needs to be solved.

[0051] This embodiment is aimed at quantum chips with a brick array structure that are widely used in quantum processors, and proposes an efficient quantum circuit mapping scheme for this type of quantum hardware. That is, by utilizing the structural characteristics of quantum chips, an efficient quantum circuit mapping scheme suitable for quantum chips with a brick array structure is implemented.

[0052] The following is an explanation of the basic concepts related to quantum circuit mapping.

[0053] Quantum circuit: A qubit is the basic unit of quantum information and the quantum counterpart of a classical bit. A qubit can exist in a superposition of states or be entangled with other qubits, enabling powerful quantum computing. A quantum gate is an operation that acts on one or more qubits. Specifically, a quantum gate defines a specific evolution of a quantum state, which can be considered the basic building block of a quantum circuit, similar to a classical logic gate. A sequence of multiple quantum gates is called a quantum circuit. A quantum circuit essentially defines the evolution of an initial quantum state. By designing / programming a quantum circuit, any quantum algorithm can be implemented.

[0054] Quantum circuit interaction graph: A quantum circuit interaction graph is a graph representation of a quantum circuit. This is a structure consisting of a set of nodes and edges connecting some nodes. Specifically, given a quantum circuit, each quantum bit in the quantum circuit is represented by a node. For each two-qubit gate in the circuit, an edge is used to connect the nodes corresponding to the quantum bits acted on by the quantum gate. In this way, a graph is constructed. This graph is the interaction graph of the quantum circuit, which is used to represent the interaction between the quantum bits involved in the execution of the quantum circuit, or the connectivity between the logical quantum bits.

[0055] Quantum processor coupling graph: A quantum processor is a quantum chip. The coupling graph of a quantum hardware device represents the physical connections between quantum bits used to implement a two-qubit gate. In other words, it shows which quantum bits can interact directly with each other, and these interactions are essential for performing multi-qubit operations required for quantum computing. The structure of the coupling graph can significantly affect the functionality of a quantum processor. A quantum processor with a dense (well-connected) coupling graph can efficiently execute quantum algorithms and reduce noise interference, while a sparse (poorly connected) coupling graph may pose challenges to the implementation of certain algorithms because it may require quantum bits that are not directly coupled to interact.

[0056] In particular, the brick array structure is one of the more commonly used quantum chip structures, and its coupling diagram is as follows: Figure 2 As shown, the brick array structure is composed of a first type of brick structure (i.e., brick structure 201) and a second type of brick structure (i.e., brick structure 202) stacked together. The advantages of quantum chips with brick array structures include good scalability, the ability to mitigate quantum gate error rates, and support for the implementation of quantum error correction codes. Figure 2 As shown, each node represents a quantum bit (qubit), and the lines between the nodes represent the coupling (coupler) between the quantum bits, that is, the connected quantum bits can interact with each other. In view of this, this embodiment is aimed at the quantum circuit mapping problem of the quantum chip with a brick array structure.

[0057] Quantum circuit compilation: Quantum circuit compilation refers to the process of converting advanced quantum algorithms or quantum gate operations into physical quantum gate sequences that can be executed on a specific hardware platform. The main goal of quantum circuit compilation is to optimize the sequence of quantum gate operations to minimize errors and noise in the calculation process, while converting quantum gates that are not supported by the hardware so that the quantum circuit meets the limitations of the hardware. The workflow of quantum circuit compilation is as follows:

[0058] 1. Determine the initial circuit mapping;

[0059] 2. Introduce SWAP gates to meet the qubit connection requirements (i.e. pre-compilation);

[0060] 3. Perform secondary mapping on the circuit to enhance fidelity (secondary quantum circuit mapping after circuit compilation); the secondary mapping of quantum circuits involves subgraph matching and quantum circuit mapping scoring;

[0061] 4. Convert the quantum gates in the circuit into hardware-native quantum gates;

[0062] 5. Optimize the circuit to minimize the total number of quantum gates;

[0063] 6. Output quantum circuit.

[0064] Among them, quantum circuit mapping is a sub-process of quantum circuit compilation, and in this embodiment, secondary quantum circuit mapping is performed on the pre-compiled quantum circuit, that is, the first logic quantum circuit is the logic quantum circuit obtained after pre-compilation. In an optional implementation, the original logic quantum circuit can be pre-compiled onto the quantum chip to obtain the pre-compiled first logic quantum circuit. In another optional implementation, a local area of ​​the quantum chip can be selected, and the original logic quantum circuit can be pre-compiled onto the local area of ​​the quantum chip to obtain the pre-compiled first logic quantum circuit. Correspondingly, based on the operation instructions of the first logic quantum circuit, the interaction diagram of the first logic quantum circuit can be obtained.

[0065] The coupling graph of the quantum chip can be obtained based on the arrangement structure information of the physical quantum bits in the quantum chip, wherein the arrangement structure information indicates that the quantum bits on the quantum chip are arranged in a brick array structure, and accordingly, its coupling graph is also a brick array structure. Based on the arrangement structure information, each quantum bit on the quantum chip can be obtained, and a node can be created for each quantum bit on the quantum chip to construct the coupling graph of the quantum chip.

[0066] The node index indicates the mapping relationship between the node position coordinates of the quantum bit and the node label. It can store the node position coordinates and node labels of the quantum bit in a key-value manner, and can efficiently retrieve the quantum bits in the quantum chip. Among them, the node position coordinates can refer to the position of the node corresponding to the quantum bit on the coupling graph, which can be represented by two-dimensional coordinates or three-dimensional coordinates, which is not specifically limited here. The node label can be the number of the node corresponding to the quantum bit of the quantum chip.

[0067] The node position coordinates of the quantum bits can be determined based on the relative position information between the quantum bits in the arrangement structure information of the quantum bits on the quantum chip. The node position coordinates of the quantum bits on the quantum chip can also be determined based on the layout information of the brick structure arranged on the quantum chip, and the arrangement structure information includes layout information, which is not specifically limited here. The node number can be determined based on the layout information of the brick structure arranged on the quantum chip, or it can be pre-set, which is not specifically limited here.

[0068] The following describes in detail the logic of the quantum circuit quadratic mapping algorithm.

[0069] The first logical quantum circuit obtained by pre-compilation of the quantum circuit can be used as input. The goal is to identify the area on the quantum chip that is topologically equivalent to the input circuit (called an isomorphic subgraph) so that the circuit can be physically realized.

[0070] This involves solving the subgraph matching problem. After completing this step, a set of isomorphic subgraphs on the quantum chip can be obtained. Each subgraph corresponds to a mapping from logical qubits in the quantum circuit to actual physical qubits on the quantum hardware, which is called a feasible quantum circuit mapping scheme.

[0071] Then, for these feasible quantum circuit mapping schemes, the corresponding quantum circuit fidelity can be estimated as a score, and the feasible quantum circuit mappings can be sorted according to their scores, and the corresponding target mapping scheme can be selected based on the score sorting. In an optional implementation, the quantum circuit mapping with the highest score (the corresponding quantum circuit with the lowest error rate) can be selected as the output. In essence, the circuit mapping is optimized under the premise of meeting the hardware limitations of the quantum chip to minimize the probability of errors during the execution of the quantum circuit.

[0072] It is worth noting that the quantum circuit remapping involves searching for a set of physical qubits on the quantum hardware whose connectivity is equivalent to the connectivity between the logical bits in the input quantum circuit. Specifically, it is necessary to search for a subgraph in the coupling graph of the quantum chip that is isomorphic to the interaction graph of the quantum circuit. This problem is called the subgraph matching problem.

[0073] However, the subgraph matching problem is an NP-complete problem, which means that the quantum circuit remapping requires a relatively large computational overhead and has poor scalability. The relevant technology cannot handle the circuit mapping problem on large-scale quantum chips. In addition, the research and development of quantum computers has made significant progress in recent years. The latest quantum computers already have hundreds of qubits, and this number is expected to increase thousands of times in the next few years. In view of these developments, the relevant quantum circuit remapping schemes will be difficult to apply to recent quantum computers.

[0074] The purpose of this embodiment is to use the symmetry of the brick array structure of the quantum chip to accelerate the search process of circuit mapping, which has the advantage of significantly improving the search speed and realizing an efficient quantum circuit mapping scheme suitable for quantum chips with a brick array structure. In addition, based on pre-compilation, the second mapping of the quantum circuit is used to obtain the target mapping scheme from the first logical quantum circuit to the quantum chip, which can optimize the mapping of the quantum circuit and improve the fidelity of the quantum circuit, thereby obtaining a high-fidelity quantum computing result.

[0075] Step S102: Search for a first subgraph isomorphic to the interaction graph in a reduced search space of the coupling graph, wherein the reduced search space includes a set of nodes in the coupling graph whose distance from the generation set does not exceed a specified distance, and the specified distance is greater than or equal to the radius of the interaction graph, and the generation set can cover the coupling graph under a matching translation operation.

[0076] The core problem of the quadratic mapping of quantum circuits is the subgraph matching problem. In the subgraph matching problem, given two graphs, usually called pattern graph G and target graph P, the goal is to find all subgraphs G′ in the target graph that are isomorphic to the pattern graph (i.e., have the same structure and connection mode). Indicates that graphs G′ and G are isomorphic.

[0077] A first subgraph isomorphic to the interaction graph may be searched in a reduced search space of the coupling graph. The reduced search space may be determined based on a spanning set, which includes a set of nodes in the coupling graph whose distances to the spanning set do not exceed a specified distance.

[0078] As long as the selected generation set can cover the entire target graph under the corresponding translation transformation, all isomorphic subgraphs can be searched based on the first subgraph under the translation transformation, and the logical correctness can be guaranteed.

[0079] The specified distance needs to be greater than or equal to the radius of the interaction graph, so that the first subgraph isomorphic to the interaction graph can be found in the reduced search space. The radius of the interaction graph can be the maximum step length from a node to the central node in the graph.

[0080] An existing or new subgraph search method may be used to search for a first subgraph isomorphic to the interaction graph in the reduced search space of the coupling graph, which is not specifically limited here.

[0081] In this step, by limiting the reduced search space of the coupling graph and searching for a subgraph isomorphic to the interaction graph in the reduced search space of the coupling graph, the scope of the subgraph search can be narrowed and the amount of computation of the subgraph search can be reduced.

[0082] Step S103: Based on the node index, the brick array structure of the coupling graph is used to perform a translation operation on the first subgraph on the coupling graph to match the generated set, so as to obtain a second subgraph isomorphic to the interaction graph.

[0083] In the field of quantum computing, symmetry plays a key role and provides a wide range of applications. It has been exploited to optimize resource usage efficiency in variational quantum eigensolvers, reduce error rates in quantum approximate optimization algorithms, efficiently design quantum error correction codes, and promote the development of quantum machine learning models.

[0084] A given logical quantum circuit can be mapped to a set of quantum bits and quantum gates on quantum hardware, so that the interaction graph of the quantum circuit and the coupling graph of the hardware are compatible, and the fidelity of the quantum circuit is high. In particular, the symmetry of the quantum chip structure can be used to significantly improve the efficiency of quantum circuit mapping.

[0085] In this step, when the first subgraph is obtained, the symmetry of the brick array structure of the coupling graph of the quantum chip can be used to simulate the movement of the first subgraph to various positions of the coupling graph by translation, and the node label of the subgraph after the movement is determined based on the node index to obtain the second subgraph, so that all subgraphs that are isomorphic to the interaction graph can be searched to form a subgraph set, and the search speed is very efficient.

[0086] Among them, different generation sets have different translation methods. In order to enable the translation operation on the first subgraph to cover the entire target graph, the translation method needs to correspond to the generation set.

[0087] In an optional embodiment, the translation operation of the first subgraph in the coupling graph can be simulated by software to obtain a second subgraph isomorphic to the interaction graph. In another optional embodiment, the symmetry of the brick array structure of the coupling graph can be used to construct an update range of the node position coordinates of the first subgraph in the translation transformation of the coupling graph, and based on the update range, the node position coordinates of the first subgraph are updated to obtain a second subgraph isomorphic to the interaction graph.

[0088] Step S104: Determine each subgraph in the subgraph set. Figure 1 A corresponding first mapping scheme, where the first mapping scheme is a mapping scheme from the first logic quantum circuit to the quantum chip, and the subgraph set includes the first subgraph and the second subgraph.

[0089] Each subgraph corresponds to a mapping from the interaction graph of the first logic quantum circuit to the quantum chip, and based on the pre-compilation, a mapping from the first logic quantum circuit to the quantum chip can be obtained. Accordingly, through the double mapping, all first mapping schemes from the first logic quantum circuit to the quantum chip can be obtained, and the first mapping scheme can be called a feasible quantum circuit mapping scheme.

[0090] Step S105: Based on the fidelity of the physical quantum gate on the quantum chip, determine a target mapping scheme from the first logical quantum circuit to the quantum chip from the first mapping scheme corresponding to the subgraph set.

[0091] In this step, the target fidelity of mapping the first logical quantum circuit to the physical quantum circuit on the quantum chip in each first mapping scheme can be obtained based on the fidelity of the physical quantum gate on the quantum chip. Based on the target fidelity, the first mapping schemes are sorted, and the first mapping scheme with the largest target fidelity can be selected as the target mapping scheme, or any first mapping scheme with a target fidelity greater than or equal to a specified threshold can be selected as the target mapping scheme.

[0092] In this embodiment, a secondary circuit mapping technique is used. After the circuit is precompiled, a subgraph matching search is performed in a reduced search space of a coupling graph determined based on a generation set to find a first subgraph isomorphic to the interaction graph of the precompiled first logic quantum circuit. Then, based on the node index, a translation operation is performed on the first subgraph on the coupling graph to match the generation set using the brick array structure of the coupling graph to obtain a second subgraph isomorphic to the interaction graph. Accordingly, all quantum circuit mappings can be searched through subgraph matching. Based on the fidelity of the physical quantum gates on the quantum chip, a target mapping scheme that maximizes the fidelity of the quantum circuit is selected from all the first mapping schemes. This fully considers the difference in error rates of different physical quantum gates, optimizes the mapping of the quantum circuit, and improves the fidelity of the quantum circuit. Moreover, by effectively reducing the search space for subgraph matching and based on node indexing, by utilizing the structural characteristics of quantum hardware, that is, utilizing the symmetry of the brick array structure of the quantum chip to perform a translation transformation of the subgraph to search for other subgraphs, this can accelerate the subgraph search process of circuit mapping, achieve efficient translation transformation of a group of quantum bits, significantly simplify the process of searching for quantum circuit mapping, and have the advantage of significantly improving the search speed, thus realizing an efficient quantum circuit mapping scheme suitable for quantum chips with a brick array structure.

[0093] Accordingly, after the input circuit is precompiled onto the quantum chip to obtain the first logical quantum circuit and the target mapping scheme is determined, the first logical quantum circuit is mapped onto the quantum chip of the brick array structure according to the target mapping scheme, so as to actually run the input circuit on the quantum chip to perform actual quantum computing tasks, such as quantum communication, quantum computing protocols, and quantum key distribution protocols. Moreover, it can improve the accuracy of quantum algorithm operation on large quantum processors, make up for the shortcomings of current quantum computing that is easily affected by environmental noise, and has important significance for the practical applications of quantum computing, such as code breaking, drug development, and machine learning.

[0094] Optionally, the step S101 specifically includes:

[0095] Creating a node for each quantum bit on the quantum chip to construct a coupling graph of the quantum chip;

[0096] Determining node numbers and node position coordinates of quantum bits on the quantum chip based on layout information of the brick structure arranged on the quantum chip, wherein the arrangement structure information includes the layout information;

[0097] A mapping relationship between the node position coordinates of the quantum bit and the node label is established to obtain the node index of the coupling graph.

[0098] In order to efficiently retrieve the quantum bits at a given position in the quantum chip, it is necessary to label these quantum bits and determine the node position coordinates of the node corresponding to each quantum bit.

[0099] Based on the arrangement structure information of the quantum bits on the quantum chip, the number of quantum bits on the quantum chip can be determined, and a node can be created for each quantum bit, and edges can be created between the nodes of two mutually coupled quantum bits, so that the coupling graph of the quantum chip can be constructed.

[0100] The node numbers and node position coordinates of the quantum bits on the quantum chip can be determined based on the layout information of the brick structure arranged on the quantum chip. In an optional implementation, the nodes corresponding to the quantum bits on the quantum chip can be numbered in a preset order (such as from bottom to top, from left to right) based on the layout information of the brick structure arranged on the quantum chip, and their node position coordinates can be determined, thereby obtaining the node numbers and node position coordinates of the quantum bits on the quantum chip.

[0101] In another optional implementation, optionally, determining the node number and node position coordinates of the quantum bit on the quantum chip based on the layout information of the brick structure arranged on the quantum chip includes:

[0102] Determining, based on the layout information of the brick structure arranged on the quantum chip, a node number and a node position coordinate of a first quantum bit on the quantum chip, where the first quantum bit is a quantum bit interconnected in the horizontal direction of the quantum chip;

[0103] The node number of a second quantum bit on the quantum chip is determined based on the layout information and the node number of the first quantum bit, and the node position coordinates of the second quantum bit are determined based on the layout information, wherein the second quantum bit is a quantum bit on the quantum chip other than the first quantum bit.

[0104] That is to say, the nodes of the brick structure in the coupling diagram in the horizontal direction can be numbered first, and when the node numbering in the horizontal direction is completed, the other nodes in the coupling diagram can be numbered.

[0105] In this embodiment, the node number and node position coordinates can be efficiently determined based on the layout information of the brick structure arranged on the quantum chip, thereby determining the node index, and further accelerating the search for quantum mapping on the quantum chip with a brick array structure based on the node index.

[0106] Optionally, the node number of the quantum bit on the quantum chip is determined by at least one of the following methods:

[0107] Based on the layout information of the brick structure arranged on the quantum chip, the first quantum bit on the quantum chip is numbered in a preset order to obtain a node number of the first quantum bit, wherein the preset order is from left to right and from bottom to top;

[0108] Based on the layout information and the node number of the first quantum bit, the second quantum bits on the quantum chip are numbered in the preset order to obtain the node number of the second quantum bit.

[0109] In an optional embodiment, the node labels of the coupling graph are as follows: Figure 3 As shown, the quantum chip in the figure is composed of a brick array of 4 rows and 3 columns, wherein the first type of brick structure includes 2 rows, the second type of brick structure includes 2 rows, and each vertex of the brick structure corresponds to a quantum bit.

[0110] Based on the layout information of the brick structure arranged on the quantum chip, the quantum bits interconnected by the horizontal coupler, that is, the quantum bits numbered between 0 and 74, can be numbered from left to right and from bottom to top. Afterwards, based on the node numbers of the quantum bits interconnected by the horizontal coupler, the remaining quantum bits, that is, the quantum bits numbered between 75 and 90, can be numbered from left to right and from bottom to top.

[0111] In this way, the numbering of nodes corresponding to quantum bits on the quantum chip can be achieved efficiently.

[0112] In an optional embodiment, optionally, the node label of the first quantum bit is: node_index = i*(4×width+3)+j, i is the row position of the node corresponding to the first quantum bit, i∈{0,1,...,height}, j is the column position of the node corresponding to the first quantum bit, j∈{0,1,...,4×width+2}, height is the number of rows of the first type and second type of brick structures arranged on the quantum chip, width is the number of columns of the second type of brick structures arranged on the quantum chip, and the layout information includes the number of rows and columns.

[0113] In this way, by limiting the numbering method of the nodes corresponding to the first quantum bit, the search process for feasible quantum circuit mapping on the quantum chip can be simplified.

[0114] Furthermore, the node numbers of the second quantum bits may be numbered in sequence from left to right and from bottom to top based on the largest node number among the node numbers of the first quantum bits, with 1 being the superposition unit.

[0115] Optionally, the node position coordinates of the quantum bit on the quantum chip are (x1, x2, k), where x1 represents the coordinate component of the brick structure to which the quantum bit corresponding node belongs in the horizontal direction in the affine coordinate system, and x2 represents the coordinate component of the brick structure to which the quantum bit corresponding node belongs in the diagonal direction of the brick in the affine coordinate system, and the diagonal direction of the brick forms an angle of 45° with the horizontal direction, and k is the relative position of the node corresponding to the quantum bit in the brick structure to which it belongs;

[0116] The node position coordinates of the quantum bits on the quantum chip are determined by at least one of the following methods:

[0117] In the case where the qubit is a first qubit, x2=i, k=(2i+j)%4, i∈{0,1,...,height}, j∈{0,1,...,4×width+2};

[0118] In the case where the qubit is a second qubit, x2=i, k=4, i∈{0,1,...,height-1}, j∈{0,1,...,width};

[0119] Among them, height is the number of rows of the first type and the second type of brick structures arranged on the quantum chip, width is the number of columns of the second type of brick structures arranged on the quantum chip, and the layout information includes the number of rows and the number of columns.

[0120] In addition to numbering, the node position coordinates of the quantum bit can be used to create the node index of the quantum bit. For example, the coordinates of the brick structure where the quantum bit is located (x1, x2) and the relative position k of the quantum bit in the brick structure can be used to specify the node position coordinates of the quantum bit, recorded as (x1, x2, k). Among them, the coordinates (x1, x2) of the brick structure are defined in an affine coordinate system, x1 represents the component of the quantum bit position vector in the horizontal direction, and x2 represents the component of the quantum bit position vector in the diagonal direction of the brick.

[0121] In this way, by defining the node position coordinates of the quantum bit through three-dimensional coordinates, the retrieval efficiency of the quantum bit by the node index can be improved.

[0122] The specific process of creating the coupling graph, determining the node position coordinates and node labels of the quantum bits is as follows:

[0123] Input: the number of rows height and columns width of the brick structure;

[0124] Output: coupling diagram of brick array structure, node index index (a dictionary storing the mapping from node position coordinates to node labels).

[0125] Step 1: Initialize the node list node_list and edge list edge_list to empty lists;

[0126] Step 2: Initialize the node index index to an empty dictionary;

[0127] Step 3: Loop the row index i∈{0,1,...,height}: Loop the column index j∈{0,1,...,4×width+2}: Execute operation a, which is used to determine the node number and node position coordinates of the node corresponding to the first quantum bit;

[0128] Operation a: Add a node to node_list and define the node index as node_index = i*(4×width+3)+j; initialize the node position coordinates (x1,x2,k) = (0,0,0), where x1 and x2 represent the coordinates of the brick structure to which the node belongs in the affine coordinate system, and k represents the relative position of the node in the brick structure; x2=i, k=(2i+j)%4; add key-value pair {(x1,x2,k):node_index} to node index index;

[0129] Step 4: Save the current maximum node label current_node;

[0130] Step 5: loop over the row index i∈{0,1,...,height-1}: loop over the column index j∈{0,1,...,width}: execute operation b, which is used to determine the node number and node position coordinates of the node corresponding to the second quantum bit;

[0131] Operation b: Update the current node index current_node←current_node+1; add a node to node_list and define the node index as node_index=current_node; initialize the node position coordinates (x1,x2,k)=(0,0,0); set x2=i, k=4; add the key-value pair {(x1,x2,k):node_index} to the node index index;

[0132] Step 6: Add the edges between nodes in the coupling graph of the brick array structure into edge_list;

[0133] Step 7: Use a graph theory software package such as rustworkx or NetworkX to create a coupled graph P of a brick array structure by taking the node_list and edge_list of the graph as input;

[0134] Step 8: Return the coupling graph P of the brick array structure and the node index index.

[0135] Optionally, the generated set includes any of the following:

[0136] Each node of two adjacent brick structures arranged vertically in the coupling graph;

[0137] The four adjacent nodes in the horizontal direction of any brick structure in the coupling diagram, and the target node in the brick structure, the line formed by the four adjacent nodes intersects vertically with the line belonging to the target node.

[0138] Any of the above-mentioned groups of generation sets and corresponding translation transformations can satisfy the above-mentioned requirement of covering the complete coupling graph. In this way, the generation sets can be flexibly selected to construct the reduced search space of the coupling graph.

[0139] Optionally, in the case where the spanning set includes nodes of two adjacent brick structures arranged vertically in the coupling graph, the translation operation matching the spanning set includes: translation in the horizontal direction and the vertical direction;

[0140] In the case where the generation set includes four adjacent nodes in the horizontal direction of any brick structure in the coupling graph and a target node in the brick structure, the translation operations matching the generation set include: translation in the horizontal direction and in the diagonal direction of the brick.

[0141] The definition of translational symmetry is paired with the selection of the spanning set. In principle, as long as the selected spanning set can cover the entire coupling graph under the corresponding translation transformation, the correctness of the subgraph matching logic can be guaranteed.

[0142] In an alternative embodiment, if Figure 3 As shown, the usable generation set S1 is a set consisting of nodes 34, 35, 36, 37, and 84, and the corresponding translation transformations T1 and T2 are translations in the horizontal direction and translations in the diagonal direction of the bricks. Specifically, when these translation transformations act on the nodes in the above generation set, the results are as follows:

[0143]

[0144]

[0145] Here, the superscript P represents the physical quantum bit. The generation set and translation transformation defined in this way satisfy the above-mentioned conditions for covering the coupling graph, thus ensuring the logical correctness of the subgraph matching process.

[0146] Other combinations of spanning sets and translation transformations can also be used, such as Figure 3 As shown, the nodes 0, 1, 2, 3, 4, 15, 16, 17, 18, 19, 20, 21, 32, 33, 34, 35, 36, 75, 76, 79, 80, i.e., the set of all nodes of two adjacent bricks arranged vertically, can be defined as the generating set S2, and the corresponding translation transformation is defined as the translation T along the horizontal direction. x and the vertical translation T y , the generated set and translation transformation selected in this way also meet the requirements of covering the coupling graph.

[0147] Since the generation set S2 is larger than the generation set S1, the corresponding reduced search space is also larger, which means that the execution process of using the generation set S2 to define the reduced search space will consume more computation in the subgraph matching process of the reduced search space. However, since the computation of this process only accounts for a small part of the entire subgraph matching process, it has little impact on the total running time of the subgraph matching.

[0148] In this way, after the corresponding generation set is selected, the sub-graph translation transformation can be performed according to the matching translation operation, thereby improving the flexibility of sub-graph matching.

[0149] Optionally, before searching the reduced search space of the coupling graph for a first subgraph isomorphic to the interaction graph, the method further includes:

[0150] Determining an r-order neighborhood of the generated set, where r is the radius of the interaction graph;

[0151] The r-order neighborhood is determined as a reduced search space of the coupling graph.

[0152] Among them, the k-order neighborhood of a node subset S of graph P is defined as the set of all nodes whose distance from S does not exceed k, denoted as If all nodes of the subgraph G′ of graph P are in the neighborhood, In addition, Indicates that G′ is a subgraph of P.

[0153] Among them, the node subset S is the generated set, and the radius r of the interaction graph can be used as the limit of the neighborhood range. In this way, the determination of the reduced search space can be achieved and the complexity of the subgraph search can be reduced.

[0154] Since there may be more than one center of the interaction graph, optionally, the radius of the interaction graph is determined by:

[0155] Taking the node located in the central area of ​​the interaction graph as the target node, obtaining the maximum step length from the node in the interaction graph to the target node, and obtaining the target step length corresponding to the target node;

[0156] The step length with the shortest distance among the target step lengths corresponding to the target nodes in the central area is determined as the radius of the interaction graph.

[0157] In this way, determination of the radius of the interaction graph may be achieved.

[0158] Optionally, the step S103 specifically includes:

[0159] Based on the node index, determining a value range of a target translation operation of the first subgraph in the coupling graph, wherein the subgraph obtained after the target translation operation does not exceed a boundary of the coupling graph, and the target translation operation is a translation operation in a translation direction matched by the generated set;

[0160] Based on the node index, the node labels of the first subgraph are updated within the value range to obtain a second subgraph isomorphic to the interaction graph.

[0161] Based on the node number of the first subgraph, the node position coordinates of the first subgraph can be retrieved from the node index of the coupling graph. Based on the node position coordinates of the first subgraph, the target translation operation is performed on the coupling graph using the symmetry of the brick array structure to determine the value range of the target translation operation of the first subgraph in the coupling graph.

[0162] Afterwards, based on the node index, the node position coordinates of the first subgraph can be updated within the value range to obtain the node position coordinates of the second subgraph, and then based on the node position coordinates of the second subgraph, the node label of the second subgraph can be retrieved from the node index.

[0163] In this way, the subgraph matching of the interaction graph of the first logic quantum circuit in the coupling graph can be achieved through translation operation.

[0164] The specific process of subgraph matching is as follows:

[0165] Input: pattern graph G, coupling graph P of brick array structure, node index index;

[0166] Output: All subgraphs in the coupling graph P that are isomorphic to the interaction graph G.

[0167] Step 1: Determine the position coordinates of the central brick structure of the coupling graph P in the affine coordinate system, recorded as (x1, x2);

[0168] Step 2: Retrieve the node number corresponding to the node coordinate (x1, x2, k) from the node index index, and define the set of these nodes as the generating set S, where k = 0, 1, 2, 3, 4;

[0169] Step 3: Calculate the radius r of the pattern graph G using a related algorithm (such as the algorithm built into the Python toolkit NetworkX).

[0170] Step 4: Calculate the r-order neighborhood of the generating set S As a reduced search space for subsequent subgraph matching;

[0171] Step 5: Find a subgraph isomorphic to the pattern graph G in the reduced search space Get a set of isomorphic subgraphs (i.e. the first subgraph);

[0172] Step 6: Initialize an empty list R;

[0173] Step 7: Search for the isomorphic subgraph G'∈R reduced Loop: Execute operation a1 and operation b1:

[0174] Operation a1: Confirm to use The range of n and m that does not exceed the boundary of the coupling graph P is denoted as feasible_movements = {(n,m): Wherein, in the case where the generated set includes four adjacent nodes in the horizontal direction of any brick structure in the coupling graph and the target node in the brick structure, It is the graph G' that is translated m steps along the diagonal direction of the bricks and then translated n steps horizontally, where n and m are both integers.

[0175] Operation b1: loop over (n,m)∈feasible_movements: Add to R;

[0176] Step 8: Return a list R of isomorphic subgraphs as output.

[0177] Optionally, when the generation set includes four adjacent nodes in the horizontal direction of any brick structure in the coupling graph and a target node in the brick structure, the target translation operation is to translate the first subgraph in the diagonal direction and the horizontal direction of the bricks in sequence, and the line formed by the four adjacent nodes intersects vertically with the line belonging to the target node. The determining, based on the node index, of a value range for the target translation operation of the first subgraph in the coupling graph includes:

[0178] Based on the node index, determining the number of steps required for the first subgraph to move horizontally and vertically to the boundary of the coupling graph in units of brick structures; and based on the number of steps required for the first subgraph to move horizontally and vertically to the boundary of the coupling graph, determining a first value range for the first subgraph to perform a target translation operation in the coupling graph, wherein the first value range represents a displacement vector of the first subgraph in an affine coordinate system, and the number of steps for the first subgraph to move vertically is an even number;

[0179] Based on the node index, determine the number of steps required for the target subgraph to move horizontally and vertically to the boundary of the coupling graph in units of brick structure; and based on the number of steps required for the target subgraph to move horizontally and vertically to the boundary of the coupling graph, determine a second value range for the first subgraph to perform a target translation operation in the coupling graph, the second value range represents a displacement vector of the first subgraph in an affine coordinate system, the number of steps for the vertical movement of the target subgraph is an even number, and the target subgraph is a subgraph obtained by translating the first subgraph in units of brick structure in the diagonal direction of the brick by one step;

[0180] The value range includes the first value range and the second value range.

[0181] When performing the target translation operation, it is necessary to ensure that the translated sub-graph is still within the boundary range of the coupling graph of the brick array structure. To this end, the translation range can be set according to the boundary shape of the coupling graph of the brick array structure. Since the horizontal boundaries of the odd and even rows of the brick array structure are different, they can be processed separately.

[0182] The first subgraph and the target subgraph can be translated in the vertical direction with an even number of steps respectively. The translation operation of the first subgraph with an even number of steps corresponds to translation to the boundary of the even rows (or odd rows) of the coupling graph of the brick array structure, while the translation operation of the target subgraph with an even number of steps corresponds to translation to the boundary of the odd rows (or even rows) of the coupling graph of the brick array structure.

[0183] Correspondingly, target translation operations are performed on the first subgraph and the target subgraph respectively to determine a first value range for the target translation operation of the first subgraph in the coupling graph, and a second value range for the target translation operation of the first subgraph in the coupling graph, thereby easily realizing the determination of the value range for the target translation operation of the first subgraph in the coupling graph.

[0184] The second value range of the target translation operation performed on the first subgraph in the coupling graph can be obtained by superimposing the number of translation steps from the first subgraph to the target subgraph on the value range of the target translation operation performed on the target subgraph in the coupling graph.

[0185] Furthermore, the first value range of the target translation operation of the first subgraph in the coupling graph and the value range of the target translation operation of the target subgraph in the coupling graph are determined in a similar manner, and the following is an explanation of the translation transformation of the first subgraph.

[0186] Optionally, the determining, based on the node index, the number of steps required for the first subgraph to move horizontally and vertically to the boundary of the coupling graph in units of brick structures, comprises:

[0187] Based on the node labels of the first subgraph, retrieve the node position coordinates of the first subgraph in the node index;

[0188] Based on the node position coordinates of the first subgraph and the layout information of the brick structures arranged on the quantum chip, the number of steps required for the first subgraph to move horizontally and vertically to the boundary of the coupling graph in units of brick structures is determined.

[0189] In this way, based on the node index, the number of steps required for the first subgraph to move horizontally and vertically to the boundary of the coupling graph in units of brick structures can be determined.

[0190] Optionally, the number of steps required for the first subgraph to move horizontally to the left to the boundary of the coupling graph in units of brick structures is: index x is the horizontal position of each node in the first subgraph;

[0191] The number of steps required for the first subgraph to move horizontally to the right to the boundary of the coupling graph in units of brick structure is: p is the number of nodes in the horizontal direction of the coupling graph;

[0192] The number of steps required for the first subgraph to move vertically downward to the boundary of the coupling graph in units of brick structures is: min(index y ), index y is the vertical position of each node in the first subgraph;

[0193] The number of steps required for the first subgraph to move vertically upward to the boundary of the coupling graph in units of brick structures is: height-max(index y )-1, height is the number of rows of the first type and the second type of brick structures arranged on the quantum chip.

[0194] Among them, index x ={index(node)%row_node_count:node∈G'}, row_node_count=4×width+3, row_node_count=p, which is the number of nodes in the horizontal direction of the coupling graph, and node is the node number of the first subgraph. y ={i:(i,j,k)∈coord_list}, coord_list is a list of node position coordinates of the first subgraph.

[0195] In this way, based on the node labels and node position coordinates of the quantum bits on the quantum chip, the symmetry of the brick array structure can be used to determine the number of steps required for the first subgraph to move horizontally and vertically to the boundary of the coupling graph in units of brick structures.

[0196] Optionally, determining a first value range for performing a target translation operation on the first subgraph in the coupling graph based on the number of steps required for the first subgraph to move horizontally and vertically to the boundary of the coupling graph respectively includes:

[0197] Determine, based on the number of steps required for the first subgraph to move horizontally and vertically to the boundary of the coupling graph, an update range of the node position coordinates of the first subgraph in a first translation process on the coupling graph, wherein the first translation process includes horizontal and vertical movement;

[0198] Based on the update range, the first value range is determined using a target formula, the target formula including a first formula And the second formula m, n is the number of steps of horizontal movement of the sub-graph in the coupling graph, m is the number of steps of vertical movement of the sub-graph in the coupling graph, and the target formula is used to determine the number of translation steps of the sub-graph in the affine coordinate system.

[0199] Correspondingly, the number of steps of horizontal translation in the coupling graph combined with the first subgraph is And the number of steps m of the first subgraph translated in the diagonal direction of the bricks in the coupling graph can determine the first value range, so that the determination of the first value range can be achieved.

[0200] Optionally, the updating of the node labels of the first subgraph within the value range based on the node index to obtain a second subgraph isomorphic to the interaction graph includes:

[0201] Updating the node position coordinates of the first subgraph within the value range;

[0202] Based on the updated node position coordinates of the first subgraph, the updated node labels of the first subgraph are retrieved from the node index to obtain a second subgraph isomorphic to the interaction graph.

[0203] In this way, the node labels of the first subgraph can be updated within a value range based on the node index, and the second subgraph can be obtained by translation transformation.

[0204] In the case where the generated set includes four adjacent nodes in the horizontal direction of any brick structure in the coupling graph and the target node in the brick structure, the specific process of the translation transformation of the first subgraph using the symmetry of the brick array structure is as follows:

[0205] Input: a subgraph G′ of the coupled graph P of brick array structure, node index index and index_reverse of the reversed index key value;

[0206] Output: All G′ are transformed into subgraphs of P through translation, that is,

[0207] Step 1: Retrieve the coordinates of all nodes of G′ in the dictionary index_reverse and add them to the list coord_list;

[0208] Step 2: Traverse all node position coordinates of the coupling graph P saved by index and determine the number of rows, height and columns, width of P;

[0209] Step 3: The number of nodes in the horizontal direction row_node_count = 4×width+3, row_node_count = p;

[0210] Step 4: index x ={index(node)%row_node_count:node∈G′};

[0211] Step 5: Calculate the number of steps required to translate G′ horizontally to the left to the boundary of the coupling graph P:

[0212] Step 6: Calculate the number of steps required to translate G′ to the right to the boundary of the coupling graph P: p is the number of nodes in the horizontal direction of the coupling graph;

[0213] Step 7: Index y ={i: (i,j,k)∈coord_list};

[0214] Step 8: Calculate the number of steps required to translate G′ down to the boundary of the coupling graph P: m down =min(index y );

[0215] Step 9: Calculate the number of steps required to translate G′ upward to the boundary of P: m up =height-max(index y )-1;

[0216] Step 10: For n∈{-n left ,-n left +1,...,n right} loop: for m∈{t: t is an even number & -m down ≤t≤m up} loop: execute operation a2:

[0217] Operation a2: copy coord_list to shifted_coord_list; update the node position coordinates in shifted_coord_list to That is, the picture The node position coordinates; retrieve the node number corresponding to the node position coordinates contained in shifted_coord_list from index; add the subgraph of the retrieved node number to R;

[0218] Step 11: Calculate the subgraph obtained by translating G′ along the diagonal direction of the brick one step

[0219] Step 12: Replace G' with G", and repeat steps 4 to 10;

[0220] Step 13: Return the subgraph list R.

[0221] Optionally, the step S101 further includes:

[0222] Selecting a local area in the area range of the quantum chip, wherein the number of physical quantum bits deployed in the local area is greater than or equal to the number of logical quantum bits of the second logical quantum circuit;

[0223] The second logic quantum circuit is precompiled onto the local region to obtain an interaction graph of the first logic quantum circuit.

[0224] In this embodiment, a local area of ​​the quantum chip can be selected to precompile the second logic quantum circuit, the physical quantum bits in the local area are interconnected, and can be any area, and the number of physical quantum bits deployed in the local area is greater than or equal to the number of logical quantum bits of the second logic quantum circuit. The second logic quantum circuit is a precompiled input circuit and is transformed into the first logic quantum circuit after precompilation.

[0225] A quantum circuit compiler can be used to precompile the input second logic quantum circuit to the selected local area to obtain the precompiled first logic quantum circuit and a mapping scheme from the first logic quantum circuit to the quantum chip.

[0226] For the original logic quantum circuit, that is, the second logic quantum circuit, after pre-compilation, it can be equivalently converted into the first logic quantum circuit. The running effect of the first logic quantum circuit on the quantum chip is consistent with the execution effect of the second logic quantum circuit. Therefore, through secondary mapping, the mapping of the original logic quantum circuit on the quantum chip can be realized.

[0227] In this implementation, by selecting a local area of ​​the quantum chip to precompile the second logic quantum circuit, the execution efficiency of the precompile can be improved, thereby further improving the mapping efficiency of the quantum circuit.

[0228] Optionally, the step S104 specifically includes:

[0229] Obtain a second mapping scheme from the first logic quantum circuit to the quantum chip, and obtain a third mapping scheme corresponding to each subgraph in the subgraph set, respectively, wherein the third mapping scheme is a mapping scheme from the interaction graph to the quantum chip;

[0230] The second mapping scheme is associated with each of the third mapping schemes to obtain a subgraph set for each subgraph. Figure 1 A corresponding first mapping scheme.

[0231] In this implementation, by associating the mapping schemes of the two mappings, all feasible quantum circuit mapping schemes from the first logic quantum circuit to the quantum chip can be obtained, thereby achieving determination of feasible quantum circuit mapping schemes.

[0232] The specific process of quantum circuit mapping is as follows:

[0233] Input: the second logic quantum circuit C, the coupling diagram P of the brick array structure of the quantum processor;

[0234] Output: Optimal mapping of quantum circuits

[0235] Step 1: Select a local area of ​​the quantum processor with a brick array structure;

[0236] Step 2: Use the quantum circuit compiler to precompile the input second logic quantum circuit C to the local area of ​​the selected quantum processor. The precompiled first logic quantum circuit is denoted as C′, and the quantum circuit mapping given by the precompilation is denoted as F pre ;

[0237] Step 3: Calculate the interaction graph G of the pre-compiled first logic quantum circuit C′;

[0238] Step 4: Use the symmetry of the brick array structure of the coupling graph to perform subgraph matching to search for all subgraphs in the coupling graph P of the quantum processor that are isomorphic to the interaction graph G. Each subgraph G j Corresponding to a mapping from G to P, denoted by F j ;

[0239] Step 5: Map the precompiled quantum circuit and the mapping F from G to P j To associate, All feasible first mapping schemes from the first logic quantum circuit to the quantum chip are obtained, where A connection symbol for two maps.

[0240] Step 6: Map all quantum circuits based on the fidelity of the physical quantum gates on the quantum chip Conduct ratings;

[0241] Step 7: Output the optimal mapping of the quantum circuit with the highest score

[0242] The computational time complexity of the quantum chip mapping of this embodiment increases linearly with the number of quantum bits in the quantum chip. Compared with the computational time complexity of the quantum chip mapping in the related art, which increases exponentially or at least polynomially with the number of quantum bits in the quantum chip, its operating efficiency is significantly improved.

[0243] Optionally, the step S105 specifically includes:

[0244] Based on the fidelity of the physical quantum gate on the quantum chip, obtaining the target fidelity of mapping the first logical quantum circuit to the physical quantum circuit on the quantum chip under each first mapping scheme;

[0245] A mapping scheme corresponding to a physical quantum circuit with the largest target fidelity is selected from the first mapping schemes corresponding to the subgraph set to obtain the target mapping scheme.

[0246] In this embodiment, by selecting the mapping scheme corresponding to the physical quantum circuit with the highest target fidelity from the first mapping scheme corresponding to the subgraph set, the symmetry of the grid chip structure can be used to efficiently search for feasible mappings of the quantum circuit, and the optimality of the quantum circuit mapping is guaranteed, thereby improving the fidelity of the quantum circuit.

[0247] In an optional implementation, the fidelity of each physical quantum gate under the first mapping scheme may be superimposed to obtain the fidelity of the physical quantum circuit.

[0248] Optionally, obtaining a target fidelity of mapping the first logical quantum circuit to a physical quantum circuit on the quantum chip under each first mapping scheme based on the fidelity of the physical quantum gate on the quantum chip includes:

[0249] Based on the fidelity of the physical quantum gate on the quantum chip, obtaining the fidelity of the physical quantum gate of the logical quantum gate in the first logical quantum circuit under each first mapping scheme;

[0250] For each first mapping scheme, the fidelity of each physical quantum gate corresponding to the first logical quantum circuit under the first mapping scheme is multiplied to obtain a target fidelity of the physical quantum circuit under the first mapping scheme.

[0251] In this implementation, by multiplying the fidelity of each physical quantum gate under the first mapping scheme, the target fidelity of the physical quantum circuit under the first mapping scheme is obtained, which can improve the accuracy and computational efficiency of the quantum circuit fidelity.

[0252] Optionally, for each logical quantum gate, a mapping relationship of the logical quantum gate to a physical quantum gate under each first mapping scheme and the fidelity of the physical quantum gate are both stored and calculated in a vector form;

[0253] The step of multiplying the fidelity of each physical quantum gate corresponding to the first logical quantum circuit under the first mapping scheme for each first mapping scheme to obtain a target fidelity of the physical quantum circuit under the first mapping scheme includes:

[0254] The first vectors corresponding to the logic quantum gates in the first logic quantum circuit are multiplied by corresponding elements at the same position to obtain a target vector, wherein the target vector includes the target fidelity of the physical quantum circuit under each of the first mapping schemes, and the first vector is a vector of the fidelity of the physical quantum gate of the logic quantum gate under each of the first mapping schemes.

[0255] After finding a set of feasible quantum circuit mappings, it is necessary to evaluate these mappings and select the circuit mapping that maximizes the quantum circuit fidelity (minimizes the error rate). In this embodiment, a scheme for efficiently estimating the quantum circuit fidelity is proposed, which is based on vectorized acceleration and can simultaneously calculate the quantum circuit fidelity corresponding to a large number of quantum circuit mappings. Among them, vectors are represented by bold symbols. The specific process is as follows:

[0256] Input: the first logical quantum circuit, a set of quantum circuit mappings L to be scored, and a mapping V from quantum gates to fidelity;

[0257] Output: The first logical quantum circuit is mapped to the quantum circuit fidelity estimate S of the quantum chip.

[0258] Step 1: Convert the first logical quantum circuit into a quantum gate sequence (i.e., a list of quantum operation instructions) C list ;

[0259] Step 2: The logical quantum gate g in the first logical quantum circuit j ∈C list To loop:

[0260] Step 2.1: Retrieve the logical quantum gate g j The corresponding physical quantum gate g under the mapping of all first mapping schemes i =L(g j ), where g i is a vector containing multiple quantum gate indices;

[0261] Step 2.2: Retrieve the fidelity F corresponding to the physical quantum gate j =V(g i );

[0262] Step 3: Calculate the quantum circuit fidelity S = Π corresponding to the quantum circuit mapping j F j ,∏ j F j is the vector F j The product of corresponding elements in the same position;

[0263] Step 4: Return the calculated quantum circuit fidelity S.

[0264] In this way, the fidelity of the quantum circuit can be efficiently estimated, thereby efficiently determining the optimal mapping scheme for the quantum circuit.

[0265] The quantum circuit mapping method of this embodiment is described in detail with a specific example as follows.

[0266] You can enter Figure 4 The logical quantum circuit shown in Figure 1, each horizontal line represents a quantum bit, denoted by The symbols on the horizontal line represent quantum gates (i.e., logical operations), the symbols on the right side of the horizontal line represent measurements on quantum bits, and quantum gates spanning multiple lines represent dual-qubit gates.

[0267] This quantum circuit can be precompiled using related modules such as Qiskit. It can be seen that the interaction diagram of this quantum circuit can be directly adapted to the coupling diagram of the quantum chip. Therefore, the precompilation process does not change the connectivity of the logical qubits in the quantum circuit.

[0268] like Figure 5 As shown, this is the interaction graph of the input quantum circuit, where each quantum bit in the input quantum circuit corresponds to a node in the graph, and each two-qubit gate in the quantum circuit corresponds to an edge between nodes in the graph.

[0269] By calculating the graph radius r=2 of the interaction graph, the second-order neighborhood of the coupling graph generation set of the quantum processor can be defined as the reduced search space. Figure 6 This is a schematic diagram of the coupling diagram of an example quantum chip. Figure 6 As shown, each circular mark represents a node, that is, a physical quantum bit, and the edges between the nodes represent the coupling connection between the quantum bits. The nodes in box 601 are a generation set of the coupling graph of the quantum chip, and the second-order neighborhood of the generation set is represented by box 602. The subgraph composed of the nodes in box 602 is defined as the reduced search space.

[0270] Figure 6 Each node in the brick structure represents a quantum bit, denoted by q i P (i is a natural number), each edge connecting the nodes represents a coupler between quantum bits, which provides hardware support for two-qubit gate operations.

[0271] In the reduced search space, we search for subgraphs that are isomorphic to the above interaction graph. There are 24 subgraph isomorphic mappings from the interaction graph to the reduced search space. For example, the following mapping. In which, the superscript L represents the logical bit, the superscript P represents the physical bit, and the subscript represents the number of the quantum bit, see Figure 4 and Figure 6 Number.

[0272]

[0273]

[0274]

[0275] For each isomorphic subgraph in the reduced search space, a horizontal and brick diagonal translation is performed until it intersects with the boundary of the quantum processor coupling graph. In particular, consider the case where each row and column of the quantum processor coupling graph contains 150 brick structures, and the processor contains 113703 quantum bits. Through translation, 536408 subgraphs that are isomorphic to the quantum circuit interaction graph can be found in the coupling graph.

[0276] In order to test the efficiency of the subgraph matching, numerical experiments were performed on a MacBook Pro 2020 (subsequent experiments were also based on this computing platform). Experiments show that by using the subgraph matching of this embodiment, the search for all isomorphic subgraphs can be completed within 3.5 seconds. In comparison, the VF2 algorithm can be used to solve the problem, which takes 108 seconds, while VF2++ takes 103 seconds. In other words, the scheme in this embodiment, by utilizing the symmetry of the brick array structure, reduces the solution time of the subgraph matching problem (the core problem of secondary circuit mapping) by 96.6% compared to related schemes.

[0277] The isomorphic subgraphs searched during each subgraph matching process correspond to a feasible quantum circuit mapping. All these feasible circuit mappings need to be evaluated, and the mapping that maximizes the quantum circuit fidelity is selected as the output. To this end, a heuristic quantum circuit fidelity estimation function is used. This function multiplies the fidelity of all quantum gates in the quantum circuit as an estimate of the quantum circuit fidelity.

[0278] For example, suppose the quantum circuit mapping M is Figure 4 The 20 quantum gates contained in the quantum circuit Mapping to actual quantum gates on a quantum processor Further, suppose the fidelity of these actual quantum gates is F i P (i=1, 2, ..., 20) The quantum circuit mapping M is scored as follows according to the following formula (1).

[0279]

[0280] Using the vectorized accelerated circuit mapping scoring function, all searched quantum circuit mappings {M j}Perform this evaluation process to obtain the fidelity of all circuit mappings and store them in the form of a binary array S = {(M j ,Score(M j ))}.

[0281] We can traverse all quantum circuit mappings in S and search for the mapping M with the highest score (i.e., the highest fidelity) opt :=argmax j Score(M j ) and returns it as the target mapping scheme.

[0282] In order to demonstrate the scalability of the quantum circuit mapping scheme of this embodiment, this scheme can be used to Figure 4 The quantum circuit in is mapped onto a quantum chip with a brick array structure of l rows and l columns, where l is 20, 30, ..., 150. In this process, the running time required for the subgraph matching and complete circuit mapping proposed in this embodiment is tested respectively, and compared with related solutions.

[0283] In the subgraph matching step, it is necessary to search for all isomorphic mappings from the interaction graph of the logical quantum circuit to the coupling graph of the quantum hardware. The efficient subgraph matching scheme using the symmetry of the brick array structure, the VF2 scheme, and the VF2++ scheme of this embodiment are used to complete this task. The corresponding running times are shown in Figure 7 .

[0284] Figure 7 The horizontal axis represents the number of quantum bits in the quantum chip, and the vertical axis represents the time required to complete the subgraph isomorphism mapping search. The three curves, namely curve 701, curve 702 and curve 703, respectively represent the running time of the efficient subgraph matching scheme using the symmetry of the brick array structure, the VF2 scheme and the VF2++ scheme of this embodiment.

[0285] As the number of quantum bits in the quantum chip increases, the time required for the VF2 algorithm and the VF2++ algorithm to complete the subgraph matching task increases significantly, while the running time of the subgraph matching algorithm of this embodiment remains almost unchanged. In other words, when the number of bits in the quantum chip increases, the subgraph matching algorithm of this embodiment runs significantly faster than the traditional subgraph matching algorithms VF2 and VF2++. This shows that the subgraph matching algorithm of this embodiment has good scalability.

[0286] Considering the running time required for the complete circuit mapping scheme in this embodiment, the numerical experimental test is conducted for quantum chips of different sizes to find Figure 4 The running time required for the optimal mapping of the input quantum circuit shown in Figure 2 is 1. The quantum chip is set to a brick array structure with l rows and l columns, which is the same as the previous two numerical experiments. The experimental results are shown in Figure 8 .

[0287] Figure 8 The horizontal axis represents the number of quantum bits in the quantum chip, and the vertical axis represents the running time of the quantum circuit mapping scheme. The two curves in the figure, namely curve 801 and curve 802, respectively represent the efficient circuit mapping scheme of this embodiment and other mapping schemes.

[0288] Figure 8 It shows that the time required for the quantum circuit mapping scheme of this embodiment to determine the optimal circuit mapping from a given quantum circuit to a quantum chip is significantly lower than that of other schemes. As the number of quantum bits in the quantum chip increases, the running time of other schemes increases significantly, while the circuit mapping search time of this embodiment increases slowly. This shows that the quantum circuit mapping scheme of this embodiment has a significant advantage in computational complexity compared to related schemes, and is particularly suitable for quantum circuit mapping of large-scale quantum chips.

[0289] Second embodiment

[0290] like Fig. 9 As shown, the present disclosure provides a quantum circuit mapping device 900, comprising:

[0291] An acquisition module 901 is used to acquire a coupling graph of the quantum chip and a node index of the coupling graph based on the arrangement structure information of the quantum bits on the quantum chip; and to acquire an interaction graph of a first logic quantum circuit precompiled onto the quantum chip; the arrangement structure information indicates that the quantum bits on the quantum chip are arranged in a brick array structure, and the node index indicates a mapping relationship between the node position coordinates of the quantum bits and the node labels, and the brick array structure is formed by stacking a first type of brick structure and a second type of brick structure, and the second type of brick structure is stacked between two adjacent first type of brick structures;

[0292] A search module 902, configured to search a first subgraph isomorphic to the interaction graph in a reduced search space of the coupling graph, the reduced search space comprising a set of nodes in the coupling graph whose distances from a generated set do not exceed a specified distance, the specified distance being greater than or equal to a radius of the interaction graph, and the generated set covering the coupling graph under a matching translation operation;

[0293] A translation operation module 903 is used to perform a translation operation on the first subgraph on the coupling graph that matches the generated set based on the node index and utilize the brick array structure of the coupling graph to obtain a second subgraph that is isomorphic to the interaction graph;

[0294] The first determining module 904 is used to determine each subgraph in the subgraph set. Figure 1a corresponding first mapping scheme, wherein the first mapping scheme is a mapping scheme from the first logic quantum circuit to the quantum chip, and the subgraph set includes the first subgraph and the second subgraph;

[0295] The second determination module 905 is used to determine a target mapping scheme from the first logical quantum circuit to the quantum chip from the first mapping scheme corresponding to the subgraph set based on the fidelity of the physical quantum gate on the quantum chip.

[0296] Optionally, the acquisition module 901 includes:

[0297] A graph creation unit, used to create a node for each quantum bit on the quantum chip to construct a coupling graph of the quantum chip;

[0298] A first determining unit, configured to determine the node numbers and node position coordinates of the quantum bits on the quantum chip based on the layout information of the brick structure arranged on the quantum chip, wherein the arrangement structure information includes the layout information;

[0299] The relationship establishing unit is used to establish a mapping relationship between the node position coordinates of the quantum bit and the node label to obtain the node index of the coupling graph.

[0300] Optionally, the first determining unit is specifically configured to:

[0301] Determining, based on the layout information of the brick structure arranged on the quantum chip, a node number and a node position coordinate of a first quantum bit on the quantum chip, where the first quantum bit is a quantum bit interconnected in the horizontal direction of the quantum chip;

[0302] The node number of a second quantum bit on the quantum chip is determined based on the layout information and the node number of the first quantum bit, and the node position coordinates of the second quantum bit are determined based on the layout information, wherein the second quantum bit is a quantum bit on the quantum chip other than the first quantum bit.

[0303] Optionally, the node number of the quantum bit on the quantum chip is determined by at least one of the following methods:

[0304] Based on the layout information of the brick structure arranged on the quantum chip, the first quantum bit on the quantum chip is numbered in a preset order to obtain a node number of the first quantum bit, wherein the preset order is from left to right and from bottom to top;

[0305] Based on the layout information and the node number of the first quantum bit, the second quantum bits on the quantum chip are numbered in the preset order to obtain the node number of the second quantum bit.

[0306] Optionally, the node label of the first quantum bit is: node_index = i*(4×width+3)+j, i is the row position of the node corresponding to the first quantum bit, i∈{0,1,...,height}, j is the column position of the node corresponding to the first quantum bit, j∈{0,1,...,4×width+2}, height is the number of rows of the first type and second type of brick structures arranged on the quantum chip, width is the number of columns of the second type of brick structures arranged on the quantum chip, and the layout information includes the number of rows and columns.

[0307] Optionally, the node position coordinates of the quantum bit on the quantum chip are (x1, x2, k), where x1 represents the coordinate component of the brick structure to which the quantum bit corresponding node belongs in the horizontal direction in the affine coordinate system, and x2 represents the coordinate component of the brick structure to which the quantum bit corresponding node belongs in the diagonal direction of the brick in the affine coordinate system, and the diagonal direction of the brick forms an angle of 45° with the horizontal direction, and k is the relative position of the node corresponding to the quantum bit in the brick structure to which it belongs;

[0308] The node position coordinates of the quantum bits on the quantum chip are determined by at least one of the following methods:

[0309] In the case where the qubit is a first qubit, x2=i, k=(2i+j)%4, i∈{0,1,...,height}, j∈{0,1,...,4×width+2};

[0310] In the case where the qubit is a second qubit, x2=i, k=4, i∈{0,1,...,height-1}, j∈{0,1,...,width};

[0311] Among them, height is the number of rows of the first type and the second type of brick structures arranged on the quantum chip, width is the number of columns of the second type of brick structures arranged on the quantum chip, and the layout information includes the number of rows and the number of columns.

[0312] Optionally, the generated set includes any of the following:

[0313] Each node of two adjacent brick structures arranged vertically in the coupling graph;

[0314] The four adjacent nodes in the horizontal direction of any brick structure in the coupling diagram, and the target node in the brick structure, the line formed by the four adjacent nodes intersects vertically with the line belonging to the target node.

[0315] Optional, where

[0316] In the case where the spanning set includes nodes of two adjacent brick structures arranged vertically in the coupling graph, the translation operation matching the spanning set includes: translation in the horizontal direction and the vertical direction;

[0317] In the case where the generation set includes four adjacent nodes in the horizontal direction of any brick structure in the coupling graph and a target node in the brick structure, the translation operations matching the generation set include: translation in the horizontal direction and in the diagonal direction of the brick.

[0318] Optionally, the translation operation module 903 includes:

[0319] A second determining unit is used to determine, based on the node index, a value range of a target translation operation performed on the first subgraph in the coupling graph, wherein the subgraph obtained after the target translation operation does not exceed a boundary of the coupling graph, and the target translation operation is a translation operation in a translation direction matched by the generated set;

[0320] A label updating unit is used to update the node labels of the first subgraph within the value range based on the node index to obtain a second subgraph isomorphic to the interaction graph.

[0321] Optionally, when the generated set includes four adjacent nodes in the horizontal direction of any brick structure in the coupling graph and a target node in the brick structure, the target translation operation is to translate the first subgraph in the diagonal direction and the horizontal direction of the bricks in sequence, so that the line formed by the four adjacent nodes intersects vertically with the line belonging to the target node, and the second determining unit is specifically used to:

[0322] Based on the node index, determining the number of steps required for the first subgraph to move horizontally and vertically to the boundary of the coupling graph in units of brick structures; and based on the number of steps required for the first subgraph to move horizontally and vertically to the boundary of the coupling graph, determining a first value range for the first subgraph to perform a target translation operation in the coupling graph, wherein the first value range represents a displacement vector of the first subgraph in an affine coordinate system, and the number of steps for the first subgraph to move vertically is an even number;

[0323] Based on the node index, determine the number of steps required for the target subgraph to move horizontally and vertically to the boundary of the coupling graph in units of brick structure; and based on the number of steps required for the target subgraph to move horizontally and vertically to the boundary of the coupling graph, determine a second value range for the first subgraph to perform a target translation operation in the coupling graph, the second value range represents a displacement vector of the first subgraph in an affine coordinate system, the number of steps for the vertical movement of the target subgraph is an even number, and the target subgraph is a subgraph obtained by translating the first subgraph in units of brick structure in the diagonal direction of the brick by one step;

[0324] The value range includes the first value range and the second value range.

[0325] Optionally, the second determining unit is specifically configured to:

[0326] Based on the node labels of the first subgraph, retrieve the node position coordinates of the first subgraph in the node index;

[0327] Based on the node position coordinates of the first subgraph and the layout information of the brick structures arranged on the quantum chip, the number of steps required for the first subgraph to move horizontally and vertically to the boundary of the coupling graph in units of brick structures is determined.

[0328] Optionally, the number of steps required for the first subgraph to move horizontally to the left to the boundary of the coupling graph in units of brick structures is: index x is the horizontal position of each node in the first subgraph;

[0329] The number of steps required for the first subgraph to move horizontally to the right to the boundary of the coupling graph in units of brick structure is: p is the number of nodes in the horizontal direction of the coupling graph;

[0330] The number of steps required for the first subgraph to move vertically downward to the boundary of the coupling graph in units of brick structures is: min(index y ), index y is the vertical position of each node in the first subgraph;

[0331] The number of steps required for the first subgraph to move vertically upward to the boundary of the coupling graph in units of brick structures is: height-max(index y )-1, height is the number of rows of the first type and the second type of brick structures arranged on the quantum chip.

[0332] Optionally, the second determining unit is further configured to:

[0333] Determine, based on the number of steps required for the first subgraph to move horizontally and vertically to the boundary of the coupling graph, an update range of the node position coordinates of the first subgraph during a first translation process on the coupling graph, wherein the first translation process includes movement in horizontal and diagonal directions;

[0334] Based on the update range, the first value range is determined using a target formula, the target formula including a first formula And the second formula m, n is the number of steps of horizontal movement of the sub-graph in the coupling graph, m is the number of steps of vertical movement of the sub-graph in the coupling graph, and the target formula is used to determine the number of translation steps of the sub-graph in the affine coordinate system.

[0335] Optionally, the label updating unit is specifically used to:

[0336] Updating the node position coordinates of the first subgraph within the value range;

[0337] Based on the updated node position coordinates of the first subgraph, the updated node labels of the first subgraph are retrieved from the node index to obtain a second subgraph isomorphic to the interaction graph.

[0338] Optionally, the device further comprises:

[0339] A third determination module is used to determine the r-order neighborhood of the generated set, where r is the radius of the interaction graph;

[0340] The fourth determination module is used to determine the r-order neighborhood as the reduced search space of the coupling graph.

[0341] Optionally, the radius of the interaction graph is determined by:

[0342] Taking the node located in the central area of ​​the interaction graph as the target node, obtaining the maximum step length from the node in the interaction graph to the target node, and obtaining the target step length corresponding to the target node;

[0343] The step length with the shortest distance among the target step lengths corresponding to the target nodes in the central area is determined as the radius of the interaction graph.

[0344] Optionally, the first determining module 904 is specifically configured to:

[0345] Obtain a second mapping scheme from the first logic quantum circuit to the quantum chip, and obtain a third mapping scheme corresponding to each subgraph in the subgraph set, respectively, wherein the third mapping scheme is a mapping scheme from the interaction graph to the quantum chip;

[0346] The second mapping scheme is associated with each of the third mapping schemes to obtain a subgraph set for each subgraph. Figure 1 A corresponding first mapping scheme.

[0347] Optionally, the second determining module 905 includes:

[0348] A fidelity acquisition unit, configured to acquire, based on the fidelity of the physical quantum gate on the quantum chip, a target fidelity of mapping the first logical quantum circuit to the physical quantum circuit on the quantum chip under each first mapping scheme;

[0349] A scheme selection unit is used to select a mapping scheme corresponding to a physical quantum circuit with the largest target fidelity from the first mapping schemes corresponding to the subgraph set to obtain the target mapping scheme.

[0350] Optionally, the fidelity acquisition unit is specifically used to:

[0351] Based on the fidelity of the physical quantum gate on the quantum chip, obtaining the fidelity of the physical quantum gate of the logical quantum gate in the first logical quantum circuit under each first mapping scheme;

[0352] For each first mapping scheme, the fidelity of each physical quantum gate corresponding to the first logical quantum circuit under the first mapping scheme is multiplied to obtain a target fidelity of the physical quantum circuit under the first mapping scheme.

[0353] Optionally, for each logical quantum gate, the mapping relationship of the logical quantum gate to the physical quantum gate under each first mapping scheme and the fidelity of the physical quantum gate are stored and calculated in vector form; the fidelity acquisition unit is specifically used to multiply the first vectors corresponding to each logical quantum gate in the first logical quantum circuit by corresponding elements at the same position to obtain a target vector, wherein the target vector includes the target fidelity of the physical quantum circuit under each first mapping scheme, and the first vector is the vector of the fidelity of the physical quantum gate of the logical quantum gate under each first mapping scheme.

[0354] Optionally, the acquisition module 901 includes:

[0355] A region selection unit, configured to select a local region in the region range of the quantum chip, wherein the number of physical quantum bits deployed in the local region is greater than or equal to the number of logical quantum bits of the second logical quantum circuit;

[0356] A pre-compilation unit is used to pre-compile the second logic quantum circuit into the local area to obtain an interaction diagram of the first logic quantum circuit.

[0357] The quantum circuit mapping device 900 provided in the present disclosure can implement each process implemented by the quantum circuit mapping method embodiment and can achieve the same beneficial effects. To avoid repetition, it will not be described here.

[0358] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0359] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.

[0360] Fig.10 A schematic block diagram of an example electronic device that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0361] like Fig.10 As shown, the device 1000 includes a computing unit 1001, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 1002 or a computer program loaded from a storage unit 1008 into a random access memory (RAM) 1003. In the RAM 1003, various programs and data required for the operation of the device 1000 can also be stored. The computing unit 1001, the ROM 1002, and the RAM 1003 are connected to each other via a bus 1004. An input / output (I / O) interface 1005 is also connected to the bus 1004.

[0362] A number of components in the device 1000 are connected to the I / O interface 1005, including: an input unit 1006, such as a keyboard, a mouse, etc.; an output unit 1007, such as various types of displays, speakers, etc.; a storage unit 1008, such as a disk, an optical disk, etc.; and a communication unit 1009, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 1009 allows the device 1000 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0363] The computing unit 1001 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 1001 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 1001 performs the various methods and processes described above, such as the quantum circuit mapping method. For example, in some embodiments, the quantum circuit mapping method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 1008. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 1000 via the ROM 1002 and / or the communication unit 1009. When the computer program is loaded into the RAM 1003 and executed by the computing unit 1001, one or more steps of the quantum circuit mapping method described above may be performed. Alternatively, in other embodiments, the computing unit 1001 may be configured to execute the quantum circuit mapping method in any other appropriate manner (for example, by means of firmware).

[0364] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0365] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0366] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0367] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0368] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0369] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0370] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0371] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A quantum circuit mapping method, comprising: Based on the arrangement structure information of the quantum bits on the quantum chip, obtaining a coupling graph of the quantum chip and a node index of the coupling graph; and obtaining an interaction graph of a first logic quantum circuit precompiled onto the quantum chip; the arrangement structure information indicates that the quantum bits on the quantum chip are arranged in a brick array structure, the node index indicates a mapping relationship between the node position coordinates of the quantum bit and the node number, the brick array structure is formed by stacking a first type of brick structure and a second type of brick structure, and the second type of brick structure is stacked between two adjacent first type of brick structures; searching for a first subgraph isomorphic to the interaction graph in a reduced search space of the coupling graph, the reduced search space comprising a set of nodes in the coupling graph whose distances to a spanning set do not exceed a specified distance, the specified distance being greater than or equal to a radius of the interaction graph, and the spanning set covering the coupling graph under a matching translation operation; Based on the node index, using the brick array structure of the coupling graph, a translation operation matching the generation set is performed on the first subgraph on the coupling graph to obtain a second subgraph isomorphic to the interaction graph; Determine a first mapping scheme that corresponds one-to-one to each subgraph in a subgraph set, where the first mapping scheme is a mapping scheme from the first logic quantum circuit to the quantum chip, and the subgraph set includes the first subgraph and the second subgraph; Based on the fidelity of the physical quantum gate on the quantum chip, determine a target mapping scheme from the first logical quantum circuit to the quantum chip from the first mapping scheme corresponding to the subgraph set; The generated set includes any of the following: Each node of two adjacent brick structures arranged vertically in the coupling graph; The four adjacent nodes in the horizontal direction of any brick structure in the coupling diagram, and the target node in the brick structure, the line formed by the four adjacent nodes intersects vertically with the line belonging to the target node.

2. The method according to claim 1, wherein: The step of obtaining a coupling graph of the quantum chip and a node index of the coupling graph based on the arrangement structure information of quantum bits on the quantum chip includes: Creating a node for each quantum bit on the quantum chip to construct a coupling graph of the quantum chip; Determining node numbers and node position coordinates of quantum bits on the quantum chip based on layout information of the brick structure arranged on the quantum chip, wherein the arrangement structure information includes the layout information; A mapping relationship between the node position coordinates of the quantum bit and the node label is established to obtain the node index of the coupling graph.

3. The method according to claim 2, wherein: The step of determining the node numbers and node position coordinates of the quantum bits on the quantum chip based on the layout information of the brick structure arranged on the quantum chip includes: Determining, based on the layout information of the brick structure arranged on the quantum chip, a node number and a node position coordinate of a first quantum bit on the quantum chip, where the first quantum bit is a quantum bit interconnected in the horizontal direction of the quantum chip; The node number of a second quantum bit on the quantum chip is determined based on the layout information and the node number of the first quantum bit, and the node position coordinates of the second quantum bit are determined based on the layout information, wherein the second quantum bit is a quantum bit on the quantum chip other than the first quantum bit.

4. The method according to claim 3, wherein: The node number of the quantum bit on the quantum chip is determined by at least one of the following methods: Based on the layout information of the brick structure arranged on the quantum chip, the first quantum bit on the quantum chip is numbered in a preset order to obtain a node number of the first quantum bit, wherein the preset order is from left to right and from bottom to top; Based on the layout information and the node number of the first quantum bit, the second quantum bits on the quantum chip are numbered in the preset order to obtain the node number of the second quantum bit.

5. The method according to claim 3, wherein: The node label of the first quantum bit is: node_index=i*(4×width+3)+j, i is the row position of the node corresponding to the first quantum bit, i∈{0,1,...,height}, j is the column position of the node corresponding to the first quantum bit, j∈{0,1,...,4×width+2}, height is the number of rows of the first type and second type of brick structures arranged on the quantum chip, width is the number of columns of the second type of brick structures arranged on the quantum chip, and the layout information includes the number of rows and columns.

6. The method according to claim 3, wherein: The node position coordinates of the quantum bit on the quantum chip are (x1, x2, k), where x1 represents the coordinate component of the brick structure to which the quantum bit corresponding node belongs in the horizontal direction in the affine coordinate system, and x2 represents the coordinate component of the brick structure to which the quantum bit corresponding node belongs in the diagonal direction of the brick in the affine coordinate system, and the diagonal direction of the brick forms an angle of 45° with the horizontal direction, and k is the relative position of the node corresponding to the quantum bit in the brick structure to which it belongs; The node position coordinates of the quantum bits on the quantum chip are determined by at least one of the following methods: In the case where the qubit is a first qubit, x2=i, k=(2i+j)%4, i∈{0,1,...,height}, j∈{0,1,...,4×width+2}; In the case where the qubit is a second qubit, x2=i, k=4, i∈{0,1,...,height-1}, j∈{0,1,...,width}; Among them, height is the number of rows of the first type and the second type of brick structures arranged on the quantum chip, width is the number of columns of the second type of brick structures arranged on the quantum chip, and the layout information includes the number of rows and the number of columns.

7. The method according to claim 1, wherein: In the case where the spanning set includes nodes of two adjacent brick structures arranged vertically in the coupling graph, the translation operation matching the spanning set includes: translation in the horizontal direction and the vertical direction; In the case where the generation set includes four adjacent nodes in the horizontal direction of any brick structure in the coupling graph and a target node in the brick structure, the translation operations matching the generation set include: translation in the horizontal direction and in the diagonal direction of the brick.

8. The method according to claim 1, wherein: The step of performing a translation operation on the first subgraph on the coupling graph that matches the spanning set based on the node index and utilizing the brick array structure of the coupling graph to obtain a second subgraph that is isomorphic to the interaction graph includes: Based on the node index, determining a value range of a target translation operation of the first subgraph in the coupling graph, wherein the subgraph obtained after the target translation operation does not exceed a boundary of the coupling graph, and the target translation operation is a translation operation in a translation direction matched by the generated set; Based on the node index, the node labels of the first subgraph are updated within the value range to obtain a second subgraph isomorphic to the interaction graph.

9. The method according to claim 8, wherein: In the case where the generated set includes four adjacent nodes in the horizontal direction of any brick structure in the coupling graph and a target node in the brick structure, the target translation operation is to translate the first subgraph in the diagonal direction and the horizontal direction of the bricks in sequence, and the line formed by the four adjacent nodes intersects vertically with the line belonging to the target node. The value range of the target translation operation of the first subgraph in the coupling graph is determined based on the node index, including: Based on the node index, determining the number of steps required for the first subgraph to move horizontally and vertically to the boundary of the coupling graph in units of brick structures; and based on the number of steps required for the first subgraph to move horizontally and vertically to the boundary of the coupling graph, determining a first value range for the first subgraph to perform a target translation operation in the coupling graph, wherein the first value range represents a displacement vector of the first subgraph in an affine coordinate system, and the number of steps for the first subgraph to move vertically is an even number; Based on the node index, determine the number of steps required for the target subgraph to move horizontally and vertically to the boundary of the coupling graph in units of brick structure; and based on the number of steps required for the target subgraph to move horizontally and vertically to the boundary of the coupling graph, determine a second value range for the first subgraph to perform a target translation operation in the coupling graph, the second value range represents a displacement vector of the first subgraph in an affine coordinate system, the number of steps for the vertical movement of the target subgraph is an even number, and the target subgraph is a subgraph obtained by translating the first subgraph in units of brick structure in the diagonal direction of the brick by one step; The value range includes the first value range and the second value range.

10. The method according to claim 9, wherein: The determining, based on the node index, the number of steps required for the first subgraph to move horizontally and vertically to the boundary of the coupling graph in units of brick structures, comprises: Based on the node labels of the first subgraph, retrieve the node position coordinates of the first subgraph in the node index; Based on the node position coordinates of the first subgraph and the layout information of the brick structures arranged on the quantum chip, the number of steps required for the first subgraph to move horizontally and vertically to the boundary of the coupling graph in units of brick structures is determined.

11. The method according to claim 10, wherein: The number of steps required for the first subgraph to move horizontally to the left to the boundary of the coupling graph in units of brick structure is: index x is the horizontal position of each node in the first subgraph; The number of steps required for the first subgraph to move horizontally to the right to the boundary of the coupling graph in units of brick structure is: p is the number of nodes in the horizontal direction of the coupling graph; The number of steps required for the first subgraph to move vertically downward to the boundary of the coupling graph in units of brick structures is: min(index y ), index y is the vertical position of each node in the first subgraph; The number of steps required for the first subgraph to move vertically upward to the boundary of the coupling graph in units of brick structures is: height-max(index y )-1, height is the number of rows of the first type and the second type of brick structures arranged on the quantum chip.

12. The method according to claim 9, wherein: The determining, based on the number of steps required for the first subgraph to move horizontally and vertically to the boundary of the coupling graph respectively, a first value range for the first subgraph to perform a target translation operation in the coupling graph comprises: Determine, based on the number of steps required for the first subgraph to move horizontally and vertically to the boundary of the coupling graph, an update range of the node position coordinates of the first subgraph in a first translation process on the coupling graph, wherein the first translation process includes horizontal and vertical movement; Based on the update range, the first value range is determined using a target formula, the target formula including a first formula And the second formula m, n is the number of steps of horizontal movement of the sub-graph in the coupling graph, m is the number of steps of vertical movement of the sub-graph in the coupling graph, and the target formula is used to determine the number of translation steps of the sub-graph in the affine coordinate system.

13. The method according to claim 8, wherein: The updating of the node labels of the first subgraph within the value range based on the node index to obtain a second subgraph isomorphic to the interaction graph includes: Updating the node position coordinates of the first subgraph within the value range; Based on the updated node position coordinates of the first subgraph, the updated node labels of the first subgraph are retrieved from the node index to obtain a second subgraph isomorphic to the interaction graph.

14. The method according to claim 1, before searching the first subgraph isomorphic to the interaction graph in the reduced search space of the coupling graph, further comprising: Determining an r-order neighborhood of the generated set, where r is the radius of the interaction graph; The r-order neighborhood is determined as a reduced search space of the coupling graph.

15. The method according to claim 1, wherein: The radius of the interaction map is determined by: Taking the node located in the central area of ​​the interaction graph as the target node, obtaining the maximum step length from the node in the interaction graph to the target node, and obtaining the target step length corresponding to the target node; The step length with the shortest distance among the target step lengths corresponding to the target nodes in the central area is determined as the radius of the interaction graph.

16. The method according to claim 1, wherein: The determining of a first mapping scheme in which each subgraph in the subgraph set corresponds to each other includes: Obtain a second mapping scheme from the first logic quantum circuit to the quantum chip, and obtain a third mapping scheme corresponding to each subgraph in the subgraph set, respectively, wherein the third mapping scheme is a mapping scheme from the interaction graph to the quantum chip; The second mapping scheme is associated with each of the third mapping schemes to obtain a first mapping scheme corresponding to each subgraph in the subgraph set.

17. The method according to claim 1, wherein: The step of determining a target mapping scheme from the first logical quantum circuit to the quantum chip from a first mapping scheme corresponding to the subgraph set based on the fidelity of the physical quantum gate on the quantum chip comprises: Based on the fidelity of the physical quantum gate on the quantum chip, obtaining the target fidelity of mapping the first logical quantum circuit to the physical quantum circuit on the quantum chip under each first mapping scheme; A mapping scheme corresponding to a physical quantum circuit with the largest target fidelity is selected from the first mapping schemes corresponding to the subgraph set to obtain the target mapping scheme.

18. The method according to claim 17, wherein: The obtaining, based on the fidelity of the physical quantum gate on the quantum chip, a target fidelity of mapping the first logical quantum circuit to the physical quantum circuit on the quantum chip under each first mapping scheme comprises: Based on the fidelity of the physical quantum gate on the quantum chip, obtaining the fidelity of the physical quantum gate of the logical quantum gate in the first logical quantum circuit under each first mapping scheme; For each first mapping scheme, the fidelity of each physical quantum gate corresponding to the first logical quantum circuit under the first mapping scheme is multiplied to obtain a target fidelity of the physical quantum circuit under the first mapping scheme.

19. The method according to claim 18, wherein: For each logical quantum gate, the mapping relationship of the logical quantum gate to the physical quantum gate under each first mapping scheme and the fidelity of the physical quantum gate are stored and calculated in vector form; The step of multiplying the fidelity of each physical quantum gate corresponding to the first logical quantum circuit under the first mapping scheme for each first mapping scheme to obtain a target fidelity of the physical quantum circuit under the first mapping scheme includes: The first vectors corresponding to the logic quantum gates in the first logic quantum circuit are multiplied by corresponding elements at the same position to obtain a target vector, wherein the target vector includes the target fidelity of the physical quantum circuit under each of the first mapping schemes, and the first vector is a vector of the fidelity of the physical quantum gate of the logic quantum gate under each of the first mapping schemes.

20. The method according to claim 1, wherein: The obtaining of the interaction graph of the first logic quantum circuit precompiled onto the quantum chip comprises: Selecting a local area in the area range of the quantum chip, wherein the number of physical quantum bits deployed in the local area is greater than or equal to the number of logical quantum bits of the second logical quantum circuit; The second logic quantum circuit is precompiled onto the local region to obtain an interaction graph of the first logic quantum circuit.

21. A quantum circuit mapping device, comprising: An acquisition module, used to acquire a coupling graph of the quantum chip and a node index of the coupling graph based on the arrangement structure information of the quantum bits on the quantum chip; and obtaining an interaction graph of a first logic quantum circuit precompiled onto the quantum chip; the arrangement structure information indicates that the quantum bits on the quantum chip are arranged in a brick array structure, the node index indicates a mapping relationship between the node position coordinates of the quantum bit and the node number, the brick array structure is formed by stacking a first type of brick structure and a second type of brick structure, and the second type of brick structure is stacked between two adjacent first type of brick structures; A search module, configured to search a first subgraph isomorphic to the interaction graph in a reduced search space of the coupling graph, the reduced search space comprising a set of nodes in the coupling graph whose distances from a generated set do not exceed a specified distance, the specified distance being greater than or equal to a radius of the interaction graph, and the generated set covering the coupling graph under a matching translation operation; A translation operation module, configured to perform a translation operation on the first subgraph on the coupling graph that matches the generated set based on the node index and utilize the brick array structure of the coupling graph to obtain a second subgraph that is isomorphic to the interaction graph; A first determining module is used to determine a first mapping scheme corresponding one-to-one to each subgraph in a subgraph set, wherein the first mapping scheme is a mapping scheme from the first logic quantum circuit to the quantum chip, and the subgraph set includes the first subgraph and the second subgraph; A second determination module is used to determine a target mapping scheme from the first logical quantum circuit to the quantum chip from the first mapping scheme corresponding to the subgraph set based on the fidelity of the physical quantum gate on the quantum chip; The generated set includes any of the following: Each node of two adjacent brick structures arranged vertically in the coupling graph; The four adjacent nodes in the horizontal direction of any brick structure in the coupling diagram, and the target node in the brick structure, the line formed by the four adjacent nodes intersects vertically with the line belonging to the target node.

22. The device according to claim 21, wherein The acquisition module comprises: A graph creation unit, used to create a node for each quantum bit on the quantum chip to construct a coupling graph of the quantum chip; A first determining unit, configured to determine the node numbers and node position coordinates of the quantum bits on the quantum chip based on the layout information of the brick structure arranged on the quantum chip, wherein the arrangement structure information includes the layout information; The relationship establishing unit is used to establish a mapping relationship between the node position coordinates of the quantum bit and the node label to obtain the node index of the coupling graph.

23. The device according to claim 22, wherein: The first determining unit is specifically configured to: Determining, based on the layout information of the brick structure arranged on the quantum chip, a node number and a node position coordinate of a first quantum bit on the quantum chip, where the first quantum bit is a quantum bit interconnected in the horizontal direction of the quantum chip; The node number of a second quantum bit on the quantum chip is determined based on the layout information and the node number of the first quantum bit, and the node position coordinates of the second quantum bit are determined based on the layout information, wherein the second quantum bit is a quantum bit on the quantum chip other than the first quantum bit.

24. The device according to claim 23, wherein: The node number of the quantum bit on the quantum chip is determined by at least one of the following methods: Based on the layout information of the brick structure arranged on the quantum chip, the first quantum bit on the quantum chip is numbered in a preset order to obtain a node number of the first quantum bit, wherein the preset order is from left to right and from bottom to top; Based on the layout information and the node number of the first quantum bit, the second quantum bits on the quantum chip are numbered in the preset order to obtain the node number of the second quantum bit.

25. The device according to claim 23, wherein: The node label of the first quantum bit is: node_index=i*(4×width+3)+j, i is the row position of the node corresponding to the first quantum bit, i∈{0,1,...,height}, j is the column position of the node corresponding to the first quantum bit, j∈{0,1,...,4×width+2}, height is the number of rows of the first type and second type of brick structures arranged on the quantum chip, width is the number of columns of the second type of brick structures arranged on the quantum chip, and the layout information includes the number of rows and columns.

26. The device according to claim 23, wherein The node position coordinates of the quantum bit on the quantum chip are (x1, x2, k), where x1 represents the coordinate component of the brick structure to which the quantum bit corresponding node belongs in the horizontal direction in the affine coordinate system, and x2 represents the coordinate component of the brick structure to which the quantum bit corresponding node belongs in the diagonal direction of the brick in the affine coordinate system, and the diagonal direction of the brick forms an angle of 45° with the horizontal direction, and k is the relative position of the node corresponding to the quantum bit in the brick structure to which it belongs; The node position coordinates of the quantum bits on the quantum chip are determined by at least one of the following methods: In the case where the qubit is a first qubit, x2=i, k=(2i+j)%4, i∈{0,1,...,height}, j∈{0,1,...,4×width+2}; In the case where the qubit is a second qubit, x2=i, k=4, i∈{0,1,...,height-1}, j∈{0,1,...,width}; Among them, height is the number of rows of the first type and the second type of brick structures arranged on the quantum chip, width is the number of columns of the second type of brick structures arranged on the quantum chip, and the layout information includes the number of rows and the number of columns.

27. The device according to claim 21, wherein In the case where the spanning set includes nodes of two adjacent brick structures arranged vertically in the coupling graph, the translation operation matching the spanning set includes: translation in the horizontal direction and the vertical direction; In the case where the generation set includes four adjacent nodes in the horizontal direction of any brick structure in the coupling graph and a target node in the brick structure, the translation operations matching the generation set include: translation in the horizontal direction and in the diagonal direction of the brick.

28. The device according to claim 21, wherein The translation operation module includes: A second determining unit is used to determine, based on the node index, a value range of a target translation operation performed on the first subgraph in the coupling graph, wherein the subgraph obtained after the target translation operation does not exceed a boundary of the coupling graph, and the target translation operation is a translation operation in a translation direction matched by the generated set; A label updating unit is used to update the node labels of the first subgraph within the value range based on the node index to obtain a second subgraph isomorphic to the interaction graph.

29. The device according to claim 28, wherein In the case where the generated set includes four adjacent nodes in the horizontal direction of any brick structure in the coupling graph and a target node in the brick structure, the target translation operation is to translate the first subgraph in the diagonal direction and the horizontal direction of the bricks in sequence, so that the line formed by the four adjacent nodes intersects vertically with the line belonging to the target node, and the second determining unit is specifically used to: Based on the node index, determining the number of steps required for the first subgraph to move horizontally and vertically to the boundary of the coupling graph in units of brick structures; and based on the number of steps required for the first subgraph to move horizontally and vertically to the boundary of the coupling graph, determining a first value range for the first subgraph to perform a target translation operation in the coupling graph, wherein the first value range represents a displacement vector of the first subgraph in an affine coordinate system, and the number of steps for the first subgraph to move vertically is an even number; Based on the node index, determining the number of steps required for the target subgraph to move horizontally and vertically to the boundary of the coupling graph in units of brick structures; Based on the number of steps required for the target subgraph to move horizontally and vertically to the boundary of the coupling graph respectively, a second value range for the target translation operation of the first subgraph in the coupling graph is determined, the second value range represents the displacement vector of the first subgraph in an affine coordinate system, the number of steps for the vertical movement of the target subgraph is an even number, and the target subgraph is a subgraph obtained by translating the first subgraph by one step in the diagonal direction of the bricks in units of brick structures; The value range includes the first value range and the second value range.

30. The device according to claim 29, wherein: The second determining unit is specifically configured to: Based on the node labels of the first subgraph, retrieve the node position coordinates of the first subgraph in the node index; Based on the node position coordinates of the first subgraph and the layout information of the brick structures arranged on the quantum chip, the number of steps required for the first subgraph to move horizontally and vertically to the boundary of the coupling graph in units of brick structures is determined.

31. The device according to claim 30, wherein The number of steps required for the first subgraph to move horizontally to the left to the boundary of the coupling graph in units of brick structure is: index x is the horizontal position of each node in the first subgraph; The number of steps required for the first subgraph to move horizontally to the right to the boundary of the coupling graph in units of brick structure is: p is the number of nodes in the horizontal direction of the coupling graph; The number of steps required for the first subgraph to move vertically downward to the boundary of the coupling graph in units of brick structures is: min(index y ), index y is the vertical position of each node in the first subgraph; The number of steps required for the first subgraph to move vertically upward to the boundary of the coupling graph in units of brick structures is: height-max(index y )-1, height is the number of rows of the first type and the second type of brick structures arranged on the quantum chip.

32. The device according to claim 29, wherein: The second determining unit is further configured to: Determine, based on the number of steps required for the first subgraph to move horizontally and vertically to the boundary of the coupling graph, an update range of the node position coordinates of the first subgraph in a first translation process on the coupling graph, wherein the first translation process includes horizontal and vertical movement; Based on the update range, the first value range is determined using a target formula, the target formula including a first formula And the second formula m, n is the number of steps of horizontal movement of the sub-graph in the coupling graph, m is the number of steps of vertical movement of the sub-graph in the coupling graph, and the target formula is used to determine the number of translation steps of the sub-graph in the affine coordinate system.

33. The apparatus of claim 28, wherein: The label updating unit is specifically used for: Updating the node position coordinates of the first subgraph within the value range; Based on the updated node position coordinates of the first subgraph, the updated node labels of the first subgraph are retrieved from the node index to obtain a second subgraph isomorphic to the interaction graph.

34. The apparatus of claim 21, further comprising: A third determination module is used to determine the r-order neighborhood of the generated set, where r is the radius of the interaction graph; The fourth determination module is used to determine the r-order neighborhood as the reduced search space of the coupling graph.

35. The apparatus of claim 21, wherein: The radius of the interaction map is determined by: Taking the node located in the central area of ​​the interaction graph as the target node, obtaining the maximum step length from the node in the interaction graph to the target node, and obtaining the target step length corresponding to the target node; The step length with the shortest distance among the target step lengths corresponding to the target nodes in the central area is determined as the radius of the interaction graph.

36. The apparatus of claim 21, wherein: The first determining module is specifically configured to: Obtain a second mapping scheme from the first logic quantum circuit to the quantum chip, and obtain a third mapping scheme corresponding to each subgraph in the subgraph set, respectively, wherein the third mapping scheme is a mapping scheme from the interaction graph to the quantum chip; The second mapping scheme is associated with each of the third mapping schemes to obtain a first mapping scheme corresponding to each subgraph in the subgraph set.

37. The apparatus of claim 21, wherein: The second determining module comprises: A fidelity acquisition unit, configured to acquire, based on the fidelity of the physical quantum gate on the quantum chip, a target fidelity of mapping the first logical quantum circuit to the physical quantum circuit on the quantum chip under each first mapping scheme; A scheme selection unit is used to select a mapping scheme corresponding to a physical quantum circuit with the largest target fidelity from the first mapping schemes corresponding to the subgraph set to obtain the target mapping scheme.

38. The device according to claim 37, wherein The fidelity acquisition unit is specifically used for: Based on the fidelity of the physical quantum gate on the quantum chip, obtaining the fidelity of the physical quantum gate of the logical quantum gate in the first logical quantum circuit under each first mapping scheme; For each first mapping scheme, the fidelity of each physical quantum gate corresponding to the first logical quantum circuit under the first mapping scheme is multiplied to obtain a target fidelity of the physical quantum circuit under the first mapping scheme.

39. The device according to claim 38, wherein For each logical quantum gate, the mapping relationship between the logical quantum gate and the physical quantum gate under each first mapping scheme and the fidelity of the physical quantum gate are stored and calculated in vector form; the fidelity acquisition unit is specifically used to multiply the first vectors corresponding to each logical quantum gate in the first logical quantum circuit according to the corresponding elements at the same position to obtain a target vector, wherein the target vector includes the target fidelity of the physical quantum circuit under each first mapping scheme, and the first vector is the vector of the fidelity of the physical quantum gate of the logical quantum gate under each first mapping scheme.

40. The device according to claim 21, wherein The acquisition module comprises: A region selection unit, configured to select a local region in the region range of the quantum chip, wherein the number of physical quantum bits deployed in the local region is greater than or equal to the number of logical quantum bits of the second logical quantum circuit; A pre-compilation unit is used to pre-compile the second logic quantum circuit into the local area to obtain an interaction diagram of the first logic quantum circuit.

41. An electronic device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 20.

42. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1-20.

43. A computer program product comprising a computer program which, when executed by a processor, implements the method according to any one of claims 1 to 20.

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