A dimensional fusion parallel fault simulation method and system for digital circuits

Abstract

The present invention discloses a method and system for dimensional fusion parallel fault simulation of digital circuits, the method comprising obtaining a first fault set, a test vector set and an FFR directed graph of a digital circuit; when a test vector set has a test vector group, obtaining the current test vector group from the test vector set, and initializing the circuit netlist of the circuit; when the first fault set is not empty, using a directed graph to assign a corresponding fault group to each circuit netlist, performing parallel fault simulation on multiple circuit netlists under the current test vector group, updating the first fault set and the second fault set until the first fault set is an empty set; updating the test vector set, the first fault set and the second fault set, returning to the step of judging the test vector set, and terminating the simulation when the test vector set is empty. The present invention effectively avoids the problem of multi-fault data competition, improves the accuracy of fault simulation, reduces the memory consumption of parallel fault simulation, and improves the memory utilization and the running speed and efficiency of fault simulation.

Description

Technical Field

[0001] The present invention relates to the field of digital circuit technology, and in particular to a dimensional fusion parallel fault simulation method and system for digital circuits. Background Art

[0002] Fault simulation, as an important part of the test vector generation system (Automatic Test Pattern Generation, ATPG) and chip reliability analysis, is a fundamental and critical issue in the field of chip testing. Existing parallel fault simulation technology is mainly based on data parallel multi-fault parallel simulation technology. The most representative of these is the fault simulation optimization scheme proposed by Siemens, which specifically optimizes the single-thread single-fault simulation performance, and then uses multi-threaded parallel fault simulation for further optimization. The optimization of single-thread fault simulation makes full use of the bit parallelism of event-driven simulation and computer bytes, which greatly reduces the simulation calculation amount of the fault circuit. In addition, since the simulation data of different fault simulations are independent of each other, different faults are simulated independently by different computing cores, and each computing core runs an efficient single-fault simulation algorithm at the same time, which can further improve the operating efficiency of the fault simulation. However, the above-mentioned fault simulation optimization scheme has the following disadvantages:

[0003] First, a fault simulation requires a complete circuit simulation value storage space. For a 20 million gate circuit, the circuit simulation value storage space for transition delay fault simulation can reach 2GB. If each fault simulation requires 2GB of memory, the memory consumption and time cost of parallel fault simulation will be greatly increased, slowing down the running speed of fault simulation.

[0004] Second, in event-driven simulation, when multiple faults activate the same logic gate at the same time, data competition, storage conflict and other problems are very likely to occur, causing some faults that should be simulated to fail to be transmitted to the lower layer due to competition failure, which in turn leads to errors in the results of fault simulation and reduces the accuracy of fault simulation. Summary of the invention

[0005] The purpose of the present invention is to solve one of the technical problems existing in the prior art to at least a certain extent.

[0006] To this end, an object of the present invention is to provide a dimensional fusion parallel fault simulation method and system for digital circuits.

[0007] In order to achieve the above technical objectives, the technical solutions adopted by the embodiments of the present invention include:

[0008] On the one hand, an embodiment of the present invention provides a dimensional fusion parallel fault simulation method for a digital circuit, comprising the following steps: obtaining a first fault set, a test vector set, and an FFR directed graph of a digital circuit to be simulated;

[0009] Determining whether the test vector set contains at least one test vector group;

[0010] When the test vector set contains at least one test vector group, obtaining a current test vector group from the test vector set, and initializing a plurality of circuit netlists of the digital circuit to a fault-free state;

[0011] When the first fault set is not empty, using the FFR directed graph to assign a corresponding fault group to each of the circuit netlists, performing parallel fault simulation on multiple circuit netlists based on the assigned fault groups under the current test vector group, and updating the first fault set and the second fault set until the first fault set is an empty set;

[0012] When the first fault set is an empty set, updating the test vector set, taking the second fault set as the first fault set, and returning to the step of determining whether the test vector set has at least one test vector group;

[0013] When the test vector set is an empty set, the fault simulation result of the digital circuit is output.

[0014] The dimensional fusion parallel fault simulation method for a digital circuit according to the above embodiment of the present invention may also have the following additional technical features:

[0015] Further, in one embodiment of the present invention, the step of obtaining a first fault set, a test vector set, and an FFR directed graph of a digital circuit to be simulated includes:

[0016] Acquire multiple faults to be simulated of the digital circuit and their numbers as a first fault set of the digital circuit, and acquire multiple test vector groups of the digital circuit as a test vector set of the digital circuit;

[0017] Dividing the digital circuit into a plurality of non-fan-out regions, taking the non-fan-out regions as basic units, and representing the connections and data flows between the non-fan-out regions by directed line segments, thereby constructing an FFR directed graph of the digital circuit;

[0018] The FFR directed graph has a hierarchical structure, the non-fan-out area is a circuit area in the digital circuit that has only one output terminal and the output terminal is a logic output terminal or a fan-out terminal, and each transmission line in each non-fan-out area is connected to at most one input terminal of a logic gate.

[0019] Further, in one embodiment of the present invention, when the first fault set is not empty, the FFR directed graph is used to assign a corresponding fault group to each of the circuit netlists, parallel fault simulation is performed on multiple circuit netlists based on the assigned fault groups under the current test vector group, and the first fault set and the second fault set are updated until the first fault set is an empty set, including:

[0020] When the first fault set is not empty, using the FFR directed graph to assign a corresponding fault group to each of the circuit netlists;

[0021] Inserting each of the fault groups into a corresponding circuit netlist, performing parallel fault simulation on multiple circuit netlists through multiple parallel threads under the current test vector group, and obtaining a detection state of each fault to be simulated;

[0022] The detection status includes any one of a completed status, an undetectable status or an abandoned status;

[0023] Add the to-be-simulated faults in the first fault set that belong to the undetectable state and the abandoned state to the second fault set, and delete the to-be-simulated faults in the first fault set that belong to the completed state, the undetectable state, and the abandoned state;

[0024] Initializing each of the circuit netlists to a fault-free state under the current test vector group;

[0025] Determine whether the first fault set is an empty set; if not, return to the step of using the FFR directed graph to assign a corresponding fault group to each of the circuit netlists; if so, enter the step of updating the test vector set.

[0026] Further, in one embodiment of the present invention, for each circuit netlist, the step of using the FFR directed graph to assign a corresponding fault group to the circuit netlist includes:

[0027] Determining transmission parameters of the circuit netlist;

[0028] According to the FFR directed graph and the transmission parameters, construct a plurality of fan-out-free transmission domains of the circuit netlist, wherein two adjacent fan-out-free transmission domains do not overlap each other, and each of the fan-out-free transmission domains includes at least one fault to be simulated and at least two fan-out-free areas;

[0029] Selecting at least one fault to be simulated from each of the fan-out-free transmission domains in turn;

[0030] Determine the priority of the selected fault to be simulated according to the number of the selected fault to be simulated, wherein the priority of the fault to be simulated with a smaller number is higher than the priority of the fault to be simulated with a larger number;

[0031] The faults to be simulated and their priorities are used as the fault groups of the circuit netlist.

[0032] Further, in one embodiment of the present invention, constructing multiple fan-out-free transmission domains of the circuit netlist according to the FFR directed graph and the transmission parameters includes:

[0033] According to the hierarchical structure of the FFR directed graph, any of the fan-out-free areas is used as an output point, and an FFR layer located before the FFR layer where the output point is located is used as a to-be-selected layer. The output point and the fan-out-free area in the to-be-selected layer that meets the transmission parameters and is connected to the output point are selected as fan-out-free transmission domains, thereby constructing multiple fan-out-free transmission domains of the circuit netlist.

[0034] Further, in one embodiment of the present invention, for each of the circuit netlists, after the fault group is inserted into the corresponding circuit netlist, the step of performing fault simulation on the circuit netlist includes:

[0035] Acquire a logic gate in the circuit netlist whose circuit level identifier and logic identifier are a second value as a logic gate to be simulated;

[0036] According to the hierarchical structure of the circuit netlist, the to-be-simulated logic gates in the circuit netlist are activated in sequence in an increasing manner of circuit hierarchy using the to-be-simulated faults in the fault group, so as to perform fault simulation on the to-be-simulated logic gates.

[0037] Furthermore, in one embodiment of the present invention, when fault-activated paths in the circuit netlist are not intertwined and are independent of each other, the same simulation value storage space is used to perform fault simulation on all to-be-simulated faults in the fault group inserted into the circuit netlist.

[0038] Further, in one embodiment of the present invention, when a plurality of the faults to be simulated activate the same logic gate to be simulated, the faults to be simulated having a priority greater than a third numerical value are retained for activation of the next circuit level, and the abandoned state is used as the detection state of the faults to be simulated having a priority less than or equal to the third numerical value.

[0039] Further, in an embodiment of the present invention, when the first fault set is an empty set, updating the test vector set includes:

[0040] When the first fault set is an empty set, the current test vector group is deleted from the test vector set, a next test vector group is selected as the current test vector group, and the test vector set is updated.

[0041] Furthermore, in one embodiment of the present invention, the method further comprises the following steps:

[0042] When the second fault set is an empty set, a fault simulation result of the digital circuit is output.

[0043] On the other hand, an embodiment of the present invention provides a dimensional fusion parallel fault simulation system for digital circuits, including:

[0044] An acquisition module, used for acquiring a first fault set, a test vector set and an FFR directed graph of a digital circuit to be simulated;

[0045] A first judging module, used to judge whether there is at least one test vector group in the test vector set;

[0046] An initialization module, used for obtaining a current test vector group from the test vector set when there is at least one test vector group in the test vector set, and initializing multiple circuit netlists of the digital circuit to a fault-free state;

[0047] A fault simulation module, used for, when the first fault set is not empty, using the FFR directed graph to assign a corresponding fault group to each circuit netlist, performing parallel fault simulation on multiple circuit netlists based on the assigned fault groups under the current test vector group, and updating the first fault set and the second fault set until the first fault set is an empty set;

[0048] An updating module, used for updating the test vector set when the first fault set is an empty set, taking the second fault set as the first fault set, and returning to the step of determining whether the test vector set has at least one test vector group;

[0049] The end module is used to output the fault simulation result of the digital circuit when the test vector set is an empty set.

[0050] On the other hand, an embodiment of the present invention provides a storage medium, in which a program executable by a processor is stored. When the program executable by the processor is executed by the processor, it is used to implement the above-mentioned dimensional fusion parallel fault simulation method of a digital circuit.

[0051] The beneficial effects of the present invention are: providing a dimensional fusion parallel fault simulation method and system for digital circuits, which can greatly reduce memory consumption when performing parallel fault detection by sharing simulation value storage space, improve memory utilization and the running speed and efficiency of fault simulation; in addition, the fault parallel simulation is driven by circuit level identification and logic gate identification combined with event management mechanism and priority simulation mechanism, which has the advantage of competitive inclusion, and can well avoid the problem of data competition caused by the same logic gate being activated by different faults, ensure that the fault is accurately transmitted to the lower layer, and improve the accuracy of fault simulation.

[0052] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained by the structures specifically pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the embodiments of the present invention or the drawings of related technical solutions in the prior art are introduced below. It should be understood that the drawings introduced below are only for the convenience of clearly describing some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0054] Figure 1 It is a flow chart of a dimensional fusion parallel fault simulation method for a digital circuit proposed by the present invention;

[0055] Figure 2 is a schematic diagram of FFR provided by the present invention;

[0056] Figure 3 is a schematic diagram of an FFR directed graph provided by the present invention;

[0057] Figure 4 It is a schematic diagram of the FFR transmission domain provided by the present invention;

[0058] Figure 5 is another schematic diagram of the FFR transmission domain provided by the present invention;

[0059] Figure 6 It is another flow chart of the dimensional fusion parallel fault simulation method for digital circuits provided by the present invention;

[0060] Figure 7 It is an application diagram of the parallel fault simulation provided by the present invention;

[0061] Figure 8 It is a schematic diagram of the FFR directed graph and the FFR transmission domain provided by the present invention;

[0062] Fig. 9 It is a schematic diagram of an array identifier of an event management mechanism for parallel fault simulation provided by the present invention. DETAILED DESCRIPTION

[0063] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0064] The present application is further described below in conjunction with the accompanying drawings and specific embodiments. The described embodiments should not be regarded as limiting the present application, and all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present application.

[0065] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0066] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0067] Fault simulation is an important part of the test pattern generation system (Automatic Test Pattern Generation, ATPG) and chip reliability analysis, and is a fundamental and critical issue in the field of chip testing. Existing parallel fault simulation technologies are mainly based on multi-fault parallel simulation technologies based on data parallelism. The most representative of these is the fault simulation optimization solution proposed by Siemens, which specifically optimizes the single-thread single-fault simulation performance and then uses multi-thread parallel fault simulation for further optimization.

[0068] Among them, the optimization of single-threaded fault simulation fully utilizes the bit parallelism of event-driven simulation and computer bytes, which greatly reduces the simulation calculation amount of fault circuits. In addition, since the simulation data of different fault simulations are independent of each other, different faults can be simulated independently by different computing cores, and each computing core runs an efficient single fault simulation algorithm at the same time, which can further improve the operating efficiency of fault simulation.

[0069] Fault simulation based on data parallelism has the important characteristic that the memory requirement is proportional to the number of threads. Therefore, to fully realize the advantages of parallel fault simulation methods, the processor needs to have a large number of computing cores and a large memory space. The memory requirements of single-threaded fault simulation usually come from the following main sources: circuit netlist; simulation values ​​of each logic gate in multiple time frames; event-driven management. Among them, the circuit netlist is static and can be shared by multiple fault simulations, while different fault simulations will produce different simulation values ​​and different event queues, so it is necessary to allocate independent logic simulation and event-driven management space for each simulated fault. For ultra-large-scale digital chips, each fault simulation requires several GB of storage space, and its simulation has high requirements for storage space.

[0070] However, for the existing mature parallel fault simulation technology, taking the fault simulation optimization solution proposed by Siemens as an example, the solution has the following disadvantages:

[0071] First, a fault simulation requires a complete circuit simulation value storage space. For a 20 million gate circuit, the circuit simulation value storage space for transition delay fault simulation can reach 2GB. If each fault simulation requires 2GB of memory, the memory consumption and time cost of parallel fault simulation will be greatly increased, which is prone to memory data explosion and slows down the running speed of fault simulation.

[0072] Second, in event-driven simulation, when multiple faults activate the same logic gate at the same time, data competition, storage conflict and other problems are very likely to occur, causing some faults that should be simulated to fail to be transmitted to the lower layer due to competition failure, which in turn leads to errors in the results of fault simulation and reduces the accuracy of fault simulation.

[0073] In view of the problems and defects existing in the prior art, the embodiments of the present invention provide a dimensional fusion parallel fault simulation method and system for digital circuits, based on the premise that the number of fault-activated logic gates is limited. The faults that can be simulated include but are not limited to single fixed-type faults, bridging faults, transition delay faults, etc. It can effectively avoid the data explosion problem caused by parallel fault simulation, reduce the memory occupied by fault simulation, greatly improve the running speed and efficiency of fault simulation, and have high availability.

[0074] A dimensional fusion parallel fault simulation method for digital circuits proposed in an embodiment of the present invention will be described in detail below.

[0075] The method proposed in the embodiment of the present invention can be applied to a terminal or a server, or can be software running in a terminal or a server. The terminal can be a tablet computer, a laptop computer, a desktop computer, etc., but is not limited thereto. The server can be an independent physical server, or a server cluster or a distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms.

[0076] Reference Figure 1 , Figure 1 : is a flow chart of a dimensional fusion parallel fault simulation method for a digital circuit proposed by the present invention, the method may include but is not limited to the following steps:

[0077] S100, obtaining a first fault set, a test vector set and an FFR directed graph of a digital circuit to be simulated.

[0078] It should be noted that the first fault set may include but is not limited to multiple faults to be simulated of the digital circuit to be simulated and their corresponding numbers. The test vector set may include but is not limited to multiple test vector groups, each test vector group includes at least one test vector, and the test vector refers to the logical value input to the digital circuit during fault detection, such as "01111011", "10110000", etc.

[0079] S200, determine whether the test vector set contains at least one test vector group; if so, go to step S300; if not, output the fault simulation result of the digital circuit and end the fault simulation.

[0080] S300, obtaining a current test vector group from a test vector set, and initializing multiple circuit netlists of a digital circuit to a fault-free state.

[0081] S400, when the first fault set is not empty, use the FFR directed graph to assign a corresponding fault group to each circuit netlist, perform parallel fault simulation on multiple circuit netlists based on the assigned fault groups under the current test vector group, and update the first fault set and the second fault set until the first fault set is an empty set.

[0082] In this step, first, based on the FFR directed graph, m non-overlapping FFR transmission domains containing faults are divided according to the grouping principle starting from the first layer FFR, and a fault is selected in one FFR transmission domain to form a fault group G. f1 , and then form the fault group G in the same way f2 ~G fk , set the priority of each group of faults according to the priority principle; then, insert a group of faults in each circuit netlist, for example, insert fault group G in netlist 1 f1 , ..., insert fault group G into netlist k fk ; Then, perform parallel fault simulation on multiple circuit netlists based on the assigned fault groups under the current test vector group, and update the first fault set and the second fault set; Then, determine whether the first fault set is not empty, in order to determine whether there are any unsimulated faults in the first fault set; When the first fault set is not empty, return to the step of using the FFR directed graph to assign a corresponding fault group to each circuit netlist; When the first fault set is an empty set, go to step S500.

[0083] S500, when the first fault set is an empty set, update the test vector set, use the second fault set as the first fault set, and return to step S200.

[0084] In this step, the current test vector group is deleted from the test vector set, and at the same time, the first fault set is made equal to the second fault set, the second fault set is cleared, and then the process returns to step S200.

[0085] In some embodiments of the present invention, the step of obtaining the first fault set, the test vector set and the FFR directed graph of the digital circuit to be simulated in step S100 may include but is not limited to:

[0086] S110, obtaining a plurality of to-be-simulated faults of the digital circuit and their numbers as a first fault set of the digital circuit, and simultaneously obtaining a plurality of test vector groups of the digital circuit as a test vector set of the digital circuit.

[0087] In this step, first, the circuit level of the digital circuit is determined according to its structure. The smaller the circuit level where the fault is located, the greater the level distance between the fault to be simulated and the output end of the digital circuit. Then, multiple faults to be simulated are numbered according to the size of the circuit level. The numbering rule is that the lower the circuit level where the fault is located, the smaller the fault number; the higher the circuit level where the fault is located, the larger the fault number.

[0088] S120, dividing the digital circuit into a plurality of non-fan-out regions, taking the non-fan-out regions as basic units, and using directed line segments to represent connections and data flows between the non-fan-out regions, thereby constructing an FFR directed graph of the digital circuit.

[0089] In the embodiment of the present invention, based on the definition of fan-out free network proposed by John P. Hayes and the concept of circuit partitioning proposed by Kurt J. Antreich, the fan-out free region (FFR) of the digital circuit is defined as follows: if a region of the digital circuit has only one output terminal, and the output terminal is a logic output terminal or a fan-out terminal, and each transmission line of the circuit in the region is connected to at most one input of a logic gate, then the circuit region is called a fan-out free region.

[0090] That is, FFR is a circuit area in a digital circuit that has only one output terminal and the output terminal is a logic output terminal or a fan-out terminal, and each transmission line in each non-fan-out area is connected to at most one input terminal of a logic gate.

[0091] For example, refer to Figure 2 , Figure 2 is a schematic diagram of the FFR provided by the present invention. According to the distribution of the fan-out terminal and the logic output terminal, Figure 2There are seven FFRs in the digital circuit shown, among which the area where logic gates G1 and G4 are located constitutes FFR1, the left area of ​​the fan-out end connected to logic gate G7 forms FFR2, the area where logic gate G2 is located constitutes FFR3, the right area of ​​the fan-out end connected to logic gate G4 (not the area where logic gate G7 is located) constitutes FFR4, the area where logic gate G7 is located constitutes FFR5, the area where logic gates G5, G8 and G9 are located constitutes FFR6, and the area where logic gates G3 and G6 are located constitutes FFR7.

[0092] After dividing the digital circuit into multiple FFRs, the embodiment of the present invention constructs a directed graph of the non-fan-out area of ​​the digital circuit according to the multiple FFRs, and the directed graph of the non-fan-out area is called an FFR directed graph. In the FFR directed graph, FFR is used as a unit, which is represented by a circle, and the connection relationship between different FFRs is represented by a directed line segment, and the arrow of the directed line segment represents the data flow direction between different FFRs.

[0093] For example, refer to Figure 3 , Figure 3 is a schematic diagram of the FFR directed graph provided by the present invention, Figure 3 The FFR directed graph shown corresponds to Figure 2 The no fan-out area distribution shown, Figure 2 The seven FFRs in the figure are represented by circles, and the connection relationship and data flow direction between the seven FFRs are represented by directed lines, thus obtaining the following: Figure 3 The FFR directed graph is shown.

[0094] In addition, the FFR directed graph has a hierarchical structure, with FFRs located in the same column as FFRs of the same FFR level. The greater the distance between the FFR and the output terminal of the digital circuit, the lower the FFR level at which the FFR is located.

[0095] For example, refer to Figure 3 In the FFR directed graph shown, FFR1, FFR2 and FFR3 are located in the same column and are farthest from the output end of the digital circuit, so FFR1, FFR2 and FFR3 are located in the first FFR level, i.e., level 1; while FFR4, FFR5, FFR6 and FFR7 are located in the same column and are closest to the output end of the digital circuit, so FFR4, FFR5, FFR6 and FFR7 are located in the second FFR level, i.e., level 2, thereby making the FFR directed graph have a hierarchical structure.

[0096] In some embodiments of the present invention, step S300 may include but is not limited to the following steps:

[0097] S310, obtaining a current test vector group from a test vector set, and performing a fault-free simulation on multiple circuit netlists of a digital circuit to be simulated, so as to initialize all circuit netlists to a fault-free state.

[0098] In some embodiments of the present invention, step S400 may include but is not limited to the following steps:

[0099] S410: When the first fault set is not empty, use the FFR directed graph to assign a corresponding fault group to each circuit netlist.

[0100] It should be noted that, in some embodiments of the present invention, all faults to be simulated in the first fault set are assigned to the corresponding circuit netlist. However, in other embodiments of the present invention, some faults to be simulated in the first fault set are assigned to the corresponding circuit netlist, but some faults to be simulated in the first fault set are still not assigned.

[0101] S420, inserting each fault group into a corresponding circuit netlist, performing parallel fault simulation on multiple circuit netlists through multiple parallel threads under the current test vector group, and obtaining a detection status of each fault to be simulated.

[0102] It should be noted that the detection status includes any one of a completed status, an undetectable status or an abandoned status.

[0103] Specifically, if the fault effect caused by a fault can be transmitted to the output end under the test vector, the fault can be detected and it is a completed state; if a fault cannot be transmitted to the output end under the test vector, or it is transmitted to the output end but the fault simulation value is consistent with the correct value, then the fault cannot be detected and it is an undetectable state; if a fault cannot be transmitted to the output end due to the influence of other faults in the group, then the fault is abandoned and it is an abandoned state.

[0104] In this step, a group of faults is inserted into each circuit netlist. For example, fault group G is inserted into netlist 1. f1 , ..., insert fault group G into netlist k fk It should be emphasized that in other embodiments of the present invention, after the fault group is inserted into the corresponding circuit netlist, there may be some faults to be simulated in the first fault set that are not grouped in the aforementioned steps and do not participate in this round of fault simulation.

[0105] S430, adding the to-be-simulated faults in the first fault set that are in the undetectable state and the abandoned state to the second fault set, and deleting the to-be-simulated faults in the first fault set that are in the completed state, the undetectable state, and the abandoned state, so as to update the first fault set and the second fault set;

[0106] S440, initializing each circuit netlist to a fault-free state under the current test vector group.

[0107] In this step, under the current measurement vector group, each netlist fault point is restored to a fault-free value, and then a fault-free simulation is performed on each netlist, thereby initializing each circuit netlist to a fault-free state.

[0108] S450, determining whether the first fault set is an empty set; if not, returning to step S410; if yes, proceeding to step S500.

[0109] In this step, since there may be some faults to be simulated in the first fault set that are not grouped in the previous steps and do not participate in this round of fault simulation, it is necessary to confirm whether the first fault set is empty. If so, perform fault simulation for the next test vector group; if not, return to the step of using the FFR directed graph to assign corresponding fault groups to each circuit netlist and perform the next round of fault simulation.

[0110] In some embodiments of the present invention, in step S410, for each circuit netlist, the step of using the FFR directed graph to assign a corresponding fault group to the circuit netlist includes:

[0111] S411, determine the transmission parameters of the circuit netlist.

[0112] It should be noted that the transmission parameters are pre-set circuit parameters.

[0113] S412, constructing multiple fan-out-free transmission domains of the circuit netlist according to the FFR directed graph and the transmission parameters.

[0114] It should be noted that a transmission domain without fan-out is called an FFR transmission domain, wherein two adjacent FFR transmission domains do not overlap each other, and each FFR transmission domain includes at least one fault to be simulated and at least two FFRs.

[0115] For example, refer to Figure 4 , Figure 4 FIG. 1 is a schematic diagram of an FFR transmission domain provided by the present invention, wherein a gray triangle represents an FFR transmission domain. Figure 4 Only part of the FFR transmission domain is shown in the figure; the two FFR transmission domains with black dashed lines on the periphery do not overlap each other, and the two FFRs with black solid lines have overlapping domains. FFR1 and FFR4 form one FFR transmission domain, and FFR3 and FFR7 form the second FFR transmission domain. These two FFR transmission domains do not overlap each other. The area formed by FFR8, FFR12 and FFR9 and the area formed by FFR9, FFR13 and FFR10 overlap each other, that is, there is an overlapping domain in these two areas, so only one of these two areas can be an FFR transmission domain.

[0116] S413, selecting at least one fault to be simulated from each fan-out-free transmission domain in turn.

[0117] In this step, according to the number of faults to be simulated, non-overlapping FFR transmission domains that meet the number requirement are selected, and a fault to be simulated is selected from each selected FFR transmission domain in turn. However, it should be noted that the number of faults to be simulated cannot be greater than the first value.

[0118] S414, determining the priority of the selected fault to be simulated according to the number of the selected fault to be simulated, and using the fault to be simulated and its priority as a fault group of the circuit netlist.

[0119] It should be noted that each circuit netlist is correspondingly assigned a fault group, and the fault group includes multiple faults to be simulated and their priorities.

[0120] In this step, the priority is related to the fault number. The faults to be simulated with small numbers are located at a low circuit level, and the path for the fault to be transmitted to the output end is often longer. Therefore, the faults to be simulated with small fault numbers have high priorities. That is, the priority of the faults to be simulated with small numbers is higher than the priority of the faults to be simulated with large numbers. Afterwards, the faults to be simulated and their priorities are used as the fault groups of the circuit netlist.

[0121] In some embodiments of the present invention, the transmission parameters of the circuit netlist may include but are not limited to the depth and width of the FFR transmission domain included in the circuit netlist, wherein the width and depth of each FFR transmission domain in the circuit netlist are the same.

[0122] More specifically, the depth of the FFR transmission domain refers to the number of FFR layers in the FFR transmission domain. The number of layers refers to the number of FFR levels. FFRs in the same column have the same FFR level, and the lower the FFR level, the greater the distance between the FFR in the FFR transmission domain and the output end of the digital circuit.

[0123] For example, refer to Figure 5 , Figure 5 This is the second schematic diagram of the FFR transmission domain provided by the present invention. In the figure, FFR transmission domain 1 includes two layers of FFR, and FFR transmission domain 2 includes three layers of FFR. Therefore, the depth of FFR transmission domain 1 is 2, and the depth of FFR transmission domain 2 is 3.

[0124] More specifically, the width of the FFR transmission domain refers to the sum of the number of FFRs having only one child node in the FFR transmission domain except the FFR at the bottom of the FFR transmission domain and the number of FFRs at the bottom of the FFR transmission domain.

[0125] For example, refer to Figure 5For FFR transmission domain 1, FFR7 has only one child node, and FFR3 is located at the bottom layer of FFR transmission domain 1, so the width of FFR transmission domain 1 is 2; for FFR transmission domain 2, FFR4, FFR5, and FFR6 are all located at the bottom layer of the transmission domain, so the width of FFR transmission domain 2 is 3.

[0126] In the embodiment of the present invention, the FFR transmission domain indicates the range in which the output FFR is affected by other FFRs. When the FFR transmission domains where multiple faults are located do not overlap with each other and are in the same FFR layer, these faults will not conflict within their FFR transmission domains during parallel simulation. Although there is still a probability of conflict when these faults are transmitted outside their FFR transmission domains, this probability is extremely small and can be ignored.

[0127] Alternatively, considering that the number of faults that can be successfully transmitted to the output end is limited, for circuits of general size, when the depth of the FFR transmission domain is greater than 4, the probability of conflict caused by parallel simulation of multiple faults will be very low.

[0128] In some embodiments of the present invention, in step S412, the step of constructing multiple fan-out-free transmission domains of the circuit netlist according to the FFR directed graph and the transmission parameters mainly includes:

[0129] According to the hierarchical structure of the FFR directed graph, any fan-out-free area is taken as the output point, the FFR level before the FFR level where the output point is located is taken as the to-be-selected level, the output point and the fan-out-free area in the to-be-selected level that meets the transmission parameters and is connected to the output point are selected as the fan-out-free transmission domain, and then multiple fan-out-free transmission domains of the circuit netlist are constructed.

[0130] In this step, according to the hierarchical structure of the FFR directed graph, take any FFR as the output point, go forward several FFR levels, find all FFRs connected to the output point in the several FFR levels ahead, and then form an FFR transmission domain that meets the preset FFR transmission domain width and depth.

[0131] For example, refer to Figure 4, if the depth and width of the FFR transmission domain are set to 2, and FFR4 is used as the output point, the connected FFR1 is found in the previous FFR level, so FFR1 and FFR4 constitute an FFR transmission domain. From FFR5 as the output point, the connected FFR1 and FFR2 are found in the previous FFR level, so FFR1, FFR2 and FFR5 constitute another FFR transmission domain, and so on, 11 FFR transmission domains can be drawn. However, among these FFR transmission domains, there are overlapping FFR transmission domains, such as the area formed by FFR8, FFR12 and FFR9 and the area formed by FFR9, FFR13 and FFR10 overlap each other, then one of every two overlapping FFR transmission domains is selected and retained, and then multiple non-overlapping FFR transmission domains in the circuit netlist are obtained.

[0132] Reference Figure 5 , if the depth and width of the FFR transmission domain are set to 2, with FFR7 as the output point, FFR3 connected to FFR7 is found in the previous FFR level, thereby forming an FFR transmission domain 1 with a width and depth of 2. For another example, if the width and depth of the FFR transmission domain are set to 3, with FFR12 as the output point, FFR8 and FFR9 connected to FFR12 are found in the previous FFR level, with FFR8 and FFR9 as the output points, FFR4 and FFR5 connected to FFR8 are found in the previous FFR level, and FFR5 and FFR6 connected to FFR9 are found in the previous FFR level, thereby forming an FFR transmission domain 2 with a width and depth of 3.

[0133] In some embodiments of the present invention, in step S400, a fault group corresponding to each circuit netlist is formed. The maximum value of the number of faults to be simulated in the fault group, i.e., the first value, is related to the circuit structure and can be calculated by the following calculation formula:

[0134]

[0135] Among them, N (i)FFR represents the number of FFRs in the i-th layer, and the FFR level of the FFR directed graph is but l (i,j) represents the width of the jth FFR transmission domain of the i-th FFR layer, j = 1, 2, 3, ..., N (i+1)FFR ; Indicates the maximum width of the FFR transmission domain in the i-th layer FFR. Take the FFR transmission domain with the largest width in the i-th layer FFR as the denominator and the number of FFRs in the i-th layer as the numerator. The integer is rounded to indicate the minimum number of non-overlapping FFR transmission domains in this layer. FFR transmission domains do not overlap, then for any layer of FFR, there are at least FFR transmission domains do not overlap. That is, for any layer of FFR, there are at least m FFR transmission domains that do not overlap. Based on this, m can be used as the maximum value of the number of faults to be simulated in the fault group, that is, the first value.

[0136] Furthermore, for common circuit structures, the width of the FFR transmission domain increases with its depth rather than strictly increasing, so the above formula can be simplified to the following formula:

[0137]

[0138] Although the simplified formula loses some of the characteristics of the circuit structure and has certain deviations, it can greatly reduce the computational complexity of fault simulation. In addition, multiple experiments can be conducted on a certain type of circuit to correct the parameters. Later, when encountering the same type of circuit, the simplified formula can be directly used and the parameters can be applied, which reduces the computational complexity while ensuring a certain accuracy.

[0139] In some embodiments of the present invention, in step S420, for each circuit netlist, after the fault group is inserted into the corresponding circuit netlist, the step of performing fault simulation on the circuit netlist mainly includes:

[0140] S421, obtaining a logic gate in the circuit netlist whose circuit level identifier and logic identifier are a second value as a logic gate to be simulated;

[0141] S422 , according to the hierarchical structure of the circuit netlist, using the to-be-simulated faults in the fault group to sequentially activate the to-be-simulated logic gates in the circuit netlist in an increasing manner of the circuit hierarchy, so as to perform fault simulation on the to-be-simulated logic gates.

[0142] In an embodiment of the present invention, a dimension fusion mechanism is used to implement fault simulation of a circuit netlist. The dimension fusion mechanism refers to a plurality of faults to be simulated in each fault group sharing a simulation value storage space and an event management mechanism to perform event-driven hierarchical fault parallel simulation. The dimension fusion mechanism is mainly divided into two aspects: an event management mechanism and a shared simulation value storage space.

[0143] Specifically, in the related art, a fault simulation requires a complete circuit simulation value storage space, while the number of logic gates activated by the event-driven simulation of the fault circuit is very limited. For a circuit of 20 million gates, the circuit simulation value storage space for the transition delay fault simulation can reach 2GB. If each fault simulation requires 2GB of memory, the memory consumption is very large. In this regard, the embodiment of the present invention is based on the aforementioned fault grouping step. When the paths of fault activation in the circuit netlist are not intertwined and independent of each other, all faults to be simulated in the fault group inserted into the circuit netlist are subjected to fault simulation using the same simulation value storage space, so that all faults in the same group can share the circuit simulation value storage space, that is, the parallel simulation of multiple faults only requires 2GB of memory, which greatly reduces the memory consumption of parallel fault simulation.

[0144] More specifically, when the simulation value storage space of the logic gate is N, the logic gate can store simulation values ​​of N faults at most.

[0145] Specifically, the event management mechanism uses a one-dimensional array circuit level identifier level_flag[N L ], two-dimensional array logic gate identifier eval_flag[N gate ][N netlist ], guiding multiple faults to perform event-driven fault simulation in a circuit-level incremental manner. L is the number of circuit levels, N gate is the number of circuit logic gates, N netlist is the number of netlists.

[0146] When a certain logic gate needs to be fault simulated, the value of its corresponding circuit level identifier and logic gate identifier is a second value. Optionally, the second value is 1. When performing fault simulation, when a certain circuit level identifier is detected to be 1, all logic gate identifiers of the circuit level are detected, and then the logic gates with circuit level identifiers and logic identifiers of 1 in the circuit netlist are obtained, which are used as the logic gates to be simulated, and fault simulation is performed on the logic gates to be simulated. If the fault effect is transmitted to the same logic gate, the corresponding identifier is only set to 1 multiple times, and the common problem of data competition when the same logic gate is activated by event-driven simulation will not occur. The embodiment of the present invention has the advantage of competition inclusion.

[0147] In addition, when the simulation value storage space of the logic gate is N, the logic gate can store the simulation values ​​of N faults at most. When there are N+1 fault simulations passing through the logic gate, that is, N+1 faults activate the same logic gate at the same time, then the simulation values ​​of N+1 faults need to be stored, and then a storage conflict will occur. In order to solve the problem of insufficient storage space for the simulation value of the logic gate caused by multiple faults activating the same logic gate at the same time, the embodiment of the present invention introduces a priority simulation mechanism in parallel fault simulation on the basis of the dimensional fusion mechanism. The priority simulation mechanism is: when multiple faults to be simulated activate the same logic gate to be simulated, the faults to be simulated with a priority greater than the third value are retained for activation of the next circuit level, and the abandoned state is used as the detection state of the faults to be simulated with a priority less than or equal to the third value. It should be noted that the third value is determined by the simulation value storage space of the logic gate. In the priority simulation mechanism, according to the priorities of multiple to-be-simulated faults that simultaneously activate the same logic gate, the to-be-simulated faults with high priorities are used as to-be-simulated faults that can be transferred to the next circuit level, while the to-be-simulated faults with low priorities are abandoned in this round of fault simulation, which is defined as the abandoned state. The abandoned low-priority to-be-simulated faults will be reassigned later and fault simulation will be performed again.

[0148] For example, assuming that the storage space of each logic gate is 1, the logic gate can store at most one fault simulation value. If two fault simulations pass through the logic gate, both faults need to store simulation values, and there is a problem of insufficient space. At this time, the fault to be simulated is determined based on the priority of the two faults, and the fault simulation value with a high priority is retained, and the fault simulation with a low priority is abandoned.

[0149] In some embodiments of the present invention, in step S500, when the first fault set is an empty set, the step of updating the test vector set includes:

[0150] When the first fault set is an empty set, the current test vector group is deleted from the test vector set, and the next test vector group is selected as the current test vector group to implement the update of the test vector set.

[0151] In some embodiments of the present invention, the method provided by the embodiment of the present invention may further include the following steps:

[0152] When the second fault set is an empty set, a fault simulation result of the digital circuit is output.

[0153] In this step, when the second fault set is an empty set, it means that all the faults to be simulated are in a completed state, and the fault simulation of the digital circuit to be simulated is completed. At this time, the fault simulation result of the digital circuit is output.

[0154] Reference Figure 6 , Figure 6It is another flow chart of the dimensional fusion parallel fault simulation method for digital circuits provided by the present invention. The implementation principle and process of the dimensional fusion parallel fault simulation method proposed in the embodiment of the present invention will be described below with an example.

[0155] Step S1, initialize the first fault set, the second fault set and the test vector set and number the faults, and divide the digital circuit into multiple FFRs according to the structure of the digital circuit, and convert them into a hierarchically distributed FFR directed graph.

[0156] Specifically, according to the digital circuit to be simulated, the first fault set F of the digital circuit is obtained. init and the test vector set T init , and create the second fault set F und Let F = F init , T = T init , The faults are numbered sequentially from low circuit level to high circuit level. The circuit is divided into multiple no fan-out regions and converted into an FFR directed graph with FFR level distribution.

[0157] Step S2, determine whether F is an empty set; if not, proceed to step S3; if so, end the simulation.

[0158] Step S3, determine whether there is a test vector group in T; if so, proceed to step S4; if not, end the simulation.

[0159] Step S4: Select a set of test vector groups w from T, and perform fault-free simulation on k circuit netlists under the test vector group w to initialize all circuit netlists to a fault-free state.

[0160] Step S5: Under the test vector group w, multiple faults to be simulated in F are grouped based on the FFR directed graph, and then the fault grouping results are used to perform fault simulation on k circuit netlists to obtain the fault detection status, which is as follows:

[0161] Step S51: Based on the FFR directed graph, select multiple fault groups G from F f1 ~G fk ,Each fault group corresponds to a circuit netlist;

[0162] Step S52: insert each fault group into the corresponding circuit netlist. f1 Inserted into circuit netlist 1, fault group G f2 Insert into circuit netlist 2, ..., fault group G fk Insert into the circuit netlist k.

[0163] Step S53: Under the test vector group w, fault simulation based on the dimension fusion mechanism is performed on the netlists 1-k at the same time to obtain the detection status of the fault to be simulated.

[0164] Step S54: Update F and F und Specifically, the undetectable faults are added to F und , remove detected and undetectable faults from F.

[0165] Step S55, under the test vector group w, perform fault-free simulation based on the dimension fusion mechanism on netlists 1-k at the same time, restore the fault points of netlists 1-k to fault-free values ​​respectively, and then restore the fault-free state of the circuit netlist.

[0166] Step S56, determine whether there are any faults to be simulated in F, if so, return to step S51; if not, go to step S6.

[0167] Step S6: Update T and F, and return to step S2. Specifically, delete the simulated test vector w from T, and update F=F und , and clear F und , then return to step S2.

[0168] The following will be Figure 2 Taking the digital circuit shown as an example, the practical application of the dimensional fusion parallel fault simulation method proposed in an embodiment of the present invention is explained.

[0169] Reference Figure 7 , Figure 7 The present invention provides Figure 2 The application diagram of the digital circuit for parallel fault simulation is shown in FIG. Figure 2 The digital circuit shown has two circuit netlists, where Figure 7 (a) is netlist 1, Figure 7 (b) is Netlist 2. Both Netlist 1 and Netlist 2 have four circuit levels, namely L1 to L4. Figure 7 In the test vector, the gray box represents the transmission of the fault effect, the white box represents the simulation value when there is no fault, and the number of circuit levels N L is 4, the number of circuit logic gates is N gate is 9, the number of netlists is N netlist is 2.

[0170] like Figure 2 The digital circuit shown can be divided into 7 FFRs, and the output of each FFR is a logic output or a fan-out. init ={a, c1, e, g}, test vector set T init={(01111011,10110000)}. Due to limited space, the test vector set in this embodiment only sets one set of test vectors. The faults are sorted into a, e, g, c1 according to the circuit level, and the faults are numbered 1 to 4 in this order.

[0171] Then, the digital circuit is converted into Figure 8 The FFR directed graph and FFR transmission domain shown in FIG. 1 are faulty. Since the circuit scale is small, the FFR transmission domain depth is set to 2 in this embodiment. The formula can be used to calculate Therefore, the maximum number of faults in a fault group is 2. In addition, the FFR levels of the FFR directed graph are level 1 and level 2, where FFR1 to FFE3 are located at level 1, and FFR4 to FFR7 are located at level 2.

[0172] Afterwards, fault simulation is performed on both netlists simultaneously.

[0173] Reference Fig. 9 , Fig. 9 It is a schematic diagram of the array identification of the event management mechanism provided by the present invention. Specifically, for netlist 1, non-overlapping FFR transmission domains containing faults are divided from the first layer FFR according to the grouping principle to obtain transmission domain 1 and transmission domain 3, and faults a and e are selected from them to be inserted into netlist 1. At the same time, the fault priority within the group is set, and the faults are sorted from high to low as a and e. For netlist 2, transmission domains 2 and 4 are selected according to the grouping principle, and faults c1 and g are selected from them to be inserted into netlist 2. At the same time, the fault priority within the group is set, and the faults are sorted from high to low as c1 and g.

[0174] Under a set of test vectors (01111011, 10110000), netlist 1 and netlist 2 set the circuit level identifiers and logic gate identifiers corresponding to faults a, e, c1, and g to 1. When the circuit level identifier of L1 is detected as 1, the identifiers of the first layer G1_0 and G2_0 in netlist 1 are detected, and the identifier of the first layer G3_1 in netlist 2 is detected; when the identifiers of the first layer G1_0 and G2_0 in netlist 1 are detected as 1, the fault simulation is performed on the logic gates G1 and G2 of netlist 1, and when the identifier of the first layer G3_1 in netlist 2 is detected as 1, the fault simulation is performed on the logic gate G3 of netlist 2.

[0175] Afterwards, the flags of L1, G1_0, G2_0, and G3_1 are reset to 0. Faults a and e in netlist 1 are transferred to logic gates G4, G5, and G6 of L2, respectively. Fault group G in netlist 2 is transferred to logic gate G6 of L2, so the flags of L2, G4_0, G5_0, G6_0, and G6_1 are set to 1.

[0176] When the circuit level identification of L2 is detected as 1, the identifications of the second layer G4_0, G5_0, and G6_0 in netlist 1 are detected, and the identification of the second layer G6_1 in netlist 2 is detected; when the identifications of the second layer G4_0, G5_0, and G6_0 in netlist 1 are detected as 1, fault simulation is performed on the logic gates G4, G5, and G6 of netlist 1, and when the identification of the second layer G6_1 in netlist 2 is detected as 1, fault simulation is performed on the logic gate G6 of netlist 2.

[0177] Afterwards, the flags of L2, G4_0, G5_0, G6_0, and G6_1 are reset to 0, and the fault e in netlist 1 is transferred to the logic gate G8 of L3, so the flag of L3, G8_0 is set to 1, and the fault group G in netlist 2 is transferred to the output end.

[0178] When the circuit level identifier of L3 is detected as 1, the identifier of the third layer G8_0 in netlist 1 is detected, and the identifier of the third layer G7_1 in netlist 2 is detected; when the identifier of the third layer G8_0 in netlist 1 is detected as 1, a fault simulation is performed on the logic gate G8 of netlist 1, and when the identifier of the third layer G7_1 in netlist 2 is detected as 1, a fault simulation is performed on the logic gate G7 of netlist 2.

[0179] Afterwards, the flags of L3, G8_0, and G7_1 are set to 0. Fault e in netlist 1 is transmitted to logic gate G9 of L4, so the flag of L4, G9_0 is set to 1.

[0180] When the circuit level identification of L4 is detected as 1, the identification of the fourth layer G9_0 in netlist 1 is detected; when the identification of the fourth layer G9_0 in netlist 1 is detected as 1, the logic gate G9 of netlist 1 is simulated. However, there is no logic gate identification 1 in the L4 layer of netlist 2, so the L4 layer of netlist 2 does not need to be simulated.

[0181] Afterwards, the flags of L4 and G9_0 are set to 0, and this round of fault simulation ends.

[0182] Through this round of fault simulation, fault a in netlist 1 cannot be transmitted to the output end under this set of test vectors, and fault e transmitted to output end p is a detectable fault, among which there is no abandoned fault. Therefore, from the first fault set F init Delete faults a and e from the fault set F, and put fault a into the second fault set F und Faults c1 and g in netlist 2 cannot be detected by the test vector, so c1 and g are removed from the first fault set F init and put it into the second fault set F und At this time, the second fault set F und ={a,c1,g}.

[0183] After this round of fault simulation, the first fault set Finit is empty, delete the current test vector group from the test vector set T, and set the first fault set F init =F und ={a,c1,g}, clear the second fault set F und However, since the test vector set T is an empty set, the fault simulation ends.

[0184] In addition, the present invention also provides a dimensional fusion parallel fault simulation system for digital circuits, comprising:

[0185] An acquisition module, used for acquiring a first fault set, a test vector set and an FFR directed graph of a digital circuit to be simulated;

[0186] A first judging module, used to judge whether there is at least one test vector group in the test vector set;

[0187] An initialization module, used for obtaining a current test vector group from the test vector set when there is at least one test vector group in the test vector set, and initializing multiple circuit netlists of the digital circuit to a fault-free state;

[0188] A fault simulation module, used for, when the first fault set is not empty, using the FFR directed graph to assign a corresponding fault group to each circuit netlist, performing parallel fault simulation on multiple circuit netlists based on the assigned fault groups under the current test vector group, and updating the first fault set and the second fault set until the first fault set is an empty set;

[0189] An updating module, used for updating the test vector set when the first fault set is an empty set, taking the second fault set as the first fault set, and returning to the step of determining whether the test vector set has at least one test vector group;

[0190] The end module is used to output the fault simulation result of the digital circuit when the test vector set is an empty set.

[0191] The contents of the above method embodiments are all applicable to the present system embodiments. The functions specifically implemented by the present system embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0192] An embodiment of the present invention further provides a computer-readable storage medium, in which a program executable by a processor is stored. When the program executable by the processor is executed by the processor, it is used to execute the aforementioned dimensional fusion parallel fault simulation method for a digital circuit.

[0193] Similarly, the contents of the above method embodiments are all applicable to the present storage medium embodiments. The functions specifically implemented by the present storage medium embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0194] In summary, the embodiments of the present invention provide a dimensional fusion parallel fault simulation method and system for digital circuits, which realizes parallel simulation of multiple faults through a dimensional fusion mechanism. The dimensional fusion mechanism can be divided into two aspects: simulation value storage space of shared logic gates and event management mechanism. At the same time, the dimensional fusion mechanism also integrates a priority simulation mechanism.

[0195] On the one hand, in the application of fault simulation, fault simulation is not a one-time operation. In the iterative optimization of chip design and manufacturing, it needs to be repeatedly run hundreds or thousands of times. For a circuit at the 20 million gate level, the circuit simulation value storage space for transition delay fault simulation can reach 2GB. If each fault requires 2GB of memory, the memory consumption is quite large. According to the FFR directed graph and the depth and width of the preset FFR transmission domain, the embodiment of the present invention searches for multiple FFR transmission domains of each circuit netlist in the digital circuit, and uses multiple FFR transmission domains to realize the grouping of multiple faults to be simulated in the first fault set, so that multiple faults in the same group can share the circuit simulation value storage space. Compared with the prior art, the embodiment of the present invention can greatly reduce the memory consumption when performing parallel fault detection by sharing the simulation value storage space, thereby improving the memory utilization and the running speed and efficiency of the fault simulation.

[0196] On the other hand, when the related technology uses event-driven simulation to activate the same logic gate, data competition problems usually occur, causing some faults that should be simulated to fail to be transmitted to the lower layer due to competition failure, which in turn leads to errors in the results of fault simulation and reduces the accuracy of fault simulation. Compared with the prior art, the embodiment of the present invention drives fault parallel simulation through circuit level identification and logic gate identification combined with event management mechanism and priority simulation mechanism, which has the advantage of competition inclusion, can well avoid the problem of data competition caused by the same logic gate being activated by different faults, ensure that the fault is accurately transmitted to the lower layer, and improve the accuracy of fault simulation.

[0197] A dimensional fusion parallel fault simulation method for digital circuits proposed in an embodiment of the present invention can greatly improve the running speed and efficiency of parallel fault simulation, solve the problems of memory explosion and data competition that occur in existing parallel fault simulation, and has high availability.

[0198] In some selectable embodiments, the function / operation mentioned in the block diagram may not occur in the order mentioned in the operation diagram. For example, depending on the function / operation involved, the two boxes shown in succession can actually be executed substantially simultaneously or the boxes can sometimes be executed in reverse order. In addition, the embodiment presented and described in the flow chart of the present invention is provided by way of example, for the purpose of providing a more comprehensive understanding of technology. The disclosed method is not limited to the operation and logic flow presented herein. Selectable embodiments are expected, wherein the order of various operations is changed and the sub-operation of a part for which is described as a larger operation is performed independently.

[0199] In addition, although the present invention is described in the context of functional modules, it should be understood that, unless otherwise specified, one or more of the functions and / or features can be integrated into a single physical device and / or software module, or one or more functions and / or features can be implemented in a separate physical device or software module. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding the present invention. More specifically, in view of the properties, functions and internal relationships of the various functional modules in the device disclosed herein, the actual implementation of the module will be understood within the conventional skills of the engineer. Therefore, those skilled in the art can implement the present invention set forth in the claims without excessive experimentation using ordinary techniques. It is also understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present invention, which is determined by the full scope of the appended claims and their equivalents.

[0200] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several programs to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc., which can store program codes.

[0201] The logic and / or steps represented in the flowchart or otherwise described herein, for example, may be considered as an ordered list of executable programs for implementing the logical functions, and may be embodied in any computer-readable medium for use by a program execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch and execute a program from a program execution system, device or apparatus), or in conjunction with such program execution systems, devices or apparatuses. For purposes of this specification, a "computer-readable medium" may be any device that can contain, store, communicate, propagate or transmit a program for use by a program execution system, device or apparatus, or in conjunction with such program execution systems, devices or apparatuses.

[0202] More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk case (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be a paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering or, if necessary, processing in another suitable manner, and then stored in a computer memory.

[0203] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable program execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0204] In the above description of this specification, the description with reference to the terms "one embodiment / example", "another embodiment / example" or "certain embodiments / examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0205] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

[0206] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present invention.

Claims

1. A dimensional fusion parallel fault simulation method for digital circuits, characterized in that: The following steps are involved: Obtaining a first fault set, a test vector set and an FFR directed graph of a digital circuit to be simulated; Determining whether the test vector set contains at least one test vector group; When the test vector set contains at least one test vector group, obtaining a current test vector group from the test vector set, and initializing a plurality of circuit netlists of the digital circuit to a fault-free state; When the first fault set is not empty, using the FFR directed graph to assign a corresponding fault group to each of the circuit netlists, performing parallel fault simulation on multiple circuit netlists based on the assigned fault groups under the current test vector group, and updating the first fault set and the second fault set until the first fault set is an empty set; When the first fault set is an empty set, updating the test vector set, taking the second fault set as the first fault set, and returning to the step of determining whether the test vector set has at least one test vector group; When the test vector set is an empty set, outputting a fault simulation result of the digital circuit; Wherein, when the first fault set is not empty, using the FFR directed graph to assign a corresponding fault group to each of the circuit netlists, performing parallel fault simulation on multiple circuit netlists based on the assigned fault groups under the current test vector group, and updating the first fault set and the second fault set until the first fault set is an empty set, including: When the first fault set is not empty, using the FFR directed graph to assign a corresponding fault group to each of the circuit netlists; Inserting each of the fault groups into a corresponding circuit netlist, performing parallel fault simulation on multiple circuit netlists through multiple parallel threads under the current test vector group, and obtaining a detection state of each fault to be simulated; The detection status includes any one of a completed status, an undetectable status or an abandoned status; Add the to-be-simulated faults in the first fault set that belong to the undetectable state and the abandoned state to the second fault set, and delete the to-be-simulated faults in the first fault set that belong to the completed state, the undetectable state, and the abandoned state; Initializing each of the circuit netlists to a fault-free state under the current test vector group; Determine whether the first fault set is an empty set; if not, return to the step of using the FFR directed graph to assign a corresponding fault group to each of the circuit netlists; if so, enter the step of updating the test vector set.

2. The method for dimensional fusion parallel fault simulation of digital circuits according to claim 1, characterized in that: The step of obtaining a first fault set, a test vector set, and an FFR directed graph of a digital circuit to be simulated includes: Acquire multiple faults to be simulated of the digital circuit and their numbers as a first fault set of the digital circuit, and acquire multiple test vector groups of the digital circuit as a test vector set of the digital circuit; Dividing the digital circuit into a plurality of non-fan-out regions, taking the non-fan-out regions as basic units, and representing the connections and data flows between the non-fan-out regions by directed line segments, thereby constructing an FFR directed graph of the digital circuit; The FFR directed graph has a hierarchical structure, the non-fan-out area is a circuit area in the digital circuit that has only one output terminal and the output terminal is a logic output terminal or a fan-out terminal, and each transmission line in each non-fan-out area is connected to at most one input terminal of a logic gate.

3. The method for dimensional fusion parallel fault simulation of digital circuits according to claim 1, characterized in that: For each of the circuit netlists, the step of using the FFR directed graph to assign a corresponding fault group to the circuit netlist comprises: Determining transmission parameters of the circuit netlist; According to the FFR directed graph and the transmission parameters, construct a plurality of fan-out-free transmission domains of the circuit netlist, wherein two adjacent fan-out-free transmission domains do not overlap each other, and each of the fan-out-free transmission domains includes at least one fault to be simulated and at least two fan-out-free areas; Selecting at least one fault to be simulated from each of the fan-out-free transmission domains in turn; Determine the priority of the selected fault to be simulated according to the number of the selected fault to be simulated, wherein the priority of the fault to be simulated with a smaller number is higher than the priority of the fault to be simulated with a larger number; The faults to be simulated and their priorities are used as the fault groups of the circuit netlist.

4. The method for dimensional fusion parallel fault simulation of digital circuits according to claim 3, characterized in that: The step of constructing a plurality of fan-out-free transmission domains of the circuit netlist according to the FFR directed graph and the transmission parameters comprises: According to the hierarchical structure of the FFR directed graph, any of the fan-out-free areas is used as an output point, and an FFR layer located before the FFR layer where the output point is located is used as a to-be-selected layer. The output point and the fan-out-free area in the to-be-selected layer that meets the transmission parameters and is connected to the output point are selected as fan-out-free transmission domains, thereby constructing multiple fan-out-free transmission domains of the circuit netlist.

5. The method for dimensional fusion parallel fault simulation of digital circuits according to claim 1, characterized in that: For each of the circuit netlists, after the fault group is inserted into the corresponding circuit netlist, the step of performing fault simulation on the circuit netlist includes: Acquire a logic gate in the circuit netlist whose circuit level identifier and logic identifier are a second value as a logic gate to be simulated; According to the hierarchical structure in the circuit netlist, the to-be-simulated logic gates in the circuit netlist are activated in sequence in an increasing manner of circuit hierarchy using the to-be-simulated faults in the fault group to perform fault simulation on the to-be-simulated logic gates.

6. The method for dimensional fusion parallel fault simulation of digital circuits according to claim 5, characterized in that: When the fault-activated paths in the circuit netlist are not interlaced and are independent of each other, the same simulation value storage space is used to perform fault simulation on all to-be-simulated faults in the fault group inserted into the circuit netlist.

7. The method for dimensional fusion parallel fault simulation of digital circuits according to claim 5, characterized in that: When multiple faults to be simulated activate the same logic gate to be simulated, the faults to be simulated with a priority greater than the third value are retained for activation of the next circuit level, and the abandoned state is used as the detection state of the faults to be simulated with a priority less than or equal to the third value.

8. The method for dimensional fusion parallel fault simulation of digital circuits according to claim 1, characterized in that: When the first fault set is an empty set, updating the test vector set comprises: When the first fault set is an empty set, the current test vector group is deleted from the test vector set, a next test vector group is selected as the current test vector group, and the test vector set is updated.

9. The method for dimensional fusion parallel fault simulation of digital circuits according to claim 1, characterized in that: The method further comprises the steps of: When the second fault set is an empty set, a fault simulation result of the digital circuit is output.

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